radeon_drv.c revision 1.1.1.3
1 /* $NetBSD: radeon_drv.c,v 1.1.1.3 2021/12/18 20:15:48 riastradh Exp $ */ 2 3 /** 4 * \file radeon_drv.c 5 * ATI Radeon driver 6 * 7 * \author Gareth Hughes <gareth (at) valinux.com> 8 */ 9 10 /* 11 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 12 * All Rights Reserved. 13 * 14 * Permission is hereby granted, free of charge, to any person obtaining a 15 * copy of this software and associated documentation files (the "Software"), 16 * to deal in the Software without restriction, including without limitation 17 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 18 * and/or sell copies of the Software, and to permit persons to whom the 19 * Software is furnished to do so, subject to the following conditions: 20 * 21 * The above copyright notice and this permission notice (including the next 22 * paragraph) shall be included in all copies or substantial portions of the 23 * Software. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 26 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 27 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 28 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 29 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 30 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 31 * OTHER DEALINGS IN THE SOFTWARE. 32 */ 33 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: radeon_drv.c,v 1.1.1.3 2021/12/18 20:15:48 riastradh Exp $"); 37 38 #include <linux/compat.h> 39 #include <linux/console.h> 40 #include <linux/module.h> 41 #include <linux/pm_runtime.h> 42 #include <linux/vga_switcheroo.h> 43 #include <linux/mmu_notifier.h> 44 45 #include <drm/drm_crtc_helper.h> 46 #include <drm/drm_drv.h> 47 #include <drm/drm_fb_helper.h> 48 #include <drm/drm_file.h> 49 #include <drm/drm_gem.h> 50 #include <drm/drm_ioctl.h> 51 #include <drm/drm_pci.h> 52 #include <drm/drm_pciids.h> 53 #include <drm/drm_probe_helper.h> 54 #include <drm/drm_vblank.h> 55 #include <drm/radeon_drm.h> 56 57 #include "radeon_drv.h" 58 59 /* 60 * KMS wrapper. 61 * - 2.0.0 - initial interface 62 * - 2.1.0 - add square tiling interface 63 * - 2.2.0 - add r6xx/r7xx const buffer support 64 * - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs 65 * - 2.4.0 - add crtc id query 66 * - 2.5.0 - add get accel 2 to work around ddx breakage for evergreen 67 * - 2.6.0 - add tiling config query (r6xx+), add initial HiZ support (r300->r500) 68 * 2.7.0 - fixups for r600 2D tiling support. (no external ABI change), add eg dyn gpr regs 69 * 2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK, clock crystal query 70 * 2.9.0 - r600 tiling (s3tc,rgtc) working, SET_PREDICATION packet 3 on r600 + eg, backend query 71 * 2.10.0 - fusion 2D tiling 72 * 2.11.0 - backend map, initial compute support for the CS checker 73 * 2.12.0 - RADEON_CS_KEEP_TILING_FLAGS 74 * 2.13.0 - virtual memory support, streamout 75 * 2.14.0 - add evergreen tiling informations 76 * 2.15.0 - add max_pipes query 77 * 2.16.0 - fix evergreen 2D tiled surface calculation 78 * 2.17.0 - add STRMOUT_BASE_UPDATE for r7xx 79 * 2.18.0 - r600-eg: allow "invalid" DB formats 80 * 2.19.0 - r600-eg: MSAA textures 81 * 2.20.0 - r600-si: RADEON_INFO_TIMESTAMP query 82 * 2.21.0 - r600-r700: FMASK and CMASK 83 * 2.22.0 - r600 only: RESOLVE_BOX allowed 84 * 2.23.0 - allow STRMOUT_BASE_UPDATE on RS780 and RS880 85 * 2.24.0 - eg only: allow MIP_ADDRESS=0 for MSAA textures 86 * 2.25.0 - eg+: new info request for num SE and num SH 87 * 2.26.0 - r600-eg: fix htile size computation 88 * 2.27.0 - r600-SI: Add CS ioctl support for async DMA 89 * 2.28.0 - r600-eg: Add MEM_WRITE packet support 90 * 2.29.0 - R500 FP16 color clear registers 91 * 2.30.0 - fix for FMASK texturing 92 * 2.31.0 - Add fastfb support for rs690 93 * 2.32.0 - new info request for rings working 94 * 2.33.0 - Add SI tiling mode array query 95 * 2.34.0 - Add CIK tiling mode array query 96 * 2.35.0 - Add CIK macrotile mode array query 97 * 2.36.0 - Fix CIK DCE tiling setup 98 * 2.37.0 - allow GS ring setup on r6xx/r7xx 99 * 2.38.0 - RADEON_GEM_OP (GET_INITIAL_DOMAIN, SET_INITIAL_DOMAIN), 100 * CIK: 1D and linear tiling modes contain valid PIPE_CONFIG 101 * 2.39.0 - Add INFO query for number of active CUs 102 * 2.40.0 - Add RADEON_GEM_GTT_WC/UC, flush HDP cache before submitting 103 * CS to GPU on >= r600 104 * 2.41.0 - evergreen/cayman: Add SET_BASE/DRAW_INDIRECT command parsing support 105 * 2.42.0 - Add VCE/VUI (Video Usability Information) support 106 * 2.43.0 - RADEON_INFO_GPU_RESET_COUNTER 107 * 2.44.0 - SET_APPEND_CNT packet3 support 108 * 2.45.0 - Allow setting shader registers using DMA/COPY packet3 on SI 109 * 2.46.0 - Add PFP_SYNC_ME support on evergreen 110 * 2.47.0 - Add UVD_NO_OP register support 111 * 2.48.0 - TA_CS_BC_BASE_ADDR allowed on SI 112 * 2.49.0 - DRM_RADEON_GEM_INFO ioctl returns correct vram_size/visible values 113 * 2.50.0 - Allows unaligned shader loads on CIK. (needed by OpenGL) 114 */ 115 #define KMS_DRIVER_MAJOR 2 116 #define KMS_DRIVER_MINOR 50 117 #define KMS_DRIVER_PATCHLEVEL 0 118 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags); 119 void radeon_driver_unload_kms(struct drm_device *dev); 120 void radeon_driver_lastclose_kms(struct drm_device *dev); 121 int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 122 void radeon_driver_postclose_kms(struct drm_device *dev, 123 struct drm_file *file_priv); 124 int radeon_suspend_kms(struct drm_device *dev, bool suspend, 125 bool fbcon, bool freeze); 126 int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon); 127 u32 radeon_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe); 128 int radeon_enable_vblank_kms(struct drm_device *dev, unsigned int pipe); 129 void radeon_disable_vblank_kms(struct drm_device *dev, unsigned int pipe); 130 void radeon_driver_irq_preinstall_kms(struct drm_device *dev); 131 int radeon_driver_irq_postinstall_kms(struct drm_device *dev); 132 void radeon_driver_irq_uninstall_kms(struct drm_device *dev); 133 irqreturn_t radeon_driver_irq_handler_kms(int irq, void *arg); 134 void radeon_gem_object_free(struct drm_gem_object *obj); 135 int radeon_gem_object_open(struct drm_gem_object *obj, 136 struct drm_file *file_priv); 137 void radeon_gem_object_close(struct drm_gem_object *obj, 138 struct drm_file *file_priv); 139 struct dma_buf *radeon_gem_prime_export(struct drm_gem_object *gobj, 140 int flags); 141 extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int crtc, 142 unsigned int flags, int *vpos, int *hpos, 143 ktime_t *stime, ktime_t *etime, 144 const struct drm_display_mode *mode); 145 extern bool radeon_is_px(struct drm_device *dev); 146 extern const struct drm_ioctl_desc radeon_ioctls_kms[]; 147 extern int radeon_max_kms_ioctl; 148 int radeon_mmap(struct file *filp, struct vm_area_struct *vma); 149 int radeon_mode_dumb_mmap(struct drm_file *filp, 150 struct drm_device *dev, 151 uint32_t handle, uint64_t *offset_p); 152 int radeon_mode_dumb_create(struct drm_file *file_priv, 153 struct drm_device *dev, 154 struct drm_mode_create_dumb *args); 155 struct sg_table *radeon_gem_prime_get_sg_table(struct drm_gem_object *obj); 156 struct drm_gem_object *radeon_gem_prime_import_sg_table(struct drm_device *dev, 157 struct dma_buf_attachment *, 158 struct sg_table *sg); 159 int radeon_gem_prime_pin(struct drm_gem_object *obj); 160 void radeon_gem_prime_unpin(struct drm_gem_object *obj); 161 void *radeon_gem_prime_vmap(struct drm_gem_object *obj); 162 void radeon_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr); 163 164 /* atpx handler */ 165 #if defined(CONFIG_VGA_SWITCHEROO) 166 void radeon_register_atpx_handler(void); 167 void radeon_unregister_atpx_handler(void); 168 bool radeon_has_atpx_dgpu_power_cntl(void); 169 bool radeon_is_atpx_hybrid(void); 170 #else 171 static inline void radeon_register_atpx_handler(void) {} 172 static inline void radeon_unregister_atpx_handler(void) {} 173 static inline bool radeon_has_atpx_dgpu_power_cntl(void) { return false; } 174 static inline bool radeon_is_atpx_hybrid(void) { return false; } 175 #endif 176 177 int radeon_no_wb; 178 int radeon_modeset = -1; 179 int radeon_dynclks = -1; 180 int radeon_r4xx_atom = 0; 181 #ifdef __powerpc__ 182 /* Default to PCI on PowerPC (fdo #95017) */ 183 int radeon_agpmode = -1; 184 #else 185 int radeon_agpmode = 0; 186 #endif 187 int radeon_vram_limit = 0; 188 int radeon_gart_size = -1; /* auto */ 189 int radeon_benchmarking = 0; 190 int radeon_testing = 0; 191 int radeon_connector_table = 0; 192 int radeon_tv = 1; 193 int radeon_audio = -1; 194 int radeon_disp_priority = 0; 195 int radeon_hw_i2c = 0; 196 int radeon_pcie_gen2 = -1; 197 int radeon_msi = -1; 198 int radeon_lockup_timeout = 10000; 199 int radeon_fastfb = 0; 200 int radeon_dpm = -1; 201 int radeon_aspm = -1; 202 int radeon_runtime_pm = -1; 203 int radeon_hard_reset = 0; 204 int radeon_vm_size = 8; 205 int radeon_vm_block_size = -1; 206 int radeon_deep_color = 0; 207 int radeon_use_pflipirq = 2; 208 int radeon_bapm = -1; 209 int radeon_backlight = -1; 210 int radeon_auxch = -1; 211 int radeon_mst = 0; 212 int radeon_uvd = 1; 213 int radeon_vce = 1; 214 215 MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers"); 216 module_param_named(no_wb, radeon_no_wb, int, 0444); 217 218 MODULE_PARM_DESC(modeset, "Disable/Enable modesetting"); 219 module_param_named(modeset, radeon_modeset, int, 0400); 220 221 MODULE_PARM_DESC(dynclks, "Disable/Enable dynamic clocks"); 222 module_param_named(dynclks, radeon_dynclks, int, 0444); 223 224 MODULE_PARM_DESC(r4xx_atom, "Enable ATOMBIOS modesetting for R4xx"); 225 module_param_named(r4xx_atom, radeon_r4xx_atom, int, 0444); 226 227 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 228 module_param_named(vramlimit, radeon_vram_limit, int, 0600); 229 230 MODULE_PARM_DESC(agpmode, "AGP Mode (-1 == PCI)"); 231 module_param_named(agpmode, radeon_agpmode, int, 0444); 232 233 MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)"); 234 module_param_named(gartsize, radeon_gart_size, int, 0600); 235 236 MODULE_PARM_DESC(benchmark, "Run benchmark"); 237 module_param_named(benchmark, radeon_benchmarking, int, 0444); 238 239 MODULE_PARM_DESC(test, "Run tests"); 240 module_param_named(test, radeon_testing, int, 0444); 241 242 MODULE_PARM_DESC(connector_table, "Force connector table"); 243 module_param_named(connector_table, radeon_connector_table, int, 0444); 244 245 MODULE_PARM_DESC(tv, "TV enable (0 = disable)"); 246 module_param_named(tv, radeon_tv, int, 0444); 247 248 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 249 module_param_named(audio, radeon_audio, int, 0444); 250 251 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 252 module_param_named(disp_priority, radeon_disp_priority, int, 0444); 253 254 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 255 module_param_named(hw_i2c, radeon_hw_i2c, int, 0444); 256 257 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 258 module_param_named(pcie_gen2, radeon_pcie_gen2, int, 0444); 259 260 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 261 module_param_named(msi, radeon_msi, int, 0444); 262 263 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 10000 = 10 seconds, 0 = disable)"); 264 module_param_named(lockup_timeout, radeon_lockup_timeout, int, 0444); 265 266 MODULE_PARM_DESC(fastfb, "Direct FB access for IGP chips (0 = disable, 1 = enable)"); 267 module_param_named(fastfb, radeon_fastfb, int, 0444); 268 269 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 270 module_param_named(dpm, radeon_dpm, int, 0444); 271 272 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 273 module_param_named(aspm, radeon_aspm, int, 0444); 274 275 MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)"); 276 module_param_named(runpm, radeon_runtime_pm, int, 0444); 277 278 MODULE_PARM_DESC(hard_reset, "PCI config reset (1 = force enable, 0 = disable (default))"); 279 module_param_named(hard_reset, radeon_hard_reset, int, 0444); 280 281 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 4GB)"); 282 module_param_named(vm_size, radeon_vm_size, int, 0444); 283 284 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 285 module_param_named(vm_block_size, radeon_vm_block_size, int, 0444); 286 287 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 288 module_param_named(deep_color, radeon_deep_color, int, 0444); 289 290 MODULE_PARM_DESC(use_pflipirq, "Pflip irqs for pageflip completion (0 = disable, 1 = as fallback, 2 = exclusive (default))"); 291 module_param_named(use_pflipirq, radeon_use_pflipirq, int, 0444); 292 293 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 294 module_param_named(bapm, radeon_bapm, int, 0444); 295 296 MODULE_PARM_DESC(backlight, "backlight support (1 = enable, 0 = disable, -1 = auto)"); 297 module_param_named(backlight, radeon_backlight, int, 0444); 298 299 MODULE_PARM_DESC(auxch, "Use native auxch experimental support (1 = enable, 0 = disable, -1 = auto)"); 300 module_param_named(auxch, radeon_auxch, int, 0444); 301 302 MODULE_PARM_DESC(mst, "DisplayPort MST experimental support (1 = enable, 0 = disable)"); 303 module_param_named(mst, radeon_mst, int, 0444); 304 305 MODULE_PARM_DESC(uvd, "uvd enable/disable uvd support (1 = enable, 0 = disable)"); 306 module_param_named(uvd, radeon_uvd, int, 0444); 307 308 MODULE_PARM_DESC(vce, "vce enable/disable vce support (1 = enable, 0 = disable)"); 309 module_param_named(vce, radeon_vce, int, 0444); 310 311 int radeon_si_support = 1; 312 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 313 module_param_named(si_support, radeon_si_support, int, 0444); 314 315 int radeon_cik_support = 1; 316 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 317 module_param_named(cik_support, radeon_cik_support, int, 0444); 318 319 static struct pci_device_id pciidlist[] = { 320 radeon_PCI_IDS 321 }; 322 323 MODULE_DEVICE_TABLE(pci, pciidlist); 324 325 static struct drm_driver kms_driver; 326 327 bool radeon_device_is_virtual(void); 328 329 static int radeon_pci_probe(struct pci_dev *pdev, 330 const struct pci_device_id *ent) 331 { 332 unsigned long flags = 0; 333 int ret; 334 335 if (!ent) 336 return -ENODEV; /* Avoid NULL-ptr deref in drm_get_pci_dev */ 337 338 flags = ent->driver_data; 339 340 if (!radeon_si_support) { 341 switch (flags & RADEON_FAMILY_MASK) { 342 case CHIP_TAHITI: 343 case CHIP_PITCAIRN: 344 case CHIP_VERDE: 345 case CHIP_OLAND: 346 case CHIP_HAINAN: 347 dev_info(&pdev->dev, 348 "SI support disabled by module param\n"); 349 return -ENODEV; 350 } 351 } 352 if (!radeon_cik_support) { 353 switch (flags & RADEON_FAMILY_MASK) { 354 case CHIP_KAVERI: 355 case CHIP_BONAIRE: 356 case CHIP_HAWAII: 357 case CHIP_KABINI: 358 case CHIP_MULLINS: 359 dev_info(&pdev->dev, 360 "CIK support disabled by module param\n"); 361 return -ENODEV; 362 } 363 } 364 365 if (vga_switcheroo_client_probe_defer(pdev)) 366 return -EPROBE_DEFER; 367 368 /* Get rid of things like offb */ 369 ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, "radeondrmfb"); 370 if (ret) 371 return ret; 372 373 return drm_get_pci_dev(pdev, ent, &kms_driver); 374 } 375 376 static void 377 radeon_pci_remove(struct pci_dev *pdev) 378 { 379 struct drm_device *dev = pci_get_drvdata(pdev); 380 381 drm_put_dev(dev); 382 } 383 384 static void 385 radeon_pci_shutdown(struct pci_dev *pdev) 386 { 387 /* if we are running in a VM, make sure the device 388 * torn down properly on reboot/shutdown 389 */ 390 if (radeon_device_is_virtual()) 391 radeon_pci_remove(pdev); 392 393 #ifdef CONFIG_PPC64 394 /* 395 * Some adapters need to be suspended before a 396 * shutdown occurs in order to prevent an error 397 * during kexec. 398 * Make this power specific becauase it breaks 399 * some non-power boards. 400 */ 401 radeon_suspend_kms(pci_get_drvdata(pdev), true, true, false); 402 #endif 403 } 404 405 static int radeon_pmops_suspend(struct device *dev) 406 { 407 struct drm_device *drm_dev = dev_get_drvdata(dev); 408 return radeon_suspend_kms(drm_dev, true, true, false); 409 } 410 411 static int radeon_pmops_resume(struct device *dev) 412 { 413 struct drm_device *drm_dev = dev_get_drvdata(dev); 414 415 /* GPU comes up enabled by the bios on resume */ 416 if (radeon_is_px(drm_dev)) { 417 pm_runtime_disable(dev); 418 pm_runtime_set_active(dev); 419 pm_runtime_enable(dev); 420 } 421 422 return radeon_resume_kms(drm_dev, true, true); 423 } 424 425 static int radeon_pmops_freeze(struct device *dev) 426 { 427 struct drm_device *drm_dev = dev_get_drvdata(dev); 428 return radeon_suspend_kms(drm_dev, false, true, true); 429 } 430 431 static int radeon_pmops_thaw(struct device *dev) 432 { 433 struct drm_device *drm_dev = dev_get_drvdata(dev); 434 return radeon_resume_kms(drm_dev, false, true); 435 } 436 437 static int radeon_pmops_runtime_suspend(struct device *dev) 438 { 439 struct pci_dev *pdev = to_pci_dev(dev); 440 struct drm_device *drm_dev = pci_get_drvdata(pdev); 441 int ret; 442 443 if (!radeon_is_px(drm_dev)) { 444 pm_runtime_forbid(dev); 445 return -EBUSY; 446 } 447 448 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 449 drm_kms_helper_poll_disable(drm_dev); 450 451 ret = radeon_suspend_kms(drm_dev, false, false, false); 452 pci_save_state(pdev); 453 pci_disable_device(pdev); 454 pci_ignore_hotplug(pdev); 455 if (radeon_is_atpx_hybrid()) 456 pci_set_power_state(pdev, PCI_D3cold); 457 else if (!radeon_has_atpx_dgpu_power_cntl()) 458 pci_set_power_state(pdev, PCI_D3hot); 459 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 460 461 return 0; 462 } 463 464 static int radeon_pmops_runtime_resume(struct device *dev) 465 { 466 struct pci_dev *pdev = to_pci_dev(dev); 467 struct drm_device *drm_dev = pci_get_drvdata(pdev); 468 int ret; 469 470 if (!radeon_is_px(drm_dev)) 471 return -EINVAL; 472 473 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 474 475 if (radeon_is_atpx_hybrid() || 476 !radeon_has_atpx_dgpu_power_cntl()) 477 pci_set_power_state(pdev, PCI_D0); 478 pci_restore_state(pdev); 479 ret = pci_enable_device(pdev); 480 if (ret) 481 return ret; 482 pci_set_master(pdev); 483 484 ret = radeon_resume_kms(drm_dev, false, false); 485 drm_kms_helper_poll_enable(drm_dev); 486 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 487 return 0; 488 } 489 490 static int radeon_pmops_runtime_idle(struct device *dev) 491 { 492 struct drm_device *drm_dev = dev_get_drvdata(dev); 493 struct drm_crtc *crtc; 494 495 if (!radeon_is_px(drm_dev)) { 496 pm_runtime_forbid(dev); 497 return -EBUSY; 498 } 499 500 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) { 501 if (crtc->enabled) { 502 DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); 503 return -EBUSY; 504 } 505 } 506 507 pm_runtime_mark_last_busy(dev); 508 pm_runtime_autosuspend(dev); 509 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 510 return 1; 511 } 512 513 long radeon_drm_ioctl(struct file *filp, 514 unsigned int cmd, unsigned long arg) 515 { 516 struct drm_file *file_priv = filp->private_data; 517 struct drm_device *dev; 518 long ret; 519 dev = file_priv->minor->dev; 520 ret = pm_runtime_get_sync(dev->dev); 521 if (ret < 0) 522 return ret; 523 524 ret = drm_ioctl(filp, cmd, arg); 525 526 pm_runtime_mark_last_busy(dev->dev); 527 pm_runtime_put_autosuspend(dev->dev); 528 return ret; 529 } 530 531 #ifdef CONFIG_COMPAT 532 static long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) 533 { 534 unsigned int nr = DRM_IOCTL_NR(cmd); 535 int ret; 536 537 if (nr < DRM_COMMAND_BASE) 538 return drm_compat_ioctl(filp, cmd, arg); 539 540 ret = radeon_drm_ioctl(filp, cmd, arg); 541 542 return ret; 543 } 544 #endif 545 546 static const struct dev_pm_ops radeon_pm_ops = { 547 .suspend = radeon_pmops_suspend, 548 .resume = radeon_pmops_resume, 549 .freeze = radeon_pmops_freeze, 550 .thaw = radeon_pmops_thaw, 551 .poweroff = radeon_pmops_freeze, 552 .restore = radeon_pmops_resume, 553 .runtime_suspend = radeon_pmops_runtime_suspend, 554 .runtime_resume = radeon_pmops_runtime_resume, 555 .runtime_idle = radeon_pmops_runtime_idle, 556 }; 557 558 static const struct file_operations radeon_driver_kms_fops = { 559 .owner = THIS_MODULE, 560 .open = drm_open, 561 .release = drm_release, 562 .unlocked_ioctl = radeon_drm_ioctl, 563 .mmap = radeon_mmap, 564 .poll = drm_poll, 565 .read = drm_read, 566 #ifdef CONFIG_COMPAT 567 .compat_ioctl = radeon_kms_compat_ioctl, 568 #endif 569 }; 570 571 static bool 572 radeon_get_crtc_scanout_position(struct drm_device *dev, unsigned int pipe, 573 bool in_vblank_irq, int *vpos, int *hpos, 574 ktime_t *stime, ktime_t *etime, 575 const struct drm_display_mode *mode) 576 { 577 return radeon_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos, 578 stime, etime, mode); 579 } 580 581 static struct drm_driver kms_driver = { 582 .driver_features = 583 DRIVER_USE_AGP | DRIVER_GEM | DRIVER_RENDER, 584 .load = radeon_driver_load_kms, 585 .open = radeon_driver_open_kms, 586 .postclose = radeon_driver_postclose_kms, 587 .lastclose = radeon_driver_lastclose_kms, 588 .unload = radeon_driver_unload_kms, 589 .get_vblank_counter = radeon_get_vblank_counter_kms, 590 .enable_vblank = radeon_enable_vblank_kms, 591 .disable_vblank = radeon_disable_vblank_kms, 592 .get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos, 593 .get_scanout_position = radeon_get_crtc_scanout_position, 594 .irq_preinstall = radeon_driver_irq_preinstall_kms, 595 .irq_postinstall = radeon_driver_irq_postinstall_kms, 596 .irq_uninstall = radeon_driver_irq_uninstall_kms, 597 .irq_handler = radeon_driver_irq_handler_kms, 598 .ioctls = radeon_ioctls_kms, 599 .gem_free_object_unlocked = radeon_gem_object_free, 600 .gem_open_object = radeon_gem_object_open, 601 .gem_close_object = radeon_gem_object_close, 602 .dumb_create = radeon_mode_dumb_create, 603 .dumb_map_offset = radeon_mode_dumb_mmap, 604 .fops = &radeon_driver_kms_fops, 605 606 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 607 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 608 .gem_prime_export = radeon_gem_prime_export, 609 .gem_prime_pin = radeon_gem_prime_pin, 610 .gem_prime_unpin = radeon_gem_prime_unpin, 611 .gem_prime_get_sg_table = radeon_gem_prime_get_sg_table, 612 .gem_prime_import_sg_table = radeon_gem_prime_import_sg_table, 613 .gem_prime_vmap = radeon_gem_prime_vmap, 614 .gem_prime_vunmap = radeon_gem_prime_vunmap, 615 616 .name = DRIVER_NAME, 617 .desc = DRIVER_DESC, 618 .date = DRIVER_DATE, 619 .major = KMS_DRIVER_MAJOR, 620 .minor = KMS_DRIVER_MINOR, 621 .patchlevel = KMS_DRIVER_PATCHLEVEL, 622 }; 623 624 static struct drm_driver *driver; 625 static struct pci_driver *pdriver; 626 627 static struct pci_driver radeon_kms_pci_driver = { 628 .name = DRIVER_NAME, 629 .id_table = pciidlist, 630 .probe = radeon_pci_probe, 631 .remove = radeon_pci_remove, 632 .shutdown = radeon_pci_shutdown, 633 .driver.pm = &radeon_pm_ops, 634 }; 635 636 static int __init radeon_init(void) 637 { 638 if (vgacon_text_force() && radeon_modeset == -1) { 639 DRM_INFO("VGACON disable radeon kernel modesetting.\n"); 640 radeon_modeset = 0; 641 } 642 /* set to modesetting by default if not nomodeset */ 643 if (radeon_modeset == -1) 644 radeon_modeset = 1; 645 646 if (radeon_modeset == 1) { 647 DRM_INFO("radeon kernel modesetting enabled.\n"); 648 driver = &kms_driver; 649 pdriver = &radeon_kms_pci_driver; 650 driver->driver_features |= DRIVER_MODESET; 651 driver->num_ioctls = radeon_max_kms_ioctl; 652 radeon_register_atpx_handler(); 653 654 } else { 655 DRM_ERROR("No UMS support in radeon module!\n"); 656 return -EINVAL; 657 } 658 659 return pci_register_driver(pdriver); 660 } 661 662 static void __exit radeon_exit(void) 663 { 664 pci_unregister_driver(pdriver); 665 radeon_unregister_atpx_handler(); 666 mmu_notifier_synchronize(); 667 } 668 669 module_init(radeon_init); 670 module_exit(radeon_exit); 671 672 MODULE_AUTHOR(DRIVER_AUTHOR); 673 MODULE_DESCRIPTION(DRIVER_DESC); 674 MODULE_LICENSE("GPL and additional rights"); 675
Indexes created Wed Oct 22 00:09:40 GMT 2025