radeon_drv.c revision 1.6
1 /* $NetBSD: radeon_drv.c,v 1.6 2018/08/27 04:58:36 riastradh Exp $ */ 2 3 /** 4 * \file radeon_drv.c 5 * ATI Radeon driver 6 * 7 * \author Gareth Hughes <gareth (at) valinux.com> 8 */ 9 10 /* 11 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 12 * All Rights Reserved. 13 * 14 * Permission is hereby granted, free of charge, to any person obtaining a 15 * copy of this software and associated documentation files (the "Software"), 16 * to deal in the Software without restriction, including without limitation 17 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 18 * and/or sell copies of the Software, and to permit persons to whom the 19 * Software is furnished to do so, subject to the following conditions: 20 * 21 * The above copyright notice and this permission notice (including the next 22 * paragraph) shall be included in all copies or substantial portions of the 23 * Software. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 26 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 27 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 28 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 29 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 30 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 31 * OTHER DEALINGS IN THE SOFTWARE. 32 */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: radeon_drv.c,v 1.6 2018/08/27 04:58:36 riastradh Exp $"); 36 37 #include <drm/drmP.h> 38 #include <drm/radeon_drm.h> 39 #include "radeon_drv.h" 40 41 #include <drm/drm_pciids.h> 42 #include <linux/console.h> 43 #include <linux/module.h> 44 #include <linux/moduleparam.h> 45 #include <linux/pm_runtime.h> 46 #include <linux/vga_switcheroo.h> 47 #include <drm/drm_gem.h> 48 49 #include "drm_crtc_helper.h" 50 #include "radeon_kfd.h" 51 52 /* 53 * KMS wrapper. 54 * - 2.0.0 - initial interface 55 * - 2.1.0 - add square tiling interface 56 * - 2.2.0 - add r6xx/r7xx const buffer support 57 * - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs 58 * - 2.4.0 - add crtc id query 59 * - 2.5.0 - add get accel 2 to work around ddx breakage for evergreen 60 * - 2.6.0 - add tiling config query (r6xx+), add initial HiZ support (r300->r500) 61 * 2.7.0 - fixups for r600 2D tiling support. (no external ABI change), add eg dyn gpr regs 62 * 2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK, clock crystal query 63 * 2.9.0 - r600 tiling (s3tc,rgtc) working, SET_PREDICATION packet 3 on r600 + eg, backend query 64 * 2.10.0 - fusion 2D tiling 65 * 2.11.0 - backend map, initial compute support for the CS checker 66 * 2.12.0 - RADEON_CS_KEEP_TILING_FLAGS 67 * 2.13.0 - virtual memory support, streamout 68 * 2.14.0 - add evergreen tiling informations 69 * 2.15.0 - add max_pipes query 70 * 2.16.0 - fix evergreen 2D tiled surface calculation 71 * 2.17.0 - add STRMOUT_BASE_UPDATE for r7xx 72 * 2.18.0 - r600-eg: allow "invalid" DB formats 73 * 2.19.0 - r600-eg: MSAA textures 74 * 2.20.0 - r600-si: RADEON_INFO_TIMESTAMP query 75 * 2.21.0 - r600-r700: FMASK and CMASK 76 * 2.22.0 - r600 only: RESOLVE_BOX allowed 77 * 2.23.0 - allow STRMOUT_BASE_UPDATE on RS780 and RS880 78 * 2.24.0 - eg only: allow MIP_ADDRESS=0 for MSAA textures 79 * 2.25.0 - eg+: new info request for num SE and num SH 80 * 2.26.0 - r600-eg: fix htile size computation 81 * 2.27.0 - r600-SI: Add CS ioctl support for async DMA 82 * 2.28.0 - r600-eg: Add MEM_WRITE packet support 83 * 2.29.0 - R500 FP16 color clear registers 84 * 2.30.0 - fix for FMASK texturing 85 * 2.31.0 - Add fastfb support for rs690 86 * 2.32.0 - new info request for rings working 87 * 2.33.0 - Add SI tiling mode array query 88 * 2.34.0 - Add CIK tiling mode array query 89 * 2.35.0 - Add CIK macrotile mode array query 90 * 2.36.0 - Fix CIK DCE tiling setup 91 * 2.37.0 - allow GS ring setup on r6xx/r7xx 92 * 2.38.0 - RADEON_GEM_OP (GET_INITIAL_DOMAIN, SET_INITIAL_DOMAIN), 93 * CIK: 1D and linear tiling modes contain valid PIPE_CONFIG 94 * 2.39.0 - Add INFO query for number of active CUs 95 * 2.40.0 - Add RADEON_GEM_GTT_WC/UC, flush HDP cache before submitting 96 * CS to GPU on >= r600 97 * 2.41.0 - evergreen/cayman: Add SET_BASE/DRAW_INDIRECT command parsing support 98 * 2.42.0 - Add VCE/VUI (Video Usability Information) support 99 * 2.43.0 - RADEON_INFO_GPU_RESET_COUNTER 100 */ 101 #define KMS_DRIVER_MAJOR 2 102 #define KMS_DRIVER_MINOR 43 103 #define KMS_DRIVER_PATCHLEVEL 0 104 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags); 105 int radeon_driver_unload_kms(struct drm_device *dev); 106 void radeon_driver_lastclose_kms(struct drm_device *dev); 107 int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 108 void radeon_driver_postclose_kms(struct drm_device *dev, 109 struct drm_file *file_priv); 110 void radeon_driver_preclose_kms(struct drm_device *dev, 111 struct drm_file *file_priv); 112 int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon); 113 int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon); 114 u32 radeon_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe); 115 int radeon_enable_vblank_kms(struct drm_device *dev, unsigned int pipe); 116 void radeon_disable_vblank_kms(struct drm_device *dev, unsigned int pipe); 117 int radeon_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe, 118 int *max_error, 119 struct timeval *vblank_time, 120 unsigned flags); 121 void radeon_driver_irq_preinstall_kms(struct drm_device *dev); 122 int radeon_driver_irq_postinstall_kms(struct drm_device *dev); 123 void radeon_driver_irq_uninstall_kms(struct drm_device *dev); 124 irqreturn_t radeon_driver_irq_handler_kms(DRM_IRQ_ARGS); 125 void radeon_gem_object_free(struct drm_gem_object *obj); 126 int radeon_gem_object_open(struct drm_gem_object *obj, 127 struct drm_file *file_priv); 128 void radeon_gem_object_close(struct drm_gem_object *obj, 129 struct drm_file *file_priv); 130 struct dma_buf *radeon_gem_prime_export(struct drm_device *dev, 131 struct drm_gem_object *gobj, 132 int flags); 133 extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int crtc, 134 unsigned int flags, int *vpos, int *hpos, 135 ktime_t *stime, ktime_t *etime, 136 const struct drm_display_mode *mode); 137 extern bool radeon_is_px(struct drm_device *dev); 138 extern const struct drm_ioctl_desc radeon_ioctls_kms[]; 139 extern int radeon_max_kms_ioctl; 140 #ifdef __NetBSD__ 141 int radeon_mmap_object(struct drm_device *, off_t, size_t, vm_prot_t, 142 struct uvm_object **, voff_t *, struct file *); 143 #else 144 int radeon_mmap(struct file *filp, struct vm_area_struct *vma); 145 #endif 146 int radeon_mode_dumb_mmap(struct drm_file *filp, 147 struct drm_device *dev, 148 uint32_t handle, uint64_t *offset_p); 149 int radeon_mode_dumb_create(struct drm_file *file_priv, 150 struct drm_device *dev, 151 struct drm_mode_create_dumb *args); 152 struct sg_table *radeon_gem_prime_get_sg_table(struct drm_gem_object *obj); 153 struct drm_gem_object *radeon_gem_prime_import_sg_table(struct drm_device *dev, 154 struct dma_buf_attachment *, 155 struct sg_table *sg); 156 int radeon_gem_prime_pin(struct drm_gem_object *obj); 157 void radeon_gem_prime_unpin(struct drm_gem_object *obj); 158 struct reservation_object *radeon_gem_prime_res_obj(struct drm_gem_object *); 159 void *radeon_gem_prime_vmap(struct drm_gem_object *obj); 160 void radeon_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr); 161 extern long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd, 162 unsigned long arg); 163 164 #if defined(CONFIG_DEBUG_FS) 165 int radeon_debugfs_init(struct drm_minor *minor); 166 void radeon_debugfs_cleanup(struct drm_minor *minor); 167 #endif 168 169 /* atpx handler */ 170 #if defined(CONFIG_VGA_SWITCHEROO) 171 void radeon_register_atpx_handler(void); 172 void radeon_unregister_atpx_handler(void); 173 #else 174 #ifndef __NetBSD__ 175 static inline void radeon_register_atpx_handler(void) {} 176 static inline void radeon_unregister_atpx_handler(void) {} 177 #endif 178 #endif 179 180 int radeon_no_wb; 181 int radeon_modeset = -1; 182 int radeon_dynclks = -1; 183 int radeon_r4xx_atom = 0; 184 int radeon_agpmode = 0; 185 int radeon_vram_limit = 0; 186 int radeon_gart_size = -1; /* auto */ 187 int radeon_benchmarking = 0; 188 int radeon_testing = 0; 189 int radeon_connector_table = 0; 190 int radeon_tv = 1; 191 int radeon_audio = -1; 192 int radeon_disp_priority = 0; 193 int radeon_hw_i2c = 0; 194 int radeon_pcie_gen2 = -1; 195 int radeon_msi = -1; 196 int radeon_lockup_timeout = 10000; 197 int radeon_fastfb = 0; 198 int radeon_dpm = -1; 199 int radeon_aspm = -1; 200 int radeon_runtime_pm = -1; 201 int radeon_hard_reset = 0; 202 int radeon_vm_size = 8; 203 int radeon_vm_block_size = -1; 204 int radeon_deep_color = 0; 205 int radeon_use_pflipirq = 2; 206 int radeon_bapm = -1; 207 int radeon_backlight = -1; 208 int radeon_auxch = -1; 209 int radeon_mst = 0; 210 211 MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers"); 212 module_param_named(no_wb, radeon_no_wb, int, 0444); 213 214 MODULE_PARM_DESC(modeset, "Disable/Enable modesetting"); 215 module_param_named(modeset, radeon_modeset, int, 0400); 216 217 MODULE_PARM_DESC(dynclks, "Disable/Enable dynamic clocks"); 218 module_param_named(dynclks, radeon_dynclks, int, 0444); 219 220 MODULE_PARM_DESC(r4xx_atom, "Enable ATOMBIOS modesetting for R4xx"); 221 module_param_named(r4xx_atom, radeon_r4xx_atom, int, 0444); 222 223 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 224 module_param_named(vramlimit, radeon_vram_limit, int, 0600); 225 226 MODULE_PARM_DESC(agpmode, "AGP Mode (-1 == PCI)"); 227 module_param_named(agpmode, radeon_agpmode, int, 0444); 228 229 MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)"); 230 module_param_named(gartsize, radeon_gart_size, int, 0600); 231 232 MODULE_PARM_DESC(benchmark, "Run benchmark"); 233 module_param_named(benchmark, radeon_benchmarking, int, 0444); 234 235 MODULE_PARM_DESC(test, "Run tests"); 236 module_param_named(test, radeon_testing, int, 0444); 237 238 MODULE_PARM_DESC(connector_table, "Force connector table"); 239 module_param_named(connector_table, radeon_connector_table, int, 0444); 240 241 MODULE_PARM_DESC(tv, "TV enable (0 = disable)"); 242 module_param_named(tv, radeon_tv, int, 0444); 243 244 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 245 module_param_named(audio, radeon_audio, int, 0444); 246 247 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 248 module_param_named(disp_priority, radeon_disp_priority, int, 0444); 249 250 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 251 module_param_named(hw_i2c, radeon_hw_i2c, int, 0444); 252 253 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 254 module_param_named(pcie_gen2, radeon_pcie_gen2, int, 0444); 255 256 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 257 module_param_named(msi, radeon_msi, int, 0444); 258 259 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 10000 = 10 seconds, 0 = disable)"); 260 module_param_named(lockup_timeout, radeon_lockup_timeout, int, 0444); 261 262 MODULE_PARM_DESC(fastfb, "Direct FB access for IGP chips (0 = disable, 1 = enable)"); 263 module_param_named(fastfb, radeon_fastfb, int, 0444); 264 265 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 266 module_param_named(dpm, radeon_dpm, int, 0444); 267 268 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 269 module_param_named(aspm, radeon_aspm, int, 0444); 270 271 MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)"); 272 module_param_named(runpm, radeon_runtime_pm, int, 0444); 273 274 MODULE_PARM_DESC(hard_reset, "PCI config reset (1 = force enable, 0 = disable (default))"); 275 module_param_named(hard_reset, radeon_hard_reset, int, 0444); 276 277 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 4GB)"); 278 module_param_named(vm_size, radeon_vm_size, int, 0444); 279 280 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 281 module_param_named(vm_block_size, radeon_vm_block_size, int, 0444); 282 283 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 284 module_param_named(deep_color, radeon_deep_color, int, 0444); 285 286 MODULE_PARM_DESC(use_pflipirq, "Pflip irqs for pageflip completion (0 = disable, 1 = as fallback, 2 = exclusive (default))"); 287 module_param_named(use_pflipirq, radeon_use_pflipirq, int, 0444); 288 289 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 290 module_param_named(bapm, radeon_bapm, int, 0444); 291 292 MODULE_PARM_DESC(backlight, "backlight support (1 = enable, 0 = disable, -1 = auto)"); 293 module_param_named(backlight, radeon_backlight, int, 0444); 294 295 MODULE_PARM_DESC(auxch, "Use native auxch experimental support (1 = enable, 0 = disable, -1 = auto)"); 296 module_param_named(auxch, radeon_auxch, int, 0444); 297 298 MODULE_PARM_DESC(mst, "DisplayPort MST experimental support (1 = enable, 0 = disable)"); 299 module_param_named(mst, radeon_mst, int, 0444); 300 301 static struct pci_device_id pciidlist[] = { 302 radeon_PCI_IDS 303 }; 304 305 MODULE_DEVICE_TABLE(pci, pciidlist); 306 307 #ifdef CONFIG_DRM_RADEON_UMS 308 309 static int radeon_suspend(struct drm_device *dev, pm_message_t state) 310 { 311 drm_radeon_private_t *dev_priv = dev->dev_private; 312 313 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) 314 return 0; 315 316 /* Disable *all* interrupts */ 317 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) 318 RADEON_WRITE(R500_DxMODE_INT_MASK, 0); 319 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0); 320 return 0; 321 } 322 323 static int radeon_resume(struct drm_device *dev) 324 { 325 drm_radeon_private_t *dev_priv = dev->dev_private; 326 327 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) 328 return 0; 329 330 /* Restore interrupt registers */ 331 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) 332 RADEON_WRITE(R500_DxMODE_INT_MASK, dev_priv->r500_disp_irq_reg); 333 RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg); 334 return 0; 335 } 336 337 338 static const struct file_operations radeon_driver_old_fops = { 339 .owner = THIS_MODULE, 340 .open = drm_open, 341 .release = drm_release, 342 .unlocked_ioctl = drm_ioctl, 343 .mmap = drm_legacy_mmap, 344 .poll = drm_poll, 345 .read = drm_read, 346 #ifdef CONFIG_COMPAT 347 .compat_ioctl = radeon_compat_ioctl, 348 #endif 349 .llseek = noop_llseek, 350 }; 351 352 static struct drm_driver driver_old = { 353 .driver_features = 354 DRIVER_USE_AGP | DRIVER_PCI_DMA | DRIVER_SG | 355 DRIVER_HAVE_IRQ | DRIVER_HAVE_DMA | DRIVER_IRQ_SHARED, 356 .dev_priv_size = sizeof(drm_radeon_buf_priv_t), 357 .load = radeon_driver_load, 358 .firstopen = radeon_driver_firstopen, 359 .open = radeon_driver_open, 360 .preclose = radeon_driver_preclose, 361 .postclose = radeon_driver_postclose, 362 .lastclose = radeon_driver_lastclose, 363 .set_busid = drm_pci_set_busid, 364 .unload = radeon_driver_unload, 365 .suspend = radeon_suspend, 366 .resume = radeon_resume, 367 .get_vblank_counter = radeon_get_vblank_counter, 368 .enable_vblank = radeon_enable_vblank, 369 .disable_vblank = radeon_disable_vblank, 370 .master_create = radeon_master_create, 371 .master_destroy = radeon_master_destroy, 372 .irq_preinstall = radeon_driver_irq_preinstall, 373 .irq_postinstall = radeon_driver_irq_postinstall, 374 .irq_uninstall = radeon_driver_irq_uninstall, 375 .irq_handler = radeon_driver_irq_handler, 376 .ioctls = radeon_ioctls, 377 .dma_ioctl = radeon_cp_buffers, 378 .fops = &radeon_driver_old_fops, 379 .name = DRIVER_NAME, 380 .desc = DRIVER_DESC, 381 .date = DRIVER_DATE, 382 .major = DRIVER_MAJOR, 383 .minor = DRIVER_MINOR, 384 .patchlevel = DRIVER_PATCHLEVEL, 385 }; 386 387 #endif 388 389 static struct drm_driver kms_driver; 390 391 #ifdef __NetBSD__ 392 393 struct drm_driver *const radeon_drm_driver = &kms_driver; 394 const struct pci_device_id *const radeon_device_ids = pciidlist; 395 const size_t radeon_n_device_ids = __arraycount(pciidlist); 396 397 /* XXX Kludge for the non-GEM GEM that radeon uses. */ 398 static const struct uvm_pagerops radeon_gem_uvm_ops; 399 400 #else 401 402 static int radeon_kick_out_firmware_fb(struct pci_dev *pdev) 403 { 404 struct apertures_struct *ap; 405 bool primary = false; 406 407 ap = alloc_apertures(1); 408 if (!ap) 409 return -ENOMEM; 410 411 ap->ranges[0].base = pci_resource_start(pdev, 0); 412 ap->ranges[0].size = pci_resource_len(pdev, 0); 413 414 #ifdef CONFIG_X86 415 primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; 416 #endif 417 remove_conflicting_framebuffers(ap, "radeondrmfb", primary); 418 kfree(ap); 419 420 return 0; 421 } 422 423 static int radeon_pci_probe(struct pci_dev *pdev, 424 const struct pci_device_id *ent) 425 { 426 int ret; 427 428 /* Get rid of things like offb */ 429 ret = radeon_kick_out_firmware_fb(pdev); 430 if (ret) 431 return ret; 432 433 return drm_get_pci_dev(pdev, ent, &kms_driver); 434 } 435 436 static void 437 radeon_pci_remove(struct pci_dev *pdev) 438 { 439 struct drm_device *dev = pci_get_drvdata(pdev); 440 441 drm_put_dev(dev); 442 } 443 444 static int radeon_pmops_suspend(struct device *dev) 445 { 446 struct pci_dev *pdev = to_pci_dev(dev); 447 struct drm_device *drm_dev = pci_get_drvdata(pdev); 448 return radeon_suspend_kms(drm_dev, true, true); 449 } 450 451 static int radeon_pmops_resume(struct device *dev) 452 { 453 struct pci_dev *pdev = to_pci_dev(dev); 454 struct drm_device *drm_dev = pci_get_drvdata(pdev); 455 return radeon_resume_kms(drm_dev, true, true); 456 } 457 458 static int radeon_pmops_freeze(struct device *dev) 459 { 460 struct pci_dev *pdev = to_pci_dev(dev); 461 struct drm_device *drm_dev = pci_get_drvdata(pdev); 462 return radeon_suspend_kms(drm_dev, false, true); 463 } 464 465 static int radeon_pmops_thaw(struct device *dev) 466 { 467 struct pci_dev *pdev = to_pci_dev(dev); 468 struct drm_device *drm_dev = pci_get_drvdata(pdev); 469 return radeon_resume_kms(drm_dev, false, true); 470 } 471 472 static int radeon_pmops_runtime_suspend(struct device *dev) 473 { 474 struct pci_dev *pdev = to_pci_dev(dev); 475 struct drm_device *drm_dev = pci_get_drvdata(pdev); 476 int ret; 477 478 if (!radeon_is_px(drm_dev)) { 479 pm_runtime_forbid(dev); 480 return -EBUSY; 481 } 482 483 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 484 drm_kms_helper_poll_disable(drm_dev); 485 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF); 486 487 ret = radeon_suspend_kms(drm_dev, false, false); 488 pci_save_state(pdev); 489 pci_disable_device(pdev); 490 pci_ignore_hotplug(pdev); 491 pci_set_power_state(pdev, PCI_D3cold); 492 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 493 494 return 0; 495 } 496 497 static int radeon_pmops_runtime_resume(struct device *dev) 498 { 499 struct pci_dev *pdev = to_pci_dev(dev); 500 struct drm_device *drm_dev = pci_get_drvdata(pdev); 501 int ret; 502 503 if (!radeon_is_px(drm_dev)) 504 return -EINVAL; 505 506 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 507 508 pci_set_power_state(pdev, PCI_D0); 509 pci_restore_state(pdev); 510 ret = pci_enable_device(pdev); 511 if (ret) 512 return ret; 513 pci_set_master(pdev); 514 515 ret = radeon_resume_kms(drm_dev, false, false); 516 drm_kms_helper_poll_enable(drm_dev); 517 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON); 518 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 519 return 0; 520 } 521 522 static int radeon_pmops_runtime_idle(struct device *dev) 523 { 524 struct pci_dev *pdev = to_pci_dev(dev); 525 struct drm_device *drm_dev = pci_get_drvdata(pdev); 526 struct drm_crtc *crtc; 527 528 if (!radeon_is_px(drm_dev)) { 529 pm_runtime_forbid(dev); 530 return -EBUSY; 531 } 532 533 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) { 534 if (crtc->enabled) { 535 DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); 536 return -EBUSY; 537 } 538 } 539 540 pm_runtime_mark_last_busy(dev); 541 pm_runtime_autosuspend(dev); 542 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 543 return 1; 544 } 545 546 long radeon_drm_ioctl(struct file *filp, 547 unsigned int cmd, unsigned long arg) 548 { 549 struct drm_file *file_priv = filp->private_data; 550 struct drm_device *dev; 551 long ret; 552 dev = file_priv->minor->dev; 553 ret = pm_runtime_get_sync(dev->dev); 554 if (ret < 0) 555 return ret; 556 557 ret = drm_ioctl(filp, cmd, arg); 558 559 pm_runtime_mark_last_busy(dev->dev); 560 pm_runtime_put_autosuspend(dev->dev); 561 return ret; 562 } 563 564 static const struct dev_pm_ops radeon_pm_ops = { 565 .suspend = radeon_pmops_suspend, 566 .resume = radeon_pmops_resume, 567 .freeze = radeon_pmops_freeze, 568 .thaw = radeon_pmops_thaw, 569 .poweroff = radeon_pmops_freeze, 570 .restore = radeon_pmops_resume, 571 .runtime_suspend = radeon_pmops_runtime_suspend, 572 .runtime_resume = radeon_pmops_runtime_resume, 573 .runtime_idle = radeon_pmops_runtime_idle, 574 }; 575 576 static const struct file_operations radeon_driver_kms_fops = { 577 .owner = THIS_MODULE, 578 .open = drm_open, 579 .release = drm_release, 580 .unlocked_ioctl = radeon_drm_ioctl, 581 .mmap = radeon_mmap, 582 .poll = drm_poll, 583 .read = drm_read, 584 #ifdef CONFIG_COMPAT 585 .compat_ioctl = radeon_kms_compat_ioctl, 586 #endif 587 }; 588 #endif /* __NetBSD__ */ 589 590 static struct drm_driver kms_driver = { 591 .driver_features = 592 DRIVER_USE_AGP | 593 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | 594 DRIVER_PRIME | DRIVER_RENDER, 595 .load = radeon_driver_load_kms, 596 .open = radeon_driver_open_kms, 597 .preclose = radeon_driver_preclose_kms, 598 .postclose = radeon_driver_postclose_kms, 599 .lastclose = radeon_driver_lastclose_kms, 600 .set_busid = drm_pci_set_busid, 601 .unload = radeon_driver_unload_kms, 602 .get_vblank_counter = radeon_get_vblank_counter_kms, 603 .enable_vblank = radeon_enable_vblank_kms, 604 .disable_vblank = radeon_disable_vblank_kms, 605 .get_vblank_timestamp = radeon_get_vblank_timestamp_kms, 606 .get_scanout_position = radeon_get_crtc_scanoutpos, 607 #if defined(CONFIG_DEBUG_FS) 608 .debugfs_init = radeon_debugfs_init, 609 .debugfs_cleanup = radeon_debugfs_cleanup, 610 #endif 611 .irq_preinstall = radeon_driver_irq_preinstall_kms, 612 .irq_postinstall = radeon_driver_irq_postinstall_kms, 613 .irq_uninstall = radeon_driver_irq_uninstall_kms, 614 .irq_handler = radeon_driver_irq_handler_kms, 615 .ioctls = radeon_ioctls_kms, 616 .gem_free_object = radeon_gem_object_free, 617 .gem_open_object = radeon_gem_object_open, 618 .gem_close_object = radeon_gem_object_close, 619 .dumb_create = radeon_mode_dumb_create, 620 .dumb_map_offset = radeon_mode_dumb_mmap, 621 .dumb_destroy = drm_gem_dumb_destroy, 622 #ifdef __NetBSD__ 623 .fops = NULL, 624 .mmap_object = &radeon_mmap_object, 625 .gem_uvm_ops = &radeon_gem_uvm_ops, 626 #else 627 .fops = &radeon_driver_kms_fops, 628 #endif 629 630 #ifndef __NetBSD__ /* XXX drm prime */ 631 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 632 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 633 .gem_prime_export = radeon_gem_prime_export, 634 .gem_prime_import = drm_gem_prime_import, 635 .gem_prime_pin = radeon_gem_prime_pin, 636 .gem_prime_unpin = radeon_gem_prime_unpin, 637 .gem_prime_res_obj = radeon_gem_prime_res_obj, 638 .gem_prime_get_sg_table = radeon_gem_prime_get_sg_table, 639 .gem_prime_import_sg_table = radeon_gem_prime_import_sg_table, 640 .gem_prime_vmap = radeon_gem_prime_vmap, 641 .gem_prime_vunmap = radeon_gem_prime_vunmap, 642 #endif 643 644 .name = DRIVER_NAME, 645 .desc = DRIVER_DESC, 646 .date = DRIVER_DATE, 647 .major = KMS_DRIVER_MAJOR, 648 .minor = KMS_DRIVER_MINOR, 649 .patchlevel = KMS_DRIVER_PATCHLEVEL, 650 }; 651 652 #ifndef __NetBSD__ 653 654 static struct drm_driver *driver; 655 static struct pci_driver *pdriver; 656 657 #ifdef CONFIG_DRM_RADEON_UMS 658 static struct pci_driver radeon_pci_driver = { 659 .name = DRIVER_NAME, 660 .id_table = pciidlist, 661 }; 662 #endif 663 664 static struct pci_driver radeon_kms_pci_driver = { 665 .name = DRIVER_NAME, 666 .id_table = pciidlist, 667 .probe = radeon_pci_probe, 668 .remove = radeon_pci_remove, 669 .driver.pm = &radeon_pm_ops, 670 }; 671 672 static int __init radeon_init(void) 673 { 674 #ifdef CONFIG_VGA_CONSOLE 675 if (vgacon_text_force() && radeon_modeset == -1) { 676 DRM_INFO("VGACON disable radeon kernel modesetting.\n"); 677 radeon_modeset = 0; 678 } 679 #endif 680 /* set to modesetting by default if not nomodeset */ 681 if (radeon_modeset == -1) 682 radeon_modeset = 1; 683 684 if (radeon_modeset == 1) { 685 DRM_INFO("radeon kernel modesetting enabled.\n"); 686 driver = &kms_driver; 687 pdriver = &radeon_kms_pci_driver; 688 driver->driver_features |= DRIVER_MODESET; 689 driver->num_ioctls = radeon_max_kms_ioctl; 690 radeon_register_atpx_handler(); 691 692 } else { 693 #ifdef CONFIG_DRM_RADEON_UMS 694 DRM_INFO("radeon userspace modesetting enabled.\n"); 695 driver = &driver_old; 696 pdriver = &radeon_pci_driver; 697 driver->driver_features &= ~DRIVER_MODESET; 698 driver->num_ioctls = radeon_max_ioctl; 699 #else 700 DRM_ERROR("No UMS support in radeon module!\n"); 701 return -EINVAL; 702 #endif 703 } 704 705 radeon_kfd_init(); 706 707 /* let modprobe override vga console setting */ 708 return drm_pci_init(driver, pdriver); 709 } 710 711 static void __exit radeon_exit(void) 712 { 713 radeon_kfd_fini(); 714 drm_pci_exit(driver, pdriver); 715 radeon_unregister_atpx_handler(); 716 } 717 718 #endif 719 720 module_init(radeon_init); 721 module_exit(radeon_exit); 722 723 MODULE_AUTHOR(DRIVER_AUTHOR); 724 MODULE_DESCRIPTION(DRIVER_DESC); 725 MODULE_LICENSE("GPL and additional rights"); 726
Indexes created Thu Oct 23 22:10:10 GMT 2025