radeon_evergreen_cs.c revision 1.2.4.2
1 /* $NetBSD: radeon_evergreen_cs.c,v 1.2.4.2 2019/06/10 22:08:26 christos Exp $ */ 2 3 /* 4 * Copyright 2010 Advanced Micro Devices, Inc. 5 * Copyright 2008 Red Hat Inc. 6 * Copyright 2009 Jerome Glisse. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: Dave Airlie 27 * Alex Deucher 28 * Jerome Glisse 29 */ 30 #include <sys/cdefs.h> 31 __KERNEL_RCSID(0, "$NetBSD: radeon_evergreen_cs.c,v 1.2.4.2 2019/06/10 22:08:26 christos Exp $"); 32 33 #include <drm/drmP.h> 34 #include "radeon.h" 35 #include "evergreend.h" 36 #include "evergreen_reg_safe.h" 37 #include "cayman_reg_safe.h" 38 39 #ifndef __NetBSD__ 40 #define MAX(a,b) (((a)>(b))?(a):(b)) 41 #define MIN(a,b) (((a)<(b))?(a):(b)) 42 #endif 43 44 #define REG_SAFE_BM_SIZE ARRAY_SIZE(evergreen_reg_safe_bm) 45 46 int r600_dma_cs_next_reloc(struct radeon_cs_parser *p, 47 struct radeon_bo_list **cs_reloc); 48 struct evergreen_cs_track { 49 u32 group_size; 50 u32 nbanks; 51 u32 npipes; 52 u32 row_size; 53 /* value we track */ 54 u32 nsamples; /* unused */ 55 struct radeon_bo *cb_color_bo[12]; 56 u32 cb_color_bo_offset[12]; 57 struct radeon_bo *cb_color_fmask_bo[8]; /* unused */ 58 struct radeon_bo *cb_color_cmask_bo[8]; /* unused */ 59 u32 cb_color_info[12]; 60 u32 cb_color_view[12]; 61 u32 cb_color_pitch[12]; 62 u32 cb_color_slice[12]; 63 u32 cb_color_slice_idx[12]; 64 u32 cb_color_attrib[12]; 65 u32 cb_color_cmask_slice[8];/* unused */ 66 u32 cb_color_fmask_slice[8];/* unused */ 67 u32 cb_target_mask; 68 u32 cb_shader_mask; /* unused */ 69 u32 vgt_strmout_config; 70 u32 vgt_strmout_buffer_config; 71 struct radeon_bo *vgt_strmout_bo[4]; 72 u32 vgt_strmout_bo_offset[4]; 73 u32 vgt_strmout_size[4]; 74 u32 db_depth_control; 75 u32 db_depth_view; 76 u32 db_depth_slice; 77 u32 db_depth_size; 78 u32 db_z_info; 79 u32 db_z_read_offset; 80 u32 db_z_write_offset; 81 struct radeon_bo *db_z_read_bo; 82 struct radeon_bo *db_z_write_bo; 83 u32 db_s_info; 84 u32 db_s_read_offset; 85 u32 db_s_write_offset; 86 struct radeon_bo *db_s_read_bo; 87 struct radeon_bo *db_s_write_bo; 88 bool sx_misc_kill_all_prims; 89 bool cb_dirty; 90 bool db_dirty; 91 bool streamout_dirty; 92 u32 htile_offset; 93 u32 htile_surface; 94 struct radeon_bo *htile_bo; 95 unsigned long indirect_draw_buffer_size; 96 const unsigned *reg_safe_bm; 97 }; 98 99 static u32 evergreen_cs_get_aray_mode(u32 tiling_flags) 100 { 101 if (tiling_flags & RADEON_TILING_MACRO) 102 return ARRAY_2D_TILED_THIN1; 103 else if (tiling_flags & RADEON_TILING_MICRO) 104 return ARRAY_1D_TILED_THIN1; 105 else 106 return ARRAY_LINEAR_GENERAL; 107 } 108 109 static u32 evergreen_cs_get_num_banks(u32 nbanks) 110 { 111 switch (nbanks) { 112 case 2: 113 return ADDR_SURF_2_BANK; 114 case 4: 115 return ADDR_SURF_4_BANK; 116 case 8: 117 default: 118 return ADDR_SURF_8_BANK; 119 case 16: 120 return ADDR_SURF_16_BANK; 121 } 122 } 123 124 static void evergreen_cs_track_init(struct evergreen_cs_track *track) 125 { 126 int i; 127 128 for (i = 0; i < 8; i++) { 129 track->cb_color_fmask_bo[i] = NULL; 130 track->cb_color_cmask_bo[i] = NULL; 131 track->cb_color_cmask_slice[i] = 0; 132 track->cb_color_fmask_slice[i] = 0; 133 } 134 135 for (i = 0; i < 12; i++) { 136 track->cb_color_bo[i] = NULL; 137 track->cb_color_bo_offset[i] = 0xFFFFFFFF; 138 track->cb_color_info[i] = 0; 139 track->cb_color_view[i] = 0xFFFFFFFF; 140 track->cb_color_pitch[i] = 0; 141 track->cb_color_slice[i] = 0xfffffff; 142 track->cb_color_slice_idx[i] = 0; 143 } 144 track->cb_target_mask = 0xFFFFFFFF; 145 track->cb_shader_mask = 0xFFFFFFFF; 146 track->cb_dirty = true; 147 148 track->db_depth_slice = 0xffffffff; 149 track->db_depth_view = 0xFFFFC000; 150 track->db_depth_size = 0xFFFFFFFF; 151 track->db_depth_control = 0xFFFFFFFF; 152 track->db_z_info = 0xFFFFFFFF; 153 track->db_z_read_offset = 0xFFFFFFFF; 154 track->db_z_write_offset = 0xFFFFFFFF; 155 track->db_z_read_bo = NULL; 156 track->db_z_write_bo = NULL; 157 track->db_s_info = 0xFFFFFFFF; 158 track->db_s_read_offset = 0xFFFFFFFF; 159 track->db_s_write_offset = 0xFFFFFFFF; 160 track->db_s_read_bo = NULL; 161 track->db_s_write_bo = NULL; 162 track->db_dirty = true; 163 track->htile_bo = NULL; 164 track->htile_offset = 0xFFFFFFFF; 165 track->htile_surface = 0; 166 167 for (i = 0; i < 4; i++) { 168 track->vgt_strmout_size[i] = 0; 169 track->vgt_strmout_bo[i] = NULL; 170 track->vgt_strmout_bo_offset[i] = 0xFFFFFFFF; 171 } 172 track->streamout_dirty = true; 173 track->sx_misc_kill_all_prims = false; 174 } 175 176 struct eg_surface { 177 /* value gathered from cs */ 178 unsigned nbx; 179 unsigned nby; 180 unsigned format; 181 unsigned mode; 182 unsigned nbanks; 183 unsigned bankw; 184 unsigned bankh; 185 unsigned tsplit; 186 unsigned mtilea; 187 unsigned nsamples; 188 /* output value */ 189 unsigned bpe; 190 unsigned layer_size; 191 unsigned palign; 192 unsigned halign; 193 unsigned long base_align; 194 }; 195 196 static int evergreen_surface_check_linear(struct radeon_cs_parser *p, 197 struct eg_surface *surf, 198 const char *prefix) 199 { 200 surf->layer_size = surf->nbx * surf->nby * surf->bpe * surf->nsamples; 201 surf->base_align = surf->bpe; 202 surf->palign = 1; 203 surf->halign = 1; 204 return 0; 205 } 206 207 static int evergreen_surface_check_linear_aligned(struct radeon_cs_parser *p, 208 struct eg_surface *surf, 209 const char *prefix) 210 { 211 struct evergreen_cs_track *track = p->track; 212 unsigned palign; 213 214 palign = MAX(64, track->group_size / surf->bpe); 215 surf->layer_size = surf->nbx * surf->nby * surf->bpe * surf->nsamples; 216 surf->base_align = track->group_size; 217 surf->palign = palign; 218 surf->halign = 1; 219 if (surf->nbx & (palign - 1)) { 220 if (prefix) { 221 dev_warn(p->dev, "%s:%d %s pitch %d invalid must be aligned with %d\n", 222 __func__, __LINE__, prefix, surf->nbx, palign); 223 } 224 return -EINVAL; 225 } 226 return 0; 227 } 228 229 static int evergreen_surface_check_1d(struct radeon_cs_parser *p, 230 struct eg_surface *surf, 231 const char *prefix) 232 { 233 struct evergreen_cs_track *track = p->track; 234 unsigned palign; 235 236 palign = track->group_size / (8 * surf->bpe * surf->nsamples); 237 palign = MAX(8, palign); 238 surf->layer_size = surf->nbx * surf->nby * surf->bpe; 239 surf->base_align = track->group_size; 240 surf->palign = palign; 241 surf->halign = 8; 242 if ((surf->nbx & (palign - 1))) { 243 if (prefix) { 244 dev_warn(p->dev, "%s:%d %s pitch %d invalid must be aligned with %d (%d %d %d)\n", 245 __func__, __LINE__, prefix, surf->nbx, palign, 246 track->group_size, surf->bpe, surf->nsamples); 247 } 248 return -EINVAL; 249 } 250 if ((surf->nby & (8 - 1))) { 251 if (prefix) { 252 dev_warn(p->dev, "%s:%d %s height %d invalid must be aligned with 8\n", 253 __func__, __LINE__, prefix, surf->nby); 254 } 255 return -EINVAL; 256 } 257 return 0; 258 } 259 260 static int evergreen_surface_check_2d(struct radeon_cs_parser *p, 261 struct eg_surface *surf, 262 const char *prefix) 263 { 264 struct evergreen_cs_track *track = p->track; 265 unsigned palign, halign, tileb, slice_pt; 266 unsigned mtile_pr, mtile_ps, mtileb; 267 268 tileb = 64 * surf->bpe * surf->nsamples; 269 slice_pt = 1; 270 if (tileb > surf->tsplit) { 271 slice_pt = tileb / surf->tsplit; 272 } 273 tileb = tileb / slice_pt; 274 /* macro tile width & height */ 275 palign = (8 * surf->bankw * track->npipes) * surf->mtilea; 276 halign = (8 * surf->bankh * surf->nbanks) / surf->mtilea; 277 mtileb = (palign / 8) * (halign / 8) * tileb; 278 mtile_pr = surf->nbx / palign; 279 mtile_ps = (mtile_pr * surf->nby) / halign; 280 surf->layer_size = mtile_ps * mtileb * slice_pt; 281 surf->base_align = (palign / 8) * (halign / 8) * tileb; 282 surf->palign = palign; 283 surf->halign = halign; 284 285 if ((surf->nbx & (palign - 1))) { 286 if (prefix) { 287 dev_warn(p->dev, "%s:%d %s pitch %d invalid must be aligned with %d\n", 288 __func__, __LINE__, prefix, surf->nbx, palign); 289 } 290 return -EINVAL; 291 } 292 if ((surf->nby & (halign - 1))) { 293 if (prefix) { 294 dev_warn(p->dev, "%s:%d %s height %d invalid must be aligned with %d\n", 295 __func__, __LINE__, prefix, surf->nby, halign); 296 } 297 return -EINVAL; 298 } 299 300 return 0; 301 } 302 303 static int evergreen_surface_check(struct radeon_cs_parser *p, 304 struct eg_surface *surf, 305 const char *prefix) 306 { 307 /* some common value computed here */ 308 surf->bpe = r600_fmt_get_blocksize(surf->format); 309 310 switch (surf->mode) { 311 case ARRAY_LINEAR_GENERAL: 312 return evergreen_surface_check_linear(p, surf, prefix); 313 case ARRAY_LINEAR_ALIGNED: 314 return evergreen_surface_check_linear_aligned(p, surf, prefix); 315 case ARRAY_1D_TILED_THIN1: 316 return evergreen_surface_check_1d(p, surf, prefix); 317 case ARRAY_2D_TILED_THIN1: 318 return evergreen_surface_check_2d(p, surf, prefix); 319 default: 320 dev_warn(p->dev, "%s:%d %s invalid array mode %d\n", 321 __func__, __LINE__, prefix, surf->mode); 322 return -EINVAL; 323 } 324 return -EINVAL; 325 } 326 327 static int evergreen_surface_value_conv_check(struct radeon_cs_parser *p, 328 struct eg_surface *surf, 329 const char *prefix) 330 { 331 switch (surf->mode) { 332 case ARRAY_2D_TILED_THIN1: 333 break; 334 case ARRAY_LINEAR_GENERAL: 335 case ARRAY_LINEAR_ALIGNED: 336 case ARRAY_1D_TILED_THIN1: 337 return 0; 338 default: 339 dev_warn(p->dev, "%s:%d %s invalid array mode %d\n", 340 __func__, __LINE__, prefix, surf->mode); 341 return -EINVAL; 342 } 343 344 switch (surf->nbanks) { 345 case 0: surf->nbanks = 2; break; 346 case 1: surf->nbanks = 4; break; 347 case 2: surf->nbanks = 8; break; 348 case 3: surf->nbanks = 16; break; 349 default: 350 dev_warn(p->dev, "%s:%d %s invalid number of banks %d\n", 351 __func__, __LINE__, prefix, surf->nbanks); 352 return -EINVAL; 353 } 354 switch (surf->bankw) { 355 case 0: surf->bankw = 1; break; 356 case 1: surf->bankw = 2; break; 357 case 2: surf->bankw = 4; break; 358 case 3: surf->bankw = 8; break; 359 default: 360 dev_warn(p->dev, "%s:%d %s invalid bankw %d\n", 361 __func__, __LINE__, prefix, surf->bankw); 362 return -EINVAL; 363 } 364 switch (surf->bankh) { 365 case 0: surf->bankh = 1; break; 366 case 1: surf->bankh = 2; break; 367 case 2: surf->bankh = 4; break; 368 case 3: surf->bankh = 8; break; 369 default: 370 dev_warn(p->dev, "%s:%d %s invalid bankh %d\n", 371 __func__, __LINE__, prefix, surf->bankh); 372 return -EINVAL; 373 } 374 switch (surf->mtilea) { 375 case 0: surf->mtilea = 1; break; 376 case 1: surf->mtilea = 2; break; 377 case 2: surf->mtilea = 4; break; 378 case 3: surf->mtilea = 8; break; 379 default: 380 dev_warn(p->dev, "%s:%d %s invalid macro tile aspect %d\n", 381 __func__, __LINE__, prefix, surf->mtilea); 382 return -EINVAL; 383 } 384 switch (surf->tsplit) { 385 case 0: surf->tsplit = 64; break; 386 case 1: surf->tsplit = 128; break; 387 case 2: surf->tsplit = 256; break; 388 case 3: surf->tsplit = 512; break; 389 case 4: surf->tsplit = 1024; break; 390 case 5: surf->tsplit = 2048; break; 391 case 6: surf->tsplit = 4096; break; 392 default: 393 dev_warn(p->dev, "%s:%d %s invalid tile split %d\n", 394 __func__, __LINE__, prefix, surf->tsplit); 395 return -EINVAL; 396 } 397 return 0; 398 } 399 400 static int evergreen_cs_track_validate_cb(struct radeon_cs_parser *p, unsigned id) 401 { 402 struct evergreen_cs_track *track = p->track; 403 struct eg_surface surf; 404 unsigned pitch, slice, mslice; 405 unsigned long offset; 406 int r; 407 408 mslice = G_028C6C_SLICE_MAX(track->cb_color_view[id]) + 1; 409 pitch = track->cb_color_pitch[id]; 410 slice = track->cb_color_slice[id]; 411 surf.nbx = (pitch + 1) * 8; 412 surf.nby = ((slice + 1) * 64) / surf.nbx; 413 surf.mode = G_028C70_ARRAY_MODE(track->cb_color_info[id]); 414 surf.format = G_028C70_FORMAT(track->cb_color_info[id]); 415 surf.tsplit = G_028C74_TILE_SPLIT(track->cb_color_attrib[id]); 416 surf.nbanks = G_028C74_NUM_BANKS(track->cb_color_attrib[id]); 417 surf.bankw = G_028C74_BANK_WIDTH(track->cb_color_attrib[id]); 418 surf.bankh = G_028C74_BANK_HEIGHT(track->cb_color_attrib[id]); 419 surf.mtilea = G_028C74_MACRO_TILE_ASPECT(track->cb_color_attrib[id]); 420 surf.nsamples = 1; 421 422 if (!r600_fmt_is_valid_color(surf.format)) { 423 dev_warn(p->dev, "%s:%d cb invalid format %d for %d (0x%08x)\n", 424 __func__, __LINE__, surf.format, 425 id, track->cb_color_info[id]); 426 return -EINVAL; 427 } 428 429 r = evergreen_surface_value_conv_check(p, &surf, "cb"); 430 if (r) { 431 return r; 432 } 433 434 r = evergreen_surface_check(p, &surf, "cb"); 435 if (r) { 436 dev_warn(p->dev, "%s:%d cb[%d] invalid (0x%08x 0x%08x 0x%08x 0x%08x)\n", 437 __func__, __LINE__, id, track->cb_color_pitch[id], 438 track->cb_color_slice[id], track->cb_color_attrib[id], 439 track->cb_color_info[id]); 440 return r; 441 } 442 443 offset = track->cb_color_bo_offset[id] << 8; 444 if (offset & (surf.base_align - 1)) { 445 dev_warn(p->dev, "%s:%d cb[%d] bo base %ld not aligned with %ld\n", 446 __func__, __LINE__, id, offset, surf.base_align); 447 return -EINVAL; 448 } 449 450 offset += surf.layer_size * mslice; 451 if (offset > radeon_bo_size(track->cb_color_bo[id])) { 452 /* old ddx are broken they allocate bo with w*h*bpp but 453 * program slice with ALIGN(h, 8), catch this and patch 454 * command stream. 455 */ 456 if (!surf.mode) { 457 uint32_t *ib = p->ib.ptr; 458 unsigned long tmp, nby, bsize, size, vmin = 0; 459 460 /* find the height the ddx wants */ 461 if (surf.nby > 8) { 462 vmin = surf.nby - 8; 463 } 464 bsize = radeon_bo_size(track->cb_color_bo[id]); 465 tmp = track->cb_color_bo_offset[id] << 8; 466 for (nby = surf.nby; nby > vmin; nby--) { 467 size = nby * surf.nbx * surf.bpe * surf.nsamples; 468 if ((tmp + size * mslice) <= bsize) { 469 break; 470 } 471 } 472 if (nby > vmin) { 473 surf.nby = nby; 474 slice = ((nby * surf.nbx) / 64) - 1; 475 if (!evergreen_surface_check(p, &surf, "cb")) { 476 /* check if this one works */ 477 tmp += surf.layer_size * mslice; 478 if (tmp <= bsize) { 479 ib[track->cb_color_slice_idx[id]] = slice; 480 goto old_ddx_ok; 481 } 482 } 483 } 484 } 485 dev_warn(p->dev, "%s:%d cb[%d] bo too small (layer size %d, " 486 "offset %d, max layer %d, bo size %ld, slice %d)\n", 487 __func__, __LINE__, id, surf.layer_size, 488 track->cb_color_bo_offset[id] << 8, mslice, 489 radeon_bo_size(track->cb_color_bo[id]), slice); 490 dev_warn(p->dev, "%s:%d problematic surf: (%d %d) (%d %d %d %d %d %d %d)\n", 491 __func__, __LINE__, surf.nbx, surf.nby, 492 surf.mode, surf.bpe, surf.nsamples, 493 surf.bankw, surf.bankh, 494 surf.tsplit, surf.mtilea); 495 return -EINVAL; 496 } 497 old_ddx_ok: 498 499 return 0; 500 } 501 502 static int evergreen_cs_track_validate_htile(struct radeon_cs_parser *p, 503 unsigned nbx, unsigned nby) 504 { 505 struct evergreen_cs_track *track = p->track; 506 unsigned long size; 507 508 if (track->htile_bo == NULL) { 509 dev_warn(p->dev, "%s:%d htile enabled without htile surface 0x%08x\n", 510 __func__, __LINE__, track->db_z_info); 511 return -EINVAL; 512 } 513 514 if (G_028ABC_LINEAR(track->htile_surface)) { 515 /* pitch must be 16 htiles aligned == 16 * 8 pixel aligned */ 516 nbx = round_up(nbx, 16 * 8); 517 /* height is npipes htiles aligned == npipes * 8 pixel aligned */ 518 nby = round_up(nby, track->npipes * 8); 519 } else { 520 /* always assume 8x8 htile */ 521 /* align is htile align * 8, htile align vary according to 522 * number of pipe and tile width and nby 523 */ 524 switch (track->npipes) { 525 case 8: 526 /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/ 527 nbx = round_up(nbx, 64 * 8); 528 nby = round_up(nby, 64 * 8); 529 break; 530 case 4: 531 /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/ 532 nbx = round_up(nbx, 64 * 8); 533 nby = round_up(nby, 32 * 8); 534 break; 535 case 2: 536 /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/ 537 nbx = round_up(nbx, 32 * 8); 538 nby = round_up(nby, 32 * 8); 539 break; 540 case 1: 541 /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/ 542 nbx = round_up(nbx, 32 * 8); 543 nby = round_up(nby, 16 * 8); 544 break; 545 default: 546 dev_warn(p->dev, "%s:%d invalid num pipes %d\n", 547 __func__, __LINE__, track->npipes); 548 return -EINVAL; 549 } 550 } 551 /* compute number of htile */ 552 nbx = nbx >> 3; 553 nby = nby >> 3; 554 /* size must be aligned on npipes * 2K boundary */ 555 size = roundup(nbx * nby * 4, track->npipes * (2 << 10)); 556 size += track->htile_offset; 557 558 if (!track->htile_bo) { 559 dev_warn(p->dev, "%s:%d htile_bo not set", __func__, __LINE__); 560 return -EINVAL; 561 } 562 if (size > radeon_bo_size(track->htile_bo)) { 563 dev_warn(p->dev, "%s:%d htile surface too small %ld for %ld (%d %d)\n", 564 __func__, __LINE__, radeon_bo_size(track->htile_bo), 565 size, nbx, nby); 566 return -EINVAL; 567 } 568 return 0; 569 } 570 571 static int evergreen_cs_track_validate_stencil(struct radeon_cs_parser *p) 572 { 573 struct evergreen_cs_track *track = p->track; 574 struct eg_surface surf; 575 unsigned pitch, slice, mslice; 576 unsigned long offset; 577 int r; 578 579 mslice = G_028008_SLICE_MAX(track->db_depth_view) + 1; 580 pitch = G_028058_PITCH_TILE_MAX(track->db_depth_size); 581 slice = track->db_depth_slice; 582 surf.nbx = (pitch + 1) * 8; 583 surf.nby = ((slice + 1) * 64) / surf.nbx; 584 surf.mode = G_028040_ARRAY_MODE(track->db_z_info); 585 surf.format = G_028044_FORMAT(track->db_s_info); 586 surf.tsplit = G_028044_TILE_SPLIT(track->db_s_info); 587 surf.nbanks = G_028040_NUM_BANKS(track->db_z_info); 588 surf.bankw = G_028040_BANK_WIDTH(track->db_z_info); 589 surf.bankh = G_028040_BANK_HEIGHT(track->db_z_info); 590 surf.mtilea = G_028040_MACRO_TILE_ASPECT(track->db_z_info); 591 surf.nsamples = 1; 592 593 if (surf.format != 1) { 594 dev_warn(p->dev, "%s:%d stencil invalid format %d\n", 595 __func__, __LINE__, surf.format); 596 return -EINVAL; 597 } 598 /* replace by color format so we can use same code */ 599 surf.format = V_028C70_COLOR_8; 600 601 r = evergreen_surface_value_conv_check(p, &surf, "stencil"); 602 if (r) { 603 return r; 604 } 605 606 r = evergreen_surface_check(p, &surf, NULL); 607 if (r) { 608 /* old userspace doesn't compute proper depth/stencil alignment 609 * check that alignment against a bigger byte per elements and 610 * only report if that alignment is wrong too. 611 */ 612 surf.format = V_028C70_COLOR_8_8_8_8; 613 r = evergreen_surface_check(p, &surf, "stencil"); 614 if (r) { 615 dev_warn(p->dev, "%s:%d stencil invalid (0x%08x 0x%08x 0x%08x 0x%08x)\n", 616 __func__, __LINE__, track->db_depth_size, 617 track->db_depth_slice, track->db_s_info, track->db_z_info); 618 } 619 return r; 620 } 621 622 offset = track->db_s_read_offset << 8; 623 if (offset & (surf.base_align - 1)) { 624 dev_warn(p->dev, "%s:%d stencil read bo base %ld not aligned with %ld\n", 625 __func__, __LINE__, offset, surf.base_align); 626 return -EINVAL; 627 } 628 offset += surf.layer_size * mslice; 629 if (!track->db_s_read_bo) { 630 dev_warn(p->dev, "%s:%d db_s_read_bo not set", __func__, __LINE__); 631 return -EINVAL; 632 } 633 if (offset > radeon_bo_size(track->db_s_read_bo)) { 634 dev_warn(p->dev, "%s:%d stencil read bo too small (layer size %d, " 635 "offset %ld, max layer %d, bo size %ld)\n", 636 __func__, __LINE__, surf.layer_size, 637 (unsigned long)track->db_s_read_offset << 8, mslice, 638 radeon_bo_size(track->db_s_read_bo)); 639 dev_warn(p->dev, "%s:%d stencil invalid (0x%08x 0x%08x 0x%08x 0x%08x)\n", 640 __func__, __LINE__, track->db_depth_size, 641 track->db_depth_slice, track->db_s_info, track->db_z_info); 642 return -EINVAL; 643 } 644 645 offset = track->db_s_write_offset << 8; 646 if (offset & (surf.base_align - 1)) { 647 dev_warn(p->dev, "%s:%d stencil write bo base %ld not aligned with %ld\n", 648 __func__, __LINE__, offset, surf.base_align); 649 return -EINVAL; 650 } 651 offset += surf.layer_size * mslice; 652 if (!track->db_s_write_bo) { 653 dev_warn(p->dev, "%s:%d db_s_write_bo not set", __func__, __LINE__); 654 return -EINVAL; 655 } 656 if (offset > radeon_bo_size(track->db_s_write_bo)) { 657 dev_warn(p->dev, "%s:%d stencil write bo too small (layer size %d, " 658 "offset %ld, max layer %d, bo size %ld)\n", 659 __func__, __LINE__, surf.layer_size, 660 (unsigned long)track->db_s_write_offset << 8, mslice, 661 radeon_bo_size(track->db_s_write_bo)); 662 return -EINVAL; 663 } 664 665 /* hyperz */ 666 if (G_028040_TILE_SURFACE_ENABLE(track->db_z_info)) { 667 r = evergreen_cs_track_validate_htile(p, surf.nbx, surf.nby); 668 if (r) { 669 return r; 670 } 671 } 672 673 return 0; 674 } 675 676 static int evergreen_cs_track_validate_depth(struct radeon_cs_parser *p) 677 { 678 struct evergreen_cs_track *track = p->track; 679 struct eg_surface surf; 680 unsigned pitch, slice, mslice; 681 unsigned long offset; 682 int r; 683 684 mslice = G_028008_SLICE_MAX(track->db_depth_view) + 1; 685 pitch = G_028058_PITCH_TILE_MAX(track->db_depth_size); 686 slice = track->db_depth_slice; 687 surf.nbx = (pitch + 1) * 8; 688 surf.nby = ((slice + 1) * 64) / surf.nbx; 689 surf.mode = G_028040_ARRAY_MODE(track->db_z_info); 690 surf.format = G_028040_FORMAT(track->db_z_info); 691 surf.tsplit = G_028040_TILE_SPLIT(track->db_z_info); 692 surf.nbanks = G_028040_NUM_BANKS(track->db_z_info); 693 surf.bankw = G_028040_BANK_WIDTH(track->db_z_info); 694 surf.bankh = G_028040_BANK_HEIGHT(track->db_z_info); 695 surf.mtilea = G_028040_MACRO_TILE_ASPECT(track->db_z_info); 696 surf.nsamples = 1; 697 698 switch (surf.format) { 699 case V_028040_Z_16: 700 surf.format = V_028C70_COLOR_16; 701 break; 702 case V_028040_Z_24: 703 case V_028040_Z_32_FLOAT: 704 surf.format = V_028C70_COLOR_8_8_8_8; 705 break; 706 default: 707 dev_warn(p->dev, "%s:%d depth invalid format %d\n", 708 __func__, __LINE__, surf.format); 709 return -EINVAL; 710 } 711 712 r = evergreen_surface_value_conv_check(p, &surf, "depth"); 713 if (r) { 714 dev_warn(p->dev, "%s:%d depth invalid (0x%08x 0x%08x 0x%08x)\n", 715 __func__, __LINE__, track->db_depth_size, 716 track->db_depth_slice, track->db_z_info); 717 return r; 718 } 719 720 r = evergreen_surface_check(p, &surf, "depth"); 721 if (r) { 722 dev_warn(p->dev, "%s:%d depth invalid (0x%08x 0x%08x 0x%08x)\n", 723 __func__, __LINE__, track->db_depth_size, 724 track->db_depth_slice, track->db_z_info); 725 return r; 726 } 727 728 offset = track->db_z_read_offset << 8; 729 if (offset & (surf.base_align - 1)) { 730 dev_warn(p->dev, "%s:%d stencil read bo base %ld not aligned with %ld\n", 731 __func__, __LINE__, offset, surf.base_align); 732 return -EINVAL; 733 } 734 offset += surf.layer_size * mslice; 735 if (!track->db_z_read_bo) { 736 dev_warn(p->dev, "%s:%d db_z_read_bo not set", __func__, __LINE__); 737 return -EINVAL; 738 } 739 if (offset > radeon_bo_size(track->db_z_read_bo)) { 740 dev_warn(p->dev, "%s:%d depth read bo too small (layer size %d, " 741 "offset %ld, max layer %d, bo size %ld)\n", 742 __func__, __LINE__, surf.layer_size, 743 (unsigned long)track->db_z_read_offset << 8, mslice, 744 radeon_bo_size(track->db_z_read_bo)); 745 return -EINVAL; 746 } 747 748 offset = track->db_z_write_offset << 8; 749 if (offset & (surf.base_align - 1)) { 750 dev_warn(p->dev, "%s:%d stencil write bo base %ld not aligned with %ld\n", 751 __func__, __LINE__, offset, surf.base_align); 752 return -EINVAL; 753 } 754 offset += surf.layer_size * mslice; 755 if (!track->db_z_write_bo) { 756 dev_warn(p->dev, "%s:%d db_z_write_bo not set", __func__, __LINE__); 757 return -EINVAL; 758 } 759 if (offset > radeon_bo_size(track->db_z_write_bo)) { 760 dev_warn(p->dev, "%s:%d depth write bo too small (layer size %d, " 761 "offset %ld, max layer %d, bo size %ld)\n", 762 __func__, __LINE__, surf.layer_size, 763 (unsigned long)track->db_z_write_offset << 8, mslice, 764 radeon_bo_size(track->db_z_write_bo)); 765 return -EINVAL; 766 } 767 768 /* hyperz */ 769 if (G_028040_TILE_SURFACE_ENABLE(track->db_z_info)) { 770 r = evergreen_cs_track_validate_htile(p, surf.nbx, surf.nby); 771 if (r) { 772 return r; 773 } 774 } 775 776 return 0; 777 } 778 779 static int evergreen_cs_track_validate_texture(struct radeon_cs_parser *p, 780 struct radeon_bo *texture, 781 struct radeon_bo *mipmap, 782 unsigned idx) 783 { 784 struct eg_surface surf; 785 unsigned long toffset, moffset; 786 unsigned dim, llevel, mslice, width, height, depth, i; 787 u32 texdw[8]; 788 int r; 789 790 texdw[0] = radeon_get_ib_value(p, idx + 0); 791 texdw[1] = radeon_get_ib_value(p, idx + 1); 792 texdw[2] = radeon_get_ib_value(p, idx + 2); 793 texdw[3] = radeon_get_ib_value(p, idx + 3); 794 texdw[4] = radeon_get_ib_value(p, idx + 4); 795 texdw[5] = radeon_get_ib_value(p, idx + 5); 796 texdw[6] = radeon_get_ib_value(p, idx + 6); 797 texdw[7] = radeon_get_ib_value(p, idx + 7); 798 dim = G_030000_DIM(texdw[0]); 799 llevel = G_030014_LAST_LEVEL(texdw[5]); 800 mslice = G_030014_LAST_ARRAY(texdw[5]) + 1; 801 width = G_030000_TEX_WIDTH(texdw[0]) + 1; 802 height = G_030004_TEX_HEIGHT(texdw[1]) + 1; 803 depth = G_030004_TEX_DEPTH(texdw[1]) + 1; 804 surf.format = G_03001C_DATA_FORMAT(texdw[7]); 805 surf.nbx = (G_030000_PITCH(texdw[0]) + 1) * 8; 806 surf.nbx = r600_fmt_get_nblocksx(surf.format, surf.nbx); 807 surf.nby = r600_fmt_get_nblocksy(surf.format, height); 808 surf.mode = G_030004_ARRAY_MODE(texdw[1]); 809 surf.tsplit = G_030018_TILE_SPLIT(texdw[6]); 810 surf.nbanks = G_03001C_NUM_BANKS(texdw[7]); 811 surf.bankw = G_03001C_BANK_WIDTH(texdw[7]); 812 surf.bankh = G_03001C_BANK_HEIGHT(texdw[7]); 813 surf.mtilea = G_03001C_MACRO_TILE_ASPECT(texdw[7]); 814 surf.nsamples = 1; 815 toffset = texdw[2] << 8; 816 moffset = texdw[3] << 8; 817 818 if (!r600_fmt_is_valid_texture(surf.format, p->family)) { 819 dev_warn(p->dev, "%s:%d texture invalid format %d\n", 820 __func__, __LINE__, surf.format); 821 return -EINVAL; 822 } 823 switch (dim) { 824 case V_030000_SQ_TEX_DIM_1D: 825 case V_030000_SQ_TEX_DIM_2D: 826 case V_030000_SQ_TEX_DIM_CUBEMAP: 827 case V_030000_SQ_TEX_DIM_1D_ARRAY: 828 case V_030000_SQ_TEX_DIM_2D_ARRAY: 829 depth = 1; 830 break; 831 case V_030000_SQ_TEX_DIM_2D_MSAA: 832 case V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA: 833 surf.nsamples = 1 << llevel; 834 llevel = 0; 835 depth = 1; 836 break; 837 case V_030000_SQ_TEX_DIM_3D: 838 break; 839 default: 840 dev_warn(p->dev, "%s:%d texture invalid dimension %d\n", 841 __func__, __LINE__, dim); 842 return -EINVAL; 843 } 844 845 r = evergreen_surface_value_conv_check(p, &surf, "texture"); 846 if (r) { 847 return r; 848 } 849 850 /* align height */ 851 evergreen_surface_check(p, &surf, NULL); 852 #ifdef __NetBSD__ /* XXX ALIGN means something else */ 853 surf.nby = round_up(surf.nby, surf.halign); 854 #else 855 surf.nby = ALIGN(surf.nby, surf.halign); 856 #endif 857 858 r = evergreen_surface_check(p, &surf, "texture"); 859 if (r) { 860 dev_warn(p->dev, "%s:%d texture invalid 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", 861 __func__, __LINE__, texdw[0], texdw[1], texdw[4], 862 texdw[5], texdw[6], texdw[7]); 863 return r; 864 } 865 866 /* check texture size */ 867 if (toffset & (surf.base_align - 1)) { 868 dev_warn(p->dev, "%s:%d texture bo base %ld not aligned with %ld\n", 869 __func__, __LINE__, toffset, surf.base_align); 870 return -EINVAL; 871 } 872 if (surf.nsamples <= 1 && moffset & (surf.base_align - 1)) { 873 dev_warn(p->dev, "%s:%d mipmap bo base %ld not aligned with %ld\n", 874 __func__, __LINE__, moffset, surf.base_align); 875 return -EINVAL; 876 } 877 if (dim == SQ_TEX_DIM_3D) { 878 toffset += surf.layer_size * depth; 879 } else { 880 toffset += surf.layer_size * mslice; 881 } 882 if (toffset > radeon_bo_size(texture)) { 883 dev_warn(p->dev, "%s:%d texture bo too small (layer size %d, " 884 "offset %ld, max layer %d, depth %d, bo size %ld) (%d %d)\n", 885 __func__, __LINE__, surf.layer_size, 886 (unsigned long)texdw[2] << 8, mslice, 887 depth, radeon_bo_size(texture), 888 surf.nbx, surf.nby); 889 return -EINVAL; 890 } 891 892 if (!mipmap) { 893 if (llevel) { 894 dev_warn(p->dev, "%s:%i got NULL MIP_ADDRESS relocation\n", 895 __func__, __LINE__); 896 return -EINVAL; 897 } else { 898 return 0; /* everything's ok */ 899 } 900 } 901 902 /* check mipmap size */ 903 for (i = 1; i <= llevel; i++) { 904 unsigned w, h, d; 905 906 w = r600_mip_minify(width, i); 907 h = r600_mip_minify(height, i); 908 d = r600_mip_minify(depth, i); 909 surf.nbx = r600_fmt_get_nblocksx(surf.format, w); 910 surf.nby = r600_fmt_get_nblocksy(surf.format, h); 911 912 switch (surf.mode) { 913 case ARRAY_2D_TILED_THIN1: 914 if (surf.nbx < surf.palign || surf.nby < surf.halign) { 915 surf.mode = ARRAY_1D_TILED_THIN1; 916 } 917 /* recompute alignment */ 918 evergreen_surface_check(p, &surf, NULL); 919 break; 920 case ARRAY_LINEAR_GENERAL: 921 case ARRAY_LINEAR_ALIGNED: 922 case ARRAY_1D_TILED_THIN1: 923 break; 924 default: 925 dev_warn(p->dev, "%s:%d invalid array mode %d\n", 926 __func__, __LINE__, surf.mode); 927 return -EINVAL; 928 } 929 #ifdef __NetBSD__ /* XXX ALIGN means something else. */ 930 surf.nbx = round_up(surf.nbx, surf.palign); 931 surf.nby = round_up(surf.nby, surf.halign); 932 #else 933 surf.nbx = ALIGN(surf.nbx, surf.palign); 934 surf.nby = ALIGN(surf.nby, surf.halign); 935 #endif 936 937 r = evergreen_surface_check(p, &surf, "mipmap"); 938 if (r) { 939 return r; 940 } 941 942 if (dim == SQ_TEX_DIM_3D) { 943 moffset += surf.layer_size * d; 944 } else { 945 moffset += surf.layer_size * mslice; 946 } 947 if (moffset > radeon_bo_size(mipmap)) { 948 dev_warn(p->dev, "%s:%d mipmap [%d] bo too small (layer size %d, " 949 "offset %ld, coffset %ld, max layer %d, depth %d, " 950 "bo size %ld) level0 (%d %d %d)\n", 951 __func__, __LINE__, i, surf.layer_size, 952 (unsigned long)texdw[3] << 8, moffset, mslice, 953 d, radeon_bo_size(mipmap), 954 width, height, depth); 955 dev_warn(p->dev, "%s:%d problematic surf: (%d %d) (%d %d %d %d %d %d %d)\n", 956 __func__, __LINE__, surf.nbx, surf.nby, 957 surf.mode, surf.bpe, surf.nsamples, 958 surf.bankw, surf.bankh, 959 surf.tsplit, surf.mtilea); 960 return -EINVAL; 961 } 962 } 963 964 return 0; 965 } 966 967 static int evergreen_cs_track_check(struct radeon_cs_parser *p) 968 { 969 struct evergreen_cs_track *track = p->track; 970 unsigned tmp, i; 971 int r; 972 unsigned buffer_mask = 0; 973 974 /* check streamout */ 975 if (track->streamout_dirty && track->vgt_strmout_config) { 976 for (i = 0; i < 4; i++) { 977 if (track->vgt_strmout_config & (1 << i)) { 978 buffer_mask |= (track->vgt_strmout_buffer_config >> (i * 4)) & 0xf; 979 } 980 } 981 982 for (i = 0; i < 4; i++) { 983 if (buffer_mask & (1 << i)) { 984 if (track->vgt_strmout_bo[i]) { 985 u64 offset = (u64)track->vgt_strmout_bo_offset[i] + 986 (u64)track->vgt_strmout_size[i]; 987 if (offset > radeon_bo_size(track->vgt_strmout_bo[i])) { 988 DRM_ERROR("streamout %d bo too small: 0x%"PRIx64", 0x%lx\n", 989 i, offset, 990 radeon_bo_size(track->vgt_strmout_bo[i])); 991 return -EINVAL; 992 } 993 } else { 994 dev_warn(p->dev, "No buffer for streamout %d\n", i); 995 return -EINVAL; 996 } 997 } 998 } 999 track->streamout_dirty = false; 1000 } 1001 1002 if (track->sx_misc_kill_all_prims) 1003 return 0; 1004 1005 /* check that we have a cb for each enabled target 1006 */ 1007 if (track->cb_dirty) { 1008 tmp = track->cb_target_mask; 1009 for (i = 0; i < 8; i++) { 1010 u32 format = G_028C70_FORMAT(track->cb_color_info[i]); 1011 1012 if (format != V_028C70_COLOR_INVALID && 1013 (tmp >> (i * 4)) & 0xF) { 1014 /* at least one component is enabled */ 1015 if (track->cb_color_bo[i] == NULL) { 1016 dev_warn(p->dev, "%s:%d mask 0x%08X | 0x%08X no cb for %d\n", 1017 __func__, __LINE__, track->cb_target_mask, track->cb_shader_mask, i); 1018 return -EINVAL; 1019 } 1020 /* check cb */ 1021 r = evergreen_cs_track_validate_cb(p, i); 1022 if (r) { 1023 return r; 1024 } 1025 } 1026 } 1027 track->cb_dirty = false; 1028 } 1029 1030 if (track->db_dirty) { 1031 /* Check stencil buffer */ 1032 if (G_028044_FORMAT(track->db_s_info) != V_028044_STENCIL_INVALID && 1033 G_028800_STENCIL_ENABLE(track->db_depth_control)) { 1034 r = evergreen_cs_track_validate_stencil(p); 1035 if (r) 1036 return r; 1037 } 1038 /* Check depth buffer */ 1039 if (G_028040_FORMAT(track->db_z_info) != V_028040_Z_INVALID && 1040 G_028800_Z_ENABLE(track->db_depth_control)) { 1041 r = evergreen_cs_track_validate_depth(p); 1042 if (r) 1043 return r; 1044 } 1045 track->db_dirty = false; 1046 } 1047 1048 return 0; 1049 } 1050 1051 /** 1052 * evergreen_cs_packet_parse_vline() - parse userspace VLINE packet 1053 * @parser: parser structure holding parsing context. 1054 * 1055 * This is an Evergreen(+)-specific function for parsing VLINE packets. 1056 * Real work is done by r600_cs_common_vline_parse function. 1057 * Here we just set up ASIC-specific register table and call 1058 * the common implementation function. 1059 */ 1060 static int evergreen_cs_packet_parse_vline(struct radeon_cs_parser *p) 1061 { 1062 1063 static uint32_t vline_start_end[6] = { 1064 EVERGREEN_VLINE_START_END + EVERGREEN_CRTC0_REGISTER_OFFSET, 1065 EVERGREEN_VLINE_START_END + EVERGREEN_CRTC1_REGISTER_OFFSET, 1066 EVERGREEN_VLINE_START_END + EVERGREEN_CRTC2_REGISTER_OFFSET, 1067 EVERGREEN_VLINE_START_END + EVERGREEN_CRTC3_REGISTER_OFFSET, 1068 EVERGREEN_VLINE_START_END + EVERGREEN_CRTC4_REGISTER_OFFSET, 1069 EVERGREEN_VLINE_START_END + EVERGREEN_CRTC5_REGISTER_OFFSET 1070 }; 1071 static uint32_t vline_status[6] = { 1072 EVERGREEN_VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, 1073 EVERGREEN_VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, 1074 EVERGREEN_VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, 1075 EVERGREEN_VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, 1076 EVERGREEN_VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, 1077 EVERGREEN_VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET 1078 }; 1079 1080 return r600_cs_common_vline_parse(p, vline_start_end, vline_status); 1081 } 1082 1083 static int evergreen_packet0_check(struct radeon_cs_parser *p, 1084 struct radeon_cs_packet *pkt, 1085 unsigned idx, unsigned reg) 1086 { 1087 int r; 1088 1089 switch (reg) { 1090 case EVERGREEN_VLINE_START_END: 1091 r = evergreen_cs_packet_parse_vline(p); 1092 if (r) { 1093 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1094 idx, reg); 1095 return r; 1096 } 1097 break; 1098 default: 1099 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n", 1100 reg, idx); 1101 return -EINVAL; 1102 } 1103 return 0; 1104 } 1105 1106 static int evergreen_cs_parse_packet0(struct radeon_cs_parser *p, 1107 struct radeon_cs_packet *pkt) 1108 { 1109 unsigned reg, i; 1110 unsigned idx; 1111 int r; 1112 1113 idx = pkt->idx + 1; 1114 reg = pkt->reg; 1115 for (i = 0; i <= pkt->count; i++, idx++, reg += 4) { 1116 r = evergreen_packet0_check(p, pkt, idx, reg); 1117 if (r) { 1118 return r; 1119 } 1120 } 1121 return 0; 1122 } 1123 1124 /** 1125 * evergreen_cs_handle_reg() - process registers that need special handling. 1126 * @parser: parser structure holding parsing context 1127 * @reg: register we are testing 1128 * @idx: index into the cs buffer 1129 */ 1130 static int evergreen_cs_handle_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) 1131 { 1132 struct evergreen_cs_track *track = (struct evergreen_cs_track *)p->track; 1133 struct radeon_bo_list *reloc; 1134 u32 tmp, *ib; 1135 int r; 1136 1137 ib = p->ib.ptr; 1138 switch (reg) { 1139 /* force following reg to 0 in an attempt to disable out buffer 1140 * which will need us to better understand how it works to perform 1141 * security check on it (Jerome) 1142 */ 1143 case SQ_ESGS_RING_SIZE: 1144 case SQ_GSVS_RING_SIZE: 1145 case SQ_ESTMP_RING_SIZE: 1146 case SQ_GSTMP_RING_SIZE: 1147 case SQ_HSTMP_RING_SIZE: 1148 case SQ_LSTMP_RING_SIZE: 1149 case SQ_PSTMP_RING_SIZE: 1150 case SQ_VSTMP_RING_SIZE: 1151 case SQ_ESGS_RING_ITEMSIZE: 1152 case SQ_ESTMP_RING_ITEMSIZE: 1153 case SQ_GSTMP_RING_ITEMSIZE: 1154 case SQ_GSVS_RING_ITEMSIZE: 1155 case SQ_GS_VERT_ITEMSIZE: 1156 case SQ_GS_VERT_ITEMSIZE_1: 1157 case SQ_GS_VERT_ITEMSIZE_2: 1158 case SQ_GS_VERT_ITEMSIZE_3: 1159 case SQ_GSVS_RING_OFFSET_1: 1160 case SQ_GSVS_RING_OFFSET_2: 1161 case SQ_GSVS_RING_OFFSET_3: 1162 case SQ_HSTMP_RING_ITEMSIZE: 1163 case SQ_LSTMP_RING_ITEMSIZE: 1164 case SQ_PSTMP_RING_ITEMSIZE: 1165 case SQ_VSTMP_RING_ITEMSIZE: 1166 case VGT_TF_RING_SIZE: 1167 /* get value to populate the IB don't remove */ 1168 /*tmp =radeon_get_ib_value(p, idx); 1169 ib[idx] = 0;*/ 1170 break; 1171 case SQ_ESGS_RING_BASE: 1172 case SQ_GSVS_RING_BASE: 1173 case SQ_ESTMP_RING_BASE: 1174 case SQ_GSTMP_RING_BASE: 1175 case SQ_HSTMP_RING_BASE: 1176 case SQ_LSTMP_RING_BASE: 1177 case SQ_PSTMP_RING_BASE: 1178 case SQ_VSTMP_RING_BASE: 1179 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1180 if (r) { 1181 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1182 "0x%04X\n", reg); 1183 return -EINVAL; 1184 } 1185 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); 1186 break; 1187 case DB_DEPTH_CONTROL: 1188 track->db_depth_control = radeon_get_ib_value(p, idx); 1189 track->db_dirty = true; 1190 break; 1191 case CAYMAN_DB_EQAA: 1192 if (p->rdev->family < CHIP_CAYMAN) { 1193 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1194 "0x%04X\n", reg); 1195 return -EINVAL; 1196 } 1197 break; 1198 case CAYMAN_DB_DEPTH_INFO: 1199 if (p->rdev->family < CHIP_CAYMAN) { 1200 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1201 "0x%04X\n", reg); 1202 return -EINVAL; 1203 } 1204 break; 1205 case DB_Z_INFO: 1206 track->db_z_info = radeon_get_ib_value(p, idx); 1207 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 1208 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1209 if (r) { 1210 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1211 "0x%04X\n", reg); 1212 return -EINVAL; 1213 } 1214 ib[idx] &= ~Z_ARRAY_MODE(0xf); 1215 track->db_z_info &= ~Z_ARRAY_MODE(0xf); 1216 ib[idx] |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); 1217 track->db_z_info |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); 1218 if (reloc->tiling_flags & RADEON_TILING_MACRO) { 1219 unsigned bankw, bankh, mtaspect, tile_split; 1220 1221 evergreen_tiling_fields(reloc->tiling_flags, 1222 &bankw, &bankh, &mtaspect, 1223 &tile_split); 1224 ib[idx] |= DB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks)); 1225 ib[idx] |= DB_TILE_SPLIT(tile_split) | 1226 DB_BANK_WIDTH(bankw) | 1227 DB_BANK_HEIGHT(bankh) | 1228 DB_MACRO_TILE_ASPECT(mtaspect); 1229 } 1230 } 1231 track->db_dirty = true; 1232 break; 1233 case DB_STENCIL_INFO: 1234 track->db_s_info = radeon_get_ib_value(p, idx); 1235 track->db_dirty = true; 1236 break; 1237 case DB_DEPTH_VIEW: 1238 track->db_depth_view = radeon_get_ib_value(p, idx); 1239 track->db_dirty = true; 1240 break; 1241 case DB_DEPTH_SIZE: 1242 track->db_depth_size = radeon_get_ib_value(p, idx); 1243 track->db_dirty = true; 1244 break; 1245 case R_02805C_DB_DEPTH_SLICE: 1246 track->db_depth_slice = radeon_get_ib_value(p, idx); 1247 track->db_dirty = true; 1248 break; 1249 case DB_Z_READ_BASE: 1250 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1251 if (r) { 1252 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1253 "0x%04X\n", reg); 1254 return -EINVAL; 1255 } 1256 track->db_z_read_offset = radeon_get_ib_value(p, idx); 1257 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); 1258 track->db_z_read_bo = reloc->robj; 1259 track->db_dirty = true; 1260 break; 1261 case DB_Z_WRITE_BASE: 1262 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1263 if (r) { 1264 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1265 "0x%04X\n", reg); 1266 return -EINVAL; 1267 } 1268 track->db_z_write_offset = radeon_get_ib_value(p, idx); 1269 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); 1270 track->db_z_write_bo = reloc->robj; 1271 track->db_dirty = true; 1272 break; 1273 case DB_STENCIL_READ_BASE: 1274 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1275 if (r) { 1276 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1277 "0x%04X\n", reg); 1278 return -EINVAL; 1279 } 1280 track->db_s_read_offset = radeon_get_ib_value(p, idx); 1281 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); 1282 track->db_s_read_bo = reloc->robj; 1283 track->db_dirty = true; 1284 break; 1285 case DB_STENCIL_WRITE_BASE: 1286 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1287 if (r) { 1288 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1289 "0x%04X\n", reg); 1290 return -EINVAL; 1291 } 1292 track->db_s_write_offset = radeon_get_ib_value(p, idx); 1293 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); 1294 track->db_s_write_bo = reloc->robj; 1295 track->db_dirty = true; 1296 break; 1297 case VGT_STRMOUT_CONFIG: 1298 track->vgt_strmout_config = radeon_get_ib_value(p, idx); 1299 track->streamout_dirty = true; 1300 break; 1301 case VGT_STRMOUT_BUFFER_CONFIG: 1302 track->vgt_strmout_buffer_config = radeon_get_ib_value(p, idx); 1303 track->streamout_dirty = true; 1304 break; 1305 case VGT_STRMOUT_BUFFER_BASE_0: 1306 case VGT_STRMOUT_BUFFER_BASE_1: 1307 case VGT_STRMOUT_BUFFER_BASE_2: 1308 case VGT_STRMOUT_BUFFER_BASE_3: 1309 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1310 if (r) { 1311 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1312 "0x%04X\n", reg); 1313 return -EINVAL; 1314 } 1315 tmp = (reg - VGT_STRMOUT_BUFFER_BASE_0) / 16; 1316 track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8; 1317 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); 1318 track->vgt_strmout_bo[tmp] = reloc->robj; 1319 track->streamout_dirty = true; 1320 break; 1321 case VGT_STRMOUT_BUFFER_SIZE_0: 1322 case VGT_STRMOUT_BUFFER_SIZE_1: 1323 case VGT_STRMOUT_BUFFER_SIZE_2: 1324 case VGT_STRMOUT_BUFFER_SIZE_3: 1325 tmp = (reg - VGT_STRMOUT_BUFFER_SIZE_0) / 16; 1326 /* size in register is DWs, convert to bytes */ 1327 track->vgt_strmout_size[tmp] = radeon_get_ib_value(p, idx) * 4; 1328 track->streamout_dirty = true; 1329 break; 1330 case CP_COHER_BASE: 1331 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1332 if (r) { 1333 dev_warn(p->dev, "missing reloc for CP_COHER_BASE " 1334 "0x%04X\n", reg); 1335 return -EINVAL; 1336 } 1337 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); 1338 break; 1339 case CB_TARGET_MASK: 1340 track->cb_target_mask = radeon_get_ib_value(p, idx); 1341 track->cb_dirty = true; 1342 break; 1343 case CB_SHADER_MASK: 1344 track->cb_shader_mask = radeon_get_ib_value(p, idx); 1345 track->cb_dirty = true; 1346 break; 1347 case PA_SC_AA_CONFIG: 1348 if (p->rdev->family >= CHIP_CAYMAN) { 1349 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1350 "0x%04X\n", reg); 1351 return -EINVAL; 1352 } 1353 tmp = radeon_get_ib_value(p, idx) & MSAA_NUM_SAMPLES_MASK; 1354 track->nsamples = 1 << tmp; 1355 break; 1356 case CAYMAN_PA_SC_AA_CONFIG: 1357 if (p->rdev->family < CHIP_CAYMAN) { 1358 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1359 "0x%04X\n", reg); 1360 return -EINVAL; 1361 } 1362 tmp = radeon_get_ib_value(p, idx) & CAYMAN_MSAA_NUM_SAMPLES_MASK; 1363 track->nsamples = 1 << tmp; 1364 break; 1365 case CB_COLOR0_VIEW: 1366 case CB_COLOR1_VIEW: 1367 case CB_COLOR2_VIEW: 1368 case CB_COLOR3_VIEW: 1369 case CB_COLOR4_VIEW: 1370 case CB_COLOR5_VIEW: 1371 case CB_COLOR6_VIEW: 1372 case CB_COLOR7_VIEW: 1373 tmp = (reg - CB_COLOR0_VIEW) / 0x3c; 1374 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx); 1375 track->cb_dirty = true; 1376 break; 1377 case CB_COLOR8_VIEW: 1378 case CB_COLOR9_VIEW: 1379 case CB_COLOR10_VIEW: 1380 case CB_COLOR11_VIEW: 1381 tmp = ((reg - CB_COLOR8_VIEW) / 0x1c) + 8; 1382 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx); 1383 track->cb_dirty = true; 1384 break; 1385 case CB_COLOR0_INFO: 1386 case CB_COLOR1_INFO: 1387 case CB_COLOR2_INFO: 1388 case CB_COLOR3_INFO: 1389 case CB_COLOR4_INFO: 1390 case CB_COLOR5_INFO: 1391 case CB_COLOR6_INFO: 1392 case CB_COLOR7_INFO: 1393 tmp = (reg - CB_COLOR0_INFO) / 0x3c; 1394 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx); 1395 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 1396 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1397 if (r) { 1398 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1399 "0x%04X\n", reg); 1400 return -EINVAL; 1401 } 1402 ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); 1403 track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); 1404 } 1405 track->cb_dirty = true; 1406 break; 1407 case CB_COLOR8_INFO: 1408 case CB_COLOR9_INFO: 1409 case CB_COLOR10_INFO: 1410 case CB_COLOR11_INFO: 1411 tmp = ((reg - CB_COLOR8_INFO) / 0x1c) + 8; 1412 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx); 1413 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 1414 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1415 if (r) { 1416 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1417 "0x%04X\n", reg); 1418 return -EINVAL; 1419 } 1420 ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); 1421 track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); 1422 } 1423 track->cb_dirty = true; 1424 break; 1425 case CB_COLOR0_PITCH: 1426 case CB_COLOR1_PITCH: 1427 case CB_COLOR2_PITCH: 1428 case CB_COLOR3_PITCH: 1429 case CB_COLOR4_PITCH: 1430 case CB_COLOR5_PITCH: 1431 case CB_COLOR6_PITCH: 1432 case CB_COLOR7_PITCH: 1433 tmp = (reg - CB_COLOR0_PITCH) / 0x3c; 1434 track->cb_color_pitch[tmp] = radeon_get_ib_value(p, idx); 1435 track->cb_dirty = true; 1436 break; 1437 case CB_COLOR8_PITCH: 1438 case CB_COLOR9_PITCH: 1439 case CB_COLOR10_PITCH: 1440 case CB_COLOR11_PITCH: 1441 tmp = ((reg - CB_COLOR8_PITCH) / 0x1c) + 8; 1442 track->cb_color_pitch[tmp] = radeon_get_ib_value(p, idx); 1443 track->cb_dirty = true; 1444 break; 1445 case CB_COLOR0_SLICE: 1446 case CB_COLOR1_SLICE: 1447 case CB_COLOR2_SLICE: 1448 case CB_COLOR3_SLICE: 1449 case CB_COLOR4_SLICE: 1450 case CB_COLOR5_SLICE: 1451 case CB_COLOR6_SLICE: 1452 case CB_COLOR7_SLICE: 1453 tmp = (reg - CB_COLOR0_SLICE) / 0x3c; 1454 track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx); 1455 track->cb_color_slice_idx[tmp] = idx; 1456 track->cb_dirty = true; 1457 break; 1458 case CB_COLOR8_SLICE: 1459 case CB_COLOR9_SLICE: 1460 case CB_COLOR10_SLICE: 1461 case CB_COLOR11_SLICE: 1462 tmp = ((reg - CB_COLOR8_SLICE) / 0x1c) + 8; 1463 track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx); 1464 track->cb_color_slice_idx[tmp] = idx; 1465 track->cb_dirty = true; 1466 break; 1467 case CB_COLOR0_ATTRIB: 1468 case CB_COLOR1_ATTRIB: 1469 case CB_COLOR2_ATTRIB: 1470 case CB_COLOR3_ATTRIB: 1471 case CB_COLOR4_ATTRIB: 1472 case CB_COLOR5_ATTRIB: 1473 case CB_COLOR6_ATTRIB: 1474 case CB_COLOR7_ATTRIB: 1475 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1476 if (r) { 1477 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1478 "0x%04X\n", reg); 1479 return -EINVAL; 1480 } 1481 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 1482 if (reloc->tiling_flags & RADEON_TILING_MACRO) { 1483 unsigned bankw, bankh, mtaspect, tile_split; 1484 1485 evergreen_tiling_fields(reloc->tiling_flags, 1486 &bankw, &bankh, &mtaspect, 1487 &tile_split); 1488 ib[idx] |= CB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks)); 1489 ib[idx] |= CB_TILE_SPLIT(tile_split) | 1490 CB_BANK_WIDTH(bankw) | 1491 CB_BANK_HEIGHT(bankh) | 1492 CB_MACRO_TILE_ASPECT(mtaspect); 1493 } 1494 } 1495 tmp = ((reg - CB_COLOR0_ATTRIB) / 0x3c); 1496 track->cb_color_attrib[tmp] = ib[idx]; 1497 track->cb_dirty = true; 1498 break; 1499 case CB_COLOR8_ATTRIB: 1500 case CB_COLOR9_ATTRIB: 1501 case CB_COLOR10_ATTRIB: 1502 case CB_COLOR11_ATTRIB: 1503 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1504 if (r) { 1505 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1506 "0x%04X\n", reg); 1507 return -EINVAL; 1508 } 1509 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 1510 if (reloc->tiling_flags & RADEON_TILING_MACRO) { 1511 unsigned bankw, bankh, mtaspect, tile_split; 1512 1513 evergreen_tiling_fields(reloc->tiling_flags, 1514 &bankw, &bankh, &mtaspect, 1515 &tile_split); 1516 ib[idx] |= CB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks)); 1517 ib[idx] |= CB_TILE_SPLIT(tile_split) | 1518 CB_BANK_WIDTH(bankw) | 1519 CB_BANK_HEIGHT(bankh) | 1520 CB_MACRO_TILE_ASPECT(mtaspect); 1521 } 1522 } 1523 tmp = ((reg - CB_COLOR8_ATTRIB) / 0x1c) + 8; 1524 track->cb_color_attrib[tmp] = ib[idx]; 1525 track->cb_dirty = true; 1526 break; 1527 case CB_COLOR0_FMASK: 1528 case CB_COLOR1_FMASK: 1529 case CB_COLOR2_FMASK: 1530 case CB_COLOR3_FMASK: 1531 case CB_COLOR4_FMASK: 1532 case CB_COLOR5_FMASK: 1533 case CB_COLOR6_FMASK: 1534 case CB_COLOR7_FMASK: 1535 tmp = (reg - CB_COLOR0_FMASK) / 0x3c; 1536 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1537 if (r) { 1538 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg); 1539 return -EINVAL; 1540 } 1541 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); 1542 track->cb_color_fmask_bo[tmp] = reloc->robj; 1543 break; 1544 case CB_COLOR0_CMASK: 1545 case CB_COLOR1_CMASK: 1546 case CB_COLOR2_CMASK: 1547 case CB_COLOR3_CMASK: 1548 case CB_COLOR4_CMASK: 1549 case CB_COLOR5_CMASK: 1550 case CB_COLOR6_CMASK: 1551 case CB_COLOR7_CMASK: 1552 tmp = (reg - CB_COLOR0_CMASK) / 0x3c; 1553 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1554 if (r) { 1555 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg); 1556 return -EINVAL; 1557 } 1558 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); 1559 track->cb_color_cmask_bo[tmp] = reloc->robj; 1560 break; 1561 case CB_COLOR0_FMASK_SLICE: 1562 case CB_COLOR1_FMASK_SLICE: 1563 case CB_COLOR2_FMASK_SLICE: 1564 case CB_COLOR3_FMASK_SLICE: 1565 case CB_COLOR4_FMASK_SLICE: 1566 case CB_COLOR5_FMASK_SLICE: 1567 case CB_COLOR6_FMASK_SLICE: 1568 case CB_COLOR7_FMASK_SLICE: 1569 tmp = (reg - CB_COLOR0_FMASK_SLICE) / 0x3c; 1570 track->cb_color_fmask_slice[tmp] = radeon_get_ib_value(p, idx); 1571 break; 1572 case CB_COLOR0_CMASK_SLICE: 1573 case CB_COLOR1_CMASK_SLICE: 1574 case CB_COLOR2_CMASK_SLICE: 1575 case CB_COLOR3_CMASK_SLICE: 1576 case CB_COLOR4_CMASK_SLICE: 1577 case CB_COLOR5_CMASK_SLICE: 1578 case CB_COLOR6_CMASK_SLICE: 1579 case CB_COLOR7_CMASK_SLICE: 1580 tmp = (reg - CB_COLOR0_CMASK_SLICE) / 0x3c; 1581 track->cb_color_cmask_slice[tmp] = radeon_get_ib_value(p, idx); 1582 break; 1583 case CB_COLOR0_BASE: 1584 case CB_COLOR1_BASE: 1585 case CB_COLOR2_BASE: 1586 case CB_COLOR3_BASE: 1587 case CB_COLOR4_BASE: 1588 case CB_COLOR5_BASE: 1589 case CB_COLOR6_BASE: 1590 case CB_COLOR7_BASE: 1591 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1592 if (r) { 1593 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1594 "0x%04X\n", reg); 1595 return -EINVAL; 1596 } 1597 tmp = (reg - CB_COLOR0_BASE) / 0x3c; 1598 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx); 1599 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); 1600 track->cb_color_bo[tmp] = reloc->robj; 1601 track->cb_dirty = true; 1602 break; 1603 case CB_COLOR8_BASE: 1604 case CB_COLOR9_BASE: 1605 case CB_COLOR10_BASE: 1606 case CB_COLOR11_BASE: 1607 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1608 if (r) { 1609 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1610 "0x%04X\n", reg); 1611 return -EINVAL; 1612 } 1613 tmp = ((reg - CB_COLOR8_BASE) / 0x1c) + 8; 1614 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx); 1615 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); 1616 track->cb_color_bo[tmp] = reloc->robj; 1617 track->cb_dirty = true; 1618 break; 1619 case DB_HTILE_DATA_BASE: 1620 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1621 if (r) { 1622 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1623 "0x%04X\n", reg); 1624 return -EINVAL; 1625 } 1626 track->htile_offset = radeon_get_ib_value(p, idx); 1627 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); 1628 track->htile_bo = reloc->robj; 1629 track->db_dirty = true; 1630 break; 1631 case DB_HTILE_SURFACE: 1632 /* 8x8 only */ 1633 track->htile_surface = radeon_get_ib_value(p, idx); 1634 /* force 8x8 htile width and height */ 1635 ib[idx] |= 3; 1636 track->db_dirty = true; 1637 break; 1638 case CB_IMMED0_BASE: 1639 case CB_IMMED1_BASE: 1640 case CB_IMMED2_BASE: 1641 case CB_IMMED3_BASE: 1642 case CB_IMMED4_BASE: 1643 case CB_IMMED5_BASE: 1644 case CB_IMMED6_BASE: 1645 case CB_IMMED7_BASE: 1646 case CB_IMMED8_BASE: 1647 case CB_IMMED9_BASE: 1648 case CB_IMMED10_BASE: 1649 case CB_IMMED11_BASE: 1650 case SQ_PGM_START_FS: 1651 case SQ_PGM_START_ES: 1652 case SQ_PGM_START_VS: 1653 case SQ_PGM_START_GS: 1654 case SQ_PGM_START_PS: 1655 case SQ_PGM_START_HS: 1656 case SQ_PGM_START_LS: 1657 case SQ_CONST_MEM_BASE: 1658 case SQ_ALU_CONST_CACHE_GS_0: 1659 case SQ_ALU_CONST_CACHE_GS_1: 1660 case SQ_ALU_CONST_CACHE_GS_2: 1661 case SQ_ALU_CONST_CACHE_GS_3: 1662 case SQ_ALU_CONST_CACHE_GS_4: 1663 case SQ_ALU_CONST_CACHE_GS_5: 1664 case SQ_ALU_CONST_CACHE_GS_6: 1665 case SQ_ALU_CONST_CACHE_GS_7: 1666 case SQ_ALU_CONST_CACHE_GS_8: 1667 case SQ_ALU_CONST_CACHE_GS_9: 1668 case SQ_ALU_CONST_CACHE_GS_10: 1669 case SQ_ALU_CONST_CACHE_GS_11: 1670 case SQ_ALU_CONST_CACHE_GS_12: 1671 case SQ_ALU_CONST_CACHE_GS_13: 1672 case SQ_ALU_CONST_CACHE_GS_14: 1673 case SQ_ALU_CONST_CACHE_GS_15: 1674 case SQ_ALU_CONST_CACHE_PS_0: 1675 case SQ_ALU_CONST_CACHE_PS_1: 1676 case SQ_ALU_CONST_CACHE_PS_2: 1677 case SQ_ALU_CONST_CACHE_PS_3: 1678 case SQ_ALU_CONST_CACHE_PS_4: 1679 case SQ_ALU_CONST_CACHE_PS_5: 1680 case SQ_ALU_CONST_CACHE_PS_6: 1681 case SQ_ALU_CONST_CACHE_PS_7: 1682 case SQ_ALU_CONST_CACHE_PS_8: 1683 case SQ_ALU_CONST_CACHE_PS_9: 1684 case SQ_ALU_CONST_CACHE_PS_10: 1685 case SQ_ALU_CONST_CACHE_PS_11: 1686 case SQ_ALU_CONST_CACHE_PS_12: 1687 case SQ_ALU_CONST_CACHE_PS_13: 1688 case SQ_ALU_CONST_CACHE_PS_14: 1689 case SQ_ALU_CONST_CACHE_PS_15: 1690 case SQ_ALU_CONST_CACHE_VS_0: 1691 case SQ_ALU_CONST_CACHE_VS_1: 1692 case SQ_ALU_CONST_CACHE_VS_2: 1693 case SQ_ALU_CONST_CACHE_VS_3: 1694 case SQ_ALU_CONST_CACHE_VS_4: 1695 case SQ_ALU_CONST_CACHE_VS_5: 1696 case SQ_ALU_CONST_CACHE_VS_6: 1697 case SQ_ALU_CONST_CACHE_VS_7: 1698 case SQ_ALU_CONST_CACHE_VS_8: 1699 case SQ_ALU_CONST_CACHE_VS_9: 1700 case SQ_ALU_CONST_CACHE_VS_10: 1701 case SQ_ALU_CONST_CACHE_VS_11: 1702 case SQ_ALU_CONST_CACHE_VS_12: 1703 case SQ_ALU_CONST_CACHE_VS_13: 1704 case SQ_ALU_CONST_CACHE_VS_14: 1705 case SQ_ALU_CONST_CACHE_VS_15: 1706 case SQ_ALU_CONST_CACHE_HS_0: 1707 case SQ_ALU_CONST_CACHE_HS_1: 1708 case SQ_ALU_CONST_CACHE_HS_2: 1709 case SQ_ALU_CONST_CACHE_HS_3: 1710 case SQ_ALU_CONST_CACHE_HS_4: 1711 case SQ_ALU_CONST_CACHE_HS_5: 1712 case SQ_ALU_CONST_CACHE_HS_6: 1713 case SQ_ALU_CONST_CACHE_HS_7: 1714 case SQ_ALU_CONST_CACHE_HS_8: 1715 case SQ_ALU_CONST_CACHE_HS_9: 1716 case SQ_ALU_CONST_CACHE_HS_10: 1717 case SQ_ALU_CONST_CACHE_HS_11: 1718 case SQ_ALU_CONST_CACHE_HS_12: 1719 case SQ_ALU_CONST_CACHE_HS_13: 1720 case SQ_ALU_CONST_CACHE_HS_14: 1721 case SQ_ALU_CONST_CACHE_HS_15: 1722 case SQ_ALU_CONST_CACHE_LS_0: 1723 case SQ_ALU_CONST_CACHE_LS_1: 1724 case SQ_ALU_CONST_CACHE_LS_2: 1725 case SQ_ALU_CONST_CACHE_LS_3: 1726 case SQ_ALU_CONST_CACHE_LS_4: 1727 case SQ_ALU_CONST_CACHE_LS_5: 1728 case SQ_ALU_CONST_CACHE_LS_6: 1729 case SQ_ALU_CONST_CACHE_LS_7: 1730 case SQ_ALU_CONST_CACHE_LS_8: 1731 case SQ_ALU_CONST_CACHE_LS_9: 1732 case SQ_ALU_CONST_CACHE_LS_10: 1733 case SQ_ALU_CONST_CACHE_LS_11: 1734 case SQ_ALU_CONST_CACHE_LS_12: 1735 case SQ_ALU_CONST_CACHE_LS_13: 1736 case SQ_ALU_CONST_CACHE_LS_14: 1737 case SQ_ALU_CONST_CACHE_LS_15: 1738 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1739 if (r) { 1740 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1741 "0x%04X\n", reg); 1742 return -EINVAL; 1743 } 1744 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); 1745 break; 1746 case SX_MEMORY_EXPORT_BASE: 1747 if (p->rdev->family >= CHIP_CAYMAN) { 1748 dev_warn(p->dev, "bad SET_CONFIG_REG " 1749 "0x%04X\n", reg); 1750 return -EINVAL; 1751 } 1752 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1753 if (r) { 1754 dev_warn(p->dev, "bad SET_CONFIG_REG " 1755 "0x%04X\n", reg); 1756 return -EINVAL; 1757 } 1758 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); 1759 break; 1760 case CAYMAN_SX_SCATTER_EXPORT_BASE: 1761 if (p->rdev->family < CHIP_CAYMAN) { 1762 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1763 "0x%04X\n", reg); 1764 return -EINVAL; 1765 } 1766 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1767 if (r) { 1768 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1769 "0x%04X\n", reg); 1770 return -EINVAL; 1771 } 1772 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); 1773 break; 1774 case SX_MISC: 1775 track->sx_misc_kill_all_prims = (radeon_get_ib_value(p, idx) & 0x1) != 0; 1776 break; 1777 default: 1778 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); 1779 return -EINVAL; 1780 } 1781 return 0; 1782 } 1783 1784 /** 1785 * evergreen_is_safe_reg() - check if register is authorized or not 1786 * @parser: parser structure holding parsing context 1787 * @reg: register we are testing 1788 * 1789 * This function will test against reg_safe_bm and return true 1790 * if register is safe or false otherwise. 1791 */ 1792 static inline bool evergreen_is_safe_reg(struct radeon_cs_parser *p, u32 reg) 1793 { 1794 struct evergreen_cs_track *track = p->track; 1795 u32 m, i; 1796 1797 i = (reg >> 7); 1798 if (unlikely(i >= REG_SAFE_BM_SIZE)) { 1799 return false; 1800 } 1801 m = 1 << ((reg >> 2) & 31); 1802 if (!(track->reg_safe_bm[i] & m)) 1803 return true; 1804 1805 return false; 1806 } 1807 1808 static int evergreen_packet3_check(struct radeon_cs_parser *p, 1809 struct radeon_cs_packet *pkt) 1810 { 1811 struct radeon_bo_list *reloc; 1812 struct evergreen_cs_track *track; 1813 uint32_t *ib; 1814 unsigned idx; 1815 unsigned i; 1816 unsigned start_reg, end_reg, reg; 1817 int r; 1818 u32 idx_value; 1819 1820 track = (struct evergreen_cs_track *)p->track; 1821 ib = p->ib.ptr; 1822 idx = pkt->idx + 1; 1823 idx_value = radeon_get_ib_value(p, idx); 1824 1825 switch (pkt->opcode) { 1826 case PACKET3_SET_PREDICATION: 1827 { 1828 int pred_op; 1829 int tmp; 1830 uint64_t offset; 1831 1832 if (pkt->count != 1) { 1833 DRM_ERROR("bad SET PREDICATION\n"); 1834 return -EINVAL; 1835 } 1836 1837 tmp = radeon_get_ib_value(p, idx + 1); 1838 pred_op = (tmp >> 16) & 0x7; 1839 1840 /* for the clear predicate operation */ 1841 if (pred_op == 0) 1842 return 0; 1843 1844 if (pred_op > 2) { 1845 DRM_ERROR("bad SET PREDICATION operation %d\n", pred_op); 1846 return -EINVAL; 1847 } 1848 1849 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1850 if (r) { 1851 DRM_ERROR("bad SET PREDICATION\n"); 1852 return -EINVAL; 1853 } 1854 1855 offset = reloc->gpu_offset + 1856 (idx_value & 0xfffffff0) + 1857 ((u64)(tmp & 0xff) << 32); 1858 1859 ib[idx + 0] = offset; 1860 ib[idx + 1] = (tmp & 0xffffff00) | (upper_32_bits(offset) & 0xff); 1861 } 1862 break; 1863 case PACKET3_CONTEXT_CONTROL: 1864 if (pkt->count != 1) { 1865 DRM_ERROR("bad CONTEXT_CONTROL\n"); 1866 return -EINVAL; 1867 } 1868 break; 1869 case PACKET3_INDEX_TYPE: 1870 case PACKET3_NUM_INSTANCES: 1871 case PACKET3_CLEAR_STATE: 1872 if (pkt->count) { 1873 DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES/CLEAR_STATE\n"); 1874 return -EINVAL; 1875 } 1876 break; 1877 case CAYMAN_PACKET3_DEALLOC_STATE: 1878 if (p->rdev->family < CHIP_CAYMAN) { 1879 DRM_ERROR("bad PACKET3_DEALLOC_STATE\n"); 1880 return -EINVAL; 1881 } 1882 if (pkt->count) { 1883 DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES/CLEAR_STATE\n"); 1884 return -EINVAL; 1885 } 1886 break; 1887 case PACKET3_INDEX_BASE: 1888 { 1889 uint64_t offset; 1890 1891 if (pkt->count != 1) { 1892 DRM_ERROR("bad INDEX_BASE\n"); 1893 return -EINVAL; 1894 } 1895 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1896 if (r) { 1897 DRM_ERROR("bad INDEX_BASE\n"); 1898 return -EINVAL; 1899 } 1900 1901 offset = reloc->gpu_offset + 1902 idx_value + 1903 ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32); 1904 1905 ib[idx+0] = offset; 1906 ib[idx+1] = upper_32_bits(offset) & 0xff; 1907 1908 r = evergreen_cs_track_check(p); 1909 if (r) { 1910 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); 1911 return r; 1912 } 1913 break; 1914 } 1915 case PACKET3_INDEX_BUFFER_SIZE: 1916 { 1917 if (pkt->count != 0) { 1918 DRM_ERROR("bad INDEX_BUFFER_SIZE\n"); 1919 return -EINVAL; 1920 } 1921 break; 1922 } 1923 case PACKET3_DRAW_INDEX: 1924 { 1925 uint64_t offset; 1926 if (pkt->count != 3) { 1927 DRM_ERROR("bad DRAW_INDEX\n"); 1928 return -EINVAL; 1929 } 1930 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1931 if (r) { 1932 DRM_ERROR("bad DRAW_INDEX\n"); 1933 return -EINVAL; 1934 } 1935 1936 offset = reloc->gpu_offset + 1937 idx_value + 1938 ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32); 1939 1940 ib[idx+0] = offset; 1941 ib[idx+1] = upper_32_bits(offset) & 0xff; 1942 1943 r = evergreen_cs_track_check(p); 1944 if (r) { 1945 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); 1946 return r; 1947 } 1948 break; 1949 } 1950 case PACKET3_DRAW_INDEX_2: 1951 { 1952 uint64_t offset; 1953 1954 if (pkt->count != 4) { 1955 DRM_ERROR("bad DRAW_INDEX_2\n"); 1956 return -EINVAL; 1957 } 1958 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1959 if (r) { 1960 DRM_ERROR("bad DRAW_INDEX_2\n"); 1961 return -EINVAL; 1962 } 1963 1964 offset = reloc->gpu_offset + 1965 radeon_get_ib_value(p, idx+1) + 1966 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); 1967 1968 ib[idx+1] = offset; 1969 ib[idx+2] = upper_32_bits(offset) & 0xff; 1970 1971 r = evergreen_cs_track_check(p); 1972 if (r) { 1973 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); 1974 return r; 1975 } 1976 break; 1977 } 1978 case PACKET3_DRAW_INDEX_AUTO: 1979 if (pkt->count != 1) { 1980 DRM_ERROR("bad DRAW_INDEX_AUTO\n"); 1981 return -EINVAL; 1982 } 1983 r = evergreen_cs_track_check(p); 1984 if (r) { 1985 dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx); 1986 return r; 1987 } 1988 break; 1989 case PACKET3_DRAW_INDEX_MULTI_AUTO: 1990 if (pkt->count != 2) { 1991 DRM_ERROR("bad DRAW_INDEX_MULTI_AUTO\n"); 1992 return -EINVAL; 1993 } 1994 r = evergreen_cs_track_check(p); 1995 if (r) { 1996 dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx); 1997 return r; 1998 } 1999 break; 2000 case PACKET3_DRAW_INDEX_IMMD: 2001 if (pkt->count < 2) { 2002 DRM_ERROR("bad DRAW_INDEX_IMMD\n"); 2003 return -EINVAL; 2004 } 2005 r = evergreen_cs_track_check(p); 2006 if (r) { 2007 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); 2008 return r; 2009 } 2010 break; 2011 case PACKET3_DRAW_INDEX_OFFSET: 2012 if (pkt->count != 2) { 2013 DRM_ERROR("bad DRAW_INDEX_OFFSET\n"); 2014 return -EINVAL; 2015 } 2016 r = evergreen_cs_track_check(p); 2017 if (r) { 2018 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); 2019 return r; 2020 } 2021 break; 2022 case PACKET3_DRAW_INDEX_OFFSET_2: 2023 if (pkt->count != 3) { 2024 DRM_ERROR("bad DRAW_INDEX_OFFSET_2\n"); 2025 return -EINVAL; 2026 } 2027 r = evergreen_cs_track_check(p); 2028 if (r) { 2029 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); 2030 return r; 2031 } 2032 break; 2033 case PACKET3_SET_BASE: 2034 { 2035 /* 2036 DW 1 HEADER Header of the packet. Shader_Type in bit 1 of the Header will correspond to the shader type of the Load, see Type-3 Packet. 2037 2 BASE_INDEX Bits [3:0] BASE_INDEX - Base Index specifies which base address is specified in the last two DWs. 2038 0001: DX11 Draw_Index_Indirect Patch Table Base: Base address for Draw_Index_Indirect data. 2039 3 ADDRESS_LO Bits [31:3] - Lower bits of QWORD-Aligned Address. Bits [2:0] - Reserved 2040 4 ADDRESS_HI Bits [31:8] - Reserved. Bits [7:0] - Upper bits of Address [47:32] 2041 */ 2042 if (pkt->count != 2) { 2043 DRM_ERROR("bad SET_BASE\n"); 2044 return -EINVAL; 2045 } 2046 2047 /* currently only supporting setting indirect draw buffer base address */ 2048 if (idx_value != 1) { 2049 DRM_ERROR("bad SET_BASE\n"); 2050 return -EINVAL; 2051 } 2052 2053 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 2054 if (r) { 2055 DRM_ERROR("bad SET_BASE\n"); 2056 return -EINVAL; 2057 } 2058 2059 track->indirect_draw_buffer_size = radeon_bo_size(reloc->robj); 2060 2061 ib[idx+1] = reloc->gpu_offset; 2062 ib[idx+2] = upper_32_bits(reloc->gpu_offset) & 0xff; 2063 2064 break; 2065 } 2066 case PACKET3_DRAW_INDIRECT: 2067 case PACKET3_DRAW_INDEX_INDIRECT: 2068 { 2069 u64 size = pkt->opcode == PACKET3_DRAW_INDIRECT ? 16 : 20; 2070 2071 /* 2072 DW 1 HEADER 2073 2 DATA_OFFSET Bits [31:0] + byte aligned offset where the required data structure starts. Bits 1:0 are zero 2074 3 DRAW_INITIATOR Draw Initiator Register. Written to the VGT_DRAW_INITIATOR register for the assigned context 2075 */ 2076 if (pkt->count != 1) { 2077 DRM_ERROR("bad DRAW_INDIRECT\n"); 2078 return -EINVAL; 2079 } 2080 2081 if (idx_value + size > track->indirect_draw_buffer_size) { 2082 dev_warn(p->dev, "DRAW_INDIRECT buffer too small %u + %"PRIx64" > %lu\n", 2083 idx_value, size, track->indirect_draw_buffer_size); 2084 return -EINVAL; 2085 } 2086 2087 r = evergreen_cs_track_check(p); 2088 if (r) { 2089 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); 2090 return r; 2091 } 2092 break; 2093 } 2094 case PACKET3_DISPATCH_DIRECT: 2095 if (pkt->count != 3) { 2096 DRM_ERROR("bad DISPATCH_DIRECT\n"); 2097 return -EINVAL; 2098 } 2099 r = evergreen_cs_track_check(p); 2100 if (r) { 2101 dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx); 2102 return r; 2103 } 2104 break; 2105 case PACKET3_DISPATCH_INDIRECT: 2106 if (pkt->count != 1) { 2107 DRM_ERROR("bad DISPATCH_INDIRECT\n"); 2108 return -EINVAL; 2109 } 2110 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 2111 if (r) { 2112 DRM_ERROR("bad DISPATCH_INDIRECT\n"); 2113 return -EINVAL; 2114 } 2115 ib[idx+0] = idx_value + (u32)(reloc->gpu_offset & 0xffffffff); 2116 r = evergreen_cs_track_check(p); 2117 if (r) { 2118 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); 2119 return r; 2120 } 2121 break; 2122 case PACKET3_WAIT_REG_MEM: 2123 if (pkt->count != 5) { 2124 DRM_ERROR("bad WAIT_REG_MEM\n"); 2125 return -EINVAL; 2126 } 2127 /* bit 4 is reg (0) or mem (1) */ 2128 if (idx_value & 0x10) { 2129 uint64_t offset; 2130 2131 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 2132 if (r) { 2133 DRM_ERROR("bad WAIT_REG_MEM\n"); 2134 return -EINVAL; 2135 } 2136 2137 offset = reloc->gpu_offset + 2138 (radeon_get_ib_value(p, idx+1) & 0xfffffffc) + 2139 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); 2140 2141 ib[idx+1] = (ib[idx+1] & 0x3) | (offset & 0xfffffffc); 2142 ib[idx+2] = upper_32_bits(offset) & 0xff; 2143 } else if (idx_value & 0x100) { 2144 DRM_ERROR("cannot use PFP on REG wait\n"); 2145 return -EINVAL; 2146 } 2147 break; 2148 case PACKET3_CP_DMA: 2149 { 2150 u32 command, size, info; 2151 u64 offset, tmp; 2152 if (pkt->count != 4) { 2153 DRM_ERROR("bad CP DMA\n"); 2154 return -EINVAL; 2155 } 2156 command = radeon_get_ib_value(p, idx+4); 2157 size = command & 0x1fffff; 2158 info = radeon_get_ib_value(p, idx+1); 2159 if ((((info & 0x60000000) >> 29) != 0) || /* src = GDS or DATA */ 2160 (((info & 0x00300000) >> 20) != 0) || /* dst = GDS */ 2161 ((((info & 0x00300000) >> 20) == 0) && 2162 (command & PACKET3_CP_DMA_CMD_DAS)) || /* dst = register */ 2163 ((((info & 0x60000000) >> 29) == 0) && 2164 (command & PACKET3_CP_DMA_CMD_SAS))) { /* src = register */ 2165 /* non mem to mem copies requires dw aligned count */ 2166 if (size % 4) { 2167 DRM_ERROR("CP DMA command requires dw count alignment\n"); 2168 return -EINVAL; 2169 } 2170 } 2171 if (command & PACKET3_CP_DMA_CMD_SAS) { 2172 /* src address space is register */ 2173 /* GDS is ok */ 2174 if (((info & 0x60000000) >> 29) != 1) { 2175 DRM_ERROR("CP DMA SAS not supported\n"); 2176 return -EINVAL; 2177 } 2178 } else { 2179 if (command & PACKET3_CP_DMA_CMD_SAIC) { 2180 DRM_ERROR("CP DMA SAIC only supported for registers\n"); 2181 return -EINVAL; 2182 } 2183 /* src address space is memory */ 2184 if (((info & 0x60000000) >> 29) == 0) { 2185 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 2186 if (r) { 2187 DRM_ERROR("bad CP DMA SRC\n"); 2188 return -EINVAL; 2189 } 2190 2191 tmp = radeon_get_ib_value(p, idx) + 2192 ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32); 2193 2194 offset = reloc->gpu_offset + tmp; 2195 2196 if ((tmp + size) > radeon_bo_size(reloc->robj)) { 2197 dev_warn(p->dev, "CP DMA src buffer too small (%"PRIu64" %lu)\n", 2198 tmp + size, radeon_bo_size(reloc->robj)); 2199 return -EINVAL; 2200 } 2201 2202 ib[idx] = offset; 2203 ib[idx+1] = (ib[idx+1] & 0xffffff00) | (upper_32_bits(offset) & 0xff); 2204 } else if (((info & 0x60000000) >> 29) != 2) { 2205 DRM_ERROR("bad CP DMA SRC_SEL\n"); 2206 return -EINVAL; 2207 } 2208 } 2209 if (command & PACKET3_CP_DMA_CMD_DAS) { 2210 /* dst address space is register */ 2211 /* GDS is ok */ 2212 if (((info & 0x00300000) >> 20) != 1) { 2213 DRM_ERROR("CP DMA DAS not supported\n"); 2214 return -EINVAL; 2215 } 2216 } else { 2217 /* dst address space is memory */ 2218 if (command & PACKET3_CP_DMA_CMD_DAIC) { 2219 DRM_ERROR("CP DMA DAIC only supported for registers\n"); 2220 return -EINVAL; 2221 } 2222 if (((info & 0x00300000) >> 20) == 0) { 2223 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 2224 if (r) { 2225 DRM_ERROR("bad CP DMA DST\n"); 2226 return -EINVAL; 2227 } 2228 2229 tmp = radeon_get_ib_value(p, idx+2) + 2230 ((u64)(radeon_get_ib_value(p, idx+3) & 0xff) << 32); 2231 2232 offset = reloc->gpu_offset + tmp; 2233 2234 if ((tmp + size) > radeon_bo_size(reloc->robj)) { 2235 dev_warn(p->dev, "CP DMA dst buffer too small (%"PRIu64" %lu)\n", 2236 tmp + size, radeon_bo_size(reloc->robj)); 2237 return -EINVAL; 2238 } 2239 2240 ib[idx+2] = offset; 2241 ib[idx+3] = upper_32_bits(offset) & 0xff; 2242 } else { 2243 DRM_ERROR("bad CP DMA DST_SEL\n"); 2244 return -EINVAL; 2245 } 2246 } 2247 break; 2248 } 2249 case PACKET3_SURFACE_SYNC: 2250 if (pkt->count != 3) { 2251 DRM_ERROR("bad SURFACE_SYNC\n"); 2252 return -EINVAL; 2253 } 2254 /* 0xffffffff/0x0 is flush all cache flag */ 2255 if (radeon_get_ib_value(p, idx + 1) != 0xffffffff || 2256 radeon_get_ib_value(p, idx + 2) != 0) { 2257 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 2258 if (r) { 2259 DRM_ERROR("bad SURFACE_SYNC\n"); 2260 return -EINVAL; 2261 } 2262 ib[idx+2] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); 2263 } 2264 break; 2265 case PACKET3_EVENT_WRITE: 2266 if (pkt->count != 2 && pkt->count != 0) { 2267 DRM_ERROR("bad EVENT_WRITE\n"); 2268 return -EINVAL; 2269 } 2270 if (pkt->count) { 2271 uint64_t offset; 2272 2273 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 2274 if (r) { 2275 DRM_ERROR("bad EVENT_WRITE\n"); 2276 return -EINVAL; 2277 } 2278 offset = reloc->gpu_offset + 2279 (radeon_get_ib_value(p, idx+1) & 0xfffffff8) + 2280 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); 2281 2282 ib[idx+1] = offset & 0xfffffff8; 2283 ib[idx+2] = upper_32_bits(offset) & 0xff; 2284 } 2285 break; 2286 case PACKET3_EVENT_WRITE_EOP: 2287 { 2288 uint64_t offset; 2289 2290 if (pkt->count != 4) { 2291 DRM_ERROR("bad EVENT_WRITE_EOP\n"); 2292 return -EINVAL; 2293 } 2294 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 2295 if (r) { 2296 DRM_ERROR("bad EVENT_WRITE_EOP\n"); 2297 return -EINVAL; 2298 } 2299 2300 offset = reloc->gpu_offset + 2301 (radeon_get_ib_value(p, idx+1) & 0xfffffffc) + 2302 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); 2303 2304 ib[idx+1] = offset & 0xfffffffc; 2305 ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff); 2306 break; 2307 } 2308 case PACKET3_EVENT_WRITE_EOS: 2309 { 2310 uint64_t offset; 2311 2312 if (pkt->count != 3) { 2313 DRM_ERROR("bad EVENT_WRITE_EOS\n"); 2314 return -EINVAL; 2315 } 2316 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 2317 if (r) { 2318 DRM_ERROR("bad EVENT_WRITE_EOS\n"); 2319 return -EINVAL; 2320 } 2321 2322 offset = reloc->gpu_offset + 2323 (radeon_get_ib_value(p, idx+1) & 0xfffffffc) + 2324 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); 2325 2326 ib[idx+1] = offset & 0xfffffffc; 2327 ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff); 2328 break; 2329 } 2330 case PACKET3_SET_CONFIG_REG: 2331 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START; 2332 end_reg = 4 * pkt->count + start_reg - 4; 2333 if ((start_reg < PACKET3_SET_CONFIG_REG_START) || 2334 (start_reg >= PACKET3_SET_CONFIG_REG_END) || 2335 (end_reg >= PACKET3_SET_CONFIG_REG_END)) { 2336 DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n"); 2337 return -EINVAL; 2338 } 2339 for (reg = start_reg, idx++; reg <= end_reg; reg += 4, idx++) { 2340 if (evergreen_is_safe_reg(p, reg)) 2341 continue; 2342 r = evergreen_cs_handle_reg(p, reg, idx); 2343 if (r) 2344 return r; 2345 } 2346 break; 2347 case PACKET3_SET_CONTEXT_REG: 2348 start_reg = (idx_value << 2) + PACKET3_SET_CONTEXT_REG_START; 2349 end_reg = 4 * pkt->count + start_reg - 4; 2350 if ((start_reg < PACKET3_SET_CONTEXT_REG_START) || 2351 (start_reg >= PACKET3_SET_CONTEXT_REG_END) || 2352 (end_reg >= PACKET3_SET_CONTEXT_REG_END)) { 2353 DRM_ERROR("bad PACKET3_SET_CONTEXT_REG\n"); 2354 return -EINVAL; 2355 } 2356 for (reg = start_reg, idx++; reg <= end_reg; reg += 4, idx++) { 2357 if (evergreen_is_safe_reg(p, reg)) 2358 continue; 2359 r = evergreen_cs_handle_reg(p, reg, idx); 2360 if (r) 2361 return r; 2362 } 2363 break; 2364 case PACKET3_SET_RESOURCE: 2365 if (pkt->count % 8) { 2366 DRM_ERROR("bad SET_RESOURCE\n"); 2367 return -EINVAL; 2368 } 2369 start_reg = (idx_value << 2) + PACKET3_SET_RESOURCE_START; 2370 end_reg = 4 * pkt->count + start_reg - 4; 2371 if ((start_reg < PACKET3_SET_RESOURCE_START) || 2372 (start_reg >= PACKET3_SET_RESOURCE_END) || 2373 (end_reg >= PACKET3_SET_RESOURCE_END)) { 2374 DRM_ERROR("bad SET_RESOURCE\n"); 2375 return -EINVAL; 2376 } 2377 for (i = 0; i < (pkt->count / 8); i++) { 2378 struct radeon_bo *texture, *mipmap; 2379 u32 toffset, moffset; 2380 u32 size, offset, mip_address, tex_dim; 2381 2382 switch (G__SQ_CONSTANT_TYPE(radeon_get_ib_value(p, idx+1+(i*8)+7))) { 2383 case SQ_TEX_VTX_VALID_TEXTURE: 2384 /* tex base */ 2385 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 2386 if (r) { 2387 DRM_ERROR("bad SET_RESOURCE (tex)\n"); 2388 return -EINVAL; 2389 } 2390 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 2391 ib[idx+1+(i*8)+1] |= 2392 TEX_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); 2393 if (reloc->tiling_flags & RADEON_TILING_MACRO) { 2394 unsigned bankw, bankh, mtaspect, tile_split; 2395 2396 evergreen_tiling_fields(reloc->tiling_flags, 2397 &bankw, &bankh, &mtaspect, 2398 &tile_split); 2399 ib[idx+1+(i*8)+6] |= TEX_TILE_SPLIT(tile_split); 2400 ib[idx+1+(i*8)+7] |= 2401 TEX_BANK_WIDTH(bankw) | 2402 TEX_BANK_HEIGHT(bankh) | 2403 MACRO_TILE_ASPECT(mtaspect) | 2404 TEX_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks)); 2405 } 2406 } 2407 texture = reloc->robj; 2408 toffset = (u32)((reloc->gpu_offset >> 8) & 0xffffffff); 2409 2410 /* tex mip base */ 2411 tex_dim = ib[idx+1+(i*8)+0] & 0x7; 2412 mip_address = ib[idx+1+(i*8)+3]; 2413 2414 if ((tex_dim == SQ_TEX_DIM_2D_MSAA || tex_dim == SQ_TEX_DIM_2D_ARRAY_MSAA) && 2415 !mip_address && 2416 !radeon_cs_packet_next_is_pkt3_nop(p)) { 2417 /* MIP_ADDRESS should point to FMASK for an MSAA texture. 2418 * It should be 0 if FMASK is disabled. */ 2419 moffset = 0; 2420 mipmap = NULL; 2421 } else { 2422 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 2423 if (r) { 2424 DRM_ERROR("bad SET_RESOURCE (tex)\n"); 2425 return -EINVAL; 2426 } 2427 moffset = (u32)((reloc->gpu_offset >> 8) & 0xffffffff); 2428 mipmap = reloc->robj; 2429 } 2430 2431 r = evergreen_cs_track_validate_texture(p, texture, mipmap, idx+1+(i*8)); 2432 if (r) 2433 return r; 2434 ib[idx+1+(i*8)+2] += toffset; 2435 ib[idx+1+(i*8)+3] += moffset; 2436 break; 2437 case SQ_TEX_VTX_VALID_BUFFER: 2438 { 2439 uint64_t offset64; 2440 /* vtx base */ 2441 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 2442 if (r) { 2443 DRM_ERROR("bad SET_RESOURCE (vtx)\n"); 2444 return -EINVAL; 2445 } 2446 offset = radeon_get_ib_value(p, idx+1+(i*8)+0); 2447 size = radeon_get_ib_value(p, idx+1+(i*8)+1); 2448 if (p->rdev && (size + offset) > radeon_bo_size(reloc->robj)) { 2449 /* force size to size of the buffer */ 2450 dev_warn(p->dev, "vbo resource seems too big for the bo\n"); 2451 ib[idx+1+(i*8)+1] = radeon_bo_size(reloc->robj) - offset; 2452 } 2453 2454 offset64 = reloc->gpu_offset + offset; 2455 ib[idx+1+(i*8)+0] = offset64; 2456 ib[idx+1+(i*8)+2] = (ib[idx+1+(i*8)+2] & 0xffffff00) | 2457 (upper_32_bits(offset64) & 0xff); 2458 break; 2459 } 2460 case SQ_TEX_VTX_INVALID_TEXTURE: 2461 case SQ_TEX_VTX_INVALID_BUFFER: 2462 default: 2463 DRM_ERROR("bad SET_RESOURCE\n"); 2464 return -EINVAL; 2465 } 2466 } 2467 break; 2468 case PACKET3_SET_ALU_CONST: 2469 /* XXX fix me ALU const buffers only */ 2470 break; 2471 case PACKET3_SET_BOOL_CONST: 2472 start_reg = (idx_value << 2) + PACKET3_SET_BOOL_CONST_START; 2473 end_reg = 4 * pkt->count + start_reg - 4; 2474 if ((start_reg < PACKET3_SET_BOOL_CONST_START) || 2475 (start_reg >= PACKET3_SET_BOOL_CONST_END) || 2476 (end_reg >= PACKET3_SET_BOOL_CONST_END)) { 2477 DRM_ERROR("bad SET_BOOL_CONST\n"); 2478 return -EINVAL; 2479 } 2480 break; 2481 case PACKET3_SET_LOOP_CONST: 2482 start_reg = (idx_value << 2) + PACKET3_SET_LOOP_CONST_START; 2483 end_reg = 4 * pkt->count + start_reg - 4; 2484 if ((start_reg < PACKET3_SET_LOOP_CONST_START) || 2485 (start_reg >= PACKET3_SET_LOOP_CONST_END) || 2486 (end_reg >= PACKET3_SET_LOOP_CONST_END)) { 2487 DRM_ERROR("bad SET_LOOP_CONST\n"); 2488 return -EINVAL; 2489 } 2490 break; 2491 case PACKET3_SET_CTL_CONST: 2492 start_reg = (idx_value << 2) + PACKET3_SET_CTL_CONST_START; 2493 end_reg = 4 * pkt->count + start_reg - 4; 2494 if ((start_reg < PACKET3_SET_CTL_CONST_START) || 2495 (start_reg >= PACKET3_SET_CTL_CONST_END) || 2496 (end_reg >= PACKET3_SET_CTL_CONST_END)) { 2497 DRM_ERROR("bad SET_CTL_CONST\n"); 2498 return -EINVAL; 2499 } 2500 break; 2501 case PACKET3_SET_SAMPLER: 2502 if (pkt->count % 3) { 2503 DRM_ERROR("bad SET_SAMPLER\n"); 2504 return -EINVAL; 2505 } 2506 start_reg = (idx_value << 2) + PACKET3_SET_SAMPLER_START; 2507 end_reg = 4 * pkt->count + start_reg - 4; 2508 if ((start_reg < PACKET3_SET_SAMPLER_START) || 2509 (start_reg >= PACKET3_SET_SAMPLER_END) || 2510 (end_reg >= PACKET3_SET_SAMPLER_END)) { 2511 DRM_ERROR("bad SET_SAMPLER\n"); 2512 return -EINVAL; 2513 } 2514 break; 2515 case PACKET3_STRMOUT_BUFFER_UPDATE: 2516 if (pkt->count != 4) { 2517 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (invalid count)\n"); 2518 return -EINVAL; 2519 } 2520 /* Updating memory at DST_ADDRESS. */ 2521 if (idx_value & 0x1) { 2522 u64 offset; 2523 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 2524 if (r) { 2525 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing dst reloc)\n"); 2526 return -EINVAL; 2527 } 2528 offset = radeon_get_ib_value(p, idx+1); 2529 offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32; 2530 if ((offset + 4) > radeon_bo_size(reloc->robj)) { 2531 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE dst bo too small: 0x%"PRIx64", 0x%lx\n", 2532 offset + 4, radeon_bo_size(reloc->robj)); 2533 return -EINVAL; 2534 } 2535 offset += reloc->gpu_offset; 2536 ib[idx+1] = offset; 2537 ib[idx+2] = upper_32_bits(offset) & 0xff; 2538 } 2539 /* Reading data from SRC_ADDRESS. */ 2540 if (((idx_value >> 1) & 0x3) == 2) { 2541 u64 offset; 2542 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 2543 if (r) { 2544 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing src reloc)\n"); 2545 return -EINVAL; 2546 } 2547 offset = radeon_get_ib_value(p, idx+3); 2548 offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; 2549 if ((offset + 4) > radeon_bo_size(reloc->robj)) { 2550 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE src bo too small: 0x%"PRIx64", 0x%lx\n", 2551 offset + 4, radeon_bo_size(reloc->robj)); 2552 return -EINVAL; 2553 } 2554 offset += reloc->gpu_offset; 2555 ib[idx+3] = offset; 2556 ib[idx+4] = upper_32_bits(offset) & 0xff; 2557 } 2558 break; 2559 case PACKET3_MEM_WRITE: 2560 { 2561 u64 offset; 2562 2563 if (pkt->count != 3) { 2564 DRM_ERROR("bad MEM_WRITE (invalid count)\n"); 2565 return -EINVAL; 2566 } 2567 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 2568 if (r) { 2569 DRM_ERROR("bad MEM_WRITE (missing reloc)\n"); 2570 return -EINVAL; 2571 } 2572 offset = radeon_get_ib_value(p, idx+0); 2573 offset += ((u64)(radeon_get_ib_value(p, idx+1) & 0xff)) << 32UL; 2574 if (offset & 0x7) { 2575 DRM_ERROR("bad MEM_WRITE (address not qwords aligned)\n"); 2576 return -EINVAL; 2577 } 2578 if ((offset + 8) > radeon_bo_size(reloc->robj)) { 2579 DRM_ERROR("bad MEM_WRITE bo too small: 0x%"PRIx64", 0x%lx\n", 2580 offset + 8, radeon_bo_size(reloc->robj)); 2581 return -EINVAL; 2582 } 2583 offset += reloc->gpu_offset; 2584 ib[idx+0] = offset; 2585 ib[idx+1] = upper_32_bits(offset) & 0xff; 2586 break; 2587 } 2588 case PACKET3_COPY_DW: 2589 if (pkt->count != 4) { 2590 DRM_ERROR("bad COPY_DW (invalid count)\n"); 2591 return -EINVAL; 2592 } 2593 if (idx_value & 0x1) { 2594 u64 offset; 2595 /* SRC is memory. */ 2596 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 2597 if (r) { 2598 DRM_ERROR("bad COPY_DW (missing src reloc)\n"); 2599 return -EINVAL; 2600 } 2601 offset = radeon_get_ib_value(p, idx+1); 2602 offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32; 2603 if ((offset + 4) > radeon_bo_size(reloc->robj)) { 2604 DRM_ERROR("bad COPY_DW src bo too small: 0x%"PRIx64", 0x%lx\n", 2605 offset + 4, radeon_bo_size(reloc->robj)); 2606 return -EINVAL; 2607 } 2608 offset += reloc->gpu_offset; 2609 ib[idx+1] = offset; 2610 ib[idx+2] = upper_32_bits(offset) & 0xff; 2611 } else { 2612 /* SRC is a reg. */ 2613 reg = radeon_get_ib_value(p, idx+1) << 2; 2614 if (!evergreen_is_safe_reg(p, reg)) { 2615 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", 2616 reg, idx + 1); 2617 return -EINVAL; 2618 } 2619 } 2620 if (idx_value & 0x2) { 2621 u64 offset; 2622 /* DST is memory. */ 2623 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 2624 if (r) { 2625 DRM_ERROR("bad COPY_DW (missing dst reloc)\n"); 2626 return -EINVAL; 2627 } 2628 offset = radeon_get_ib_value(p, idx+3); 2629 offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; 2630 if ((offset + 4) > radeon_bo_size(reloc->robj)) { 2631 DRM_ERROR("bad COPY_DW dst bo too small: 0x%"PRIx64", 0x%lx\n", 2632 offset + 4, radeon_bo_size(reloc->robj)); 2633 return -EINVAL; 2634 } 2635 offset += reloc->gpu_offset; 2636 ib[idx+3] = offset; 2637 ib[idx+4] = upper_32_bits(offset) & 0xff; 2638 } else { 2639 /* DST is a reg. */ 2640 reg = radeon_get_ib_value(p, idx+3) << 2; 2641 if (!evergreen_is_safe_reg(p, reg)) { 2642 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", 2643 reg, idx + 3); 2644 return -EINVAL; 2645 } 2646 } 2647 break; 2648 case PACKET3_NOP: 2649 break; 2650 default: 2651 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode); 2652 return -EINVAL; 2653 } 2654 return 0; 2655 } 2656 2657 int evergreen_cs_parse(struct radeon_cs_parser *p) 2658 { 2659 struct radeon_cs_packet pkt; 2660 struct evergreen_cs_track *track; 2661 u32 tmp; 2662 int r; 2663 2664 if (p->track == NULL) { 2665 /* initialize tracker, we are in kms */ 2666 track = kzalloc(sizeof(*track), GFP_KERNEL); 2667 if (track == NULL) 2668 return -ENOMEM; 2669 evergreen_cs_track_init(track); 2670 if (p->rdev->family >= CHIP_CAYMAN) { 2671 tmp = p->rdev->config.cayman.tile_config; 2672 track->reg_safe_bm = cayman_reg_safe_bm; 2673 } else { 2674 tmp = p->rdev->config.evergreen.tile_config; 2675 track->reg_safe_bm = evergreen_reg_safe_bm; 2676 } 2677 BUILD_BUG_ON(ARRAY_SIZE(cayman_reg_safe_bm) != REG_SAFE_BM_SIZE); 2678 BUILD_BUG_ON(ARRAY_SIZE(evergreen_reg_safe_bm) != REG_SAFE_BM_SIZE); 2679 switch (tmp & 0xf) { 2680 case 0: 2681 track->npipes = 1; 2682 break; 2683 case 1: 2684 default: 2685 track->npipes = 2; 2686 break; 2687 case 2: 2688 track->npipes = 4; 2689 break; 2690 case 3: 2691 track->npipes = 8; 2692 break; 2693 } 2694 2695 switch ((tmp & 0xf0) >> 4) { 2696 case 0: 2697 track->nbanks = 4; 2698 break; 2699 case 1: 2700 default: 2701 track->nbanks = 8; 2702 break; 2703 case 2: 2704 track->nbanks = 16; 2705 break; 2706 } 2707 2708 switch ((tmp & 0xf00) >> 8) { 2709 case 0: 2710 track->group_size = 256; 2711 break; 2712 case 1: 2713 default: 2714 track->group_size = 512; 2715 break; 2716 } 2717 2718 switch ((tmp & 0xf000) >> 12) { 2719 case 0: 2720 track->row_size = 1; 2721 break; 2722 case 1: 2723 default: 2724 track->row_size = 2; 2725 break; 2726 case 2: 2727 track->row_size = 4; 2728 break; 2729 } 2730 2731 p->track = track; 2732 } 2733 do { 2734 r = radeon_cs_packet_parse(p, &pkt, p->idx); 2735 if (r) { 2736 kfree(p->track); 2737 p->track = NULL; 2738 return r; 2739 } 2740 p->idx += pkt.count + 2; 2741 switch (pkt.type) { 2742 case RADEON_PACKET_TYPE0: 2743 r = evergreen_cs_parse_packet0(p, &pkt); 2744 break; 2745 case RADEON_PACKET_TYPE2: 2746 break; 2747 case RADEON_PACKET_TYPE3: 2748 r = evergreen_packet3_check(p, &pkt); 2749 break; 2750 default: 2751 DRM_ERROR("Unknown packet type %d !\n", pkt.type); 2752 kfree(p->track); 2753 p->track = NULL; 2754 return -EINVAL; 2755 } 2756 if (r) { 2757 kfree(p->track); 2758 p->track = NULL; 2759 return r; 2760 } 2761 } while (p->idx < p->chunk_ib->length_dw); 2762 #if 0 2763 for (r = 0; r < p->ib.length_dw; r++) { 2764 printk(KERN_INFO "%05d 0x%08X\n", r, p->ib.ptr[r]); 2765 mdelay(1); 2766 } 2767 #endif 2768 kfree(p->track); 2769 p->track = NULL; 2770 return 0; 2771 } 2772 2773 /** 2774 * evergreen_dma_cs_parse() - parse the DMA IB 2775 * @p: parser structure holding parsing context. 2776 * 2777 * Parses the DMA IB from the CS ioctl and updates 2778 * the GPU addresses based on the reloc information and 2779 * checks for errors. (Evergreen-Cayman) 2780 * Returns 0 for success and an error on failure. 2781 **/ 2782 int evergreen_dma_cs_parse(struct radeon_cs_parser *p) 2783 { 2784 struct radeon_cs_chunk *ib_chunk = p->chunk_ib; 2785 struct radeon_bo_list *src_reloc, *dst_reloc, *dst2_reloc; 2786 u32 header, cmd, count, sub_cmd; 2787 uint32_t *ib = p->ib.ptr; 2788 u32 idx; 2789 u64 src_offset, dst_offset, dst2_offset; 2790 int r; 2791 2792 do { 2793 if (p->idx >= ib_chunk->length_dw) { 2794 DRM_ERROR("Can not parse packet at %d after CS end %d !\n", 2795 p->idx, ib_chunk->length_dw); 2796 return -EINVAL; 2797 } 2798 idx = p->idx; 2799 header = radeon_get_ib_value(p, idx); 2800 cmd = GET_DMA_CMD(header); 2801 count = GET_DMA_COUNT(header); 2802 sub_cmd = GET_DMA_SUB_CMD(header); 2803 2804 switch (cmd) { 2805 case DMA_PACKET_WRITE: 2806 r = r600_dma_cs_next_reloc(p, &dst_reloc); 2807 if (r) { 2808 DRM_ERROR("bad DMA_PACKET_WRITE\n"); 2809 return -EINVAL; 2810 } 2811 switch (sub_cmd) { 2812 /* tiled */ 2813 case 8: 2814 dst_offset = radeon_get_ib_value(p, idx+1); 2815 dst_offset <<= 8; 2816 2817 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); 2818 p->idx += count + 7; 2819 break; 2820 /* linear */ 2821 case 0: 2822 dst_offset = radeon_get_ib_value(p, idx+1); 2823 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32; 2824 2825 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); 2826 ib[idx+2] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; 2827 p->idx += count + 3; 2828 break; 2829 default: 2830 DRM_ERROR("bad DMA_PACKET_WRITE [%6d] 0x%08x sub cmd is not 0 or 8\n", idx, header); 2831 return -EINVAL; 2832 } 2833 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { 2834 dev_warn(p->dev, "DMA write buffer too small (%"PRIu64" %lu)\n", 2835 dst_offset, radeon_bo_size(dst_reloc->robj)); 2836 return -EINVAL; 2837 } 2838 break; 2839 case DMA_PACKET_COPY: 2840 r = r600_dma_cs_next_reloc(p, &src_reloc); 2841 if (r) { 2842 DRM_ERROR("bad DMA_PACKET_COPY\n"); 2843 return -EINVAL; 2844 } 2845 r = r600_dma_cs_next_reloc(p, &dst_reloc); 2846 if (r) { 2847 DRM_ERROR("bad DMA_PACKET_COPY\n"); 2848 return -EINVAL; 2849 } 2850 switch (sub_cmd) { 2851 /* Copy L2L, DW aligned */ 2852 case 0x00: 2853 /* L2L, dw */ 2854 src_offset = radeon_get_ib_value(p, idx+2); 2855 src_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; 2856 dst_offset = radeon_get_ib_value(p, idx+1); 2857 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32; 2858 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) { 2859 dev_warn(p->dev, "DMA L2L, dw src buffer too small (%"PRIu64" %lu)\n", 2860 src_offset + (count * 4), radeon_bo_size(src_reloc->robj)); 2861 return -EINVAL; 2862 } 2863 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { 2864 dev_warn(p->dev, "DMA L2L, dw dst buffer too small (%"PRIu64" %lu)\n", 2865 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); 2866 return -EINVAL; 2867 } 2868 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); 2869 ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xfffffffc); 2870 ib[idx+3] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; 2871 ib[idx+4] += upper_32_bits(src_reloc->gpu_offset) & 0xff; 2872 p->idx += 5; 2873 break; 2874 /* Copy L2T/T2L */ 2875 case 0x08: 2876 /* detile bit */ 2877 if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) { 2878 /* tiled src, linear dst */ 2879 src_offset = radeon_get_ib_value(p, idx+1); 2880 src_offset <<= 8; 2881 ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8); 2882 2883 dst_offset = radeon_get_ib_value(p, idx + 7); 2884 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32; 2885 ib[idx+7] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); 2886 ib[idx+8] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; 2887 } else { 2888 /* linear src, tiled dst */ 2889 src_offset = radeon_get_ib_value(p, idx+7); 2890 src_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32; 2891 ib[idx+7] += (u32)(src_reloc->gpu_offset & 0xfffffffc); 2892 ib[idx+8] += upper_32_bits(src_reloc->gpu_offset) & 0xff; 2893 2894 dst_offset = radeon_get_ib_value(p, idx+1); 2895 dst_offset <<= 8; 2896 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); 2897 } 2898 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) { 2899 dev_warn(p->dev, "DMA L2T, src buffer too small (%"PRIu64" %lu)\n", 2900 src_offset + (count * 4), radeon_bo_size(src_reloc->robj)); 2901 return -EINVAL; 2902 } 2903 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { 2904 dev_warn(p->dev, "DMA L2T, dst buffer too small (%"PRIu64" %lu)\n", 2905 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); 2906 return -EINVAL; 2907 } 2908 p->idx += 9; 2909 break; 2910 /* Copy L2L, byte aligned */ 2911 case 0x40: 2912 /* L2L, byte */ 2913 src_offset = radeon_get_ib_value(p, idx+2); 2914 src_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; 2915 dst_offset = radeon_get_ib_value(p, idx+1); 2916 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32; 2917 if ((src_offset + count) > radeon_bo_size(src_reloc->robj)) { 2918 dev_warn(p->dev, "DMA L2L, byte src buffer too small (%"PRIu64" %lu)\n", 2919 src_offset + count, radeon_bo_size(src_reloc->robj)); 2920 return -EINVAL; 2921 } 2922 if ((dst_offset + count) > radeon_bo_size(dst_reloc->robj)) { 2923 dev_warn(p->dev, "DMA L2L, byte dst buffer too small (%"PRIu64" %lu)\n", 2924 dst_offset + count, radeon_bo_size(dst_reloc->robj)); 2925 return -EINVAL; 2926 } 2927 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xffffffff); 2928 ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xffffffff); 2929 ib[idx+3] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; 2930 ib[idx+4] += upper_32_bits(src_reloc->gpu_offset) & 0xff; 2931 p->idx += 5; 2932 break; 2933 /* Copy L2L, partial */ 2934 case 0x41: 2935 /* L2L, partial */ 2936 if (p->family < CHIP_CAYMAN) { 2937 DRM_ERROR("L2L Partial is cayman only !\n"); 2938 return -EINVAL; 2939 } 2940 ib[idx+1] += (u32)(src_reloc->gpu_offset & 0xffffffff); 2941 ib[idx+2] += upper_32_bits(src_reloc->gpu_offset) & 0xff; 2942 ib[idx+4] += (u32)(dst_reloc->gpu_offset & 0xffffffff); 2943 ib[idx+5] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; 2944 2945 p->idx += 9; 2946 break; 2947 /* Copy L2L, DW aligned, broadcast */ 2948 case 0x44: 2949 /* L2L, dw, broadcast */ 2950 r = r600_dma_cs_next_reloc(p, &dst2_reloc); 2951 if (r) { 2952 DRM_ERROR("bad L2L, dw, broadcast DMA_PACKET_COPY\n"); 2953 return -EINVAL; 2954 } 2955 dst_offset = radeon_get_ib_value(p, idx+1); 2956 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; 2957 dst2_offset = radeon_get_ib_value(p, idx+2); 2958 dst2_offset |= ((u64)(radeon_get_ib_value(p, idx+5) & 0xff)) << 32; 2959 src_offset = radeon_get_ib_value(p, idx+3); 2960 src_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32; 2961 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) { 2962 dev_warn(p->dev, "DMA L2L, dw, broadcast src buffer too small (%"PRIu64" %lu)\n", 2963 src_offset + (count * 4), radeon_bo_size(src_reloc->robj)); 2964 return -EINVAL; 2965 } 2966 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { 2967 dev_warn(p->dev, "DMA L2L, dw, broadcast dst buffer too small (%"PRIu64" %lu)\n", 2968 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); 2969 return -EINVAL; 2970 } 2971 if ((dst2_offset + (count * 4)) > radeon_bo_size(dst2_reloc->robj)) { 2972 dev_warn(p->dev, "DMA L2L, dw, broadcast dst2 buffer too small (%"PRIu64" %lu)\n", 2973 dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj)); 2974 return -EINVAL; 2975 } 2976 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); 2977 ib[idx+2] += (u32)(dst2_reloc->gpu_offset & 0xfffffffc); 2978 ib[idx+3] += (u32)(src_reloc->gpu_offset & 0xfffffffc); 2979 ib[idx+4] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; 2980 ib[idx+5] += upper_32_bits(dst2_reloc->gpu_offset) & 0xff; 2981 ib[idx+6] += upper_32_bits(src_reloc->gpu_offset) & 0xff; 2982 p->idx += 7; 2983 break; 2984 /* Copy L2T Frame to Field */ 2985 case 0x48: 2986 if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) { 2987 DRM_ERROR("bad L2T, frame to fields DMA_PACKET_COPY\n"); 2988 return -EINVAL; 2989 } 2990 r = r600_dma_cs_next_reloc(p, &dst2_reloc); 2991 if (r) { 2992 DRM_ERROR("bad L2T, frame to fields DMA_PACKET_COPY\n"); 2993 return -EINVAL; 2994 } 2995 dst_offset = radeon_get_ib_value(p, idx+1); 2996 dst_offset <<= 8; 2997 dst2_offset = radeon_get_ib_value(p, idx+2); 2998 dst2_offset <<= 8; 2999 src_offset = radeon_get_ib_value(p, idx+8); 3000 src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32; 3001 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) { 3002 dev_warn(p->dev, "DMA L2T, frame to fields src buffer too small (%"PRIu64" %lu)\n", 3003 src_offset + (count * 4), radeon_bo_size(src_reloc->robj)); 3004 return -EINVAL; 3005 } 3006 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { 3007 dev_warn(p->dev, "DMA L2T, frame to fields buffer too small (%"PRIu64" %lu)\n", 3008 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); 3009 return -EINVAL; 3010 } 3011 if ((dst2_offset + (count * 4)) > radeon_bo_size(dst2_reloc->robj)) { 3012 dev_warn(p->dev, "DMA L2T, frame to fields buffer too small (%"PRIu64" %lu)\n", 3013 dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj)); 3014 return -EINVAL; 3015 } 3016 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); 3017 ib[idx+2] += (u32)(dst2_reloc->gpu_offset >> 8); 3018 ib[idx+8] += (u32)(src_reloc->gpu_offset & 0xfffffffc); 3019 ib[idx+9] += upper_32_bits(src_reloc->gpu_offset) & 0xff; 3020 p->idx += 10; 3021 break; 3022 /* Copy L2T/T2L, partial */ 3023 case 0x49: 3024 /* L2T, T2L partial */ 3025 if (p->family < CHIP_CAYMAN) { 3026 DRM_ERROR("L2T, T2L Partial is cayman only !\n"); 3027 return -EINVAL; 3028 } 3029 /* detile bit */ 3030 if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) { 3031 /* tiled src, linear dst */ 3032 ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8); 3033 3034 ib[idx+7] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); 3035 ib[idx+8] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; 3036 } else { 3037 /* linear src, tiled dst */ 3038 ib[idx+7] += (u32)(src_reloc->gpu_offset & 0xfffffffc); 3039 ib[idx+8] += upper_32_bits(src_reloc->gpu_offset) & 0xff; 3040 3041 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); 3042 } 3043 p->idx += 12; 3044 break; 3045 /* Copy L2T broadcast */ 3046 case 0x4b: 3047 /* L2T, broadcast */ 3048 if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) { 3049 DRM_ERROR("bad L2T, broadcast DMA_PACKET_COPY\n"); 3050 return -EINVAL; 3051 } 3052 r = r600_dma_cs_next_reloc(p, &dst2_reloc); 3053 if (r) { 3054 DRM_ERROR("bad L2T, broadcast DMA_PACKET_COPY\n"); 3055 return -EINVAL; 3056 } 3057 dst_offset = radeon_get_ib_value(p, idx+1); 3058 dst_offset <<= 8; 3059 dst2_offset = radeon_get_ib_value(p, idx+2); 3060 dst2_offset <<= 8; 3061 src_offset = radeon_get_ib_value(p, idx+8); 3062 src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32; 3063 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) { 3064 dev_warn(p->dev, "DMA L2T, broadcast src buffer too small (%"PRIu64" %lu)\n", 3065 src_offset + (count * 4), radeon_bo_size(src_reloc->robj)); 3066 return -EINVAL; 3067 } 3068 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { 3069 dev_warn(p->dev, "DMA L2T, broadcast dst buffer too small (%"PRIu64" %lu)\n", 3070 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); 3071 return -EINVAL; 3072 } 3073 if ((dst2_offset + (count * 4)) > radeon_bo_size(dst2_reloc->robj)) { 3074 dev_warn(p->dev, "DMA L2T, broadcast dst2 buffer too small (%"PRIu64" %lu)\n", 3075 dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj)); 3076 return -EINVAL; 3077 } 3078 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); 3079 ib[idx+2] += (u32)(dst2_reloc->gpu_offset >> 8); 3080 ib[idx+8] += (u32)(src_reloc->gpu_offset & 0xfffffffc); 3081 ib[idx+9] += upper_32_bits(src_reloc->gpu_offset) & 0xff; 3082 p->idx += 10; 3083 break; 3084 /* Copy L2T/T2L (tile units) */ 3085 case 0x4c: 3086 /* L2T, T2L */ 3087 /* detile bit */ 3088 if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) { 3089 /* tiled src, linear dst */ 3090 src_offset = radeon_get_ib_value(p, idx+1); 3091 src_offset <<= 8; 3092 ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8); 3093 3094 dst_offset = radeon_get_ib_value(p, idx+7); 3095 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32; 3096 ib[idx+7] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); 3097 ib[idx+8] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; 3098 } else { 3099 /* linear src, tiled dst */ 3100 src_offset = radeon_get_ib_value(p, idx+7); 3101 src_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32; 3102 ib[idx+7] += (u32)(src_reloc->gpu_offset & 0xfffffffc); 3103 ib[idx+8] += upper_32_bits(src_reloc->gpu_offset) & 0xff; 3104 3105 dst_offset = radeon_get_ib_value(p, idx+1); 3106 dst_offset <<= 8; 3107 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); 3108 } 3109 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) { 3110 dev_warn(p->dev, "DMA L2T, T2L src buffer too small (%"PRIu64" %lu)\n", 3111 src_offset + (count * 4), radeon_bo_size(src_reloc->robj)); 3112 return -EINVAL; 3113 } 3114 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { 3115 dev_warn(p->dev, "DMA L2T, T2L dst buffer too small (%"PRIu64" %lu)\n", 3116 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); 3117 return -EINVAL; 3118 } 3119 p->idx += 9; 3120 break; 3121 /* Copy T2T, partial (tile units) */ 3122 case 0x4d: 3123 /* T2T partial */ 3124 if (p->family < CHIP_CAYMAN) { 3125 DRM_ERROR("L2T, T2L Partial is cayman only !\n"); 3126 return -EINVAL; 3127 } 3128 ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8); 3129 ib[idx+4] += (u32)(dst_reloc->gpu_offset >> 8); 3130 p->idx += 13; 3131 break; 3132 /* Copy L2T broadcast (tile units) */ 3133 case 0x4f: 3134 /* L2T, broadcast */ 3135 if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) { 3136 DRM_ERROR("bad L2T, broadcast DMA_PACKET_COPY\n"); 3137 return -EINVAL; 3138 } 3139 r = r600_dma_cs_next_reloc(p, &dst2_reloc); 3140 if (r) { 3141 DRM_ERROR("bad L2T, broadcast DMA_PACKET_COPY\n"); 3142 return -EINVAL; 3143 } 3144 dst_offset = radeon_get_ib_value(p, idx+1); 3145 dst_offset <<= 8; 3146 dst2_offset = radeon_get_ib_value(p, idx+2); 3147 dst2_offset <<= 8; 3148 src_offset = radeon_get_ib_value(p, idx+8); 3149 src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32; 3150 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) { 3151 dev_warn(p->dev, "DMA L2T, broadcast src buffer too small (%"PRIu64" %lu)\n", 3152 src_offset + (count * 4), radeon_bo_size(src_reloc->robj)); 3153 return -EINVAL; 3154 } 3155 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { 3156 dev_warn(p->dev, "DMA L2T, broadcast dst buffer too small (%"PRIu64" %lu)\n", 3157 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); 3158 return -EINVAL; 3159 } 3160 if ((dst2_offset + (count * 4)) > radeon_bo_size(dst2_reloc->robj)) { 3161 dev_warn(p->dev, "DMA L2T, broadcast dst2 buffer too small (%"PRIu64" %lu)\n", 3162 dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj)); 3163 return -EINVAL; 3164 } 3165 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); 3166 ib[idx+2] += (u32)(dst2_reloc->gpu_offset >> 8); 3167 ib[idx+8] += (u32)(src_reloc->gpu_offset & 0xfffffffc); 3168 ib[idx+9] += upper_32_bits(src_reloc->gpu_offset) & 0xff; 3169 p->idx += 10; 3170 break; 3171 default: 3172 DRM_ERROR("bad DMA_PACKET_COPY [%6d] 0x%08x invalid sub cmd\n", idx, header); 3173 return -EINVAL; 3174 } 3175 break; 3176 case DMA_PACKET_CONSTANT_FILL: 3177 r = r600_dma_cs_next_reloc(p, &dst_reloc); 3178 if (r) { 3179 DRM_ERROR("bad DMA_PACKET_CONSTANT_FILL\n"); 3180 return -EINVAL; 3181 } 3182 dst_offset = radeon_get_ib_value(p, idx+1); 3183 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0x00ff0000)) << 16; 3184 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { 3185 dev_warn(p->dev, "DMA constant fill buffer too small (%"PRIu64" %lu)\n", 3186 dst_offset, radeon_bo_size(dst_reloc->robj)); 3187 return -EINVAL; 3188 } 3189 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); 3190 ib[idx+3] += (upper_32_bits(dst_reloc->gpu_offset) << 16) & 0x00ff0000; 3191 p->idx += 4; 3192 break; 3193 case DMA_PACKET_NOP: 3194 p->idx += 1; 3195 break; 3196 default: 3197 DRM_ERROR("Unknown packet type %d at %d !\n", cmd, idx); 3198 return -EINVAL; 3199 } 3200 } while (p->idx < p->chunk_ib->length_dw); 3201 #if 0 3202 for (r = 0; r < p->ib->length_dw; r++) { 3203 printk(KERN_INFO "%05d 0x%08X\n", r, p->ib.ptr[r]); 3204 mdelay(1); 3205 } 3206 #endif 3207 return 0; 3208 } 3209 3210 /* vm parser */ 3211 static bool evergreen_vm_reg_valid(u32 reg) 3212 { 3213 /* context regs are fine */ 3214 if (reg >= 0x28000) 3215 return true; 3216 3217 /* check config regs */ 3218 switch (reg) { 3219 case WAIT_UNTIL: 3220 case GRBM_GFX_INDEX: 3221 case CP_STRMOUT_CNTL: 3222 case CP_COHER_CNTL: 3223 case CP_COHER_SIZE: 3224 case VGT_VTX_VECT_EJECT_REG: 3225 case VGT_CACHE_INVALIDATION: 3226 case VGT_GS_VERTEX_REUSE: 3227 case VGT_PRIMITIVE_TYPE: 3228 case VGT_INDEX_TYPE: 3229 case VGT_NUM_INDICES: 3230 case VGT_NUM_INSTANCES: 3231 case VGT_COMPUTE_DIM_X: 3232 case VGT_COMPUTE_DIM_Y: 3233 case VGT_COMPUTE_DIM_Z: 3234 case VGT_COMPUTE_START_X: 3235 case VGT_COMPUTE_START_Y: 3236 case VGT_COMPUTE_START_Z: 3237 case VGT_COMPUTE_INDEX: 3238 case VGT_COMPUTE_THREAD_GROUP_SIZE: 3239 case VGT_HS_OFFCHIP_PARAM: 3240 case PA_CL_ENHANCE: 3241 case PA_SU_LINE_STIPPLE_VALUE: 3242 case PA_SC_LINE_STIPPLE_STATE: 3243 case PA_SC_ENHANCE: 3244 case SQ_DYN_GPR_CNTL_PS_FLUSH_REQ: 3245 case SQ_DYN_GPR_SIMD_LOCK_EN: 3246 case SQ_CONFIG: 3247 case SQ_GPR_RESOURCE_MGMT_1: 3248 case SQ_GLOBAL_GPR_RESOURCE_MGMT_1: 3249 case SQ_GLOBAL_GPR_RESOURCE_MGMT_2: 3250 case SQ_CONST_MEM_BASE: 3251 case SQ_STATIC_THREAD_MGMT_1: 3252 case SQ_STATIC_THREAD_MGMT_2: 3253 case SQ_STATIC_THREAD_MGMT_3: 3254 case SPI_CONFIG_CNTL: 3255 case SPI_CONFIG_CNTL_1: 3256 case TA_CNTL_AUX: 3257 case DB_DEBUG: 3258 case DB_DEBUG2: 3259 case DB_DEBUG3: 3260 case DB_DEBUG4: 3261 case DB_WATERMARKS: 3262 case TD_PS_BORDER_COLOR_INDEX: 3263 case TD_PS_BORDER_COLOR_RED: 3264 case TD_PS_BORDER_COLOR_GREEN: 3265 case TD_PS_BORDER_COLOR_BLUE: 3266 case TD_PS_BORDER_COLOR_ALPHA: 3267 case TD_VS_BORDER_COLOR_INDEX: 3268 case TD_VS_BORDER_COLOR_RED: 3269 case TD_VS_BORDER_COLOR_GREEN: 3270 case TD_VS_BORDER_COLOR_BLUE: 3271 case TD_VS_BORDER_COLOR_ALPHA: 3272 case TD_GS_BORDER_COLOR_INDEX: 3273 case TD_GS_BORDER_COLOR_RED: 3274 case TD_GS_BORDER_COLOR_GREEN: 3275 case TD_GS_BORDER_COLOR_BLUE: 3276 case TD_GS_BORDER_COLOR_ALPHA: 3277 case TD_HS_BORDER_COLOR_INDEX: 3278 case TD_HS_BORDER_COLOR_RED: 3279 case TD_HS_BORDER_COLOR_GREEN: 3280 case TD_HS_BORDER_COLOR_BLUE: 3281 case TD_HS_BORDER_COLOR_ALPHA: 3282 case TD_LS_BORDER_COLOR_INDEX: 3283 case TD_LS_BORDER_COLOR_RED: 3284 case TD_LS_BORDER_COLOR_GREEN: 3285 case TD_LS_BORDER_COLOR_BLUE: 3286 case TD_LS_BORDER_COLOR_ALPHA: 3287 case TD_CS_BORDER_COLOR_INDEX: 3288 case TD_CS_BORDER_COLOR_RED: 3289 case TD_CS_BORDER_COLOR_GREEN: 3290 case TD_CS_BORDER_COLOR_BLUE: 3291 case TD_CS_BORDER_COLOR_ALPHA: 3292 case SQ_ESGS_RING_SIZE: 3293 case SQ_GSVS_RING_SIZE: 3294 case SQ_ESTMP_RING_SIZE: 3295 case SQ_GSTMP_RING_SIZE: 3296 case SQ_HSTMP_RING_SIZE: 3297 case SQ_LSTMP_RING_SIZE: 3298 case SQ_PSTMP_RING_SIZE: 3299 case SQ_VSTMP_RING_SIZE: 3300 case SQ_ESGS_RING_ITEMSIZE: 3301 case SQ_ESTMP_RING_ITEMSIZE: 3302 case SQ_GSTMP_RING_ITEMSIZE: 3303 case SQ_GSVS_RING_ITEMSIZE: 3304 case SQ_GS_VERT_ITEMSIZE: 3305 case SQ_GS_VERT_ITEMSIZE_1: 3306 case SQ_GS_VERT_ITEMSIZE_2: 3307 case SQ_GS_VERT_ITEMSIZE_3: 3308 case SQ_GSVS_RING_OFFSET_1: 3309 case SQ_GSVS_RING_OFFSET_2: 3310 case SQ_GSVS_RING_OFFSET_3: 3311 case SQ_HSTMP_RING_ITEMSIZE: 3312 case SQ_LSTMP_RING_ITEMSIZE: 3313 case SQ_PSTMP_RING_ITEMSIZE: 3314 case SQ_VSTMP_RING_ITEMSIZE: 3315 case VGT_TF_RING_SIZE: 3316 case SQ_ESGS_RING_BASE: 3317 case SQ_GSVS_RING_BASE: 3318 case SQ_ESTMP_RING_BASE: 3319 case SQ_GSTMP_RING_BASE: 3320 case SQ_HSTMP_RING_BASE: 3321 case SQ_LSTMP_RING_BASE: 3322 case SQ_PSTMP_RING_BASE: 3323 case SQ_VSTMP_RING_BASE: 3324 case CAYMAN_VGT_OFFCHIP_LDS_BASE: 3325 case CAYMAN_SQ_EX_ALLOC_TABLE_SLOTS: 3326 return true; 3327 default: 3328 DRM_ERROR("Invalid register 0x%x in CS\n", reg); 3329 return false; 3330 } 3331 } 3332 3333 static int evergreen_vm_packet3_check(struct radeon_device *rdev, 3334 u32 *ib, struct radeon_cs_packet *pkt) 3335 { 3336 u32 idx = pkt->idx + 1; 3337 u32 idx_value = ib[idx]; 3338 u32 start_reg, end_reg, reg, i; 3339 u32 command, info; 3340 3341 switch (pkt->opcode) { 3342 case PACKET3_NOP: 3343 break; 3344 case PACKET3_SET_BASE: 3345 if (idx_value != 1) { 3346 DRM_ERROR("bad SET_BASE"); 3347 return -EINVAL; 3348 } 3349 break; 3350 case PACKET3_CLEAR_STATE: 3351 case PACKET3_INDEX_BUFFER_SIZE: 3352 case PACKET3_DISPATCH_DIRECT: 3353 case PACKET3_DISPATCH_INDIRECT: 3354 case PACKET3_MODE_CONTROL: 3355 case PACKET3_SET_PREDICATION: 3356 case PACKET3_COND_EXEC: 3357 case PACKET3_PRED_EXEC: 3358 case PACKET3_DRAW_INDIRECT: 3359 case PACKET3_DRAW_INDEX_INDIRECT: 3360 case PACKET3_INDEX_BASE: 3361 case PACKET3_DRAW_INDEX_2: 3362 case PACKET3_CONTEXT_CONTROL: 3363 case PACKET3_DRAW_INDEX_OFFSET: 3364 case PACKET3_INDEX_TYPE: 3365 case PACKET3_DRAW_INDEX: 3366 case PACKET3_DRAW_INDEX_AUTO: 3367 case PACKET3_DRAW_INDEX_IMMD: 3368 case PACKET3_NUM_INSTANCES: 3369 case PACKET3_DRAW_INDEX_MULTI_AUTO: 3370 case PACKET3_STRMOUT_BUFFER_UPDATE: 3371 case PACKET3_DRAW_INDEX_OFFSET_2: 3372 case PACKET3_DRAW_INDEX_MULTI_ELEMENT: 3373 case PACKET3_MPEG_INDEX: 3374 case PACKET3_WAIT_REG_MEM: 3375 case PACKET3_MEM_WRITE: 3376 case PACKET3_SURFACE_SYNC: 3377 case PACKET3_EVENT_WRITE: 3378 case PACKET3_EVENT_WRITE_EOP: 3379 case PACKET3_EVENT_WRITE_EOS: 3380 case PACKET3_SET_CONTEXT_REG: 3381 case PACKET3_SET_BOOL_CONST: 3382 case PACKET3_SET_LOOP_CONST: 3383 case PACKET3_SET_RESOURCE: 3384 case PACKET3_SET_SAMPLER: 3385 case PACKET3_SET_CTL_CONST: 3386 case PACKET3_SET_RESOURCE_OFFSET: 3387 case PACKET3_SET_CONTEXT_REG_INDIRECT: 3388 case PACKET3_SET_RESOURCE_INDIRECT: 3389 case CAYMAN_PACKET3_DEALLOC_STATE: 3390 break; 3391 case PACKET3_COND_WRITE: 3392 if (idx_value & 0x100) { 3393 reg = ib[idx + 5] * 4; 3394 if (!evergreen_vm_reg_valid(reg)) 3395 return -EINVAL; 3396 } 3397 break; 3398 case PACKET3_COPY_DW: 3399 if (idx_value & 0x2) { 3400 reg = ib[idx + 3] * 4; 3401 if (!evergreen_vm_reg_valid(reg)) 3402 return -EINVAL; 3403 } 3404 break; 3405 case PACKET3_SET_CONFIG_REG: 3406 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START; 3407 end_reg = 4 * pkt->count + start_reg - 4; 3408 if ((start_reg < PACKET3_SET_CONFIG_REG_START) || 3409 (start_reg >= PACKET3_SET_CONFIG_REG_END) || 3410 (end_reg >= PACKET3_SET_CONFIG_REG_END)) { 3411 DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n"); 3412 return -EINVAL; 3413 } 3414 for (i = 0; i < pkt->count; i++) { 3415 reg = start_reg + (4 * i); 3416 if (!evergreen_vm_reg_valid(reg)) 3417 return -EINVAL; 3418 } 3419 break; 3420 case PACKET3_CP_DMA: 3421 command = ib[idx + 4]; 3422 info = ib[idx + 1]; 3423 if ((((info & 0x60000000) >> 29) != 0) || /* src = GDS or DATA */ 3424 (((info & 0x00300000) >> 20) != 0) || /* dst = GDS */ 3425 ((((info & 0x00300000) >> 20) == 0) && 3426 (command & PACKET3_CP_DMA_CMD_DAS)) || /* dst = register */ 3427 ((((info & 0x60000000) >> 29) == 0) && 3428 (command & PACKET3_CP_DMA_CMD_SAS))) { /* src = register */ 3429 /* non mem to mem copies requires dw aligned count */ 3430 if ((command & 0x1fffff) % 4) { 3431 DRM_ERROR("CP DMA command requires dw count alignment\n"); 3432 return -EINVAL; 3433 } 3434 } 3435 if (command & PACKET3_CP_DMA_CMD_SAS) { 3436 /* src address space is register */ 3437 if (((info & 0x60000000) >> 29) == 0) { 3438 start_reg = idx_value << 2; 3439 if (command & PACKET3_CP_DMA_CMD_SAIC) { 3440 reg = start_reg; 3441 if (!evergreen_vm_reg_valid(reg)) { 3442 DRM_ERROR("CP DMA Bad SRC register\n"); 3443 return -EINVAL; 3444 } 3445 } else { 3446 for (i = 0; i < (command & 0x1fffff); i++) { 3447 reg = start_reg + (4 * i); 3448 if (!evergreen_vm_reg_valid(reg)) { 3449 DRM_ERROR("CP DMA Bad SRC register\n"); 3450 return -EINVAL; 3451 } 3452 } 3453 } 3454 } 3455 } 3456 if (command & PACKET3_CP_DMA_CMD_DAS) { 3457 /* dst address space is register */ 3458 if (((info & 0x00300000) >> 20) == 0) { 3459 start_reg = ib[idx + 2]; 3460 if (command & PACKET3_CP_DMA_CMD_DAIC) { 3461 reg = start_reg; 3462 if (!evergreen_vm_reg_valid(reg)) { 3463 DRM_ERROR("CP DMA Bad DST register\n"); 3464 return -EINVAL; 3465 } 3466 } else { 3467 for (i = 0; i < (command & 0x1fffff); i++) { 3468 reg = start_reg + (4 * i); 3469 if (!evergreen_vm_reg_valid(reg)) { 3470 DRM_ERROR("CP DMA Bad DST register\n"); 3471 return -EINVAL; 3472 } 3473 } 3474 } 3475 } 3476 } 3477 break; 3478 default: 3479 return -EINVAL; 3480 } 3481 return 0; 3482 } 3483 3484 int evergreen_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib) 3485 { 3486 int ret = 0; 3487 u32 idx = 0; 3488 struct radeon_cs_packet pkt; 3489 3490 do { 3491 pkt.idx = idx; 3492 pkt.type = RADEON_CP_PACKET_GET_TYPE(ib->ptr[idx]); 3493 pkt.count = RADEON_CP_PACKET_GET_COUNT(ib->ptr[idx]); 3494 pkt.one_reg_wr = 0; 3495 switch (pkt.type) { 3496 case RADEON_PACKET_TYPE0: 3497 dev_err(rdev->dev, "Packet0 not allowed!\n"); 3498 ret = -EINVAL; 3499 break; 3500 case RADEON_PACKET_TYPE2: 3501 idx += 1; 3502 break; 3503 case RADEON_PACKET_TYPE3: 3504 pkt.opcode = RADEON_CP_PACKET3_GET_OPCODE(ib->ptr[idx]); 3505 ret = evergreen_vm_packet3_check(rdev, ib->ptr, &pkt); 3506 idx += pkt.count + 2; 3507 break; 3508 default: 3509 dev_err(rdev->dev, "Unknown packet type %d !\n", pkt.type); 3510 ret = -EINVAL; 3511 break; 3512 } 3513 if (ret) 3514 break; 3515 } while (idx < ib->length_dw); 3516 3517 return ret; 3518 } 3519 3520 /** 3521 * evergreen_dma_ib_parse() - parse the DMA IB for VM 3522 * @rdev: radeon_device pointer 3523 * @ib: radeon_ib pointer 3524 * 3525 * Parses the DMA IB from the VM CS ioctl 3526 * checks for errors. (Cayman-SI) 3527 * Returns 0 for success and an error on failure. 3528 **/ 3529 int evergreen_dma_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib) 3530 { 3531 u32 idx = 0; 3532 u32 header, cmd, count, sub_cmd; 3533 3534 do { 3535 header = ib->ptr[idx]; 3536 cmd = GET_DMA_CMD(header); 3537 count = GET_DMA_COUNT(header); 3538 sub_cmd = GET_DMA_SUB_CMD(header); 3539 3540 switch (cmd) { 3541 case DMA_PACKET_WRITE: 3542 switch (sub_cmd) { 3543 /* tiled */ 3544 case 8: 3545 idx += count + 7; 3546 break; 3547 /* linear */ 3548 case 0: 3549 idx += count + 3; 3550 break; 3551 default: 3552 DRM_ERROR("bad DMA_PACKET_WRITE [%6d] 0x%08x sub cmd is not 0 or 8\n", idx, ib->ptr[idx]); 3553 return -EINVAL; 3554 } 3555 break; 3556 case DMA_PACKET_COPY: 3557 switch (sub_cmd) { 3558 /* Copy L2L, DW aligned */ 3559 case 0x00: 3560 idx += 5; 3561 break; 3562 /* Copy L2T/T2L */ 3563 case 0x08: 3564 idx += 9; 3565 break; 3566 /* Copy L2L, byte aligned */ 3567 case 0x40: 3568 idx += 5; 3569 break; 3570 /* Copy L2L, partial */ 3571 case 0x41: 3572 idx += 9; 3573 break; 3574 /* Copy L2L, DW aligned, broadcast */ 3575 case 0x44: 3576 idx += 7; 3577 break; 3578 /* Copy L2T Frame to Field */ 3579 case 0x48: 3580 idx += 10; 3581 break; 3582 /* Copy L2T/T2L, partial */ 3583 case 0x49: 3584 idx += 12; 3585 break; 3586 /* Copy L2T broadcast */ 3587 case 0x4b: 3588 idx += 10; 3589 break; 3590 /* Copy L2T/T2L (tile units) */ 3591 case 0x4c: 3592 idx += 9; 3593 break; 3594 /* Copy T2T, partial (tile units) */ 3595 case 0x4d: 3596 idx += 13; 3597 break; 3598 /* Copy L2T broadcast (tile units) */ 3599 case 0x4f: 3600 idx += 10; 3601 break; 3602 default: 3603 DRM_ERROR("bad DMA_PACKET_COPY [%6d] 0x%08x invalid sub cmd\n", idx, ib->ptr[idx]); 3604 return -EINVAL; 3605 } 3606 break; 3607 case DMA_PACKET_CONSTANT_FILL: 3608 idx += 4; 3609 break; 3610 case DMA_PACKET_NOP: 3611 idx += 1; 3612 break; 3613 default: 3614 DRM_ERROR("Unknown packet type %d at %d !\n", cmd, idx); 3615 return -EINVAL; 3616 } 3617 } while (idx < ib->length_dw); 3618 3619 return 0; 3620 } 3621
Indexes created Sat Oct 25 16:10:12 GMT 2025