radeon_i2c.c revision 1.1.1.2
1 /* $NetBSD: radeon_i2c.c,v 1.1.1.2 2018/08/27 01:34:58 riastradh Exp $ */ 2 3 /* 4 * Copyright 2007-8 Advanced Micro Devices, Inc. 5 * Copyright 2008 Red Hat Inc. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 11 * and/or sell copies of the Software, and to permit persons to whom the 12 * Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 23 * OTHER DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: Dave Airlie 26 * Alex Deucher 27 */ 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: radeon_i2c.c,v 1.1.1.2 2018/08/27 01:34:58 riastradh Exp $"); 30 31 #include <linux/export.h> 32 33 #include <drm/drmP.h> 34 #include <drm/drm_edid.h> 35 #include <drm/radeon_drm.h> 36 #include "radeon.h" 37 #include "atom.h" 38 39 extern int radeon_atom_hw_i2c_xfer(struct i2c_adapter *i2c_adap, 40 struct i2c_msg *msgs, int num); 41 extern u32 radeon_atom_hw_i2c_func(struct i2c_adapter *adap); 42 43 /** 44 * radeon_ddc_probe 45 * 46 */ 47 bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux) 48 { 49 u8 out = 0x0; 50 u8 buf[8]; 51 int ret; 52 struct i2c_msg msgs[] = { 53 { 54 .addr = DDC_ADDR, 55 .flags = 0, 56 .len = 1, 57 .buf = &out, 58 }, 59 { 60 .addr = DDC_ADDR, 61 .flags = I2C_M_RD, 62 .len = 8, 63 .buf = buf, 64 } 65 }; 66 67 /* on hw with routers, select right port */ 68 if (radeon_connector->router.ddc_valid) 69 radeon_router_select_ddc_port(radeon_connector); 70 71 if (use_aux) { 72 ret = i2c_transfer(&radeon_connector->ddc_bus->aux.ddc, msgs, 2); 73 } else { 74 ret = i2c_transfer(&radeon_connector->ddc_bus->adapter, msgs, 2); 75 } 76 77 if (ret != 2) 78 /* Couldn't find an accessible DDC on this connector */ 79 return false; 80 /* Probe also for valid EDID header 81 * EDID header starts with: 82 * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00. 83 * Only the first 6 bytes must be valid as 84 * drm_edid_block_valid() can fix the last 2 bytes */ 85 if (drm_edid_header_is_valid(buf) < 6) { 86 /* Couldn't find an accessible EDID on this 87 * connector */ 88 return false; 89 } 90 return true; 91 } 92 93 /* bit banging i2c */ 94 95 static int pre_xfer(struct i2c_adapter *i2c_adap) 96 { 97 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); 98 struct radeon_device *rdev = i2c->dev->dev_private; 99 struct radeon_i2c_bus_rec *rec = &i2c->rec; 100 uint32_t temp; 101 102 mutex_lock(&i2c->mutex); 103 104 /* RV410 appears to have a bug where the hw i2c in reset 105 * holds the i2c port in a bad state - switch hw i2c away before 106 * doing DDC - do this for all r200s/r300s/r400s for safety sake 107 */ 108 if (rec->hw_capable) { 109 if ((rdev->family >= CHIP_R200) && !ASIC_IS_AVIVO(rdev)) { 110 u32 reg; 111 112 if (rdev->family >= CHIP_RV350) 113 reg = RADEON_GPIO_MONID; 114 else if ((rdev->family == CHIP_R300) || 115 (rdev->family == CHIP_R350)) 116 reg = RADEON_GPIO_DVI_DDC; 117 else 118 reg = RADEON_GPIO_CRT2_DDC; 119 120 mutex_lock(&rdev->dc_hw_i2c_mutex); 121 if (rec->a_clk_reg == reg) { 122 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST | 123 R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1))); 124 } else { 125 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST | 126 R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3))); 127 } 128 mutex_unlock(&rdev->dc_hw_i2c_mutex); 129 } 130 } 131 132 /* switch the pads to ddc mode */ 133 if (ASIC_IS_DCE3(rdev) && rec->hw_capable) { 134 temp = RREG32(rec->mask_clk_reg); 135 temp &= ~(1 << 16); 136 WREG32(rec->mask_clk_reg, temp); 137 } 138 139 /* clear the output pin values */ 140 temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask; 141 WREG32(rec->a_clk_reg, temp); 142 143 temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask; 144 WREG32(rec->a_data_reg, temp); 145 146 /* set the pins to input */ 147 temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask; 148 WREG32(rec->en_clk_reg, temp); 149 150 temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask; 151 WREG32(rec->en_data_reg, temp); 152 153 /* mask the gpio pins for software use */ 154 temp = RREG32(rec->mask_clk_reg) | rec->mask_clk_mask; 155 WREG32(rec->mask_clk_reg, temp); 156 temp = RREG32(rec->mask_clk_reg); 157 158 temp = RREG32(rec->mask_data_reg) | rec->mask_data_mask; 159 WREG32(rec->mask_data_reg, temp); 160 temp = RREG32(rec->mask_data_reg); 161 162 return 0; 163 } 164 165 static void post_xfer(struct i2c_adapter *i2c_adap) 166 { 167 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); 168 struct radeon_device *rdev = i2c->dev->dev_private; 169 struct radeon_i2c_bus_rec *rec = &i2c->rec; 170 uint32_t temp; 171 172 /* unmask the gpio pins for software use */ 173 temp = RREG32(rec->mask_clk_reg) & ~rec->mask_clk_mask; 174 WREG32(rec->mask_clk_reg, temp); 175 temp = RREG32(rec->mask_clk_reg); 176 177 temp = RREG32(rec->mask_data_reg) & ~rec->mask_data_mask; 178 WREG32(rec->mask_data_reg, temp); 179 temp = RREG32(rec->mask_data_reg); 180 181 mutex_unlock(&i2c->mutex); 182 } 183 184 static int get_clock(void *i2c_priv) 185 { 186 struct radeon_i2c_chan *i2c = i2c_priv; 187 struct radeon_device *rdev = i2c->dev->dev_private; 188 struct radeon_i2c_bus_rec *rec = &i2c->rec; 189 uint32_t val; 190 191 /* read the value off the pin */ 192 val = RREG32(rec->y_clk_reg); 193 val &= rec->y_clk_mask; 194 195 return (val != 0); 196 } 197 198 199 static int get_data(void *i2c_priv) 200 { 201 struct radeon_i2c_chan *i2c = i2c_priv; 202 struct radeon_device *rdev = i2c->dev->dev_private; 203 struct radeon_i2c_bus_rec *rec = &i2c->rec; 204 uint32_t val; 205 206 /* read the value off the pin */ 207 val = RREG32(rec->y_data_reg); 208 val &= rec->y_data_mask; 209 210 return (val != 0); 211 } 212 213 static void set_clock(void *i2c_priv, int clock) 214 { 215 struct radeon_i2c_chan *i2c = i2c_priv; 216 struct radeon_device *rdev = i2c->dev->dev_private; 217 struct radeon_i2c_bus_rec *rec = &i2c->rec; 218 uint32_t val; 219 220 /* set pin direction */ 221 val = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask; 222 val |= clock ? 0 : rec->en_clk_mask; 223 WREG32(rec->en_clk_reg, val); 224 } 225 226 static void set_data(void *i2c_priv, int data) 227 { 228 struct radeon_i2c_chan *i2c = i2c_priv; 229 struct radeon_device *rdev = i2c->dev->dev_private; 230 struct radeon_i2c_bus_rec *rec = &i2c->rec; 231 uint32_t val; 232 233 /* set pin direction */ 234 val = RREG32(rec->en_data_reg) & ~rec->en_data_mask; 235 val |= data ? 0 : rec->en_data_mask; 236 WREG32(rec->en_data_reg, val); 237 } 238 239 /* hw i2c */ 240 241 static u32 radeon_get_i2c_prescale(struct radeon_device *rdev) 242 { 243 u32 sclk = rdev->pm.current_sclk; 244 u32 prescale = 0; 245 u32 nm; 246 u8 n, m, loop; 247 int i2c_clock; 248 249 switch (rdev->family) { 250 case CHIP_R100: 251 case CHIP_RV100: 252 case CHIP_RS100: 253 case CHIP_RV200: 254 case CHIP_RS200: 255 case CHIP_R200: 256 case CHIP_RV250: 257 case CHIP_RS300: 258 case CHIP_RV280: 259 case CHIP_R300: 260 case CHIP_R350: 261 case CHIP_RV350: 262 i2c_clock = 60; 263 nm = (sclk * 10) / (i2c_clock * 4); 264 for (loop = 1; loop < 255; loop++) { 265 if ((nm / loop) < loop) 266 break; 267 } 268 n = loop - 1; 269 m = loop - 2; 270 prescale = m | (n << 8); 271 break; 272 case CHIP_RV380: 273 case CHIP_RS400: 274 case CHIP_RS480: 275 case CHIP_R420: 276 case CHIP_R423: 277 case CHIP_RV410: 278 prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128; 279 break; 280 case CHIP_RS600: 281 case CHIP_RS690: 282 case CHIP_RS740: 283 /* todo */ 284 break; 285 case CHIP_RV515: 286 case CHIP_R520: 287 case CHIP_RV530: 288 case CHIP_RV560: 289 case CHIP_RV570: 290 case CHIP_R580: 291 i2c_clock = 50; 292 if (rdev->family == CHIP_R520) 293 prescale = (127 << 8) + ((sclk * 10) / (4 * 127 * i2c_clock)); 294 else 295 prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128; 296 break; 297 case CHIP_R600: 298 case CHIP_RV610: 299 case CHIP_RV630: 300 case CHIP_RV670: 301 /* todo */ 302 break; 303 case CHIP_RV620: 304 case CHIP_RV635: 305 case CHIP_RS780: 306 case CHIP_RS880: 307 case CHIP_RV770: 308 case CHIP_RV730: 309 case CHIP_RV710: 310 case CHIP_RV740: 311 /* todo */ 312 break; 313 case CHIP_CEDAR: 314 case CHIP_REDWOOD: 315 case CHIP_JUNIPER: 316 case CHIP_CYPRESS: 317 case CHIP_HEMLOCK: 318 /* todo */ 319 break; 320 default: 321 DRM_ERROR("i2c: unhandled radeon chip\n"); 322 break; 323 } 324 return prescale; 325 } 326 327 328 /* hw i2c engine for r1xx-4xx hardware 329 * hw can buffer up to 15 bytes 330 */ 331 static int r100_hw_i2c_xfer(struct i2c_adapter *i2c_adap, 332 struct i2c_msg *msgs, int num) 333 { 334 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); 335 struct radeon_device *rdev = i2c->dev->dev_private; 336 struct radeon_i2c_bus_rec *rec = &i2c->rec; 337 struct i2c_msg *p; 338 int i, j, k, ret = num; 339 u32 prescale; 340 u32 i2c_cntl_0, i2c_cntl_1, i2c_data; 341 u32 tmp, reg; 342 343 mutex_lock(&rdev->dc_hw_i2c_mutex); 344 /* take the pm lock since we need a constant sclk */ 345 mutex_lock(&rdev->pm.mutex); 346 347 prescale = radeon_get_i2c_prescale(rdev); 348 349 reg = ((prescale << RADEON_I2C_PRESCALE_SHIFT) | 350 RADEON_I2C_DRIVE_EN | 351 RADEON_I2C_START | 352 RADEON_I2C_STOP | 353 RADEON_I2C_GO); 354 355 if (rdev->is_atom_bios) { 356 tmp = RREG32(RADEON_BIOS_6_SCRATCH); 357 WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE); 358 } 359 360 if (rec->mm_i2c) { 361 i2c_cntl_0 = RADEON_I2C_CNTL_0; 362 i2c_cntl_1 = RADEON_I2C_CNTL_1; 363 i2c_data = RADEON_I2C_DATA; 364 } else { 365 i2c_cntl_0 = RADEON_DVI_I2C_CNTL_0; 366 i2c_cntl_1 = RADEON_DVI_I2C_CNTL_1; 367 i2c_data = RADEON_DVI_I2C_DATA; 368 369 switch (rdev->family) { 370 case CHIP_R100: 371 case CHIP_RV100: 372 case CHIP_RS100: 373 case CHIP_RV200: 374 case CHIP_RS200: 375 case CHIP_RS300: 376 switch (rec->mask_clk_reg) { 377 case RADEON_GPIO_DVI_DDC: 378 /* no gpio select bit */ 379 break; 380 default: 381 DRM_ERROR("gpio not supported with hw i2c\n"); 382 ret = -EINVAL; 383 goto done; 384 } 385 break; 386 case CHIP_R200: 387 /* only bit 4 on r200 */ 388 switch (rec->mask_clk_reg) { 389 case RADEON_GPIO_DVI_DDC: 390 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); 391 break; 392 case RADEON_GPIO_MONID: 393 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); 394 break; 395 default: 396 DRM_ERROR("gpio not supported with hw i2c\n"); 397 ret = -EINVAL; 398 goto done; 399 } 400 break; 401 case CHIP_RV250: 402 case CHIP_RV280: 403 /* bits 3 and 4 */ 404 switch (rec->mask_clk_reg) { 405 case RADEON_GPIO_DVI_DDC: 406 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); 407 break; 408 case RADEON_GPIO_VGA_DDC: 409 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2); 410 break; 411 case RADEON_GPIO_CRT2_DDC: 412 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); 413 break; 414 default: 415 DRM_ERROR("gpio not supported with hw i2c\n"); 416 ret = -EINVAL; 417 goto done; 418 } 419 break; 420 case CHIP_R300: 421 case CHIP_R350: 422 /* only bit 4 on r300/r350 */ 423 switch (rec->mask_clk_reg) { 424 case RADEON_GPIO_VGA_DDC: 425 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); 426 break; 427 case RADEON_GPIO_DVI_DDC: 428 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); 429 break; 430 default: 431 DRM_ERROR("gpio not supported with hw i2c\n"); 432 ret = -EINVAL; 433 goto done; 434 } 435 break; 436 case CHIP_RV350: 437 case CHIP_RV380: 438 case CHIP_R420: 439 case CHIP_R423: 440 case CHIP_RV410: 441 case CHIP_RS400: 442 case CHIP_RS480: 443 /* bits 3 and 4 */ 444 switch (rec->mask_clk_reg) { 445 case RADEON_GPIO_VGA_DDC: 446 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); 447 break; 448 case RADEON_GPIO_DVI_DDC: 449 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2); 450 break; 451 case RADEON_GPIO_MONID: 452 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); 453 break; 454 default: 455 DRM_ERROR("gpio not supported with hw i2c\n"); 456 ret = -EINVAL; 457 goto done; 458 } 459 break; 460 default: 461 DRM_ERROR("unsupported asic\n"); 462 ret = -EINVAL; 463 goto done; 464 break; 465 } 466 } 467 468 /* check for bus probe */ 469 p = &msgs[0]; 470 if ((num == 1) && (p->len == 0)) { 471 WREG32(i2c_cntl_0, (RADEON_I2C_DONE | 472 RADEON_I2C_NACK | 473 RADEON_I2C_HALT | 474 RADEON_I2C_SOFT_RST)); 475 WREG32(i2c_data, (p->addr << 1) & 0xff); 476 WREG32(i2c_data, 0); 477 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) | 478 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) | 479 RADEON_I2C_EN | 480 (48 << RADEON_I2C_TIME_LIMIT_SHIFT))); 481 WREG32(i2c_cntl_0, reg); 482 for (k = 0; k < 32; k++) { 483 udelay(10); 484 tmp = RREG32(i2c_cntl_0); 485 if (tmp & RADEON_I2C_GO) 486 continue; 487 tmp = RREG32(i2c_cntl_0); 488 if (tmp & RADEON_I2C_DONE) 489 break; 490 else { 491 DRM_DEBUG("i2c write error 0x%08x\n", tmp); 492 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT); 493 ret = -EIO; 494 goto done; 495 } 496 } 497 goto done; 498 } 499 500 for (i = 0; i < num; i++) { 501 p = &msgs[i]; 502 for (j = 0; j < p->len; j++) { 503 if (p->flags & I2C_M_RD) { 504 WREG32(i2c_cntl_0, (RADEON_I2C_DONE | 505 RADEON_I2C_NACK | 506 RADEON_I2C_HALT | 507 RADEON_I2C_SOFT_RST)); 508 WREG32(i2c_data, ((p->addr << 1) & 0xff) | 0x1); 509 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) | 510 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) | 511 RADEON_I2C_EN | 512 (48 << RADEON_I2C_TIME_LIMIT_SHIFT))); 513 WREG32(i2c_cntl_0, reg | RADEON_I2C_RECEIVE); 514 for (k = 0; k < 32; k++) { 515 udelay(10); 516 tmp = RREG32(i2c_cntl_0); 517 if (tmp & RADEON_I2C_GO) 518 continue; 519 tmp = RREG32(i2c_cntl_0); 520 if (tmp & RADEON_I2C_DONE) 521 break; 522 else { 523 DRM_DEBUG("i2c read error 0x%08x\n", tmp); 524 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT); 525 ret = -EIO; 526 goto done; 527 } 528 } 529 p->buf[j] = RREG32(i2c_data) & 0xff; 530 } else { 531 WREG32(i2c_cntl_0, (RADEON_I2C_DONE | 532 RADEON_I2C_NACK | 533 RADEON_I2C_HALT | 534 RADEON_I2C_SOFT_RST)); 535 WREG32(i2c_data, (p->addr << 1) & 0xff); 536 WREG32(i2c_data, p->buf[j]); 537 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) | 538 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) | 539 RADEON_I2C_EN | 540 (48 << RADEON_I2C_TIME_LIMIT_SHIFT))); 541 WREG32(i2c_cntl_0, reg); 542 for (k = 0; k < 32; k++) { 543 udelay(10); 544 tmp = RREG32(i2c_cntl_0); 545 if (tmp & RADEON_I2C_GO) 546 continue; 547 tmp = RREG32(i2c_cntl_0); 548 if (tmp & RADEON_I2C_DONE) 549 break; 550 else { 551 DRM_DEBUG("i2c write error 0x%08x\n", tmp); 552 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT); 553 ret = -EIO; 554 goto done; 555 } 556 } 557 } 558 } 559 } 560 561 done: 562 WREG32(i2c_cntl_0, 0); 563 WREG32(i2c_cntl_1, 0); 564 WREG32(i2c_cntl_0, (RADEON_I2C_DONE | 565 RADEON_I2C_NACK | 566 RADEON_I2C_HALT | 567 RADEON_I2C_SOFT_RST)); 568 569 if (rdev->is_atom_bios) { 570 tmp = RREG32(RADEON_BIOS_6_SCRATCH); 571 tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE; 572 WREG32(RADEON_BIOS_6_SCRATCH, tmp); 573 } 574 575 mutex_unlock(&rdev->pm.mutex); 576 mutex_unlock(&rdev->dc_hw_i2c_mutex); 577 578 return ret; 579 } 580 581 /* hw i2c engine for r5xx hardware 582 * hw can buffer up to 15 bytes 583 */ 584 static int r500_hw_i2c_xfer(struct i2c_adapter *i2c_adap, 585 struct i2c_msg *msgs, int num) 586 { 587 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); 588 struct radeon_device *rdev = i2c->dev->dev_private; 589 struct radeon_i2c_bus_rec *rec = &i2c->rec; 590 struct i2c_msg *p; 591 int i, j, remaining, current_count, buffer_offset, ret = num; 592 u32 prescale; 593 u32 tmp, reg; 594 u32 saved1, saved2; 595 596 mutex_lock(&rdev->dc_hw_i2c_mutex); 597 /* take the pm lock since we need a constant sclk */ 598 mutex_lock(&rdev->pm.mutex); 599 600 prescale = radeon_get_i2c_prescale(rdev); 601 602 /* clear gpio mask bits */ 603 tmp = RREG32(rec->mask_clk_reg); 604 tmp &= ~rec->mask_clk_mask; 605 WREG32(rec->mask_clk_reg, tmp); 606 tmp = RREG32(rec->mask_clk_reg); 607 608 tmp = RREG32(rec->mask_data_reg); 609 tmp &= ~rec->mask_data_mask; 610 WREG32(rec->mask_data_reg, tmp); 611 tmp = RREG32(rec->mask_data_reg); 612 613 /* clear pin values */ 614 tmp = RREG32(rec->a_clk_reg); 615 tmp &= ~rec->a_clk_mask; 616 WREG32(rec->a_clk_reg, tmp); 617 tmp = RREG32(rec->a_clk_reg); 618 619 tmp = RREG32(rec->a_data_reg); 620 tmp &= ~rec->a_data_mask; 621 WREG32(rec->a_data_reg, tmp); 622 tmp = RREG32(rec->a_data_reg); 623 624 /* set the pins to input */ 625 tmp = RREG32(rec->en_clk_reg); 626 tmp &= ~rec->en_clk_mask; 627 WREG32(rec->en_clk_reg, tmp); 628 tmp = RREG32(rec->en_clk_reg); 629 630 tmp = RREG32(rec->en_data_reg); 631 tmp &= ~rec->en_data_mask; 632 WREG32(rec->en_data_reg, tmp); 633 tmp = RREG32(rec->en_data_reg); 634 635 /* */ 636 tmp = RREG32(RADEON_BIOS_6_SCRATCH); 637 WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE); 638 saved1 = RREG32(AVIVO_DC_I2C_CONTROL1); 639 saved2 = RREG32(0x494); 640 WREG32(0x494, saved2 | 0x1); 641 642 WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_WANTS_TO_USE_I2C); 643 for (i = 0; i < 50; i++) { 644 udelay(1); 645 if (RREG32(AVIVO_DC_I2C_ARBITRATION) & AVIVO_DC_I2C_SW_CAN_USE_I2C) 646 break; 647 } 648 if (i == 50) { 649 DRM_ERROR("failed to get i2c bus\n"); 650 ret = -EBUSY; 651 goto done; 652 } 653 654 reg = AVIVO_DC_I2C_START | AVIVO_DC_I2C_STOP | AVIVO_DC_I2C_EN; 655 switch (rec->mask_clk_reg) { 656 case AVIVO_DC_GPIO_DDC1_MASK: 657 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC1); 658 break; 659 case AVIVO_DC_GPIO_DDC2_MASK: 660 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC2); 661 break; 662 case AVIVO_DC_GPIO_DDC3_MASK: 663 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC3); 664 break; 665 default: 666 DRM_ERROR("gpio not supported with hw i2c\n"); 667 ret = -EINVAL; 668 goto done; 669 } 670 671 /* check for bus probe */ 672 p = &msgs[0]; 673 if ((num == 1) && (p->len == 0)) { 674 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | 675 AVIVO_DC_I2C_NACK | 676 AVIVO_DC_I2C_HALT)); 677 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); 678 udelay(1); 679 WREG32(AVIVO_DC_I2C_RESET, 0); 680 681 WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff); 682 WREG32(AVIVO_DC_I2C_DATA, 0); 683 684 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48)); 685 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) | 686 AVIVO_DC_I2C_DATA_COUNT(1) | 687 (prescale << 16))); 688 WREG32(AVIVO_DC_I2C_CONTROL1, reg); 689 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO); 690 for (j = 0; j < 200; j++) { 691 udelay(50); 692 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 693 if (tmp & AVIVO_DC_I2C_GO) 694 continue; 695 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 696 if (tmp & AVIVO_DC_I2C_DONE) 697 break; 698 else { 699 DRM_DEBUG("i2c write error 0x%08x\n", tmp); 700 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT); 701 ret = -EIO; 702 goto done; 703 } 704 } 705 goto done; 706 } 707 708 for (i = 0; i < num; i++) { 709 p = &msgs[i]; 710 remaining = p->len; 711 buffer_offset = 0; 712 if (p->flags & I2C_M_RD) { 713 while (remaining) { 714 if (remaining > 15) 715 current_count = 15; 716 else 717 current_count = remaining; 718 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | 719 AVIVO_DC_I2C_NACK | 720 AVIVO_DC_I2C_HALT)); 721 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); 722 udelay(1); 723 WREG32(AVIVO_DC_I2C_RESET, 0); 724 725 WREG32(AVIVO_DC_I2C_DATA, ((p->addr << 1) & 0xff) | 0x1); 726 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48)); 727 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) | 728 AVIVO_DC_I2C_DATA_COUNT(current_count) | 729 (prescale << 16))); 730 WREG32(AVIVO_DC_I2C_CONTROL1, reg | AVIVO_DC_I2C_RECEIVE); 731 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO); 732 for (j = 0; j < 200; j++) { 733 udelay(50); 734 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 735 if (tmp & AVIVO_DC_I2C_GO) 736 continue; 737 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 738 if (tmp & AVIVO_DC_I2C_DONE) 739 break; 740 else { 741 DRM_DEBUG("i2c read error 0x%08x\n", tmp); 742 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT); 743 ret = -EIO; 744 goto done; 745 } 746 } 747 for (j = 0; j < current_count; j++) 748 p->buf[buffer_offset + j] = RREG32(AVIVO_DC_I2C_DATA) & 0xff; 749 remaining -= current_count; 750 buffer_offset += current_count; 751 } 752 } else { 753 while (remaining) { 754 if (remaining > 15) 755 current_count = 15; 756 else 757 current_count = remaining; 758 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | 759 AVIVO_DC_I2C_NACK | 760 AVIVO_DC_I2C_HALT)); 761 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); 762 udelay(1); 763 WREG32(AVIVO_DC_I2C_RESET, 0); 764 765 WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff); 766 for (j = 0; j < current_count; j++) 767 WREG32(AVIVO_DC_I2C_DATA, p->buf[buffer_offset + j]); 768 769 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48)); 770 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) | 771 AVIVO_DC_I2C_DATA_COUNT(current_count) | 772 (prescale << 16))); 773 WREG32(AVIVO_DC_I2C_CONTROL1, reg); 774 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO); 775 for (j = 0; j < 200; j++) { 776 udelay(50); 777 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 778 if (tmp & AVIVO_DC_I2C_GO) 779 continue; 780 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 781 if (tmp & AVIVO_DC_I2C_DONE) 782 break; 783 else { 784 DRM_DEBUG("i2c write error 0x%08x\n", tmp); 785 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT); 786 ret = -EIO; 787 goto done; 788 } 789 } 790 remaining -= current_count; 791 buffer_offset += current_count; 792 } 793 } 794 } 795 796 done: 797 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | 798 AVIVO_DC_I2C_NACK | 799 AVIVO_DC_I2C_HALT)); 800 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); 801 udelay(1); 802 WREG32(AVIVO_DC_I2C_RESET, 0); 803 804 WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_DONE_USING_I2C); 805 WREG32(AVIVO_DC_I2C_CONTROL1, saved1); 806 WREG32(0x494, saved2); 807 tmp = RREG32(RADEON_BIOS_6_SCRATCH); 808 tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE; 809 WREG32(RADEON_BIOS_6_SCRATCH, tmp); 810 811 mutex_unlock(&rdev->pm.mutex); 812 mutex_unlock(&rdev->dc_hw_i2c_mutex); 813 814 return ret; 815 } 816 817 static int radeon_hw_i2c_xfer(struct i2c_adapter *i2c_adap, 818 struct i2c_msg *msgs, int num) 819 { 820 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); 821 struct radeon_device *rdev = i2c->dev->dev_private; 822 struct radeon_i2c_bus_rec *rec = &i2c->rec; 823 int ret = 0; 824 825 mutex_lock(&i2c->mutex); 826 827 switch (rdev->family) { 828 case CHIP_R100: 829 case CHIP_RV100: 830 case CHIP_RS100: 831 case CHIP_RV200: 832 case CHIP_RS200: 833 case CHIP_R200: 834 case CHIP_RV250: 835 case CHIP_RS300: 836 case CHIP_RV280: 837 case CHIP_R300: 838 case CHIP_R350: 839 case CHIP_RV350: 840 case CHIP_RV380: 841 case CHIP_R420: 842 case CHIP_R423: 843 case CHIP_RV410: 844 case CHIP_RS400: 845 case CHIP_RS480: 846 ret = r100_hw_i2c_xfer(i2c_adap, msgs, num); 847 break; 848 case CHIP_RS600: 849 case CHIP_RS690: 850 case CHIP_RS740: 851 /* XXX fill in hw i2c implementation */ 852 break; 853 case CHIP_RV515: 854 case CHIP_R520: 855 case CHIP_RV530: 856 case CHIP_RV560: 857 case CHIP_RV570: 858 case CHIP_R580: 859 if (rec->mm_i2c) 860 ret = r100_hw_i2c_xfer(i2c_adap, msgs, num); 861 else 862 ret = r500_hw_i2c_xfer(i2c_adap, msgs, num); 863 break; 864 case CHIP_R600: 865 case CHIP_RV610: 866 case CHIP_RV630: 867 case CHIP_RV670: 868 /* XXX fill in hw i2c implementation */ 869 break; 870 case CHIP_RV620: 871 case CHIP_RV635: 872 case CHIP_RS780: 873 case CHIP_RS880: 874 case CHIP_RV770: 875 case CHIP_RV730: 876 case CHIP_RV710: 877 case CHIP_RV740: 878 /* XXX fill in hw i2c implementation */ 879 break; 880 case CHIP_CEDAR: 881 case CHIP_REDWOOD: 882 case CHIP_JUNIPER: 883 case CHIP_CYPRESS: 884 case CHIP_HEMLOCK: 885 /* XXX fill in hw i2c implementation */ 886 break; 887 default: 888 DRM_ERROR("i2c: unhandled radeon chip\n"); 889 ret = -EIO; 890 break; 891 } 892 893 mutex_unlock(&i2c->mutex); 894 895 return ret; 896 } 897 898 static u32 radeon_hw_i2c_func(struct i2c_adapter *adap) 899 { 900 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 901 } 902 903 static const struct i2c_algorithm radeon_i2c_algo = { 904 .master_xfer = radeon_hw_i2c_xfer, 905 .functionality = radeon_hw_i2c_func, 906 }; 907 908 static const struct i2c_algorithm radeon_atom_i2c_algo = { 909 .master_xfer = radeon_atom_hw_i2c_xfer, 910 .functionality = radeon_atom_hw_i2c_func, 911 }; 912 913 struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, 914 struct radeon_i2c_bus_rec *rec, 915 const char *name) 916 { 917 struct radeon_device *rdev = dev->dev_private; 918 struct radeon_i2c_chan *i2c; 919 int ret; 920 921 /* don't add the mm_i2c bus unless hw_i2c is enabled */ 922 if (rec->mm_i2c && (radeon_hw_i2c == 0)) 923 return NULL; 924 925 i2c = kzalloc(sizeof(struct radeon_i2c_chan), GFP_KERNEL); 926 if (i2c == NULL) 927 return NULL; 928 929 i2c->rec = *rec; 930 i2c->adapter.owner = THIS_MODULE; 931 i2c->adapter.class = I2C_CLASS_DDC; 932 i2c->adapter.dev.parent = &dev->pdev->dev; 933 i2c->dev = dev; 934 i2c_set_adapdata(&i2c->adapter, i2c); 935 mutex_init(&i2c->mutex); 936 if (rec->mm_i2c || 937 (rec->hw_capable && 938 radeon_hw_i2c && 939 ((rdev->family <= CHIP_RS480) || 940 ((rdev->family >= CHIP_RV515) && (rdev->family <= CHIP_R580))))) { 941 /* set the radeon hw i2c adapter */ 942 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name), 943 "Radeon i2c hw bus %s", name); 944 i2c->adapter.algo = &radeon_i2c_algo; 945 ret = i2c_add_adapter(&i2c->adapter); 946 if (ret) { 947 DRM_ERROR("Failed to register hw i2c %s\n", name); 948 goto out_free; 949 } 950 } else if (rec->hw_capable && 951 radeon_hw_i2c && 952 ASIC_IS_DCE3(rdev)) { 953 /* hw i2c using atom */ 954 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name), 955 "Radeon i2c hw bus %s", name); 956 i2c->adapter.algo = &radeon_atom_i2c_algo; 957 ret = i2c_add_adapter(&i2c->adapter); 958 if (ret) { 959 DRM_ERROR("Failed to register hw i2c %s\n", name); 960 goto out_free; 961 } 962 } else { 963 /* set the radeon bit adapter */ 964 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name), 965 "Radeon i2c bit bus %s", name); 966 i2c->adapter.algo_data = &i2c->bit; 967 i2c->bit.pre_xfer = pre_xfer; 968 i2c->bit.post_xfer = post_xfer; 969 i2c->bit.setsda = set_data; 970 i2c->bit.setscl = set_clock; 971 i2c->bit.getsda = get_data; 972 i2c->bit.getscl = get_clock; 973 i2c->bit.udelay = 10; 974 i2c->bit.timeout = usecs_to_jiffies(2200); /* from VESA */ 975 i2c->bit.data = i2c; 976 ret = i2c_bit_add_bus(&i2c->adapter); 977 if (ret) { 978 DRM_ERROR("Failed to register bit i2c %s\n", name); 979 goto out_free; 980 } 981 } 982 983 return i2c; 984 out_free: 985 kfree(i2c); 986 return NULL; 987 988 } 989 990 void radeon_i2c_destroy(struct radeon_i2c_chan *i2c) 991 { 992 if (!i2c) 993 return; 994 i2c_del_adapter(&i2c->adapter); 995 if (i2c->has_aux) 996 drm_dp_aux_unregister(&i2c->aux); 997 kfree(i2c); 998 } 999 1000 /* Add the default buses */ 1001 void radeon_i2c_init(struct radeon_device *rdev) 1002 { 1003 if (radeon_hw_i2c) 1004 DRM_INFO("hw_i2c forced on, you may experience display detection problems!\n"); 1005 1006 if (rdev->is_atom_bios) 1007 radeon_atombios_i2c_init(rdev); 1008 else 1009 radeon_combios_i2c_init(rdev); 1010 } 1011 1012 /* remove all the buses */ 1013 void radeon_i2c_fini(struct radeon_device *rdev) 1014 { 1015 int i; 1016 1017 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) { 1018 if (rdev->i2c_bus[i]) { 1019 radeon_i2c_destroy(rdev->i2c_bus[i]); 1020 rdev->i2c_bus[i] = NULL; 1021 } 1022 } 1023 } 1024 1025 /* Add additional buses */ 1026 void radeon_i2c_add(struct radeon_device *rdev, 1027 struct radeon_i2c_bus_rec *rec, 1028 const char *name) 1029 { 1030 struct drm_device *dev = rdev->ddev; 1031 int i; 1032 1033 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) { 1034 if (!rdev->i2c_bus[i]) { 1035 rdev->i2c_bus[i] = radeon_i2c_create(dev, rec, name); 1036 return; 1037 } 1038 } 1039 } 1040 1041 /* looks up bus based on id */ 1042 struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev, 1043 struct radeon_i2c_bus_rec *i2c_bus) 1044 { 1045 int i; 1046 1047 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) { 1048 if (rdev->i2c_bus[i] && 1049 (rdev->i2c_bus[i]->rec.i2c_id == i2c_bus->i2c_id)) { 1050 return rdev->i2c_bus[i]; 1051 } 1052 } 1053 return NULL; 1054 } 1055 1056 void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus, 1057 u8 slave_addr, 1058 u8 addr, 1059 u8 *val) 1060 { 1061 u8 out_buf[2]; 1062 u8 in_buf[2]; 1063 struct i2c_msg msgs[] = { 1064 { 1065 .addr = slave_addr, 1066 .flags = 0, 1067 .len = 1, 1068 .buf = out_buf, 1069 }, 1070 { 1071 .addr = slave_addr, 1072 .flags = I2C_M_RD, 1073 .len = 1, 1074 .buf = in_buf, 1075 } 1076 }; 1077 1078 out_buf[0] = addr; 1079 out_buf[1] = 0; 1080 1081 if (i2c_transfer(&i2c_bus->adapter, msgs, 2) == 2) { 1082 *val = in_buf[0]; 1083 DRM_DEBUG("val = 0x%02x\n", *val); 1084 } else { 1085 DRM_DEBUG("i2c 0x%02x 0x%02x read failed\n", 1086 addr, *val); 1087 } 1088 } 1089 1090 void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c_bus, 1091 u8 slave_addr, 1092 u8 addr, 1093 u8 val) 1094 { 1095 uint8_t out_buf[2]; 1096 struct i2c_msg msg = { 1097 .addr = slave_addr, 1098 .flags = 0, 1099 .len = 2, 1100 .buf = out_buf, 1101 }; 1102 1103 out_buf[0] = addr; 1104 out_buf[1] = val; 1105 1106 if (i2c_transfer(&i2c_bus->adapter, &msg, 1) != 1) 1107 DRM_DEBUG("i2c 0x%02x 0x%02x write failed\n", 1108 addr, val); 1109 } 1110 1111 /* ddc router switching */ 1112 void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector) 1113 { 1114 u8 val; 1115 1116 if (!radeon_connector->router.ddc_valid) 1117 return; 1118 1119 if (!radeon_connector->router_bus) 1120 return; 1121 1122 radeon_i2c_get_byte(radeon_connector->router_bus, 1123 radeon_connector->router.i2c_addr, 1124 0x3, &val); 1125 val &= ~radeon_connector->router.ddc_mux_control_pin; 1126 radeon_i2c_put_byte(radeon_connector->router_bus, 1127 radeon_connector->router.i2c_addr, 1128 0x3, val); 1129 radeon_i2c_get_byte(radeon_connector->router_bus, 1130 radeon_connector->router.i2c_addr, 1131 0x1, &val); 1132 val &= ~radeon_connector->router.ddc_mux_control_pin; 1133 val |= radeon_connector->router.ddc_mux_state; 1134 radeon_i2c_put_byte(radeon_connector->router_bus, 1135 radeon_connector->router.i2c_addr, 1136 0x1, val); 1137 } 1138 1139 /* clock/data router switching */ 1140 void radeon_router_select_cd_port(struct radeon_connector *radeon_connector) 1141 { 1142 u8 val; 1143 1144 if (!radeon_connector->router.cd_valid) 1145 return; 1146 1147 if (!radeon_connector->router_bus) 1148 return; 1149 1150 radeon_i2c_get_byte(radeon_connector->router_bus, 1151 radeon_connector->router.i2c_addr, 1152 0x3, &val); 1153 val &= ~radeon_connector->router.cd_mux_control_pin; 1154 radeon_i2c_put_byte(radeon_connector->router_bus, 1155 radeon_connector->router.i2c_addr, 1156 0x3, val); 1157 radeon_i2c_get_byte(radeon_connector->router_bus, 1158 radeon_connector->router.i2c_addr, 1159 0x1, &val); 1160 val &= ~radeon_connector->router.cd_mux_control_pin; 1161 val |= radeon_connector->router.cd_mux_state; 1162 radeon_i2c_put_byte(radeon_connector->router_bus, 1163 radeon_connector->router.i2c_addr, 1164 0x1, val); 1165 } 1166 1167
Indexes created Sat Oct 18 21:09:54 GMT 2025