radeon_i2c.c revision 1.1.1.3
1 /* $NetBSD: radeon_i2c.c,v 1.1.1.3 2021/12/18 20:15:48 riastradh Exp $ */ 2 3 /* 4 * Copyright 2007-8 Advanced Micro Devices, Inc. 5 * Copyright 2008 Red Hat Inc. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 11 * and/or sell copies of the Software, and to permit persons to whom the 12 * Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 23 * OTHER DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: Dave Airlie 26 * Alex Deucher 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: radeon_i2c.c,v 1.1.1.3 2021/12/18 20:15:48 riastradh Exp $"); 31 32 #include <linux/export.h> 33 #include <linux/pci.h> 34 35 #include <drm/drm_device.h> 36 #include <drm/drm_edid.h> 37 #include <drm/radeon_drm.h> 38 39 #include "radeon.h" 40 #include "atom.h" 41 42 extern int radeon_atom_hw_i2c_xfer(struct i2c_adapter *i2c_adap, 43 struct i2c_msg *msgs, int num); 44 extern u32 radeon_atom_hw_i2c_func(struct i2c_adapter *adap); 45 46 /** 47 * radeon_ddc_probe 48 * 49 */ 50 bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux) 51 { 52 u8 out = 0x0; 53 u8 buf[8]; 54 int ret; 55 struct i2c_msg msgs[] = { 56 { 57 .addr = DDC_ADDR, 58 .flags = 0, 59 .len = 1, 60 .buf = &out, 61 }, 62 { 63 .addr = DDC_ADDR, 64 .flags = I2C_M_RD, 65 .len = 8, 66 .buf = buf, 67 } 68 }; 69 70 /* on hw with routers, select right port */ 71 if (radeon_connector->router.ddc_valid) 72 radeon_router_select_ddc_port(radeon_connector); 73 74 if (use_aux) { 75 ret = i2c_transfer(&radeon_connector->ddc_bus->aux.ddc, msgs, 2); 76 } else { 77 ret = i2c_transfer(&radeon_connector->ddc_bus->adapter, msgs, 2); 78 } 79 80 if (ret != 2) 81 /* Couldn't find an accessible DDC on this connector */ 82 return false; 83 /* Probe also for valid EDID header 84 * EDID header starts with: 85 * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00. 86 * Only the first 6 bytes must be valid as 87 * drm_edid_block_valid() can fix the last 2 bytes */ 88 if (drm_edid_header_is_valid(buf) < 6) { 89 /* Couldn't find an accessible EDID on this 90 * connector */ 91 return false; 92 } 93 return true; 94 } 95 96 /* bit banging i2c */ 97 98 static int pre_xfer(struct i2c_adapter *i2c_adap) 99 { 100 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); 101 struct radeon_device *rdev = i2c->dev->dev_private; 102 struct radeon_i2c_bus_rec *rec = &i2c->rec; 103 uint32_t temp; 104 105 mutex_lock(&i2c->mutex); 106 107 /* RV410 appears to have a bug where the hw i2c in reset 108 * holds the i2c port in a bad state - switch hw i2c away before 109 * doing DDC - do this for all r200s/r300s/r400s for safety sake 110 */ 111 if (rec->hw_capable) { 112 if ((rdev->family >= CHIP_R200) && !ASIC_IS_AVIVO(rdev)) { 113 u32 reg; 114 115 if (rdev->family >= CHIP_RV350) 116 reg = RADEON_GPIO_MONID; 117 else if ((rdev->family == CHIP_R300) || 118 (rdev->family == CHIP_R350)) 119 reg = RADEON_GPIO_DVI_DDC; 120 else 121 reg = RADEON_GPIO_CRT2_DDC; 122 123 mutex_lock(&rdev->dc_hw_i2c_mutex); 124 if (rec->a_clk_reg == reg) { 125 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST | 126 R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1))); 127 } else { 128 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST | 129 R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3))); 130 } 131 mutex_unlock(&rdev->dc_hw_i2c_mutex); 132 } 133 } 134 135 /* switch the pads to ddc mode */ 136 if (ASIC_IS_DCE3(rdev) && rec->hw_capable) { 137 temp = RREG32(rec->mask_clk_reg); 138 temp &= ~(1 << 16); 139 WREG32(rec->mask_clk_reg, temp); 140 } 141 142 /* clear the output pin values */ 143 temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask; 144 WREG32(rec->a_clk_reg, temp); 145 146 temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask; 147 WREG32(rec->a_data_reg, temp); 148 149 /* set the pins to input */ 150 temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask; 151 WREG32(rec->en_clk_reg, temp); 152 153 temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask; 154 WREG32(rec->en_data_reg, temp); 155 156 /* mask the gpio pins for software use */ 157 temp = RREG32(rec->mask_clk_reg) | rec->mask_clk_mask; 158 WREG32(rec->mask_clk_reg, temp); 159 temp = RREG32(rec->mask_clk_reg); 160 161 temp = RREG32(rec->mask_data_reg) | rec->mask_data_mask; 162 WREG32(rec->mask_data_reg, temp); 163 temp = RREG32(rec->mask_data_reg); 164 165 return 0; 166 } 167 168 static void post_xfer(struct i2c_adapter *i2c_adap) 169 { 170 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); 171 struct radeon_device *rdev = i2c->dev->dev_private; 172 struct radeon_i2c_bus_rec *rec = &i2c->rec; 173 uint32_t temp; 174 175 /* unmask the gpio pins for software use */ 176 temp = RREG32(rec->mask_clk_reg) & ~rec->mask_clk_mask; 177 WREG32(rec->mask_clk_reg, temp); 178 temp = RREG32(rec->mask_clk_reg); 179 180 temp = RREG32(rec->mask_data_reg) & ~rec->mask_data_mask; 181 WREG32(rec->mask_data_reg, temp); 182 temp = RREG32(rec->mask_data_reg); 183 184 mutex_unlock(&i2c->mutex); 185 } 186 187 static int get_clock(void *i2c_priv) 188 { 189 struct radeon_i2c_chan *i2c = i2c_priv; 190 struct radeon_device *rdev = i2c->dev->dev_private; 191 struct radeon_i2c_bus_rec *rec = &i2c->rec; 192 uint32_t val; 193 194 /* read the value off the pin */ 195 val = RREG32(rec->y_clk_reg); 196 val &= rec->y_clk_mask; 197 198 return (val != 0); 199 } 200 201 202 static int get_data(void *i2c_priv) 203 { 204 struct radeon_i2c_chan *i2c = i2c_priv; 205 struct radeon_device *rdev = i2c->dev->dev_private; 206 struct radeon_i2c_bus_rec *rec = &i2c->rec; 207 uint32_t val; 208 209 /* read the value off the pin */ 210 val = RREG32(rec->y_data_reg); 211 val &= rec->y_data_mask; 212 213 return (val != 0); 214 } 215 216 static void set_clock(void *i2c_priv, int clock) 217 { 218 struct radeon_i2c_chan *i2c = i2c_priv; 219 struct radeon_device *rdev = i2c->dev->dev_private; 220 struct radeon_i2c_bus_rec *rec = &i2c->rec; 221 uint32_t val; 222 223 /* set pin direction */ 224 val = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask; 225 val |= clock ? 0 : rec->en_clk_mask; 226 WREG32(rec->en_clk_reg, val); 227 } 228 229 static void set_data(void *i2c_priv, int data) 230 { 231 struct radeon_i2c_chan *i2c = i2c_priv; 232 struct radeon_device *rdev = i2c->dev->dev_private; 233 struct radeon_i2c_bus_rec *rec = &i2c->rec; 234 uint32_t val; 235 236 /* set pin direction */ 237 val = RREG32(rec->en_data_reg) & ~rec->en_data_mask; 238 val |= data ? 0 : rec->en_data_mask; 239 WREG32(rec->en_data_reg, val); 240 } 241 242 /* hw i2c */ 243 244 static u32 radeon_get_i2c_prescale(struct radeon_device *rdev) 245 { 246 u32 sclk = rdev->pm.current_sclk; 247 u32 prescale = 0; 248 u32 nm; 249 u8 n, m, loop; 250 int i2c_clock; 251 252 switch (rdev->family) { 253 case CHIP_R100: 254 case CHIP_RV100: 255 case CHIP_RS100: 256 case CHIP_RV200: 257 case CHIP_RS200: 258 case CHIP_R200: 259 case CHIP_RV250: 260 case CHIP_RS300: 261 case CHIP_RV280: 262 case CHIP_R300: 263 case CHIP_R350: 264 case CHIP_RV350: 265 i2c_clock = 60; 266 nm = (sclk * 10) / (i2c_clock * 4); 267 for (loop = 1; loop < 255; loop++) { 268 if ((nm / loop) < loop) 269 break; 270 } 271 n = loop - 1; 272 m = loop - 2; 273 prescale = m | (n << 8); 274 break; 275 case CHIP_RV380: 276 case CHIP_RS400: 277 case CHIP_RS480: 278 case CHIP_R420: 279 case CHIP_R423: 280 case CHIP_RV410: 281 prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128; 282 break; 283 case CHIP_RS600: 284 case CHIP_RS690: 285 case CHIP_RS740: 286 /* todo */ 287 break; 288 case CHIP_RV515: 289 case CHIP_R520: 290 case CHIP_RV530: 291 case CHIP_RV560: 292 case CHIP_RV570: 293 case CHIP_R580: 294 i2c_clock = 50; 295 if (rdev->family == CHIP_R520) 296 prescale = (127 << 8) + ((sclk * 10) / (4 * 127 * i2c_clock)); 297 else 298 prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128; 299 break; 300 case CHIP_R600: 301 case CHIP_RV610: 302 case CHIP_RV630: 303 case CHIP_RV670: 304 /* todo */ 305 break; 306 case CHIP_RV620: 307 case CHIP_RV635: 308 case CHIP_RS780: 309 case CHIP_RS880: 310 case CHIP_RV770: 311 case CHIP_RV730: 312 case CHIP_RV710: 313 case CHIP_RV740: 314 /* todo */ 315 break; 316 case CHIP_CEDAR: 317 case CHIP_REDWOOD: 318 case CHIP_JUNIPER: 319 case CHIP_CYPRESS: 320 case CHIP_HEMLOCK: 321 /* todo */ 322 break; 323 default: 324 DRM_ERROR("i2c: unhandled radeon chip\n"); 325 break; 326 } 327 return prescale; 328 } 329 330 331 /* hw i2c engine for r1xx-4xx hardware 332 * hw can buffer up to 15 bytes 333 */ 334 static int r100_hw_i2c_xfer(struct i2c_adapter *i2c_adap, 335 struct i2c_msg *msgs, int num) 336 { 337 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); 338 struct radeon_device *rdev = i2c->dev->dev_private; 339 struct radeon_i2c_bus_rec *rec = &i2c->rec; 340 struct i2c_msg *p; 341 int i, j, k, ret = num; 342 u32 prescale; 343 u32 i2c_cntl_0, i2c_cntl_1, i2c_data; 344 u32 tmp, reg; 345 346 mutex_lock(&rdev->dc_hw_i2c_mutex); 347 /* take the pm lock since we need a constant sclk */ 348 mutex_lock(&rdev->pm.mutex); 349 350 prescale = radeon_get_i2c_prescale(rdev); 351 352 reg = ((prescale << RADEON_I2C_PRESCALE_SHIFT) | 353 RADEON_I2C_DRIVE_EN | 354 RADEON_I2C_START | 355 RADEON_I2C_STOP | 356 RADEON_I2C_GO); 357 358 if (rdev->is_atom_bios) { 359 tmp = RREG32(RADEON_BIOS_6_SCRATCH); 360 WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE); 361 } 362 363 if (rec->mm_i2c) { 364 i2c_cntl_0 = RADEON_I2C_CNTL_0; 365 i2c_cntl_1 = RADEON_I2C_CNTL_1; 366 i2c_data = RADEON_I2C_DATA; 367 } else { 368 i2c_cntl_0 = RADEON_DVI_I2C_CNTL_0; 369 i2c_cntl_1 = RADEON_DVI_I2C_CNTL_1; 370 i2c_data = RADEON_DVI_I2C_DATA; 371 372 switch (rdev->family) { 373 case CHIP_R100: 374 case CHIP_RV100: 375 case CHIP_RS100: 376 case CHIP_RV200: 377 case CHIP_RS200: 378 case CHIP_RS300: 379 switch (rec->mask_clk_reg) { 380 case RADEON_GPIO_DVI_DDC: 381 /* no gpio select bit */ 382 break; 383 default: 384 DRM_ERROR("gpio not supported with hw i2c\n"); 385 ret = -EINVAL; 386 goto done; 387 } 388 break; 389 case CHIP_R200: 390 /* only bit 4 on r200 */ 391 switch (rec->mask_clk_reg) { 392 case RADEON_GPIO_DVI_DDC: 393 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); 394 break; 395 case RADEON_GPIO_MONID: 396 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); 397 break; 398 default: 399 DRM_ERROR("gpio not supported with hw i2c\n"); 400 ret = -EINVAL; 401 goto done; 402 } 403 break; 404 case CHIP_RV250: 405 case CHIP_RV280: 406 /* bits 3 and 4 */ 407 switch (rec->mask_clk_reg) { 408 case RADEON_GPIO_DVI_DDC: 409 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); 410 break; 411 case RADEON_GPIO_VGA_DDC: 412 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2); 413 break; 414 case RADEON_GPIO_CRT2_DDC: 415 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); 416 break; 417 default: 418 DRM_ERROR("gpio not supported with hw i2c\n"); 419 ret = -EINVAL; 420 goto done; 421 } 422 break; 423 case CHIP_R300: 424 case CHIP_R350: 425 /* only bit 4 on r300/r350 */ 426 switch (rec->mask_clk_reg) { 427 case RADEON_GPIO_VGA_DDC: 428 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); 429 break; 430 case RADEON_GPIO_DVI_DDC: 431 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); 432 break; 433 default: 434 DRM_ERROR("gpio not supported with hw i2c\n"); 435 ret = -EINVAL; 436 goto done; 437 } 438 break; 439 case CHIP_RV350: 440 case CHIP_RV380: 441 case CHIP_R420: 442 case CHIP_R423: 443 case CHIP_RV410: 444 case CHIP_RS400: 445 case CHIP_RS480: 446 /* bits 3 and 4 */ 447 switch (rec->mask_clk_reg) { 448 case RADEON_GPIO_VGA_DDC: 449 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); 450 break; 451 case RADEON_GPIO_DVI_DDC: 452 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2); 453 break; 454 case RADEON_GPIO_MONID: 455 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); 456 break; 457 default: 458 DRM_ERROR("gpio not supported with hw i2c\n"); 459 ret = -EINVAL; 460 goto done; 461 } 462 break; 463 default: 464 DRM_ERROR("unsupported asic\n"); 465 ret = -EINVAL; 466 goto done; 467 break; 468 } 469 } 470 471 /* check for bus probe */ 472 p = &msgs[0]; 473 if ((num == 1) && (p->len == 0)) { 474 WREG32(i2c_cntl_0, (RADEON_I2C_DONE | 475 RADEON_I2C_NACK | 476 RADEON_I2C_HALT | 477 RADEON_I2C_SOFT_RST)); 478 WREG32(i2c_data, (p->addr << 1) & 0xff); 479 WREG32(i2c_data, 0); 480 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) | 481 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) | 482 RADEON_I2C_EN | 483 (48 << RADEON_I2C_TIME_LIMIT_SHIFT))); 484 WREG32(i2c_cntl_0, reg); 485 for (k = 0; k < 32; k++) { 486 udelay(10); 487 tmp = RREG32(i2c_cntl_0); 488 if (tmp & RADEON_I2C_GO) 489 continue; 490 tmp = RREG32(i2c_cntl_0); 491 if (tmp & RADEON_I2C_DONE) 492 break; 493 else { 494 DRM_DEBUG("i2c write error 0x%08x\n", tmp); 495 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT); 496 ret = -EIO; 497 goto done; 498 } 499 } 500 goto done; 501 } 502 503 for (i = 0; i < num; i++) { 504 p = &msgs[i]; 505 for (j = 0; j < p->len; j++) { 506 if (p->flags & I2C_M_RD) { 507 WREG32(i2c_cntl_0, (RADEON_I2C_DONE | 508 RADEON_I2C_NACK | 509 RADEON_I2C_HALT | 510 RADEON_I2C_SOFT_RST)); 511 WREG32(i2c_data, ((p->addr << 1) & 0xff) | 0x1); 512 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) | 513 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) | 514 RADEON_I2C_EN | 515 (48 << RADEON_I2C_TIME_LIMIT_SHIFT))); 516 WREG32(i2c_cntl_0, reg | RADEON_I2C_RECEIVE); 517 for (k = 0; k < 32; k++) { 518 udelay(10); 519 tmp = RREG32(i2c_cntl_0); 520 if (tmp & RADEON_I2C_GO) 521 continue; 522 tmp = RREG32(i2c_cntl_0); 523 if (tmp & RADEON_I2C_DONE) 524 break; 525 else { 526 DRM_DEBUG("i2c read error 0x%08x\n", tmp); 527 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT); 528 ret = -EIO; 529 goto done; 530 } 531 } 532 p->buf[j] = RREG32(i2c_data) & 0xff; 533 } else { 534 WREG32(i2c_cntl_0, (RADEON_I2C_DONE | 535 RADEON_I2C_NACK | 536 RADEON_I2C_HALT | 537 RADEON_I2C_SOFT_RST)); 538 WREG32(i2c_data, (p->addr << 1) & 0xff); 539 WREG32(i2c_data, p->buf[j]); 540 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) | 541 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) | 542 RADEON_I2C_EN | 543 (48 << RADEON_I2C_TIME_LIMIT_SHIFT))); 544 WREG32(i2c_cntl_0, reg); 545 for (k = 0; k < 32; k++) { 546 udelay(10); 547 tmp = RREG32(i2c_cntl_0); 548 if (tmp & RADEON_I2C_GO) 549 continue; 550 tmp = RREG32(i2c_cntl_0); 551 if (tmp & RADEON_I2C_DONE) 552 break; 553 else { 554 DRM_DEBUG("i2c write error 0x%08x\n", tmp); 555 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT); 556 ret = -EIO; 557 goto done; 558 } 559 } 560 } 561 } 562 } 563 564 done: 565 WREG32(i2c_cntl_0, 0); 566 WREG32(i2c_cntl_1, 0); 567 WREG32(i2c_cntl_0, (RADEON_I2C_DONE | 568 RADEON_I2C_NACK | 569 RADEON_I2C_HALT | 570 RADEON_I2C_SOFT_RST)); 571 572 if (rdev->is_atom_bios) { 573 tmp = RREG32(RADEON_BIOS_6_SCRATCH); 574 tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE; 575 WREG32(RADEON_BIOS_6_SCRATCH, tmp); 576 } 577 578 mutex_unlock(&rdev->pm.mutex); 579 mutex_unlock(&rdev->dc_hw_i2c_mutex); 580 581 return ret; 582 } 583 584 /* hw i2c engine for r5xx hardware 585 * hw can buffer up to 15 bytes 586 */ 587 static int r500_hw_i2c_xfer(struct i2c_adapter *i2c_adap, 588 struct i2c_msg *msgs, int num) 589 { 590 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); 591 struct radeon_device *rdev = i2c->dev->dev_private; 592 struct radeon_i2c_bus_rec *rec = &i2c->rec; 593 struct i2c_msg *p; 594 int i, j, remaining, current_count, buffer_offset, ret = num; 595 u32 prescale; 596 u32 tmp, reg; 597 u32 saved1, saved2; 598 599 mutex_lock(&rdev->dc_hw_i2c_mutex); 600 /* take the pm lock since we need a constant sclk */ 601 mutex_lock(&rdev->pm.mutex); 602 603 prescale = radeon_get_i2c_prescale(rdev); 604 605 /* clear gpio mask bits */ 606 tmp = RREG32(rec->mask_clk_reg); 607 tmp &= ~rec->mask_clk_mask; 608 WREG32(rec->mask_clk_reg, tmp); 609 tmp = RREG32(rec->mask_clk_reg); 610 611 tmp = RREG32(rec->mask_data_reg); 612 tmp &= ~rec->mask_data_mask; 613 WREG32(rec->mask_data_reg, tmp); 614 tmp = RREG32(rec->mask_data_reg); 615 616 /* clear pin values */ 617 tmp = RREG32(rec->a_clk_reg); 618 tmp &= ~rec->a_clk_mask; 619 WREG32(rec->a_clk_reg, tmp); 620 tmp = RREG32(rec->a_clk_reg); 621 622 tmp = RREG32(rec->a_data_reg); 623 tmp &= ~rec->a_data_mask; 624 WREG32(rec->a_data_reg, tmp); 625 tmp = RREG32(rec->a_data_reg); 626 627 /* set the pins to input */ 628 tmp = RREG32(rec->en_clk_reg); 629 tmp &= ~rec->en_clk_mask; 630 WREG32(rec->en_clk_reg, tmp); 631 tmp = RREG32(rec->en_clk_reg); 632 633 tmp = RREG32(rec->en_data_reg); 634 tmp &= ~rec->en_data_mask; 635 WREG32(rec->en_data_reg, tmp); 636 tmp = RREG32(rec->en_data_reg); 637 638 /* */ 639 tmp = RREG32(RADEON_BIOS_6_SCRATCH); 640 WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE); 641 saved1 = RREG32(AVIVO_DC_I2C_CONTROL1); 642 saved2 = RREG32(0x494); 643 WREG32(0x494, saved2 | 0x1); 644 645 WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_WANTS_TO_USE_I2C); 646 for (i = 0; i < 50; i++) { 647 udelay(1); 648 if (RREG32(AVIVO_DC_I2C_ARBITRATION) & AVIVO_DC_I2C_SW_CAN_USE_I2C) 649 break; 650 } 651 if (i == 50) { 652 DRM_ERROR("failed to get i2c bus\n"); 653 ret = -EBUSY; 654 goto done; 655 } 656 657 reg = AVIVO_DC_I2C_START | AVIVO_DC_I2C_STOP | AVIVO_DC_I2C_EN; 658 switch (rec->mask_clk_reg) { 659 case AVIVO_DC_GPIO_DDC1_MASK: 660 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC1); 661 break; 662 case AVIVO_DC_GPIO_DDC2_MASK: 663 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC2); 664 break; 665 case AVIVO_DC_GPIO_DDC3_MASK: 666 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC3); 667 break; 668 default: 669 DRM_ERROR("gpio not supported with hw i2c\n"); 670 ret = -EINVAL; 671 goto done; 672 } 673 674 /* check for bus probe */ 675 p = &msgs[0]; 676 if ((num == 1) && (p->len == 0)) { 677 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | 678 AVIVO_DC_I2C_NACK | 679 AVIVO_DC_I2C_HALT)); 680 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); 681 udelay(1); 682 WREG32(AVIVO_DC_I2C_RESET, 0); 683 684 WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff); 685 WREG32(AVIVO_DC_I2C_DATA, 0); 686 687 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48)); 688 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) | 689 AVIVO_DC_I2C_DATA_COUNT(1) | 690 (prescale << 16))); 691 WREG32(AVIVO_DC_I2C_CONTROL1, reg); 692 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO); 693 for (j = 0; j < 200; j++) { 694 udelay(50); 695 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 696 if (tmp & AVIVO_DC_I2C_GO) 697 continue; 698 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 699 if (tmp & AVIVO_DC_I2C_DONE) 700 break; 701 else { 702 DRM_DEBUG("i2c write error 0x%08x\n", tmp); 703 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT); 704 ret = -EIO; 705 goto done; 706 } 707 } 708 goto done; 709 } 710 711 for (i = 0; i < num; i++) { 712 p = &msgs[i]; 713 remaining = p->len; 714 buffer_offset = 0; 715 if (p->flags & I2C_M_RD) { 716 while (remaining) { 717 if (remaining > 15) 718 current_count = 15; 719 else 720 current_count = remaining; 721 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | 722 AVIVO_DC_I2C_NACK | 723 AVIVO_DC_I2C_HALT)); 724 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); 725 udelay(1); 726 WREG32(AVIVO_DC_I2C_RESET, 0); 727 728 WREG32(AVIVO_DC_I2C_DATA, ((p->addr << 1) & 0xff) | 0x1); 729 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48)); 730 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) | 731 AVIVO_DC_I2C_DATA_COUNT(current_count) | 732 (prescale << 16))); 733 WREG32(AVIVO_DC_I2C_CONTROL1, reg | AVIVO_DC_I2C_RECEIVE); 734 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO); 735 for (j = 0; j < 200; j++) { 736 udelay(50); 737 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 738 if (tmp & AVIVO_DC_I2C_GO) 739 continue; 740 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 741 if (tmp & AVIVO_DC_I2C_DONE) 742 break; 743 else { 744 DRM_DEBUG("i2c read error 0x%08x\n", tmp); 745 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT); 746 ret = -EIO; 747 goto done; 748 } 749 } 750 for (j = 0; j < current_count; j++) 751 p->buf[buffer_offset + j] = RREG32(AVIVO_DC_I2C_DATA) & 0xff; 752 remaining -= current_count; 753 buffer_offset += current_count; 754 } 755 } else { 756 while (remaining) { 757 if (remaining > 15) 758 current_count = 15; 759 else 760 current_count = remaining; 761 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | 762 AVIVO_DC_I2C_NACK | 763 AVIVO_DC_I2C_HALT)); 764 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); 765 udelay(1); 766 WREG32(AVIVO_DC_I2C_RESET, 0); 767 768 WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff); 769 for (j = 0; j < current_count; j++) 770 WREG32(AVIVO_DC_I2C_DATA, p->buf[buffer_offset + j]); 771 772 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48)); 773 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) | 774 AVIVO_DC_I2C_DATA_COUNT(current_count) | 775 (prescale << 16))); 776 WREG32(AVIVO_DC_I2C_CONTROL1, reg); 777 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO); 778 for (j = 0; j < 200; j++) { 779 udelay(50); 780 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 781 if (tmp & AVIVO_DC_I2C_GO) 782 continue; 783 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 784 if (tmp & AVIVO_DC_I2C_DONE) 785 break; 786 else { 787 DRM_DEBUG("i2c write error 0x%08x\n", tmp); 788 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT); 789 ret = -EIO; 790 goto done; 791 } 792 } 793 remaining -= current_count; 794 buffer_offset += current_count; 795 } 796 } 797 } 798 799 done: 800 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | 801 AVIVO_DC_I2C_NACK | 802 AVIVO_DC_I2C_HALT)); 803 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); 804 udelay(1); 805 WREG32(AVIVO_DC_I2C_RESET, 0); 806 807 WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_DONE_USING_I2C); 808 WREG32(AVIVO_DC_I2C_CONTROL1, saved1); 809 WREG32(0x494, saved2); 810 tmp = RREG32(RADEON_BIOS_6_SCRATCH); 811 tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE; 812 WREG32(RADEON_BIOS_6_SCRATCH, tmp); 813 814 mutex_unlock(&rdev->pm.mutex); 815 mutex_unlock(&rdev->dc_hw_i2c_mutex); 816 817 return ret; 818 } 819 820 static int radeon_hw_i2c_xfer(struct i2c_adapter *i2c_adap, 821 struct i2c_msg *msgs, int num) 822 { 823 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); 824 struct radeon_device *rdev = i2c->dev->dev_private; 825 struct radeon_i2c_bus_rec *rec = &i2c->rec; 826 int ret = 0; 827 828 mutex_lock(&i2c->mutex); 829 830 switch (rdev->family) { 831 case CHIP_R100: 832 case CHIP_RV100: 833 case CHIP_RS100: 834 case CHIP_RV200: 835 case CHIP_RS200: 836 case CHIP_R200: 837 case CHIP_RV250: 838 case CHIP_RS300: 839 case CHIP_RV280: 840 case CHIP_R300: 841 case CHIP_R350: 842 case CHIP_RV350: 843 case CHIP_RV380: 844 case CHIP_R420: 845 case CHIP_R423: 846 case CHIP_RV410: 847 case CHIP_RS400: 848 case CHIP_RS480: 849 ret = r100_hw_i2c_xfer(i2c_adap, msgs, num); 850 break; 851 case CHIP_RS600: 852 case CHIP_RS690: 853 case CHIP_RS740: 854 /* XXX fill in hw i2c implementation */ 855 break; 856 case CHIP_RV515: 857 case CHIP_R520: 858 case CHIP_RV530: 859 case CHIP_RV560: 860 case CHIP_RV570: 861 case CHIP_R580: 862 if (rec->mm_i2c) 863 ret = r100_hw_i2c_xfer(i2c_adap, msgs, num); 864 else 865 ret = r500_hw_i2c_xfer(i2c_adap, msgs, num); 866 break; 867 case CHIP_R600: 868 case CHIP_RV610: 869 case CHIP_RV630: 870 case CHIP_RV670: 871 /* XXX fill in hw i2c implementation */ 872 break; 873 case CHIP_RV620: 874 case CHIP_RV635: 875 case CHIP_RS780: 876 case CHIP_RS880: 877 case CHIP_RV770: 878 case CHIP_RV730: 879 case CHIP_RV710: 880 case CHIP_RV740: 881 /* XXX fill in hw i2c implementation */ 882 break; 883 case CHIP_CEDAR: 884 case CHIP_REDWOOD: 885 case CHIP_JUNIPER: 886 case CHIP_CYPRESS: 887 case CHIP_HEMLOCK: 888 /* XXX fill in hw i2c implementation */ 889 break; 890 default: 891 DRM_ERROR("i2c: unhandled radeon chip\n"); 892 ret = -EIO; 893 break; 894 } 895 896 mutex_unlock(&i2c->mutex); 897 898 return ret; 899 } 900 901 static u32 radeon_hw_i2c_func(struct i2c_adapter *adap) 902 { 903 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 904 } 905 906 static const struct i2c_algorithm radeon_i2c_algo = { 907 .master_xfer = radeon_hw_i2c_xfer, 908 .functionality = radeon_hw_i2c_func, 909 }; 910 911 static const struct i2c_algorithm radeon_atom_i2c_algo = { 912 .master_xfer = radeon_atom_hw_i2c_xfer, 913 .functionality = radeon_atom_hw_i2c_func, 914 }; 915 916 struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, 917 struct radeon_i2c_bus_rec *rec, 918 const char *name) 919 { 920 struct radeon_device *rdev = dev->dev_private; 921 struct radeon_i2c_chan *i2c; 922 int ret; 923 924 /* don't add the mm_i2c bus unless hw_i2c is enabled */ 925 if (rec->mm_i2c && (radeon_hw_i2c == 0)) 926 return NULL; 927 928 i2c = kzalloc(sizeof(struct radeon_i2c_chan), GFP_KERNEL); 929 if (i2c == NULL) 930 return NULL; 931 932 i2c->rec = *rec; 933 i2c->adapter.owner = THIS_MODULE; 934 i2c->adapter.class = I2C_CLASS_DDC; 935 i2c->adapter.dev.parent = &dev->pdev->dev; 936 i2c->dev = dev; 937 i2c_set_adapdata(&i2c->adapter, i2c); 938 mutex_init(&i2c->mutex); 939 if (rec->mm_i2c || 940 (rec->hw_capable && 941 radeon_hw_i2c && 942 ((rdev->family <= CHIP_RS480) || 943 ((rdev->family >= CHIP_RV515) && (rdev->family <= CHIP_R580))))) { 944 /* set the radeon hw i2c adapter */ 945 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name), 946 "Radeon i2c hw bus %s", name); 947 i2c->adapter.algo = &radeon_i2c_algo; 948 ret = i2c_add_adapter(&i2c->adapter); 949 if (ret) 950 goto out_free; 951 } else if (rec->hw_capable && 952 radeon_hw_i2c && 953 ASIC_IS_DCE3(rdev)) { 954 /* hw i2c using atom */ 955 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name), 956 "Radeon i2c hw bus %s", name); 957 i2c->adapter.algo = &radeon_atom_i2c_algo; 958 ret = i2c_add_adapter(&i2c->adapter); 959 if (ret) 960 goto out_free; 961 } else { 962 /* set the radeon bit adapter */ 963 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name), 964 "Radeon i2c bit bus %s", name); 965 i2c->adapter.algo_data = &i2c->bit; 966 i2c->bit.pre_xfer = pre_xfer; 967 i2c->bit.post_xfer = post_xfer; 968 i2c->bit.setsda = set_data; 969 i2c->bit.setscl = set_clock; 970 i2c->bit.getsda = get_data; 971 i2c->bit.getscl = get_clock; 972 i2c->bit.udelay = 10; 973 i2c->bit.timeout = usecs_to_jiffies(2200); /* from VESA */ 974 i2c->bit.data = i2c; 975 ret = i2c_bit_add_bus(&i2c->adapter); 976 if (ret) { 977 DRM_ERROR("Failed to register bit i2c %s\n", name); 978 goto out_free; 979 } 980 } 981 982 return i2c; 983 out_free: 984 kfree(i2c); 985 return NULL; 986 987 } 988 989 void radeon_i2c_destroy(struct radeon_i2c_chan *i2c) 990 { 991 if (!i2c) 992 return; 993 WARN_ON(i2c->has_aux); 994 i2c_del_adapter(&i2c->adapter); 995 kfree(i2c); 996 } 997 998 /* Add the default buses */ 999 void radeon_i2c_init(struct radeon_device *rdev) 1000 { 1001 if (radeon_hw_i2c) 1002 DRM_INFO("hw_i2c forced on, you may experience display detection problems!\n"); 1003 1004 if (rdev->is_atom_bios) 1005 radeon_atombios_i2c_init(rdev); 1006 else 1007 radeon_combios_i2c_init(rdev); 1008 } 1009 1010 /* remove all the buses */ 1011 void radeon_i2c_fini(struct radeon_device *rdev) 1012 { 1013 int i; 1014 1015 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) { 1016 if (rdev->i2c_bus[i]) { 1017 radeon_i2c_destroy(rdev->i2c_bus[i]); 1018 rdev->i2c_bus[i] = NULL; 1019 } 1020 } 1021 } 1022 1023 /* Add additional buses */ 1024 void radeon_i2c_add(struct radeon_device *rdev, 1025 struct radeon_i2c_bus_rec *rec, 1026 const char *name) 1027 { 1028 struct drm_device *dev = rdev->ddev; 1029 int i; 1030 1031 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) { 1032 if (!rdev->i2c_bus[i]) { 1033 rdev->i2c_bus[i] = radeon_i2c_create(dev, rec, name); 1034 return; 1035 } 1036 } 1037 } 1038 1039 /* looks up bus based on id */ 1040 struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev, 1041 struct radeon_i2c_bus_rec *i2c_bus) 1042 { 1043 int i; 1044 1045 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) { 1046 if (rdev->i2c_bus[i] && 1047 (rdev->i2c_bus[i]->rec.i2c_id == i2c_bus->i2c_id)) { 1048 return rdev->i2c_bus[i]; 1049 } 1050 } 1051 return NULL; 1052 } 1053 1054 void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus, 1055 u8 slave_addr, 1056 u8 addr, 1057 u8 *val) 1058 { 1059 u8 out_buf[2]; 1060 u8 in_buf[2]; 1061 struct i2c_msg msgs[] = { 1062 { 1063 .addr = slave_addr, 1064 .flags = 0, 1065 .len = 1, 1066 .buf = out_buf, 1067 }, 1068 { 1069 .addr = slave_addr, 1070 .flags = I2C_M_RD, 1071 .len = 1, 1072 .buf = in_buf, 1073 } 1074 }; 1075 1076 out_buf[0] = addr; 1077 out_buf[1] = 0; 1078 1079 if (i2c_transfer(&i2c_bus->adapter, msgs, 2) == 2) { 1080 *val = in_buf[0]; 1081 DRM_DEBUG("val = 0x%02x\n", *val); 1082 } else { 1083 DRM_DEBUG("i2c 0x%02x 0x%02x read failed\n", 1084 addr, *val); 1085 } 1086 } 1087 1088 void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c_bus, 1089 u8 slave_addr, 1090 u8 addr, 1091 u8 val) 1092 { 1093 uint8_t out_buf[2]; 1094 struct i2c_msg msg = { 1095 .addr = slave_addr, 1096 .flags = 0, 1097 .len = 2, 1098 .buf = out_buf, 1099 }; 1100 1101 out_buf[0] = addr; 1102 out_buf[1] = val; 1103 1104 if (i2c_transfer(&i2c_bus->adapter, &msg, 1) != 1) 1105 DRM_DEBUG("i2c 0x%02x 0x%02x write failed\n", 1106 addr, val); 1107 } 1108 1109 /* ddc router switching */ 1110 void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector) 1111 { 1112 u8 val; 1113 1114 if (!radeon_connector->router.ddc_valid) 1115 return; 1116 1117 if (!radeon_connector->router_bus) 1118 return; 1119 1120 radeon_i2c_get_byte(radeon_connector->router_bus, 1121 radeon_connector->router.i2c_addr, 1122 0x3, &val); 1123 val &= ~radeon_connector->router.ddc_mux_control_pin; 1124 radeon_i2c_put_byte(radeon_connector->router_bus, 1125 radeon_connector->router.i2c_addr, 1126 0x3, val); 1127 radeon_i2c_get_byte(radeon_connector->router_bus, 1128 radeon_connector->router.i2c_addr, 1129 0x1, &val); 1130 val &= ~radeon_connector->router.ddc_mux_control_pin; 1131 val |= radeon_connector->router.ddc_mux_state; 1132 radeon_i2c_put_byte(radeon_connector->router_bus, 1133 radeon_connector->router.i2c_addr, 1134 0x1, val); 1135 } 1136 1137 /* clock/data router switching */ 1138 void radeon_router_select_cd_port(struct radeon_connector *radeon_connector) 1139 { 1140 u8 val; 1141 1142 if (!radeon_connector->router.cd_valid) 1143 return; 1144 1145 if (!radeon_connector->router_bus) 1146 return; 1147 1148 radeon_i2c_get_byte(radeon_connector->router_bus, 1149 radeon_connector->router.i2c_addr, 1150 0x3, &val); 1151 val &= ~radeon_connector->router.cd_mux_control_pin; 1152 radeon_i2c_put_byte(radeon_connector->router_bus, 1153 radeon_connector->router.i2c_addr, 1154 0x3, val); 1155 radeon_i2c_get_byte(radeon_connector->router_bus, 1156 radeon_connector->router.i2c_addr, 1157 0x1, &val); 1158 val &= ~radeon_connector->router.cd_mux_control_pin; 1159 val |= radeon_connector->router.cd_mux_state; 1160 radeon_i2c_put_byte(radeon_connector->router_bus, 1161 radeon_connector->router.i2c_addr, 1162 0x1, val); 1163 } 1164 1165
Indexes created Tue Oct 21 16:10:11 GMT 2025