radeon_i2c.c revision 1.3.16.1
1 /* $NetBSD: radeon_i2c.c,v 1.3.16.1 2018/09/06 06:56:32 pgoyette Exp $ */ 2 3 /* 4 * Copyright 2007-8 Advanced Micro Devices, Inc. 5 * Copyright 2008 Red Hat Inc. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 11 * and/or sell copies of the Software, and to permit persons to whom the 12 * Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 23 * OTHER DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: Dave Airlie 26 * Alex Deucher 27 */ 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: radeon_i2c.c,v 1.3.16.1 2018/09/06 06:56:32 pgoyette Exp $"); 30 31 #include <linux/export.h> 32 #include <linux/module.h> 33 34 #include <drm/drmP.h> 35 #include <drm/drm_edid.h> 36 #include <drm/radeon_drm.h> 37 #include "radeon.h" 38 #include "atom.h" 39 40 extern int radeon_atom_hw_i2c_xfer(struct i2c_adapter *i2c_adap, 41 struct i2c_msg *msgs, int num); 42 extern u32 radeon_atom_hw_i2c_func(struct i2c_adapter *adap); 43 44 /** 45 * radeon_ddc_probe 46 * 47 */ 48 bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux) 49 { 50 u8 out = 0x0; 51 u8 buf[8]; 52 int ret; 53 struct i2c_msg msgs[] = { 54 { 55 .addr = DDC_ADDR, 56 .flags = 0, 57 .len = 1, 58 .buf = &out, 59 }, 60 { 61 .addr = DDC_ADDR, 62 .flags = I2C_M_RD, 63 .len = 8, 64 .buf = buf, 65 } 66 }; 67 68 /* on hw with routers, select right port */ 69 if (radeon_connector->router.ddc_valid) 70 radeon_router_select_ddc_port(radeon_connector); 71 72 if (use_aux) { 73 ret = i2c_transfer(&radeon_connector->ddc_bus->aux.ddc, msgs, 2); 74 } else { 75 ret = i2c_transfer(&radeon_connector->ddc_bus->adapter, msgs, 2); 76 } 77 78 if (ret != 2) 79 /* Couldn't find an accessible DDC on this connector */ 80 return false; 81 /* Probe also for valid EDID header 82 * EDID header starts with: 83 * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00. 84 * Only the first 6 bytes must be valid as 85 * drm_edid_block_valid() can fix the last 2 bytes */ 86 if (drm_edid_header_is_valid(buf) < 6) { 87 /* Couldn't find an accessible EDID on this 88 * connector */ 89 return false; 90 } 91 return true; 92 } 93 94 /* bit banging i2c */ 95 96 static int pre_xfer(struct i2c_adapter *i2c_adap) 97 { 98 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); 99 struct radeon_device *rdev = i2c->dev->dev_private; 100 struct radeon_i2c_bus_rec *rec = &i2c->rec; 101 uint32_t temp; 102 103 mutex_lock(&i2c->mutex); 104 105 /* RV410 appears to have a bug where the hw i2c in reset 106 * holds the i2c port in a bad state - switch hw i2c away before 107 * doing DDC - do this for all r200s/r300s/r400s for safety sake 108 */ 109 if (rec->hw_capable) { 110 if ((rdev->family >= CHIP_R200) && !ASIC_IS_AVIVO(rdev)) { 111 u32 reg; 112 113 if (rdev->family >= CHIP_RV350) 114 reg = RADEON_GPIO_MONID; 115 else if ((rdev->family == CHIP_R300) || 116 (rdev->family == CHIP_R350)) 117 reg = RADEON_GPIO_DVI_DDC; 118 else 119 reg = RADEON_GPIO_CRT2_DDC; 120 121 mutex_lock(&rdev->dc_hw_i2c_mutex); 122 if (rec->a_clk_reg == reg) { 123 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST | 124 R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1))); 125 } else { 126 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST | 127 R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3))); 128 } 129 mutex_unlock(&rdev->dc_hw_i2c_mutex); 130 } 131 } 132 133 /* switch the pads to ddc mode */ 134 if (ASIC_IS_DCE3(rdev) && rec->hw_capable) { 135 temp = RREG32(rec->mask_clk_reg); 136 temp &= ~(1 << 16); 137 WREG32(rec->mask_clk_reg, temp); 138 } 139 140 /* clear the output pin values */ 141 temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask; 142 WREG32(rec->a_clk_reg, temp); 143 144 temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask; 145 WREG32(rec->a_data_reg, temp); 146 147 /* set the pins to input */ 148 temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask; 149 WREG32(rec->en_clk_reg, temp); 150 151 temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask; 152 WREG32(rec->en_data_reg, temp); 153 154 /* mask the gpio pins for software use */ 155 temp = RREG32(rec->mask_clk_reg) | rec->mask_clk_mask; 156 WREG32(rec->mask_clk_reg, temp); 157 temp = RREG32(rec->mask_clk_reg); 158 159 temp = RREG32(rec->mask_data_reg) | rec->mask_data_mask; 160 WREG32(rec->mask_data_reg, temp); 161 temp = RREG32(rec->mask_data_reg); 162 163 return 0; 164 } 165 166 static void post_xfer(struct i2c_adapter *i2c_adap) 167 { 168 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); 169 struct radeon_device *rdev = i2c->dev->dev_private; 170 struct radeon_i2c_bus_rec *rec = &i2c->rec; 171 uint32_t temp; 172 173 /* unmask the gpio pins for software use */ 174 temp = RREG32(rec->mask_clk_reg) & ~rec->mask_clk_mask; 175 WREG32(rec->mask_clk_reg, temp); 176 temp = RREG32(rec->mask_clk_reg); 177 178 temp = RREG32(rec->mask_data_reg) & ~rec->mask_data_mask; 179 WREG32(rec->mask_data_reg, temp); 180 temp = RREG32(rec->mask_data_reg); 181 182 mutex_unlock(&i2c->mutex); 183 } 184 185 static int get_clock(void *i2c_priv) 186 { 187 struct radeon_i2c_chan *i2c = i2c_priv; 188 struct radeon_device *rdev = i2c->dev->dev_private; 189 struct radeon_i2c_bus_rec *rec = &i2c->rec; 190 uint32_t val; 191 192 /* read the value off the pin */ 193 val = RREG32(rec->y_clk_reg); 194 val &= rec->y_clk_mask; 195 196 return (val != 0); 197 } 198 199 200 static int get_data(void *i2c_priv) 201 { 202 struct radeon_i2c_chan *i2c = i2c_priv; 203 struct radeon_device *rdev = i2c->dev->dev_private; 204 struct radeon_i2c_bus_rec *rec = &i2c->rec; 205 uint32_t val; 206 207 /* read the value off the pin */ 208 val = RREG32(rec->y_data_reg); 209 val &= rec->y_data_mask; 210 211 return (val != 0); 212 } 213 214 static void set_clock(void *i2c_priv, int clock) 215 { 216 struct radeon_i2c_chan *i2c = i2c_priv; 217 struct radeon_device *rdev = i2c->dev->dev_private; 218 struct radeon_i2c_bus_rec *rec = &i2c->rec; 219 uint32_t val; 220 221 /* set pin direction */ 222 val = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask; 223 val |= clock ? 0 : rec->en_clk_mask; 224 WREG32(rec->en_clk_reg, val); 225 } 226 227 static void set_data(void *i2c_priv, int data) 228 { 229 struct radeon_i2c_chan *i2c = i2c_priv; 230 struct radeon_device *rdev = i2c->dev->dev_private; 231 struct radeon_i2c_bus_rec *rec = &i2c->rec; 232 uint32_t val; 233 234 /* set pin direction */ 235 val = RREG32(rec->en_data_reg) & ~rec->en_data_mask; 236 val |= data ? 0 : rec->en_data_mask; 237 WREG32(rec->en_data_reg, val); 238 } 239 240 /* hw i2c */ 241 242 static u32 radeon_get_i2c_prescale(struct radeon_device *rdev) 243 { 244 u32 sclk = rdev->pm.current_sclk; 245 u32 prescale = 0; 246 u32 nm; 247 u8 n, m, loop; 248 int i2c_clock; 249 250 switch (rdev->family) { 251 case CHIP_R100: 252 case CHIP_RV100: 253 case CHIP_RS100: 254 case CHIP_RV200: 255 case CHIP_RS200: 256 case CHIP_R200: 257 case CHIP_RV250: 258 case CHIP_RS300: 259 case CHIP_RV280: 260 case CHIP_R300: 261 case CHIP_R350: 262 case CHIP_RV350: 263 i2c_clock = 60; 264 nm = (sclk * 10) / (i2c_clock * 4); 265 for (loop = 1; loop < 255; loop++) { 266 if ((nm / loop) < loop) 267 break; 268 } 269 n = loop - 1; 270 m = loop - 2; 271 prescale = m | (n << 8); 272 break; 273 case CHIP_RV380: 274 case CHIP_RS400: 275 case CHIP_RS480: 276 case CHIP_R420: 277 case CHIP_R423: 278 case CHIP_RV410: 279 prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128; 280 break; 281 case CHIP_RS600: 282 case CHIP_RS690: 283 case CHIP_RS740: 284 /* todo */ 285 break; 286 case CHIP_RV515: 287 case CHIP_R520: 288 case CHIP_RV530: 289 case CHIP_RV560: 290 case CHIP_RV570: 291 case CHIP_R580: 292 i2c_clock = 50; 293 if (rdev->family == CHIP_R520) 294 prescale = (127 << 8) + ((sclk * 10) / (4 * 127 * i2c_clock)); 295 else 296 prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128; 297 break; 298 case CHIP_R600: 299 case CHIP_RV610: 300 case CHIP_RV630: 301 case CHIP_RV670: 302 /* todo */ 303 break; 304 case CHIP_RV620: 305 case CHIP_RV635: 306 case CHIP_RS780: 307 case CHIP_RS880: 308 case CHIP_RV770: 309 case CHIP_RV730: 310 case CHIP_RV710: 311 case CHIP_RV740: 312 /* todo */ 313 break; 314 case CHIP_CEDAR: 315 case CHIP_REDWOOD: 316 case CHIP_JUNIPER: 317 case CHIP_CYPRESS: 318 case CHIP_HEMLOCK: 319 /* todo */ 320 break; 321 default: 322 DRM_ERROR("i2c: unhandled radeon chip\n"); 323 break; 324 } 325 return prescale; 326 } 327 328 329 /* hw i2c engine for r1xx-4xx hardware 330 * hw can buffer up to 15 bytes 331 */ 332 static int r100_hw_i2c_xfer(struct i2c_adapter *i2c_adap, 333 struct i2c_msg *msgs, int num) 334 { 335 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); 336 struct radeon_device *rdev = i2c->dev->dev_private; 337 struct radeon_i2c_bus_rec *rec = &i2c->rec; 338 struct i2c_msg *p; 339 int i, j, k, ret = num; 340 u32 prescale; 341 u32 i2c_cntl_0, i2c_cntl_1, i2c_data; 342 u32 tmp, reg; 343 344 mutex_lock(&rdev->dc_hw_i2c_mutex); 345 /* take the pm lock since we need a constant sclk */ 346 mutex_lock(&rdev->pm.mutex); 347 348 prescale = radeon_get_i2c_prescale(rdev); 349 350 reg = ((prescale << RADEON_I2C_PRESCALE_SHIFT) | 351 RADEON_I2C_DRIVE_EN | 352 RADEON_I2C_START | 353 RADEON_I2C_STOP | 354 RADEON_I2C_GO); 355 356 if (rdev->is_atom_bios) { 357 tmp = RREG32(RADEON_BIOS_6_SCRATCH); 358 WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE); 359 } 360 361 if (rec->mm_i2c) { 362 i2c_cntl_0 = RADEON_I2C_CNTL_0; 363 i2c_cntl_1 = RADEON_I2C_CNTL_1; 364 i2c_data = RADEON_I2C_DATA; 365 } else { 366 i2c_cntl_0 = RADEON_DVI_I2C_CNTL_0; 367 i2c_cntl_1 = RADEON_DVI_I2C_CNTL_1; 368 i2c_data = RADEON_DVI_I2C_DATA; 369 370 switch (rdev->family) { 371 case CHIP_R100: 372 case CHIP_RV100: 373 case CHIP_RS100: 374 case CHIP_RV200: 375 case CHIP_RS200: 376 case CHIP_RS300: 377 switch (rec->mask_clk_reg) { 378 case RADEON_GPIO_DVI_DDC: 379 /* no gpio select bit */ 380 break; 381 default: 382 DRM_ERROR("gpio not supported with hw i2c\n"); 383 ret = -EINVAL; 384 goto done; 385 } 386 break; 387 case CHIP_R200: 388 /* only bit 4 on r200 */ 389 switch (rec->mask_clk_reg) { 390 case RADEON_GPIO_DVI_DDC: 391 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); 392 break; 393 case RADEON_GPIO_MONID: 394 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); 395 break; 396 default: 397 DRM_ERROR("gpio not supported with hw i2c\n"); 398 ret = -EINVAL; 399 goto done; 400 } 401 break; 402 case CHIP_RV250: 403 case CHIP_RV280: 404 /* bits 3 and 4 */ 405 switch (rec->mask_clk_reg) { 406 case RADEON_GPIO_DVI_DDC: 407 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); 408 break; 409 case RADEON_GPIO_VGA_DDC: 410 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2); 411 break; 412 case RADEON_GPIO_CRT2_DDC: 413 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); 414 break; 415 default: 416 DRM_ERROR("gpio not supported with hw i2c\n"); 417 ret = -EINVAL; 418 goto done; 419 } 420 break; 421 case CHIP_R300: 422 case CHIP_R350: 423 /* only bit 4 on r300/r350 */ 424 switch (rec->mask_clk_reg) { 425 case RADEON_GPIO_VGA_DDC: 426 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); 427 break; 428 case RADEON_GPIO_DVI_DDC: 429 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); 430 break; 431 default: 432 DRM_ERROR("gpio not supported with hw i2c\n"); 433 ret = -EINVAL; 434 goto done; 435 } 436 break; 437 case CHIP_RV350: 438 case CHIP_RV380: 439 case CHIP_R420: 440 case CHIP_R423: 441 case CHIP_RV410: 442 case CHIP_RS400: 443 case CHIP_RS480: 444 /* bits 3 and 4 */ 445 switch (rec->mask_clk_reg) { 446 case RADEON_GPIO_VGA_DDC: 447 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); 448 break; 449 case RADEON_GPIO_DVI_DDC: 450 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2); 451 break; 452 case RADEON_GPIO_MONID: 453 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); 454 break; 455 default: 456 DRM_ERROR("gpio not supported with hw i2c\n"); 457 ret = -EINVAL; 458 goto done; 459 } 460 break; 461 default: 462 DRM_ERROR("unsupported asic\n"); 463 ret = -EINVAL; 464 goto done; 465 break; 466 } 467 } 468 469 /* check for bus probe */ 470 p = &msgs[0]; 471 if ((num == 1) && (p->len == 0)) { 472 WREG32(i2c_cntl_0, (RADEON_I2C_DONE | 473 RADEON_I2C_NACK | 474 RADEON_I2C_HALT | 475 RADEON_I2C_SOFT_RST)); 476 WREG32(i2c_data, (p->addr << 1) & 0xff); 477 WREG32(i2c_data, 0); 478 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) | 479 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) | 480 RADEON_I2C_EN | 481 (48 << RADEON_I2C_TIME_LIMIT_SHIFT))); 482 WREG32(i2c_cntl_0, reg); 483 for (k = 0; k < 32; k++) { 484 udelay(10); 485 tmp = RREG32(i2c_cntl_0); 486 if (tmp & RADEON_I2C_GO) 487 continue; 488 tmp = RREG32(i2c_cntl_0); 489 if (tmp & RADEON_I2C_DONE) 490 break; 491 else { 492 DRM_DEBUG("i2c write error 0x%08x\n", tmp); 493 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT); 494 ret = -EIO; 495 goto done; 496 } 497 } 498 goto done; 499 } 500 501 for (i = 0; i < num; i++) { 502 p = &msgs[i]; 503 for (j = 0; j < p->len; j++) { 504 if (p->flags & I2C_M_RD) { 505 WREG32(i2c_cntl_0, (RADEON_I2C_DONE | 506 RADEON_I2C_NACK | 507 RADEON_I2C_HALT | 508 RADEON_I2C_SOFT_RST)); 509 WREG32(i2c_data, ((p->addr << 1) & 0xff) | 0x1); 510 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) | 511 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) | 512 RADEON_I2C_EN | 513 (48 << RADEON_I2C_TIME_LIMIT_SHIFT))); 514 WREG32(i2c_cntl_0, reg | RADEON_I2C_RECEIVE); 515 for (k = 0; k < 32; k++) { 516 udelay(10); 517 tmp = RREG32(i2c_cntl_0); 518 if (tmp & RADEON_I2C_GO) 519 continue; 520 tmp = RREG32(i2c_cntl_0); 521 if (tmp & RADEON_I2C_DONE) 522 break; 523 else { 524 DRM_DEBUG("i2c read error 0x%08x\n", tmp); 525 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT); 526 ret = -EIO; 527 goto done; 528 } 529 } 530 p->buf[j] = RREG32(i2c_data) & 0xff; 531 } else { 532 WREG32(i2c_cntl_0, (RADEON_I2C_DONE | 533 RADEON_I2C_NACK | 534 RADEON_I2C_HALT | 535 RADEON_I2C_SOFT_RST)); 536 WREG32(i2c_data, (p->addr << 1) & 0xff); 537 WREG32(i2c_data, p->buf[j]); 538 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) | 539 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) | 540 RADEON_I2C_EN | 541 (48 << RADEON_I2C_TIME_LIMIT_SHIFT))); 542 WREG32(i2c_cntl_0, reg); 543 for (k = 0; k < 32; k++) { 544 udelay(10); 545 tmp = RREG32(i2c_cntl_0); 546 if (tmp & RADEON_I2C_GO) 547 continue; 548 tmp = RREG32(i2c_cntl_0); 549 if (tmp & RADEON_I2C_DONE) 550 break; 551 else { 552 DRM_DEBUG("i2c write error 0x%08x\n", tmp); 553 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT); 554 ret = -EIO; 555 goto done; 556 } 557 } 558 } 559 } 560 } 561 562 done: 563 WREG32(i2c_cntl_0, 0); 564 WREG32(i2c_cntl_1, 0); 565 WREG32(i2c_cntl_0, (RADEON_I2C_DONE | 566 RADEON_I2C_NACK | 567 RADEON_I2C_HALT | 568 RADEON_I2C_SOFT_RST)); 569 570 if (rdev->is_atom_bios) { 571 tmp = RREG32(RADEON_BIOS_6_SCRATCH); 572 tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE; 573 WREG32(RADEON_BIOS_6_SCRATCH, tmp); 574 } 575 576 mutex_unlock(&rdev->pm.mutex); 577 mutex_unlock(&rdev->dc_hw_i2c_mutex); 578 579 return ret; 580 } 581 582 /* hw i2c engine for r5xx hardware 583 * hw can buffer up to 15 bytes 584 */ 585 static int r500_hw_i2c_xfer(struct i2c_adapter *i2c_adap, 586 struct i2c_msg *msgs, int num) 587 { 588 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); 589 struct radeon_device *rdev = i2c->dev->dev_private; 590 struct radeon_i2c_bus_rec *rec = &i2c->rec; 591 struct i2c_msg *p; 592 int i, j, remaining, current_count, buffer_offset, ret = num; 593 u32 prescale; 594 u32 tmp, reg; 595 u32 saved1, saved2; 596 597 mutex_lock(&rdev->dc_hw_i2c_mutex); 598 /* take the pm lock since we need a constant sclk */ 599 mutex_lock(&rdev->pm.mutex); 600 601 prescale = radeon_get_i2c_prescale(rdev); 602 603 /* clear gpio mask bits */ 604 tmp = RREG32(rec->mask_clk_reg); 605 tmp &= ~rec->mask_clk_mask; 606 WREG32(rec->mask_clk_reg, tmp); 607 tmp = RREG32(rec->mask_clk_reg); 608 609 tmp = RREG32(rec->mask_data_reg); 610 tmp &= ~rec->mask_data_mask; 611 WREG32(rec->mask_data_reg, tmp); 612 tmp = RREG32(rec->mask_data_reg); 613 614 /* clear pin values */ 615 tmp = RREG32(rec->a_clk_reg); 616 tmp &= ~rec->a_clk_mask; 617 WREG32(rec->a_clk_reg, tmp); 618 tmp = RREG32(rec->a_clk_reg); 619 620 tmp = RREG32(rec->a_data_reg); 621 tmp &= ~rec->a_data_mask; 622 WREG32(rec->a_data_reg, tmp); 623 tmp = RREG32(rec->a_data_reg); 624 625 /* set the pins to input */ 626 tmp = RREG32(rec->en_clk_reg); 627 tmp &= ~rec->en_clk_mask; 628 WREG32(rec->en_clk_reg, tmp); 629 tmp = RREG32(rec->en_clk_reg); 630 631 tmp = RREG32(rec->en_data_reg); 632 tmp &= ~rec->en_data_mask; 633 WREG32(rec->en_data_reg, tmp); 634 tmp = RREG32(rec->en_data_reg); 635 636 /* */ 637 tmp = RREG32(RADEON_BIOS_6_SCRATCH); 638 WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE); 639 saved1 = RREG32(AVIVO_DC_I2C_CONTROL1); 640 saved2 = RREG32(0x494); 641 WREG32(0x494, saved2 | 0x1); 642 643 WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_WANTS_TO_USE_I2C); 644 for (i = 0; i < 50; i++) { 645 udelay(1); 646 if (RREG32(AVIVO_DC_I2C_ARBITRATION) & AVIVO_DC_I2C_SW_CAN_USE_I2C) 647 break; 648 } 649 if (i == 50) { 650 DRM_ERROR("failed to get i2c bus\n"); 651 ret = -EBUSY; 652 goto done; 653 } 654 655 reg = AVIVO_DC_I2C_START | AVIVO_DC_I2C_STOP | AVIVO_DC_I2C_EN; 656 switch (rec->mask_clk_reg) { 657 case AVIVO_DC_GPIO_DDC1_MASK: 658 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC1); 659 break; 660 case AVIVO_DC_GPIO_DDC2_MASK: 661 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC2); 662 break; 663 case AVIVO_DC_GPIO_DDC3_MASK: 664 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC3); 665 break; 666 default: 667 DRM_ERROR("gpio not supported with hw i2c\n"); 668 ret = -EINVAL; 669 goto done; 670 } 671 672 /* check for bus probe */ 673 p = &msgs[0]; 674 if ((num == 1) && (p->len == 0)) { 675 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | 676 AVIVO_DC_I2C_NACK | 677 AVIVO_DC_I2C_HALT)); 678 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); 679 udelay(1); 680 WREG32(AVIVO_DC_I2C_RESET, 0); 681 682 WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff); 683 WREG32(AVIVO_DC_I2C_DATA, 0); 684 685 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48)); 686 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) | 687 AVIVO_DC_I2C_DATA_COUNT(1) | 688 (prescale << 16))); 689 WREG32(AVIVO_DC_I2C_CONTROL1, reg); 690 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO); 691 for (j = 0; j < 200; j++) { 692 udelay(50); 693 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 694 if (tmp & AVIVO_DC_I2C_GO) 695 continue; 696 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 697 if (tmp & AVIVO_DC_I2C_DONE) 698 break; 699 else { 700 DRM_DEBUG("i2c write error 0x%08x\n", tmp); 701 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT); 702 ret = -EIO; 703 goto done; 704 } 705 } 706 goto done; 707 } 708 709 for (i = 0; i < num; i++) { 710 p = &msgs[i]; 711 remaining = p->len; 712 buffer_offset = 0; 713 if (p->flags & I2C_M_RD) { 714 while (remaining) { 715 if (remaining > 15) 716 current_count = 15; 717 else 718 current_count = remaining; 719 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | 720 AVIVO_DC_I2C_NACK | 721 AVIVO_DC_I2C_HALT)); 722 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); 723 udelay(1); 724 WREG32(AVIVO_DC_I2C_RESET, 0); 725 726 WREG32(AVIVO_DC_I2C_DATA, ((p->addr << 1) & 0xff) | 0x1); 727 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48)); 728 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) | 729 AVIVO_DC_I2C_DATA_COUNT(current_count) | 730 (prescale << 16))); 731 WREG32(AVIVO_DC_I2C_CONTROL1, reg | AVIVO_DC_I2C_RECEIVE); 732 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO); 733 for (j = 0; j < 200; j++) { 734 udelay(50); 735 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 736 if (tmp & AVIVO_DC_I2C_GO) 737 continue; 738 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 739 if (tmp & AVIVO_DC_I2C_DONE) 740 break; 741 else { 742 DRM_DEBUG("i2c read error 0x%08x\n", tmp); 743 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT); 744 ret = -EIO; 745 goto done; 746 } 747 } 748 for (j = 0; j < current_count; j++) 749 p->buf[buffer_offset + j] = RREG32(AVIVO_DC_I2C_DATA) & 0xff; 750 remaining -= current_count; 751 buffer_offset += current_count; 752 } 753 } else { 754 while (remaining) { 755 if (remaining > 15) 756 current_count = 15; 757 else 758 current_count = remaining; 759 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | 760 AVIVO_DC_I2C_NACK | 761 AVIVO_DC_I2C_HALT)); 762 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); 763 udelay(1); 764 WREG32(AVIVO_DC_I2C_RESET, 0); 765 766 WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff); 767 for (j = 0; j < current_count; j++) 768 WREG32(AVIVO_DC_I2C_DATA, p->buf[buffer_offset + j]); 769 770 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48)); 771 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) | 772 AVIVO_DC_I2C_DATA_COUNT(current_count) | 773 (prescale << 16))); 774 WREG32(AVIVO_DC_I2C_CONTROL1, reg); 775 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO); 776 for (j = 0; j < 200; j++) { 777 udelay(50); 778 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 779 if (tmp & AVIVO_DC_I2C_GO) 780 continue; 781 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 782 if (tmp & AVIVO_DC_I2C_DONE) 783 break; 784 else { 785 DRM_DEBUG("i2c write error 0x%08x\n", tmp); 786 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT); 787 ret = -EIO; 788 goto done; 789 } 790 } 791 remaining -= current_count; 792 buffer_offset += current_count; 793 } 794 } 795 } 796 797 done: 798 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | 799 AVIVO_DC_I2C_NACK | 800 AVIVO_DC_I2C_HALT)); 801 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); 802 udelay(1); 803 WREG32(AVIVO_DC_I2C_RESET, 0); 804 805 WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_DONE_USING_I2C); 806 WREG32(AVIVO_DC_I2C_CONTROL1, saved1); 807 WREG32(0x494, saved2); 808 tmp = RREG32(RADEON_BIOS_6_SCRATCH); 809 tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE; 810 WREG32(RADEON_BIOS_6_SCRATCH, tmp); 811 812 mutex_unlock(&rdev->pm.mutex); 813 mutex_unlock(&rdev->dc_hw_i2c_mutex); 814 815 return ret; 816 } 817 818 static int radeon_hw_i2c_xfer(struct i2c_adapter *i2c_adap, 819 struct i2c_msg *msgs, int num) 820 { 821 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); 822 struct radeon_device *rdev = i2c->dev->dev_private; 823 struct radeon_i2c_bus_rec *rec = &i2c->rec; 824 int ret = 0; 825 826 mutex_lock(&i2c->mutex); 827 828 switch (rdev->family) { 829 case CHIP_R100: 830 case CHIP_RV100: 831 case CHIP_RS100: 832 case CHIP_RV200: 833 case CHIP_RS200: 834 case CHIP_R200: 835 case CHIP_RV250: 836 case CHIP_RS300: 837 case CHIP_RV280: 838 case CHIP_R300: 839 case CHIP_R350: 840 case CHIP_RV350: 841 case CHIP_RV380: 842 case CHIP_R420: 843 case CHIP_R423: 844 case CHIP_RV410: 845 case CHIP_RS400: 846 case CHIP_RS480: 847 ret = r100_hw_i2c_xfer(i2c_adap, msgs, num); 848 break; 849 case CHIP_RS600: 850 case CHIP_RS690: 851 case CHIP_RS740: 852 /* XXX fill in hw i2c implementation */ 853 break; 854 case CHIP_RV515: 855 case CHIP_R520: 856 case CHIP_RV530: 857 case CHIP_RV560: 858 case CHIP_RV570: 859 case CHIP_R580: 860 if (rec->mm_i2c) 861 ret = r100_hw_i2c_xfer(i2c_adap, msgs, num); 862 else 863 ret = r500_hw_i2c_xfer(i2c_adap, msgs, num); 864 break; 865 case CHIP_R600: 866 case CHIP_RV610: 867 case CHIP_RV630: 868 case CHIP_RV670: 869 /* XXX fill in hw i2c implementation */ 870 break; 871 case CHIP_RV620: 872 case CHIP_RV635: 873 case CHIP_RS780: 874 case CHIP_RS880: 875 case CHIP_RV770: 876 case CHIP_RV730: 877 case CHIP_RV710: 878 case CHIP_RV740: 879 /* XXX fill in hw i2c implementation */ 880 break; 881 case CHIP_CEDAR: 882 case CHIP_REDWOOD: 883 case CHIP_JUNIPER: 884 case CHIP_CYPRESS: 885 case CHIP_HEMLOCK: 886 /* XXX fill in hw i2c implementation */ 887 break; 888 default: 889 DRM_ERROR("i2c: unhandled radeon chip\n"); 890 ret = -EIO; 891 break; 892 } 893 894 mutex_unlock(&i2c->mutex); 895 896 return ret; 897 } 898 899 static u32 radeon_hw_i2c_func(struct i2c_adapter *adap) 900 { 901 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 902 } 903 904 static const struct i2c_algorithm radeon_i2c_algo = { 905 .master_xfer = radeon_hw_i2c_xfer, 906 .functionality = radeon_hw_i2c_func, 907 }; 908 909 static const struct i2c_algorithm radeon_atom_i2c_algo = { 910 .master_xfer = radeon_atom_hw_i2c_xfer, 911 .functionality = radeon_atom_hw_i2c_func, 912 }; 913 914 struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, 915 struct radeon_i2c_bus_rec *rec, 916 const char *name) 917 { 918 struct radeon_device *rdev = dev->dev_private; 919 struct radeon_i2c_chan *i2c; 920 int ret; 921 922 /* don't add the mm_i2c bus unless hw_i2c is enabled */ 923 if (rec->mm_i2c && (radeon_hw_i2c == 0)) 924 return NULL; 925 926 i2c = kzalloc(sizeof(struct radeon_i2c_chan), GFP_KERNEL); 927 if (i2c == NULL) 928 return NULL; 929 930 i2c->rec = *rec; 931 i2c->adapter.owner = THIS_MODULE; 932 i2c->adapter.class = I2C_CLASS_DDC; 933 i2c->adapter.dev.parent = dev->dev; 934 i2c->dev = dev; 935 i2c_set_adapdata(&i2c->adapter, i2c); 936 #ifdef __NetBSD__ 937 linux_mutex_init(&i2c->mutex); 938 #else 939 mutex_init(&i2c->mutex); 940 #endif 941 if (rec->mm_i2c || 942 (rec->hw_capable && 943 radeon_hw_i2c && 944 ((rdev->family <= CHIP_RS480) || 945 ((rdev->family >= CHIP_RV515) && (rdev->family <= CHIP_R580))))) { 946 /* set the radeon hw i2c adapter */ 947 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name), 948 "Radeon i2c hw bus %s", name); 949 i2c->adapter.algo = &radeon_i2c_algo; 950 ret = i2c_add_adapter(&i2c->adapter); 951 if (ret) { 952 DRM_ERROR("Failed to register hw i2c %s\n", name); 953 goto out_free; 954 } 955 } else if (rec->hw_capable && 956 radeon_hw_i2c && 957 ASIC_IS_DCE3(rdev)) { 958 /* hw i2c using atom */ 959 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name), 960 "Radeon i2c hw bus %s", name); 961 i2c->adapter.algo = &radeon_atom_i2c_algo; 962 ret = i2c_add_adapter(&i2c->adapter); 963 if (ret) { 964 DRM_ERROR("Failed to register hw i2c %s\n", name); 965 goto out_free; 966 } 967 } else { 968 /* set the radeon bit adapter */ 969 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name), 970 "Radeon i2c bit bus %s", name); 971 i2c->adapter.algo_data = &i2c->bit; 972 i2c->bit.pre_xfer = pre_xfer; 973 i2c->bit.post_xfer = post_xfer; 974 i2c->bit.setsda = set_data; 975 i2c->bit.setscl = set_clock; 976 i2c->bit.getsda = get_data; 977 i2c->bit.getscl = get_clock; 978 i2c->bit.udelay = 10; 979 i2c->bit.timeout = usecs_to_jiffies(2200); /* from VESA */ 980 i2c->bit.data = i2c; 981 ret = i2c_bit_add_bus(&i2c->adapter); 982 if (ret) { 983 DRM_ERROR("Failed to register bit i2c %s\n", name); 984 goto out_free; 985 } 986 } 987 988 return i2c; 989 out_free: 990 #ifdef __NetBSD__ 991 linux_mutex_destroy(&i2c->mutex); 992 #else 993 mutex_destroy(&i2c->mutex); 994 #endif 995 kfree(i2c); 996 return NULL; 997 998 } 999 1000 void radeon_i2c_destroy(struct radeon_i2c_chan *i2c) 1001 { 1002 if (!i2c) 1003 return; 1004 i2c_del_adapter(&i2c->adapter); 1005 if (i2c->has_aux) 1006 drm_dp_aux_unregister(&i2c->aux); 1007 #ifdef __NetBSD__ 1008 linux_mutex_destroy(&i2c->mutex); 1009 #else 1010 mutex_destroy(&i2c->mutex); 1011 #endif 1012 kfree(i2c); 1013 } 1014 1015 /* Add the default buses */ 1016 void radeon_i2c_init(struct radeon_device *rdev) 1017 { 1018 if (radeon_hw_i2c) 1019 DRM_INFO("hw_i2c forced on, you may experience display detection problems!\n"); 1020 1021 if (rdev->is_atom_bios) 1022 radeon_atombios_i2c_init(rdev); 1023 else 1024 radeon_combios_i2c_init(rdev); 1025 } 1026 1027 /* remove all the buses */ 1028 void radeon_i2c_fini(struct radeon_device *rdev) 1029 { 1030 int i; 1031 1032 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) { 1033 if (rdev->i2c_bus[i]) { 1034 radeon_i2c_destroy(rdev->i2c_bus[i]); 1035 rdev->i2c_bus[i] = NULL; 1036 } 1037 } 1038 } 1039 1040 /* Add additional buses */ 1041 void radeon_i2c_add(struct radeon_device *rdev, 1042 struct radeon_i2c_bus_rec *rec, 1043 const char *name) 1044 { 1045 struct drm_device *dev = rdev->ddev; 1046 int i; 1047 1048 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) { 1049 if (!rdev->i2c_bus[i]) { 1050 rdev->i2c_bus[i] = radeon_i2c_create(dev, rec, name); 1051 return; 1052 } 1053 } 1054 } 1055 1056 /* looks up bus based on id */ 1057 struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev, 1058 struct radeon_i2c_bus_rec *i2c_bus) 1059 { 1060 int i; 1061 1062 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) { 1063 if (rdev->i2c_bus[i] && 1064 (rdev->i2c_bus[i]->rec.i2c_id == i2c_bus->i2c_id)) { 1065 return rdev->i2c_bus[i]; 1066 } 1067 } 1068 return NULL; 1069 } 1070 1071 void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus, 1072 u8 slave_addr, 1073 u8 addr, 1074 u8 *val) 1075 { 1076 u8 out_buf[2]; 1077 u8 in_buf[2]; 1078 struct i2c_msg msgs[] = { 1079 { 1080 .addr = slave_addr, 1081 .flags = 0, 1082 .len = 1, 1083 .buf = out_buf, 1084 }, 1085 { 1086 .addr = slave_addr, 1087 .flags = I2C_M_RD, 1088 .len = 1, 1089 .buf = in_buf, 1090 } 1091 }; 1092 1093 out_buf[0] = addr; 1094 out_buf[1] = 0; 1095 1096 if (i2c_transfer(&i2c_bus->adapter, msgs, 2) == 2) { 1097 *val = in_buf[0]; 1098 DRM_DEBUG("val = 0x%02x\n", *val); 1099 } else { 1100 DRM_DEBUG("i2c 0x%02x 0x%02x read failed\n", 1101 addr, *val); 1102 } 1103 } 1104 1105 void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c_bus, 1106 u8 slave_addr, 1107 u8 addr, 1108 u8 val) 1109 { 1110 uint8_t out_buf[2]; 1111 struct i2c_msg msg = { 1112 .addr = slave_addr, 1113 .flags = 0, 1114 .len = 2, 1115 .buf = out_buf, 1116 }; 1117 1118 out_buf[0] = addr; 1119 out_buf[1] = val; 1120 1121 if (i2c_transfer(&i2c_bus->adapter, &msg, 1) != 1) 1122 DRM_DEBUG("i2c 0x%02x 0x%02x write failed\n", 1123 addr, val); 1124 } 1125 1126 /* ddc router switching */ 1127 void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector) 1128 { 1129 u8 val; 1130 1131 if (!radeon_connector->router.ddc_valid) 1132 return; 1133 1134 if (!radeon_connector->router_bus) 1135 return; 1136 1137 radeon_i2c_get_byte(radeon_connector->router_bus, 1138 radeon_connector->router.i2c_addr, 1139 0x3, &val); 1140 val &= ~radeon_connector->router.ddc_mux_control_pin; 1141 radeon_i2c_put_byte(radeon_connector->router_bus, 1142 radeon_connector->router.i2c_addr, 1143 0x3, val); 1144 radeon_i2c_get_byte(radeon_connector->router_bus, 1145 radeon_connector->router.i2c_addr, 1146 0x1, &val); 1147 val &= ~radeon_connector->router.ddc_mux_control_pin; 1148 val |= radeon_connector->router.ddc_mux_state; 1149 radeon_i2c_put_byte(radeon_connector->router_bus, 1150 radeon_connector->router.i2c_addr, 1151 0x1, val); 1152 } 1153 1154 /* clock/data router switching */ 1155 void radeon_router_select_cd_port(struct radeon_connector *radeon_connector) 1156 { 1157 u8 val; 1158 1159 if (!radeon_connector->router.cd_valid) 1160 return; 1161 1162 if (!radeon_connector->router_bus) 1163 return; 1164 1165 radeon_i2c_get_byte(radeon_connector->router_bus, 1166 radeon_connector->router.i2c_addr, 1167 0x3, &val); 1168 val &= ~radeon_connector->router.cd_mux_control_pin; 1169 radeon_i2c_put_byte(radeon_connector->router_bus, 1170 radeon_connector->router.i2c_addr, 1171 0x3, val); 1172 radeon_i2c_get_byte(radeon_connector->router_bus, 1173 radeon_connector->router.i2c_addr, 1174 0x1, &val); 1175 val &= ~radeon_connector->router.cd_mux_control_pin; 1176 val |= radeon_connector->router.cd_mux_state; 1177 radeon_i2c_put_byte(radeon_connector->router_bus, 1178 radeon_connector->router.i2c_addr, 1179 0x1, val); 1180 } 1181 1182
Indexes created Mon Oct 20 20:10:13 GMT 2025