radeon_i2c.c revision 1.5.6.1 1 /* $NetBSD: radeon_i2c.c,v 1.5.6.1 2020/02/29 20:20:16 ad Exp $ */
2
3 /*
4 * Copyright 2007-8 Advanced Micro Devices, Inc.
5 * Copyright 2008 Red Hat Inc.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
23 * OTHER DEALINGS IN THE SOFTWARE.
24 *
25 * Authors: Dave Airlie
26 * Alex Deucher
27 */
28 #include <sys/cdefs.h>
29 __KERNEL_RCSID(0, "$NetBSD: radeon_i2c.c,v 1.5.6.1 2020/02/29 20:20:16 ad Exp $");
30
31 #include <linux/export.h>
32
33 #include <drm/drmP.h>
34 #include <drm/drm_edid.h>
35 #include <drm/radeon_drm.h>
36 #include "radeon.h"
37 #include "atom.h"
38
39 #include <linux/nbsd-namespace.h>
40
41 extern int radeon_atom_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
42 struct i2c_msg *msgs, int num);
43 extern u32 radeon_atom_hw_i2c_func(struct i2c_adapter *adap);
44
45 /**
46 * radeon_ddc_probe
47 *
48 */
49 bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux)
50 {
51 u8 out = 0x0;
52 u8 buf[8];
53 int ret;
54 struct i2c_msg msgs[] = {
55 {
56 .addr = DDC_ADDR,
57 .flags = 0,
58 .len = 1,
59 .buf = &out,
60 },
61 {
62 .addr = DDC_ADDR,
63 .flags = I2C_M_RD,
64 .len = 8,
65 .buf = buf,
66 }
67 };
68
69 /* on hw with routers, select right port */
70 if (radeon_connector->router.ddc_valid)
71 radeon_router_select_ddc_port(radeon_connector);
72
73 if (use_aux) {
74 ret = i2c_transfer(&radeon_connector->ddc_bus->aux.ddc, msgs, 2);
75 } else {
76 ret = i2c_transfer(&radeon_connector->ddc_bus->adapter, msgs, 2);
77 }
78
79 if (ret != 2)
80 /* Couldn't find an accessible DDC on this connector */
81 return false;
82 /* Probe also for valid EDID header
83 * EDID header starts with:
84 * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00.
85 * Only the first 6 bytes must be valid as
86 * drm_edid_block_valid() can fix the last 2 bytes */
87 if (drm_edid_header_is_valid(buf) < 6) {
88 /* Couldn't find an accessible EDID on this
89 * connector */
90 return false;
91 }
92 return true;
93 }
94
95 /* bit banging i2c */
96
97 static int pre_xfer(struct i2c_adapter *i2c_adap)
98 {
99 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
100 struct radeon_device *rdev = i2c->dev->dev_private;
101 struct radeon_i2c_bus_rec *rec = &i2c->rec;
102 uint32_t temp;
103
104 mutex_lock(&i2c->mutex);
105
106 /* RV410 appears to have a bug where the hw i2c in reset
107 * holds the i2c port in a bad state - switch hw i2c away before
108 * doing DDC - do this for all r200s/r300s/r400s for safety sake
109 */
110 if (rec->hw_capable) {
111 if ((rdev->family >= CHIP_R200) && !ASIC_IS_AVIVO(rdev)) {
112 u32 reg;
113
114 if (rdev->family >= CHIP_RV350)
115 reg = RADEON_GPIO_MONID;
116 else if ((rdev->family == CHIP_R300) ||
117 (rdev->family == CHIP_R350))
118 reg = RADEON_GPIO_DVI_DDC;
119 else
120 reg = RADEON_GPIO_CRT2_DDC;
121
122 mutex_lock(&rdev->dc_hw_i2c_mutex);
123 if (rec->a_clk_reg == reg) {
124 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST |
125 R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1)));
126 } else {
127 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST |
128 R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3)));
129 }
130 mutex_unlock(&rdev->dc_hw_i2c_mutex);
131 }
132 }
133
134 /* switch the pads to ddc mode */
135 if (ASIC_IS_DCE3(rdev) && rec->hw_capable) {
136 temp = RREG32(rec->mask_clk_reg);
137 temp &= ~(1 << 16);
138 WREG32(rec->mask_clk_reg, temp);
139 }
140
141 /* clear the output pin values */
142 temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask;
143 WREG32(rec->a_clk_reg, temp);
144
145 temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask;
146 WREG32(rec->a_data_reg, temp);
147
148 /* set the pins to input */
149 temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
150 WREG32(rec->en_clk_reg, temp);
151
152 temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
153 WREG32(rec->en_data_reg, temp);
154
155 /* mask the gpio pins for software use */
156 temp = RREG32(rec->mask_clk_reg) | rec->mask_clk_mask;
157 WREG32(rec->mask_clk_reg, temp);
158 temp = RREG32(rec->mask_clk_reg);
159
160 temp = RREG32(rec->mask_data_reg) | rec->mask_data_mask;
161 WREG32(rec->mask_data_reg, temp);
162 temp = RREG32(rec->mask_data_reg);
163
164 return 0;
165 }
166
167 static void post_xfer(struct i2c_adapter *i2c_adap)
168 {
169 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
170 struct radeon_device *rdev = i2c->dev->dev_private;
171 struct radeon_i2c_bus_rec *rec = &i2c->rec;
172 uint32_t temp;
173
174 /* unmask the gpio pins for software use */
175 temp = RREG32(rec->mask_clk_reg) & ~rec->mask_clk_mask;
176 WREG32(rec->mask_clk_reg, temp);
177 temp = RREG32(rec->mask_clk_reg);
178
179 temp = RREG32(rec->mask_data_reg) & ~rec->mask_data_mask;
180 WREG32(rec->mask_data_reg, temp);
181 temp = RREG32(rec->mask_data_reg);
182
183 mutex_unlock(&i2c->mutex);
184 }
185
186 static int get_clock(void *i2c_priv)
187 {
188 struct radeon_i2c_chan *i2c = i2c_priv;
189 struct radeon_device *rdev = i2c->dev->dev_private;
190 struct radeon_i2c_bus_rec *rec = &i2c->rec;
191 uint32_t val;
192
193 /* read the value off the pin */
194 val = RREG32(rec->y_clk_reg);
195 val &= rec->y_clk_mask;
196
197 return (val != 0);
198 }
199
200
201 static int get_data(void *i2c_priv)
202 {
203 struct radeon_i2c_chan *i2c = i2c_priv;
204 struct radeon_device *rdev = i2c->dev->dev_private;
205 struct radeon_i2c_bus_rec *rec = &i2c->rec;
206 uint32_t val;
207
208 /* read the value off the pin */
209 val = RREG32(rec->y_data_reg);
210 val &= rec->y_data_mask;
211
212 return (val != 0);
213 }
214
215 static void set_clock(void *i2c_priv, int clock)
216 {
217 struct radeon_i2c_chan *i2c = i2c_priv;
218 struct radeon_device *rdev = i2c->dev->dev_private;
219 struct radeon_i2c_bus_rec *rec = &i2c->rec;
220 uint32_t val;
221
222 /* set pin direction */
223 val = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
224 val |= clock ? 0 : rec->en_clk_mask;
225 WREG32(rec->en_clk_reg, val);
226 }
227
228 static void set_data(void *i2c_priv, int data)
229 {
230 struct radeon_i2c_chan *i2c = i2c_priv;
231 struct radeon_device *rdev = i2c->dev->dev_private;
232 struct radeon_i2c_bus_rec *rec = &i2c->rec;
233 uint32_t val;
234
235 /* set pin direction */
236 val = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
237 val |= data ? 0 : rec->en_data_mask;
238 WREG32(rec->en_data_reg, val);
239 }
240
241 /* hw i2c */
242
243 static u32 radeon_get_i2c_prescale(struct radeon_device *rdev)
244 {
245 u32 sclk = rdev->pm.current_sclk;
246 u32 prescale = 0;
247 u32 nm;
248 u8 n, m, loop;
249 int i2c_clock;
250
251 switch (rdev->family) {
252 case CHIP_R100:
253 case CHIP_RV100:
254 case CHIP_RS100:
255 case CHIP_RV200:
256 case CHIP_RS200:
257 case CHIP_R200:
258 case CHIP_RV250:
259 case CHIP_RS300:
260 case CHIP_RV280:
261 case CHIP_R300:
262 case CHIP_R350:
263 case CHIP_RV350:
264 i2c_clock = 60;
265 nm = (sclk * 10) / (i2c_clock * 4);
266 for (loop = 1; loop < 255; loop++) {
267 if ((nm / loop) < loop)
268 break;
269 }
270 n = loop - 1;
271 m = loop - 2;
272 prescale = m | (n << 8);
273 break;
274 case CHIP_RV380:
275 case CHIP_RS400:
276 case CHIP_RS480:
277 case CHIP_R420:
278 case CHIP_R423:
279 case CHIP_RV410:
280 prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128;
281 break;
282 case CHIP_RS600:
283 case CHIP_RS690:
284 case CHIP_RS740:
285 /* todo */
286 break;
287 case CHIP_RV515:
288 case CHIP_R520:
289 case CHIP_RV530:
290 case CHIP_RV560:
291 case CHIP_RV570:
292 case CHIP_R580:
293 i2c_clock = 50;
294 if (rdev->family == CHIP_R520)
295 prescale = (127 << 8) + ((sclk * 10) / (4 * 127 * i2c_clock));
296 else
297 prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128;
298 break;
299 case CHIP_R600:
300 case CHIP_RV610:
301 case CHIP_RV630:
302 case CHIP_RV670:
303 /* todo */
304 break;
305 case CHIP_RV620:
306 case CHIP_RV635:
307 case CHIP_RS780:
308 case CHIP_RS880:
309 case CHIP_RV770:
310 case CHIP_RV730:
311 case CHIP_RV710:
312 case CHIP_RV740:
313 /* todo */
314 break;
315 case CHIP_CEDAR:
316 case CHIP_REDWOOD:
317 case CHIP_JUNIPER:
318 case CHIP_CYPRESS:
319 case CHIP_HEMLOCK:
320 /* todo */
321 break;
322 default:
323 DRM_ERROR("i2c: unhandled radeon chip\n");
324 break;
325 }
326 return prescale;
327 }
328
329
330 /* hw i2c engine for r1xx-4xx hardware
331 * hw can buffer up to 15 bytes
332 */
333 static int r100_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
334 struct i2c_msg *msgs, int num)
335 {
336 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
337 struct radeon_device *rdev = i2c->dev->dev_private;
338 struct radeon_i2c_bus_rec *rec = &i2c->rec;
339 struct i2c_msg *p;
340 int i, j, k, ret = num;
341 u32 prescale;
342 u32 i2c_cntl_0, i2c_cntl_1, i2c_data;
343 u32 tmp, reg;
344
345 mutex_lock(&rdev->dc_hw_i2c_mutex);
346 /* take the pm lock since we need a constant sclk */
347 mutex_lock(&rdev->pm.mutex);
348
349 prescale = radeon_get_i2c_prescale(rdev);
350
351 reg = ((prescale << RADEON_I2C_PRESCALE_SHIFT) |
352 RADEON_I2C_DRIVE_EN |
353 RADEON_I2C_START |
354 RADEON_I2C_STOP |
355 RADEON_I2C_GO);
356
357 if (rdev->is_atom_bios) {
358 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
359 WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE);
360 }
361
362 if (rec->mm_i2c) {
363 i2c_cntl_0 = RADEON_I2C_CNTL_0;
364 i2c_cntl_1 = RADEON_I2C_CNTL_1;
365 i2c_data = RADEON_I2C_DATA;
366 } else {
367 i2c_cntl_0 = RADEON_DVI_I2C_CNTL_0;
368 i2c_cntl_1 = RADEON_DVI_I2C_CNTL_1;
369 i2c_data = RADEON_DVI_I2C_DATA;
370
371 switch (rdev->family) {
372 case CHIP_R100:
373 case CHIP_RV100:
374 case CHIP_RS100:
375 case CHIP_RV200:
376 case CHIP_RS200:
377 case CHIP_RS300:
378 switch (rec->mask_clk_reg) {
379 case RADEON_GPIO_DVI_DDC:
380 /* no gpio select bit */
381 break;
382 default:
383 DRM_ERROR("gpio not supported with hw i2c\n");
384 ret = -EINVAL;
385 goto done;
386 }
387 break;
388 case CHIP_R200:
389 /* only bit 4 on r200 */
390 switch (rec->mask_clk_reg) {
391 case RADEON_GPIO_DVI_DDC:
392 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
393 break;
394 case RADEON_GPIO_MONID:
395 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
396 break;
397 default:
398 DRM_ERROR("gpio not supported with hw i2c\n");
399 ret = -EINVAL;
400 goto done;
401 }
402 break;
403 case CHIP_RV250:
404 case CHIP_RV280:
405 /* bits 3 and 4 */
406 switch (rec->mask_clk_reg) {
407 case RADEON_GPIO_DVI_DDC:
408 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
409 break;
410 case RADEON_GPIO_VGA_DDC:
411 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2);
412 break;
413 case RADEON_GPIO_CRT2_DDC:
414 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
415 break;
416 default:
417 DRM_ERROR("gpio not supported with hw i2c\n");
418 ret = -EINVAL;
419 goto done;
420 }
421 break;
422 case CHIP_R300:
423 case CHIP_R350:
424 /* only bit 4 on r300/r350 */
425 switch (rec->mask_clk_reg) {
426 case RADEON_GPIO_VGA_DDC:
427 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
428 break;
429 case RADEON_GPIO_DVI_DDC:
430 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
431 break;
432 default:
433 DRM_ERROR("gpio not supported with hw i2c\n");
434 ret = -EINVAL;
435 goto done;
436 }
437 break;
438 case CHIP_RV350:
439 case CHIP_RV380:
440 case CHIP_R420:
441 case CHIP_R423:
442 case CHIP_RV410:
443 case CHIP_RS400:
444 case CHIP_RS480:
445 /* bits 3 and 4 */
446 switch (rec->mask_clk_reg) {
447 case RADEON_GPIO_VGA_DDC:
448 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
449 break;
450 case RADEON_GPIO_DVI_DDC:
451 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2);
452 break;
453 case RADEON_GPIO_MONID:
454 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
455 break;
456 default:
457 DRM_ERROR("gpio not supported with hw i2c\n");
458 ret = -EINVAL;
459 goto done;
460 }
461 break;
462 default:
463 DRM_ERROR("unsupported asic\n");
464 ret = -EINVAL;
465 goto done;
466 break;
467 }
468 }
469
470 /* check for bus probe */
471 p = &msgs[0];
472 if ((num == 1) && (p->len == 0)) {
473 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
474 RADEON_I2C_NACK |
475 RADEON_I2C_HALT |
476 RADEON_I2C_SOFT_RST));
477 WREG32(i2c_data, (p->addr << 1) & 0xff);
478 WREG32(i2c_data, 0);
479 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
480 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) |
481 RADEON_I2C_EN |
482 (48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
483 WREG32(i2c_cntl_0, reg);
484 for (k = 0; k < 32; k++) {
485 udelay(10);
486 tmp = RREG32(i2c_cntl_0);
487 if (tmp & RADEON_I2C_GO)
488 continue;
489 tmp = RREG32(i2c_cntl_0);
490 if (tmp & RADEON_I2C_DONE)
491 break;
492 else {
493 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
494 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
495 ret = -EIO;
496 goto done;
497 }
498 }
499 goto done;
500 }
501
502 for (i = 0; i < num; i++) {
503 p = &msgs[i];
504 for (j = 0; j < p->len; j++) {
505 if (p->flags & I2C_M_RD) {
506 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
507 RADEON_I2C_NACK |
508 RADEON_I2C_HALT |
509 RADEON_I2C_SOFT_RST));
510 WREG32(i2c_data, ((p->addr << 1) & 0xff) | 0x1);
511 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
512 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) |
513 RADEON_I2C_EN |
514 (48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
515 WREG32(i2c_cntl_0, reg | RADEON_I2C_RECEIVE);
516 for (k = 0; k < 32; k++) {
517 udelay(10);
518 tmp = RREG32(i2c_cntl_0);
519 if (tmp & RADEON_I2C_GO)
520 continue;
521 tmp = RREG32(i2c_cntl_0);
522 if (tmp & RADEON_I2C_DONE)
523 break;
524 else {
525 DRM_DEBUG("i2c read error 0x%08x\n", tmp);
526 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
527 ret = -EIO;
528 goto done;
529 }
530 }
531 p->buf[j] = RREG32(i2c_data) & 0xff;
532 } else {
533 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
534 RADEON_I2C_NACK |
535 RADEON_I2C_HALT |
536 RADEON_I2C_SOFT_RST));
537 WREG32(i2c_data, (p->addr << 1) & 0xff);
538 WREG32(i2c_data, p->buf[j]);
539 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
540 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) |
541 RADEON_I2C_EN |
542 (48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
543 WREG32(i2c_cntl_0, reg);
544 for (k = 0; k < 32; k++) {
545 udelay(10);
546 tmp = RREG32(i2c_cntl_0);
547 if (tmp & RADEON_I2C_GO)
548 continue;
549 tmp = RREG32(i2c_cntl_0);
550 if (tmp & RADEON_I2C_DONE)
551 break;
552 else {
553 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
554 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
555 ret = -EIO;
556 goto done;
557 }
558 }
559 }
560 }
561 }
562
563 done:
564 WREG32(i2c_cntl_0, 0);
565 WREG32(i2c_cntl_1, 0);
566 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
567 RADEON_I2C_NACK |
568 RADEON_I2C_HALT |
569 RADEON_I2C_SOFT_RST));
570
571 if (rdev->is_atom_bios) {
572 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
573 tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE;
574 WREG32(RADEON_BIOS_6_SCRATCH, tmp);
575 }
576
577 mutex_unlock(&rdev->pm.mutex);
578 mutex_unlock(&rdev->dc_hw_i2c_mutex);
579
580 return ret;
581 }
582
583 /* hw i2c engine for r5xx hardware
584 * hw can buffer up to 15 bytes
585 */
586 static int r500_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
587 struct i2c_msg *msgs, int num)
588 {
589 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
590 struct radeon_device *rdev = i2c->dev->dev_private;
591 struct radeon_i2c_bus_rec *rec = &i2c->rec;
592 struct i2c_msg *p;
593 int i, j, remaining, current_count, buffer_offset, ret = num;
594 u32 prescale;
595 u32 tmp, reg;
596 u32 saved1, saved2;
597
598 mutex_lock(&rdev->dc_hw_i2c_mutex);
599 /* take the pm lock since we need a constant sclk */
600 mutex_lock(&rdev->pm.mutex);
601
602 prescale = radeon_get_i2c_prescale(rdev);
603
604 /* clear gpio mask bits */
605 tmp = RREG32(rec->mask_clk_reg);
606 tmp &= ~rec->mask_clk_mask;
607 WREG32(rec->mask_clk_reg, tmp);
608 tmp = RREG32(rec->mask_clk_reg);
609
610 tmp = RREG32(rec->mask_data_reg);
611 tmp &= ~rec->mask_data_mask;
612 WREG32(rec->mask_data_reg, tmp);
613 tmp = RREG32(rec->mask_data_reg);
614
615 /* clear pin values */
616 tmp = RREG32(rec->a_clk_reg);
617 tmp &= ~rec->a_clk_mask;
618 WREG32(rec->a_clk_reg, tmp);
619 tmp = RREG32(rec->a_clk_reg);
620
621 tmp = RREG32(rec->a_data_reg);
622 tmp &= ~rec->a_data_mask;
623 WREG32(rec->a_data_reg, tmp);
624 tmp = RREG32(rec->a_data_reg);
625
626 /* set the pins to input */
627 tmp = RREG32(rec->en_clk_reg);
628 tmp &= ~rec->en_clk_mask;
629 WREG32(rec->en_clk_reg, tmp);
630 tmp = RREG32(rec->en_clk_reg);
631
632 tmp = RREG32(rec->en_data_reg);
633 tmp &= ~rec->en_data_mask;
634 WREG32(rec->en_data_reg, tmp);
635 tmp = RREG32(rec->en_data_reg);
636
637 /* */
638 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
639 WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE);
640 saved1 = RREG32(AVIVO_DC_I2C_CONTROL1);
641 saved2 = RREG32(0x494);
642 WREG32(0x494, saved2 | 0x1);
643
644 WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_WANTS_TO_USE_I2C);
645 for (i = 0; i < 50; i++) {
646 udelay(1);
647 if (RREG32(AVIVO_DC_I2C_ARBITRATION) & AVIVO_DC_I2C_SW_CAN_USE_I2C)
648 break;
649 }
650 if (i == 50) {
651 DRM_ERROR("failed to get i2c bus\n");
652 ret = -EBUSY;
653 goto done;
654 }
655
656 reg = AVIVO_DC_I2C_START | AVIVO_DC_I2C_STOP | AVIVO_DC_I2C_EN;
657 switch (rec->mask_clk_reg) {
658 case AVIVO_DC_GPIO_DDC1_MASK:
659 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC1);
660 break;
661 case AVIVO_DC_GPIO_DDC2_MASK:
662 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC2);
663 break;
664 case AVIVO_DC_GPIO_DDC3_MASK:
665 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC3);
666 break;
667 default:
668 DRM_ERROR("gpio not supported with hw i2c\n");
669 ret = -EINVAL;
670 goto done;
671 }
672
673 /* check for bus probe */
674 p = &msgs[0];
675 if ((num == 1) && (p->len == 0)) {
676 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
677 AVIVO_DC_I2C_NACK |
678 AVIVO_DC_I2C_HALT));
679 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
680 udelay(1);
681 WREG32(AVIVO_DC_I2C_RESET, 0);
682
683 WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff);
684 WREG32(AVIVO_DC_I2C_DATA, 0);
685
686 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
687 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
688 AVIVO_DC_I2C_DATA_COUNT(1) |
689 (prescale << 16)));
690 WREG32(AVIVO_DC_I2C_CONTROL1, reg);
691 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
692 for (j = 0; j < 200; j++) {
693 udelay(50);
694 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
695 if (tmp & AVIVO_DC_I2C_GO)
696 continue;
697 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
698 if (tmp & AVIVO_DC_I2C_DONE)
699 break;
700 else {
701 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
702 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
703 ret = -EIO;
704 goto done;
705 }
706 }
707 goto done;
708 }
709
710 for (i = 0; i < num; i++) {
711 p = &msgs[i];
712 remaining = p->len;
713 buffer_offset = 0;
714 if (p->flags & I2C_M_RD) {
715 while (remaining) {
716 if (remaining > 15)
717 current_count = 15;
718 else
719 current_count = remaining;
720 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
721 AVIVO_DC_I2C_NACK |
722 AVIVO_DC_I2C_HALT));
723 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
724 udelay(1);
725 WREG32(AVIVO_DC_I2C_RESET, 0);
726
727 WREG32(AVIVO_DC_I2C_DATA, ((p->addr << 1) & 0xff) | 0x1);
728 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
729 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
730 AVIVO_DC_I2C_DATA_COUNT(current_count) |
731 (prescale << 16)));
732 WREG32(AVIVO_DC_I2C_CONTROL1, reg | AVIVO_DC_I2C_RECEIVE);
733 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
734 for (j = 0; j < 200; j++) {
735 udelay(50);
736 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
737 if (tmp & AVIVO_DC_I2C_GO)
738 continue;
739 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
740 if (tmp & AVIVO_DC_I2C_DONE)
741 break;
742 else {
743 DRM_DEBUG("i2c read error 0x%08x\n", tmp);
744 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
745 ret = -EIO;
746 goto done;
747 }
748 }
749 for (j = 0; j < current_count; j++)
750 p->buf[buffer_offset + j] = RREG32(AVIVO_DC_I2C_DATA) & 0xff;
751 remaining -= current_count;
752 buffer_offset += current_count;
753 }
754 } else {
755 while (remaining) {
756 if (remaining > 15)
757 current_count = 15;
758 else
759 current_count = remaining;
760 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
761 AVIVO_DC_I2C_NACK |
762 AVIVO_DC_I2C_HALT));
763 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
764 udelay(1);
765 WREG32(AVIVO_DC_I2C_RESET, 0);
766
767 WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff);
768 for (j = 0; j < current_count; j++)
769 WREG32(AVIVO_DC_I2C_DATA, p->buf[buffer_offset + j]);
770
771 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
772 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
773 AVIVO_DC_I2C_DATA_COUNT(current_count) |
774 (prescale << 16)));
775 WREG32(AVIVO_DC_I2C_CONTROL1, reg);
776 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
777 for (j = 0; j < 200; j++) {
778 udelay(50);
779 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
780 if (tmp & AVIVO_DC_I2C_GO)
781 continue;
782 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
783 if (tmp & AVIVO_DC_I2C_DONE)
784 break;
785 else {
786 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
787 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
788 ret = -EIO;
789 goto done;
790 }
791 }
792 remaining -= current_count;
793 buffer_offset += current_count;
794 }
795 }
796 }
797
798 done:
799 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
800 AVIVO_DC_I2C_NACK |
801 AVIVO_DC_I2C_HALT));
802 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
803 udelay(1);
804 WREG32(AVIVO_DC_I2C_RESET, 0);
805
806 WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_DONE_USING_I2C);
807 WREG32(AVIVO_DC_I2C_CONTROL1, saved1);
808 WREG32(0x494, saved2);
809 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
810 tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE;
811 WREG32(RADEON_BIOS_6_SCRATCH, tmp);
812
813 mutex_unlock(&rdev->pm.mutex);
814 mutex_unlock(&rdev->dc_hw_i2c_mutex);
815
816 return ret;
817 }
818
819 static int radeon_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
820 struct i2c_msg *msgs, int num)
821 {
822 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
823 struct radeon_device *rdev = i2c->dev->dev_private;
824 struct radeon_i2c_bus_rec *rec = &i2c->rec;
825 int ret = 0;
826
827 mutex_lock(&i2c->mutex);
828
829 switch (rdev->family) {
830 case CHIP_R100:
831 case CHIP_RV100:
832 case CHIP_RS100:
833 case CHIP_RV200:
834 case CHIP_RS200:
835 case CHIP_R200:
836 case CHIP_RV250:
837 case CHIP_RS300:
838 case CHIP_RV280:
839 case CHIP_R300:
840 case CHIP_R350:
841 case CHIP_RV350:
842 case CHIP_RV380:
843 case CHIP_R420:
844 case CHIP_R423:
845 case CHIP_RV410:
846 case CHIP_RS400:
847 case CHIP_RS480:
848 ret = r100_hw_i2c_xfer(i2c_adap, msgs, num);
849 break;
850 case CHIP_RS600:
851 case CHIP_RS690:
852 case CHIP_RS740:
853 /* XXX fill in hw i2c implementation */
854 break;
855 case CHIP_RV515:
856 case CHIP_R520:
857 case CHIP_RV530:
858 case CHIP_RV560:
859 case CHIP_RV570:
860 case CHIP_R580:
861 if (rec->mm_i2c)
862 ret = r100_hw_i2c_xfer(i2c_adap, msgs, num);
863 else
864 ret = r500_hw_i2c_xfer(i2c_adap, msgs, num);
865 break;
866 case CHIP_R600:
867 case CHIP_RV610:
868 case CHIP_RV630:
869 case CHIP_RV670:
870 /* XXX fill in hw i2c implementation */
871 break;
872 case CHIP_RV620:
873 case CHIP_RV635:
874 case CHIP_RS780:
875 case CHIP_RS880:
876 case CHIP_RV770:
877 case CHIP_RV730:
878 case CHIP_RV710:
879 case CHIP_RV740:
880 /* XXX fill in hw i2c implementation */
881 break;
882 case CHIP_CEDAR:
883 case CHIP_REDWOOD:
884 case CHIP_JUNIPER:
885 case CHIP_CYPRESS:
886 case CHIP_HEMLOCK:
887 /* XXX fill in hw i2c implementation */
888 break;
889 default:
890 DRM_ERROR("i2c: unhandled radeon chip\n");
891 ret = -EIO;
892 break;
893 }
894
895 mutex_unlock(&i2c->mutex);
896
897 return ret;
898 }
899
900 static u32 radeon_hw_i2c_func(struct i2c_adapter *adap)
901 {
902 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
903 }
904
905 static const struct i2c_algorithm radeon_i2c_algo = {
906 .master_xfer = radeon_hw_i2c_xfer,
907 .functionality = radeon_hw_i2c_func,
908 };
909
910 static const struct i2c_algorithm radeon_atom_i2c_algo = {
911 .master_xfer = radeon_atom_hw_i2c_xfer,
912 .functionality = radeon_atom_hw_i2c_func,
913 };
914
915 struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
916 struct radeon_i2c_bus_rec *rec,
917 const char *name)
918 {
919 struct radeon_device *rdev = dev->dev_private;
920 struct radeon_i2c_chan *i2c;
921 int ret;
922
923 /* don't add the mm_i2c bus unless hw_i2c is enabled */
924 if (rec->mm_i2c && (radeon_hw_i2c == 0))
925 return NULL;
926
927 i2c = kzalloc(sizeof(struct radeon_i2c_chan), GFP_KERNEL);
928 if (i2c == NULL)
929 return NULL;
930
931 i2c->rec = *rec;
932 i2c->adapter.owner = THIS_MODULE;
933 i2c->adapter.class = I2C_CLASS_DDC;
934 i2c->adapter.dev.parent = dev->dev;
935 i2c->dev = dev;
936 i2c_set_adapdata(&i2c->adapter, i2c);
937 mutex_init(&i2c->mutex);
938 if (rec->mm_i2c ||
939 (rec->hw_capable &&
940 radeon_hw_i2c &&
941 ((rdev->family <= CHIP_RS480) ||
942 ((rdev->family >= CHIP_RV515) && (rdev->family <= CHIP_R580))))) {
943 /* set the radeon hw i2c adapter */
944 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
945 "Radeon i2c hw bus %s", name);
946 i2c->adapter.algo = &radeon_i2c_algo;
947 ret = i2c_add_adapter(&i2c->adapter);
948 if (ret) {
949 DRM_ERROR("Failed to register hw i2c %s\n", name);
950 goto out_free;
951 }
952 } else if (rec->hw_capable &&
953 radeon_hw_i2c &&
954 ASIC_IS_DCE3(rdev)) {
955 /* hw i2c using atom */
956 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
957 "Radeon i2c hw bus %s", name);
958 i2c->adapter.algo = &radeon_atom_i2c_algo;
959 ret = i2c_add_adapter(&i2c->adapter);
960 if (ret) {
961 DRM_ERROR("Failed to register hw i2c %s\n", name);
962 goto out_free;
963 }
964 } else {
965 /* set the radeon bit adapter */
966 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
967 "Radeon i2c bit bus %s", name);
968 i2c->adapter.algo_data = &i2c->bit;
969 i2c->bit.pre_xfer = pre_xfer;
970 i2c->bit.post_xfer = post_xfer;
971 i2c->bit.setsda = set_data;
972 i2c->bit.setscl = set_clock;
973 i2c->bit.getsda = get_data;
974 i2c->bit.getscl = get_clock;
975 i2c->bit.udelay = 10;
976 i2c->bit.timeout = usecs_to_jiffies(2200); /* from VESA */
977 i2c->bit.data = i2c;
978 ret = i2c_bit_add_bus(&i2c->adapter);
979 if (ret) {
980 DRM_ERROR("Failed to register bit i2c %s\n", name);
981 goto out_free;
982 }
983 }
984
985 return i2c;
986 out_free:
987 mutex_destroy(&i2c->mutex);
988 kfree(i2c);
989 return NULL;
990
991 }
992
993 void radeon_i2c_destroy(struct radeon_i2c_chan *i2c)
994 {
995 if (!i2c)
996 return;
997 i2c_del_adapter(&i2c->adapter);
998 if (i2c->has_aux)
999 drm_dp_aux_unregister(&i2c->aux);
1000 mutex_destroy(&i2c->mutex);
1001 kfree(i2c);
1002 }
1003
1004 /* Add the default buses */
1005 void radeon_i2c_init(struct radeon_device *rdev)
1006 {
1007 if (radeon_hw_i2c)
1008 DRM_INFO("hw_i2c forced on, you may experience display detection problems!\n");
1009
1010 if (rdev->is_atom_bios)
1011 radeon_atombios_i2c_init(rdev);
1012 else
1013 radeon_combios_i2c_init(rdev);
1014 }
1015
1016 /* remove all the buses */
1017 void radeon_i2c_fini(struct radeon_device *rdev)
1018 {
1019 int i;
1020
1021 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) {
1022 if (rdev->i2c_bus[i]) {
1023 radeon_i2c_destroy(rdev->i2c_bus[i]);
1024 rdev->i2c_bus[i] = NULL;
1025 }
1026 }
1027 }
1028
1029 /* Add additional buses */
1030 void radeon_i2c_add(struct radeon_device *rdev,
1031 struct radeon_i2c_bus_rec *rec,
1032 const char *name)
1033 {
1034 struct drm_device *dev = rdev->ddev;
1035 int i;
1036
1037 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) {
1038 if (!rdev->i2c_bus[i]) {
1039 rdev->i2c_bus[i] = radeon_i2c_create(dev, rec, name);
1040 return;
1041 }
1042 }
1043 }
1044
1045 /* looks up bus based on id */
1046 struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev,
1047 struct radeon_i2c_bus_rec *i2c_bus)
1048 {
1049 int i;
1050
1051 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) {
1052 if (rdev->i2c_bus[i] &&
1053 (rdev->i2c_bus[i]->rec.i2c_id == i2c_bus->i2c_id)) {
1054 return rdev->i2c_bus[i];
1055 }
1056 }
1057 return NULL;
1058 }
1059
1060 void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus,
1061 u8 slave_addr,
1062 u8 addr,
1063 u8 *val)
1064 {
1065 u8 out_buf[2];
1066 u8 in_buf[2];
1067 struct i2c_msg msgs[] = {
1068 {
1069 .addr = slave_addr,
1070 .flags = 0,
1071 .len = 1,
1072 .buf = out_buf,
1073 },
1074 {
1075 .addr = slave_addr,
1076 .flags = I2C_M_RD,
1077 .len = 1,
1078 .buf = in_buf,
1079 }
1080 };
1081
1082 out_buf[0] = addr;
1083 out_buf[1] = 0;
1084
1085 if (i2c_transfer(&i2c_bus->adapter, msgs, 2) == 2) {
1086 *val = in_buf[0];
1087 DRM_DEBUG("val = 0x%02x\n", *val);
1088 } else {
1089 DRM_DEBUG("i2c 0x%02x 0x%02x read failed\n",
1090 addr, *val);
1091 }
1092 }
1093
1094 void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c_bus,
1095 u8 slave_addr,
1096 u8 addr,
1097 u8 val)
1098 {
1099 uint8_t out_buf[2];
1100 struct i2c_msg msg = {
1101 .addr = slave_addr,
1102 .flags = 0,
1103 .len = 2,
1104 .buf = out_buf,
1105 };
1106
1107 out_buf[0] = addr;
1108 out_buf[1] = val;
1109
1110 if (i2c_transfer(&i2c_bus->adapter, &msg, 1) != 1)
1111 DRM_DEBUG("i2c 0x%02x 0x%02x write failed\n",
1112 addr, val);
1113 }
1114
1115 /* ddc router switching */
1116 void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector)
1117 {
1118 u8 val;
1119
1120 if (!radeon_connector->router.ddc_valid)
1121 return;
1122
1123 if (!radeon_connector->router_bus)
1124 return;
1125
1126 radeon_i2c_get_byte(radeon_connector->router_bus,
1127 radeon_connector->router.i2c_addr,
1128 0x3, &val);
1129 val &= ~radeon_connector->router.ddc_mux_control_pin;
1130 radeon_i2c_put_byte(radeon_connector->router_bus,
1131 radeon_connector->router.i2c_addr,
1132 0x3, val);
1133 radeon_i2c_get_byte(radeon_connector->router_bus,
1134 radeon_connector->router.i2c_addr,
1135 0x1, &val);
1136 val &= ~radeon_connector->router.ddc_mux_control_pin;
1137 val |= radeon_connector->router.ddc_mux_state;
1138 radeon_i2c_put_byte(radeon_connector->router_bus,
1139 radeon_connector->router.i2c_addr,
1140 0x1, val);
1141 }
1142
1143 /* clock/data router switching */
1144 void radeon_router_select_cd_port(struct radeon_connector *radeon_connector)
1145 {
1146 u8 val;
1147
1148 if (!radeon_connector->router.cd_valid)
1149 return;
1150
1151 if (!radeon_connector->router_bus)
1152 return;
1153
1154 radeon_i2c_get_byte(radeon_connector->router_bus,
1155 radeon_connector->router.i2c_addr,
1156 0x3, &val);
1157 val &= ~radeon_connector->router.cd_mux_control_pin;
1158 radeon_i2c_put_byte(radeon_connector->router_bus,
1159 radeon_connector->router.i2c_addr,
1160 0x3, val);
1161 radeon_i2c_get_byte(radeon_connector->router_bus,
1162 radeon_connector->router.i2c_addr,
1163 0x1, &val);
1164 val &= ~radeon_connector->router.cd_mux_control_pin;
1165 val |= radeon_connector->router.cd_mux_state;
1166 radeon_i2c_put_byte(radeon_connector->router_bus,
1167 radeon_connector->router.i2c_addr,
1168 0x1, val);
1169 }
1170
1171