radeon_kms.c revision 1.1.1.2
1 /* $NetBSD: radeon_kms.c,v 1.1.1.2 2018/08/27 01:34:58 riastradh Exp $ */ 2 3 /* 4 * Copyright 2008 Advanced Micro Devices, Inc. 5 * Copyright 2008 Red Hat Inc. 6 * Copyright 2009 Jerome Glisse. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: Dave Airlie 27 * Alex Deucher 28 * Jerome Glisse 29 */ 30 #include <sys/cdefs.h> 31 __KERNEL_RCSID(0, "$NetBSD: radeon_kms.c,v 1.1.1.2 2018/08/27 01:34:58 riastradh Exp $"); 32 33 #include <drm/drmP.h> 34 #include "radeon.h" 35 #include <drm/radeon_drm.h> 36 #include "radeon_asic.h" 37 38 #include <linux/vga_switcheroo.h> 39 #include <linux/slab.h> 40 #include <linux/pm_runtime.h> 41 42 #include "radeon_kfd.h" 43 44 #if defined(CONFIG_VGA_SWITCHEROO) 45 bool radeon_has_atpx(void); 46 #else 47 static inline bool radeon_has_atpx(void) { return false; } 48 #endif 49 50 /** 51 * radeon_driver_unload_kms - Main unload function for KMS. 52 * 53 * @dev: drm dev pointer 54 * 55 * This is the main unload function for KMS (all asics). 56 * It calls radeon_modeset_fini() to tear down the 57 * displays, and radeon_device_fini() to tear down 58 * the rest of the device (CP, writeback, etc.). 59 * Returns 0 on success. 60 */ 61 int radeon_driver_unload_kms(struct drm_device *dev) 62 { 63 struct radeon_device *rdev = dev->dev_private; 64 65 if (rdev == NULL) 66 return 0; 67 68 if (rdev->rmmio == NULL) 69 goto done_free; 70 71 pm_runtime_get_sync(dev->dev); 72 73 radeon_kfd_device_fini(rdev); 74 75 radeon_acpi_fini(rdev); 76 77 radeon_modeset_fini(rdev); 78 radeon_device_fini(rdev); 79 80 done_free: 81 kfree(rdev); 82 dev->dev_private = NULL; 83 return 0; 84 } 85 86 /** 87 * radeon_driver_load_kms - Main load function for KMS. 88 * 89 * @dev: drm dev pointer 90 * @flags: device flags 91 * 92 * This is the main load function for KMS (all asics). 93 * It calls radeon_device_init() to set up the non-display 94 * parts of the chip (asic init, CP, writeback, etc.), and 95 * radeon_modeset_init() to set up the display parts 96 * (crtcs, encoders, hotplug detect, etc.). 97 * Returns 0 on success, error on failure. 98 */ 99 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags) 100 { 101 struct radeon_device *rdev; 102 int r, acpi_status; 103 104 rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL); 105 if (rdev == NULL) { 106 return -ENOMEM; 107 } 108 dev->dev_private = (void *)rdev; 109 110 /* update BUS flag */ 111 if (drm_pci_device_is_agp(dev)) { 112 flags |= RADEON_IS_AGP; 113 } else if (pci_is_pcie(dev->pdev)) { 114 flags |= RADEON_IS_PCIE; 115 } else { 116 flags |= RADEON_IS_PCI; 117 } 118 119 if ((radeon_runtime_pm != 0) && 120 radeon_has_atpx() && 121 ((flags & RADEON_IS_IGP) == 0)) 122 flags |= RADEON_IS_PX; 123 124 /* radeon_device_init should report only fatal error 125 * like memory allocation failure or iomapping failure, 126 * or memory manager initialization failure, it must 127 * properly initialize the GPU MC controller and permit 128 * VRAM allocation 129 */ 130 r = radeon_device_init(rdev, dev, dev->pdev, flags); 131 if (r) { 132 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n"); 133 goto out; 134 } 135 136 /* Again modeset_init should fail only on fatal error 137 * otherwise it should provide enough functionalities 138 * for shadowfb to run 139 */ 140 r = radeon_modeset_init(rdev); 141 if (r) 142 dev_err(&dev->pdev->dev, "Fatal error during modeset init\n"); 143 144 /* Call ACPI methods: require modeset init 145 * but failure is not fatal 146 */ 147 if (!r) { 148 acpi_status = radeon_acpi_init(rdev); 149 if (acpi_status) 150 dev_dbg(&dev->pdev->dev, 151 "Error during ACPI methods call\n"); 152 } 153 154 radeon_kfd_device_probe(rdev); 155 radeon_kfd_device_init(rdev); 156 157 if (radeon_is_px(dev)) { 158 pm_runtime_use_autosuspend(dev->dev); 159 pm_runtime_set_autosuspend_delay(dev->dev, 5000); 160 pm_runtime_set_active(dev->dev); 161 pm_runtime_allow(dev->dev); 162 pm_runtime_mark_last_busy(dev->dev); 163 pm_runtime_put_autosuspend(dev->dev); 164 } 165 166 out: 167 if (r) 168 radeon_driver_unload_kms(dev); 169 170 171 return r; 172 } 173 174 /** 175 * radeon_set_filp_rights - Set filp right. 176 * 177 * @dev: drm dev pointer 178 * @owner: drm file 179 * @applier: drm file 180 * @value: value 181 * 182 * Sets the filp rights for the device (all asics). 183 */ 184 static void radeon_set_filp_rights(struct drm_device *dev, 185 struct drm_file **owner, 186 struct drm_file *applier, 187 uint32_t *value) 188 { 189 struct radeon_device *rdev = dev->dev_private; 190 191 mutex_lock(&rdev->gem.mutex); 192 if (*value == 1) { 193 /* wants rights */ 194 if (!*owner) 195 *owner = applier; 196 } else if (*value == 0) { 197 /* revokes rights */ 198 if (*owner == applier) 199 *owner = NULL; 200 } 201 *value = *owner == applier ? 1 : 0; 202 mutex_unlock(&rdev->gem.mutex); 203 } 204 205 /* 206 * Userspace get information ioctl 207 */ 208 /** 209 * radeon_info_ioctl - answer a device specific request. 210 * 211 * @rdev: radeon device pointer 212 * @data: request object 213 * @filp: drm filp 214 * 215 * This function is used to pass device specific parameters to the userspace 216 * drivers. Examples include: pci device id, pipeline parms, tiling params, 217 * etc. (all asics). 218 * Returns 0 on success, -EINVAL on failure. 219 */ 220 static int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 221 { 222 struct radeon_device *rdev = dev->dev_private; 223 struct drm_radeon_info *info = data; 224 struct radeon_mode_info *minfo = &rdev->mode_info; 225 uint32_t *value, value_tmp, *value_ptr, value_size; 226 uint64_t value64; 227 struct drm_crtc *crtc; 228 int i, found; 229 230 value_ptr = (uint32_t *)((unsigned long)info->value); 231 value = &value_tmp; 232 value_size = sizeof(uint32_t); 233 234 switch (info->request) { 235 case RADEON_INFO_DEVICE_ID: 236 *value = dev->pdev->device; 237 break; 238 case RADEON_INFO_NUM_GB_PIPES: 239 *value = rdev->num_gb_pipes; 240 break; 241 case RADEON_INFO_NUM_Z_PIPES: 242 *value = rdev->num_z_pipes; 243 break; 244 case RADEON_INFO_ACCEL_WORKING: 245 /* xf86-video-ati 6.13.0 relies on this being false for evergreen */ 246 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK)) 247 *value = false; 248 else 249 *value = rdev->accel_working; 250 break; 251 case RADEON_INFO_CRTC_FROM_ID: 252 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { 253 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); 254 return -EFAULT; 255 } 256 for (i = 0, found = 0; i < rdev->num_crtc; i++) { 257 crtc = (struct drm_crtc *)minfo->crtcs[i]; 258 if (crtc && crtc->base.id == *value) { 259 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 260 *value = radeon_crtc->crtc_id; 261 found = 1; 262 break; 263 } 264 } 265 if (!found) { 266 DRM_DEBUG_KMS("unknown crtc id %d\n", *value); 267 return -EINVAL; 268 } 269 break; 270 case RADEON_INFO_ACCEL_WORKING2: 271 if (rdev->family == CHIP_HAWAII) { 272 if (rdev->accel_working) { 273 if (rdev->new_fw) 274 *value = 3; 275 else 276 *value = 2; 277 } else { 278 *value = 0; 279 } 280 } else { 281 *value = rdev->accel_working; 282 } 283 break; 284 case RADEON_INFO_TILING_CONFIG: 285 if (rdev->family >= CHIP_BONAIRE) 286 *value = rdev->config.cik.tile_config; 287 else if (rdev->family >= CHIP_TAHITI) 288 *value = rdev->config.si.tile_config; 289 else if (rdev->family >= CHIP_CAYMAN) 290 *value = rdev->config.cayman.tile_config; 291 else if (rdev->family >= CHIP_CEDAR) 292 *value = rdev->config.evergreen.tile_config; 293 else if (rdev->family >= CHIP_RV770) 294 *value = rdev->config.rv770.tile_config; 295 else if (rdev->family >= CHIP_R600) 296 *value = rdev->config.r600.tile_config; 297 else { 298 DRM_DEBUG_KMS("tiling config is r6xx+ only!\n"); 299 return -EINVAL; 300 } 301 break; 302 case RADEON_INFO_WANT_HYPERZ: 303 /* The "value" here is both an input and output parameter. 304 * If the input value is 1, filp requests hyper-z access. 305 * If the input value is 0, filp revokes its hyper-z access. 306 * 307 * When returning, the value is 1 if filp owns hyper-z access, 308 * 0 otherwise. */ 309 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { 310 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); 311 return -EFAULT; 312 } 313 if (*value >= 2) { 314 DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", *value); 315 return -EINVAL; 316 } 317 radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, value); 318 break; 319 case RADEON_INFO_WANT_CMASK: 320 /* The same logic as Hyper-Z. */ 321 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { 322 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); 323 return -EFAULT; 324 } 325 if (*value >= 2) { 326 DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", *value); 327 return -EINVAL; 328 } 329 radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, value); 330 break; 331 case RADEON_INFO_CLOCK_CRYSTAL_FREQ: 332 /* return clock value in KHz */ 333 if (rdev->asic->get_xclk) 334 *value = radeon_get_xclk(rdev) * 10; 335 else 336 *value = rdev->clock.spll.reference_freq * 10; 337 break; 338 case RADEON_INFO_NUM_BACKENDS: 339 if (rdev->family >= CHIP_BONAIRE) 340 *value = rdev->config.cik.max_backends_per_se * 341 rdev->config.cik.max_shader_engines; 342 else if (rdev->family >= CHIP_TAHITI) 343 *value = rdev->config.si.max_backends_per_se * 344 rdev->config.si.max_shader_engines; 345 else if (rdev->family >= CHIP_CAYMAN) 346 *value = rdev->config.cayman.max_backends_per_se * 347 rdev->config.cayman.max_shader_engines; 348 else if (rdev->family >= CHIP_CEDAR) 349 *value = rdev->config.evergreen.max_backends; 350 else if (rdev->family >= CHIP_RV770) 351 *value = rdev->config.rv770.max_backends; 352 else if (rdev->family >= CHIP_R600) 353 *value = rdev->config.r600.max_backends; 354 else { 355 return -EINVAL; 356 } 357 break; 358 case RADEON_INFO_NUM_TILE_PIPES: 359 if (rdev->family >= CHIP_BONAIRE) 360 *value = rdev->config.cik.max_tile_pipes; 361 else if (rdev->family >= CHIP_TAHITI) 362 *value = rdev->config.si.max_tile_pipes; 363 else if (rdev->family >= CHIP_CAYMAN) 364 *value = rdev->config.cayman.max_tile_pipes; 365 else if (rdev->family >= CHIP_CEDAR) 366 *value = rdev->config.evergreen.max_tile_pipes; 367 else if (rdev->family >= CHIP_RV770) 368 *value = rdev->config.rv770.max_tile_pipes; 369 else if (rdev->family >= CHIP_R600) 370 *value = rdev->config.r600.max_tile_pipes; 371 else { 372 return -EINVAL; 373 } 374 break; 375 case RADEON_INFO_FUSION_GART_WORKING: 376 *value = 1; 377 break; 378 case RADEON_INFO_BACKEND_MAP: 379 if (rdev->family >= CHIP_BONAIRE) 380 *value = rdev->config.cik.backend_map; 381 else if (rdev->family >= CHIP_TAHITI) 382 *value = rdev->config.si.backend_map; 383 else if (rdev->family >= CHIP_CAYMAN) 384 *value = rdev->config.cayman.backend_map; 385 else if (rdev->family >= CHIP_CEDAR) 386 *value = rdev->config.evergreen.backend_map; 387 else if (rdev->family >= CHIP_RV770) 388 *value = rdev->config.rv770.backend_map; 389 else if (rdev->family >= CHIP_R600) 390 *value = rdev->config.r600.backend_map; 391 else { 392 return -EINVAL; 393 } 394 break; 395 case RADEON_INFO_VA_START: 396 /* this is where we report if vm is supported or not */ 397 if (rdev->family < CHIP_CAYMAN) 398 return -EINVAL; 399 *value = RADEON_VA_RESERVED_SIZE; 400 break; 401 case RADEON_INFO_IB_VM_MAX_SIZE: 402 /* this is where we report if vm is supported or not */ 403 if (rdev->family < CHIP_CAYMAN) 404 return -EINVAL; 405 *value = RADEON_IB_VM_MAX_SIZE; 406 break; 407 case RADEON_INFO_MAX_PIPES: 408 if (rdev->family >= CHIP_BONAIRE) 409 *value = rdev->config.cik.max_cu_per_sh; 410 else if (rdev->family >= CHIP_TAHITI) 411 *value = rdev->config.si.max_cu_per_sh; 412 else if (rdev->family >= CHIP_CAYMAN) 413 *value = rdev->config.cayman.max_pipes_per_simd; 414 else if (rdev->family >= CHIP_CEDAR) 415 *value = rdev->config.evergreen.max_pipes; 416 else if (rdev->family >= CHIP_RV770) 417 *value = rdev->config.rv770.max_pipes; 418 else if (rdev->family >= CHIP_R600) 419 *value = rdev->config.r600.max_pipes; 420 else { 421 return -EINVAL; 422 } 423 break; 424 case RADEON_INFO_TIMESTAMP: 425 if (rdev->family < CHIP_R600) { 426 DRM_DEBUG_KMS("timestamp is r6xx+ only!\n"); 427 return -EINVAL; 428 } 429 value = (uint32_t*)&value64; 430 value_size = sizeof(uint64_t); 431 value64 = radeon_get_gpu_clock_counter(rdev); 432 break; 433 case RADEON_INFO_MAX_SE: 434 if (rdev->family >= CHIP_BONAIRE) 435 *value = rdev->config.cik.max_shader_engines; 436 else if (rdev->family >= CHIP_TAHITI) 437 *value = rdev->config.si.max_shader_engines; 438 else if (rdev->family >= CHIP_CAYMAN) 439 *value = rdev->config.cayman.max_shader_engines; 440 else if (rdev->family >= CHIP_CEDAR) 441 *value = rdev->config.evergreen.num_ses; 442 else 443 *value = 1; 444 break; 445 case RADEON_INFO_MAX_SH_PER_SE: 446 if (rdev->family >= CHIP_BONAIRE) 447 *value = rdev->config.cik.max_sh_per_se; 448 else if (rdev->family >= CHIP_TAHITI) 449 *value = rdev->config.si.max_sh_per_se; 450 else 451 return -EINVAL; 452 break; 453 case RADEON_INFO_FASTFB_WORKING: 454 *value = rdev->fastfb_working; 455 break; 456 case RADEON_INFO_RING_WORKING: 457 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { 458 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); 459 return -EFAULT; 460 } 461 switch (*value) { 462 case RADEON_CS_RING_GFX: 463 case RADEON_CS_RING_COMPUTE: 464 *value = rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready; 465 break; 466 case RADEON_CS_RING_DMA: 467 *value = rdev->ring[R600_RING_TYPE_DMA_INDEX].ready; 468 *value |= rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready; 469 break; 470 case RADEON_CS_RING_UVD: 471 *value = rdev->ring[R600_RING_TYPE_UVD_INDEX].ready; 472 break; 473 case RADEON_CS_RING_VCE: 474 *value = rdev->ring[TN_RING_TYPE_VCE1_INDEX].ready; 475 break; 476 default: 477 return -EINVAL; 478 } 479 break; 480 case RADEON_INFO_SI_TILE_MODE_ARRAY: 481 if (rdev->family >= CHIP_BONAIRE) { 482 value = rdev->config.cik.tile_mode_array; 483 value_size = sizeof(uint32_t)*32; 484 } else if (rdev->family >= CHIP_TAHITI) { 485 value = rdev->config.si.tile_mode_array; 486 value_size = sizeof(uint32_t)*32; 487 } else { 488 DRM_DEBUG_KMS("tile mode array is si+ only!\n"); 489 return -EINVAL; 490 } 491 break; 492 case RADEON_INFO_CIK_MACROTILE_MODE_ARRAY: 493 if (rdev->family >= CHIP_BONAIRE) { 494 value = rdev->config.cik.macrotile_mode_array; 495 value_size = sizeof(uint32_t)*16; 496 } else { 497 DRM_DEBUG_KMS("macrotile mode array is cik+ only!\n"); 498 return -EINVAL; 499 } 500 break; 501 case RADEON_INFO_SI_CP_DMA_COMPUTE: 502 *value = 1; 503 break; 504 case RADEON_INFO_SI_BACKEND_ENABLED_MASK: 505 if (rdev->family >= CHIP_BONAIRE) { 506 *value = rdev->config.cik.backend_enable_mask; 507 } else if (rdev->family >= CHIP_TAHITI) { 508 *value = rdev->config.si.backend_enable_mask; 509 } else { 510 DRM_DEBUG_KMS("BACKEND_ENABLED_MASK is si+ only!\n"); 511 } 512 break; 513 case RADEON_INFO_MAX_SCLK: 514 if ((rdev->pm.pm_method == PM_METHOD_DPM) && 515 rdev->pm.dpm_enabled) 516 *value = rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10; 517 else 518 *value = rdev->pm.default_sclk * 10; 519 break; 520 case RADEON_INFO_VCE_FW_VERSION: 521 *value = rdev->vce.fw_version; 522 break; 523 case RADEON_INFO_VCE_FB_VERSION: 524 *value = rdev->vce.fb_version; 525 break; 526 case RADEON_INFO_NUM_BYTES_MOVED: 527 value = (uint32_t*)&value64; 528 value_size = sizeof(uint64_t); 529 value64 = atomic64_read(&rdev->num_bytes_moved); 530 break; 531 case RADEON_INFO_VRAM_USAGE: 532 value = (uint32_t*)&value64; 533 value_size = sizeof(uint64_t); 534 value64 = atomic64_read(&rdev->vram_usage); 535 break; 536 case RADEON_INFO_GTT_USAGE: 537 value = (uint32_t*)&value64; 538 value_size = sizeof(uint64_t); 539 value64 = atomic64_read(&rdev->gtt_usage); 540 break; 541 case RADEON_INFO_ACTIVE_CU_COUNT: 542 if (rdev->family >= CHIP_BONAIRE) 543 *value = rdev->config.cik.active_cus; 544 else if (rdev->family >= CHIP_TAHITI) 545 *value = rdev->config.si.active_cus; 546 else if (rdev->family >= CHIP_CAYMAN) 547 *value = rdev->config.cayman.active_simds; 548 else if (rdev->family >= CHIP_CEDAR) 549 *value = rdev->config.evergreen.active_simds; 550 else if (rdev->family >= CHIP_RV770) 551 *value = rdev->config.rv770.active_simds; 552 else if (rdev->family >= CHIP_R600) 553 *value = rdev->config.r600.active_simds; 554 else 555 *value = 1; 556 break; 557 case RADEON_INFO_CURRENT_GPU_TEMP: 558 /* get temperature in millidegrees C */ 559 if (rdev->asic->pm.get_temperature) 560 *value = radeon_get_temperature(rdev); 561 else 562 *value = 0; 563 break; 564 case RADEON_INFO_CURRENT_GPU_SCLK: 565 /* get sclk in Mhz */ 566 if (rdev->pm.dpm_enabled) 567 *value = radeon_dpm_get_current_sclk(rdev) / 100; 568 else 569 *value = rdev->pm.current_sclk / 100; 570 break; 571 case RADEON_INFO_CURRENT_GPU_MCLK: 572 /* get mclk in Mhz */ 573 if (rdev->pm.dpm_enabled) 574 *value = radeon_dpm_get_current_mclk(rdev) / 100; 575 else 576 *value = rdev->pm.current_mclk / 100; 577 break; 578 case RADEON_INFO_READ_REG: 579 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { 580 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); 581 return -EFAULT; 582 } 583 if (radeon_get_allowed_info_register(rdev, *value, value)) 584 return -EINVAL; 585 break; 586 case RADEON_INFO_VA_UNMAP_WORKING: 587 *value = true; 588 break; 589 case RADEON_INFO_GPU_RESET_COUNTER: 590 *value = atomic_read(&rdev->gpu_reset_counter); 591 break; 592 default: 593 DRM_DEBUG_KMS("Invalid request %d\n", info->request); 594 return -EINVAL; 595 } 596 if (copy_to_user(value_ptr, (char*)value, value_size)) { 597 DRM_ERROR("copy_to_user %s:%u\n", __func__, __LINE__); 598 return -EFAULT; 599 } 600 return 0; 601 } 602 603 604 /* 605 * Outdated mess for old drm with Xorg being in charge (void function now). 606 */ 607 /** 608 * radeon_driver_lastclose_kms - drm callback for last close 609 * 610 * @dev: drm dev pointer 611 * 612 * Switch vga_switcheroo state after last close (all asics). 613 */ 614 void radeon_driver_lastclose_kms(struct drm_device *dev) 615 { 616 struct radeon_device *rdev = dev->dev_private; 617 618 radeon_fbdev_restore_mode(rdev); 619 vga_switcheroo_process_delayed_switch(); 620 } 621 622 /** 623 * radeon_driver_open_kms - drm callback for open 624 * 625 * @dev: drm dev pointer 626 * @file_priv: drm file 627 * 628 * On device open, init vm on cayman+ (all asics). 629 * Returns 0 on success, error on failure. 630 */ 631 int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) 632 { 633 struct radeon_device *rdev = dev->dev_private; 634 int r; 635 636 file_priv->driver_priv = NULL; 637 638 r = pm_runtime_get_sync(dev->dev); 639 if (r < 0) 640 return r; 641 642 /* new gpu have virtual address space support */ 643 if (rdev->family >= CHIP_CAYMAN) { 644 struct radeon_fpriv *fpriv; 645 struct radeon_vm *vm; 646 int r; 647 648 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); 649 if (unlikely(!fpriv)) { 650 return -ENOMEM; 651 } 652 653 if (rdev->accel_working) { 654 vm = &fpriv->vm; 655 r = radeon_vm_init(rdev, vm); 656 if (r) { 657 kfree(fpriv); 658 return r; 659 } 660 661 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false); 662 if (r) { 663 radeon_vm_fini(rdev, vm); 664 kfree(fpriv); 665 return r; 666 } 667 668 /* map the ib pool buffer read only into 669 * virtual address space */ 670 vm->ib_bo_va = radeon_vm_bo_add(rdev, vm, 671 rdev->ring_tmp_bo.bo); 672 r = radeon_vm_bo_set_addr(rdev, vm->ib_bo_va, 673 RADEON_VA_IB_OFFSET, 674 RADEON_VM_PAGE_READABLE | 675 RADEON_VM_PAGE_SNOOPED); 676 if (r) { 677 radeon_vm_fini(rdev, vm); 678 kfree(fpriv); 679 return r; 680 } 681 } 682 file_priv->driver_priv = fpriv; 683 } 684 685 pm_runtime_mark_last_busy(dev->dev); 686 pm_runtime_put_autosuspend(dev->dev); 687 return 0; 688 } 689 690 /** 691 * radeon_driver_postclose_kms - drm callback for post close 692 * 693 * @dev: drm dev pointer 694 * @file_priv: drm file 695 * 696 * On device post close, tear down vm on cayman+ (all asics). 697 */ 698 void radeon_driver_postclose_kms(struct drm_device *dev, 699 struct drm_file *file_priv) 700 { 701 struct radeon_device *rdev = dev->dev_private; 702 703 /* new gpu have virtual address space support */ 704 if (rdev->family >= CHIP_CAYMAN && file_priv->driver_priv) { 705 struct radeon_fpriv *fpriv = file_priv->driver_priv; 706 struct radeon_vm *vm = &fpriv->vm; 707 int r; 708 709 if (rdev->accel_working) { 710 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false); 711 if (!r) { 712 if (vm->ib_bo_va) 713 radeon_vm_bo_rmv(rdev, vm->ib_bo_va); 714 radeon_bo_unreserve(rdev->ring_tmp_bo.bo); 715 } 716 radeon_vm_fini(rdev, vm); 717 } 718 719 kfree(fpriv); 720 file_priv->driver_priv = NULL; 721 } 722 } 723 724 /** 725 * radeon_driver_preclose_kms - drm callback for pre close 726 * 727 * @dev: drm dev pointer 728 * @file_priv: drm file 729 * 730 * On device pre close, tear down hyperz and cmask filps on r1xx-r5xx 731 * (all asics). 732 */ 733 void radeon_driver_preclose_kms(struct drm_device *dev, 734 struct drm_file *file_priv) 735 { 736 struct radeon_device *rdev = dev->dev_private; 737 738 mutex_lock(&rdev->gem.mutex); 739 if (rdev->hyperz_filp == file_priv) 740 rdev->hyperz_filp = NULL; 741 if (rdev->cmask_filp == file_priv) 742 rdev->cmask_filp = NULL; 743 mutex_unlock(&rdev->gem.mutex); 744 745 radeon_uvd_free_handles(rdev, file_priv); 746 radeon_vce_free_handles(rdev, file_priv); 747 } 748 749 /* 750 * VBlank related functions. 751 */ 752 /** 753 * radeon_get_vblank_counter_kms - get frame count 754 * 755 * @dev: drm dev pointer 756 * @crtc: crtc to get the frame count from 757 * 758 * Gets the frame count on the requested crtc (all asics). 759 * Returns frame count on success, -EINVAL on failure. 760 */ 761 u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc) 762 { 763 int vpos, hpos, stat; 764 u32 count; 765 struct radeon_device *rdev = dev->dev_private; 766 767 if (crtc < 0 || crtc >= rdev->num_crtc) { 768 DRM_ERROR("Invalid crtc %d\n", crtc); 769 return -EINVAL; 770 } 771 772 /* The hw increments its frame counter at start of vsync, not at start 773 * of vblank, as is required by DRM core vblank counter handling. 774 * Cook the hw count here to make it appear to the caller as if it 775 * incremented at start of vblank. We measure distance to start of 776 * vblank in vpos. vpos therefore will be >= 0 between start of vblank 777 * and start of vsync, so vpos >= 0 means to bump the hw frame counter 778 * result by 1 to give the proper appearance to caller. 779 */ 780 if (rdev->mode_info.crtcs[crtc]) { 781 /* Repeat readout if needed to provide stable result if 782 * we cross start of vsync during the queries. 783 */ 784 do { 785 count = radeon_get_vblank_counter(rdev, crtc); 786 /* Ask radeon_get_crtc_scanoutpos to return vpos as 787 * distance to start of vblank, instead of regular 788 * vertical scanout pos. 789 */ 790 stat = radeon_get_crtc_scanoutpos( 791 dev, crtc, GET_DISTANCE_TO_VBLANKSTART, 792 &vpos, &hpos, NULL, NULL, 793 &rdev->mode_info.crtcs[crtc]->base.hwmode); 794 } while (count != radeon_get_vblank_counter(rdev, crtc)); 795 796 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != 797 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) { 798 DRM_DEBUG_VBL("Query failed! stat %d\n", stat); 799 } 800 else { 801 DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n", 802 crtc, vpos); 803 804 /* Bump counter if we are at >= leading edge of vblank, 805 * but before vsync where vpos would turn negative and 806 * the hw counter really increments. 807 */ 808 if (vpos >= 0) 809 count++; 810 } 811 } 812 else { 813 /* Fallback to use value as is. */ 814 count = radeon_get_vblank_counter(rdev, crtc); 815 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n"); 816 } 817 818 return count; 819 } 820 821 /** 822 * radeon_enable_vblank_kms - enable vblank interrupt 823 * 824 * @dev: drm dev pointer 825 * @crtc: crtc to enable vblank interrupt for 826 * 827 * Enable the interrupt on the requested crtc (all asics). 828 * Returns 0 on success, -EINVAL on failure. 829 */ 830 int radeon_enable_vblank_kms(struct drm_device *dev, int crtc) 831 { 832 struct radeon_device *rdev = dev->dev_private; 833 unsigned long irqflags; 834 int r; 835 836 if (crtc < 0 || crtc >= rdev->num_crtc) { 837 DRM_ERROR("Invalid crtc %d\n", crtc); 838 return -EINVAL; 839 } 840 841 spin_lock_irqsave(&rdev->irq.lock, irqflags); 842 rdev->irq.crtc_vblank_int[crtc] = true; 843 r = radeon_irq_set(rdev); 844 spin_unlock_irqrestore(&rdev->irq.lock, irqflags); 845 return r; 846 } 847 848 /** 849 * radeon_disable_vblank_kms - disable vblank interrupt 850 * 851 * @dev: drm dev pointer 852 * @crtc: crtc to disable vblank interrupt for 853 * 854 * Disable the interrupt on the requested crtc (all asics). 855 */ 856 void radeon_disable_vblank_kms(struct drm_device *dev, int crtc) 857 { 858 struct radeon_device *rdev = dev->dev_private; 859 unsigned long irqflags; 860 861 if (crtc < 0 || crtc >= rdev->num_crtc) { 862 DRM_ERROR("Invalid crtc %d\n", crtc); 863 return; 864 } 865 866 spin_lock_irqsave(&rdev->irq.lock, irqflags); 867 rdev->irq.crtc_vblank_int[crtc] = false; 868 radeon_irq_set(rdev); 869 spin_unlock_irqrestore(&rdev->irq.lock, irqflags); 870 } 871 872 /** 873 * radeon_get_vblank_timestamp_kms - get vblank timestamp 874 * 875 * @dev: drm dev pointer 876 * @crtc: crtc to get the timestamp for 877 * @max_error: max error 878 * @vblank_time: time value 879 * @flags: flags passed to the driver 880 * 881 * Gets the timestamp on the requested crtc based on the 882 * scanout position. (all asics). 883 * Returns postive status flags on success, negative error on failure. 884 */ 885 int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc, 886 int *max_error, 887 struct timeval *vblank_time, 888 unsigned flags) 889 { 890 struct drm_crtc *drmcrtc; 891 struct radeon_device *rdev = dev->dev_private; 892 893 if (crtc < 0 || crtc >= dev->num_crtcs) { 894 DRM_ERROR("Invalid crtc %d\n", crtc); 895 return -EINVAL; 896 } 897 898 /* Get associated drm_crtc: */ 899 drmcrtc = &rdev->mode_info.crtcs[crtc]->base; 900 if (!drmcrtc) 901 return -EINVAL; 902 903 /* Helper routine in DRM core does all the work: */ 904 return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc, max_error, 905 vblank_time, flags, 906 &drmcrtc->hwmode); 907 } 908 909 const struct drm_ioctl_desc radeon_ioctls_kms[] = { 910 DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 911 DRM_IOCTL_DEF_DRV(RADEON_CP_START, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 912 DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 913 DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 914 DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, drm_invalid_op, DRM_AUTH), 915 DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, drm_invalid_op, DRM_AUTH), 916 DRM_IOCTL_DEF_DRV(RADEON_RESET, drm_invalid_op, DRM_AUTH), 917 DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, drm_invalid_op, DRM_AUTH), 918 DRM_IOCTL_DEF_DRV(RADEON_SWAP, drm_invalid_op, DRM_AUTH), 919 DRM_IOCTL_DEF_DRV(RADEON_CLEAR, drm_invalid_op, DRM_AUTH), 920 DRM_IOCTL_DEF_DRV(RADEON_VERTEX, drm_invalid_op, DRM_AUTH), 921 DRM_IOCTL_DEF_DRV(RADEON_INDICES, drm_invalid_op, DRM_AUTH), 922 DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, drm_invalid_op, DRM_AUTH), 923 DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, drm_invalid_op, DRM_AUTH), 924 DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 925 DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, drm_invalid_op, DRM_AUTH), 926 DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, drm_invalid_op, DRM_AUTH), 927 DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, drm_invalid_op, DRM_AUTH), 928 DRM_IOCTL_DEF_DRV(RADEON_FLIP, drm_invalid_op, DRM_AUTH), 929 DRM_IOCTL_DEF_DRV(RADEON_ALLOC, drm_invalid_op, DRM_AUTH), 930 DRM_IOCTL_DEF_DRV(RADEON_FREE, drm_invalid_op, DRM_AUTH), 931 DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 932 DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, drm_invalid_op, DRM_AUTH), 933 DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, drm_invalid_op, DRM_AUTH), 934 DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, drm_invalid_op, DRM_AUTH), 935 DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, drm_invalid_op, DRM_AUTH), 936 DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, drm_invalid_op, DRM_AUTH), 937 /* KMS */ 938 DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 939 DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 940 DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 941 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 942 DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH), 943 DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH), 944 DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 945 DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 946 DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 947 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 948 DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 949 DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 950 DRM_IOCTL_DEF_DRV(RADEON_GEM_VA, radeon_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 951 DRM_IOCTL_DEF_DRV(RADEON_GEM_OP, radeon_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 952 DRM_IOCTL_DEF_DRV(RADEON_GEM_USERPTR, radeon_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 953 }; 954 int radeon_max_kms_ioctl = ARRAY_SIZE(radeon_ioctls_kms); 955
Indexes created Tue Oct 21 16:10:11 GMT 2025