radeon_kms.c revision 1.1.1.3
1 /* $NetBSD: radeon_kms.c,v 1.1.1.3 2021/12/18 20:15:48 riastradh Exp $ */ 2 3 /* 4 * Copyright 2008 Advanced Micro Devices, Inc. 5 * Copyright 2008 Red Hat Inc. 6 * Copyright 2009 Jerome Glisse. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: Dave Airlie 27 * Alex Deucher 28 * Jerome Glisse 29 */ 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: radeon_kms.c,v 1.1.1.3 2021/12/18 20:15:48 riastradh Exp $"); 33 34 #include <linux/pci.h> 35 #include <linux/pm_runtime.h> 36 #include <linux/slab.h> 37 #include <linux/uaccess.h> 38 #include <linux/vga_switcheroo.h> 39 40 #include <drm/drm_fb_helper.h> 41 #include <drm/drm_file.h> 42 #include <drm/drm_ioctl.h> 43 #include <drm/radeon_drm.h> 44 45 #include "radeon.h" 46 #include "radeon_asic.h" 47 48 #if defined(CONFIG_VGA_SWITCHEROO) 49 bool radeon_has_atpx(void); 50 #else 51 static inline bool radeon_has_atpx(void) { return false; } 52 #endif 53 54 /** 55 * radeon_driver_unload_kms - Main unload function for KMS. 56 * 57 * @dev: drm dev pointer 58 * 59 * This is the main unload function for KMS (all asics). 60 * It calls radeon_modeset_fini() to tear down the 61 * displays, and radeon_device_fini() to tear down 62 * the rest of the device (CP, writeback, etc.). 63 * Returns 0 on success. 64 */ 65 void radeon_driver_unload_kms(struct drm_device *dev) 66 { 67 struct radeon_device *rdev = dev->dev_private; 68 69 if (rdev == NULL) 70 return; 71 72 if (rdev->rmmio == NULL) 73 goto done_free; 74 75 if (radeon_is_px(dev)) { 76 pm_runtime_get_sync(dev->dev); 77 pm_runtime_forbid(dev->dev); 78 } 79 80 radeon_acpi_fini(rdev); 81 82 radeon_modeset_fini(rdev); 83 radeon_device_fini(rdev); 84 85 done_free: 86 kfree(rdev); 87 dev->dev_private = NULL; 88 } 89 90 /** 91 * radeon_driver_load_kms - Main load function for KMS. 92 * 93 * @dev: drm dev pointer 94 * @flags: device flags 95 * 96 * This is the main load function for KMS (all asics). 97 * It calls radeon_device_init() to set up the non-display 98 * parts of the chip (asic init, CP, writeback, etc.), and 99 * radeon_modeset_init() to set up the display parts 100 * (crtcs, encoders, hotplug detect, etc.). 101 * Returns 0 on success, error on failure. 102 */ 103 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags) 104 { 105 struct radeon_device *rdev; 106 int r, acpi_status; 107 108 rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL); 109 if (rdev == NULL) { 110 return -ENOMEM; 111 } 112 dev->dev_private = (void *)rdev; 113 114 /* update BUS flag */ 115 if (pci_find_capability(dev->pdev, PCI_CAP_ID_AGP)) { 116 flags |= RADEON_IS_AGP; 117 } else if (pci_is_pcie(dev->pdev)) { 118 flags |= RADEON_IS_PCIE; 119 } else { 120 flags |= RADEON_IS_PCI; 121 } 122 123 if ((radeon_runtime_pm != 0) && 124 radeon_has_atpx() && 125 ((flags & RADEON_IS_IGP) == 0) && 126 !pci_is_thunderbolt_attached(dev->pdev)) 127 flags |= RADEON_IS_PX; 128 129 /* radeon_device_init should report only fatal error 130 * like memory allocation failure or iomapping failure, 131 * or memory manager initialization failure, it must 132 * properly initialize the GPU MC controller and permit 133 * VRAM allocation 134 */ 135 r = radeon_device_init(rdev, dev, dev->pdev, flags); 136 if (r) { 137 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n"); 138 goto out; 139 } 140 141 /* Again modeset_init should fail only on fatal error 142 * otherwise it should provide enough functionalities 143 * for shadowfb to run 144 */ 145 r = radeon_modeset_init(rdev); 146 if (r) 147 dev_err(&dev->pdev->dev, "Fatal error during modeset init\n"); 148 149 /* Call ACPI methods: require modeset init 150 * but failure is not fatal 151 */ 152 if (!r) { 153 acpi_status = radeon_acpi_init(rdev); 154 if (acpi_status) 155 dev_dbg(&dev->pdev->dev, 156 "Error during ACPI methods call\n"); 157 } 158 159 if (radeon_is_px(dev)) { 160 dev_pm_set_driver_flags(dev->dev, DPM_FLAG_NEVER_SKIP); 161 pm_runtime_use_autosuspend(dev->dev); 162 pm_runtime_set_autosuspend_delay(dev->dev, 5000); 163 pm_runtime_set_active(dev->dev); 164 pm_runtime_allow(dev->dev); 165 pm_runtime_mark_last_busy(dev->dev); 166 pm_runtime_put_autosuspend(dev->dev); 167 } 168 169 out: 170 if (r) 171 radeon_driver_unload_kms(dev); 172 173 174 return r; 175 } 176 177 /** 178 * radeon_set_filp_rights - Set filp right. 179 * 180 * @dev: drm dev pointer 181 * @owner: drm file 182 * @applier: drm file 183 * @value: value 184 * 185 * Sets the filp rights for the device (all asics). 186 */ 187 static void radeon_set_filp_rights(struct drm_device *dev, 188 struct drm_file **owner, 189 struct drm_file *applier, 190 uint32_t *value) 191 { 192 struct radeon_device *rdev = dev->dev_private; 193 194 mutex_lock(&rdev->gem.mutex); 195 if (*value == 1) { 196 /* wants rights */ 197 if (!*owner) 198 *owner = applier; 199 } else if (*value == 0) { 200 /* revokes rights */ 201 if (*owner == applier) 202 *owner = NULL; 203 } 204 *value = *owner == applier ? 1 : 0; 205 mutex_unlock(&rdev->gem.mutex); 206 } 207 208 /* 209 * Userspace get information ioctl 210 */ 211 /** 212 * radeon_info_ioctl - answer a device specific request. 213 * 214 * @rdev: radeon device pointer 215 * @data: request object 216 * @filp: drm filp 217 * 218 * This function is used to pass device specific parameters to the userspace 219 * drivers. Examples include: pci device id, pipeline parms, tiling params, 220 * etc. (all asics). 221 * Returns 0 on success, -EINVAL on failure. 222 */ 223 static int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 224 { 225 struct radeon_device *rdev = dev->dev_private; 226 struct drm_radeon_info *info = data; 227 struct radeon_mode_info *minfo = &rdev->mode_info; 228 uint32_t *value, value_tmp, *value_ptr, value_size; 229 uint64_t value64; 230 struct drm_crtc *crtc; 231 int i, found; 232 233 value_ptr = (uint32_t *)((unsigned long)info->value); 234 value = &value_tmp; 235 value_size = sizeof(uint32_t); 236 237 switch (info->request) { 238 case RADEON_INFO_DEVICE_ID: 239 *value = dev->pdev->device; 240 break; 241 case RADEON_INFO_NUM_GB_PIPES: 242 *value = rdev->num_gb_pipes; 243 break; 244 case RADEON_INFO_NUM_Z_PIPES: 245 *value = rdev->num_z_pipes; 246 break; 247 case RADEON_INFO_ACCEL_WORKING: 248 /* xf86-video-ati 6.13.0 relies on this being false for evergreen */ 249 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK)) 250 *value = false; 251 else 252 *value = rdev->accel_working; 253 break; 254 case RADEON_INFO_CRTC_FROM_ID: 255 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { 256 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); 257 return -EFAULT; 258 } 259 for (i = 0, found = 0; i < rdev->num_crtc; i++) { 260 crtc = (struct drm_crtc *)minfo->crtcs[i]; 261 if (crtc && crtc->base.id == *value) { 262 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 263 *value = radeon_crtc->crtc_id; 264 found = 1; 265 break; 266 } 267 } 268 if (!found) { 269 DRM_DEBUG_KMS("unknown crtc id %d\n", *value); 270 return -EINVAL; 271 } 272 break; 273 case RADEON_INFO_ACCEL_WORKING2: 274 if (rdev->family == CHIP_HAWAII) { 275 if (rdev->accel_working) { 276 if (rdev->new_fw) 277 *value = 3; 278 else 279 *value = 2; 280 } else { 281 *value = 0; 282 } 283 } else { 284 *value = rdev->accel_working; 285 } 286 break; 287 case RADEON_INFO_TILING_CONFIG: 288 if (rdev->family >= CHIP_BONAIRE) 289 *value = rdev->config.cik.tile_config; 290 else if (rdev->family >= CHIP_TAHITI) 291 *value = rdev->config.si.tile_config; 292 else if (rdev->family >= CHIP_CAYMAN) 293 *value = rdev->config.cayman.tile_config; 294 else if (rdev->family >= CHIP_CEDAR) 295 *value = rdev->config.evergreen.tile_config; 296 else if (rdev->family >= CHIP_RV770) 297 *value = rdev->config.rv770.tile_config; 298 else if (rdev->family >= CHIP_R600) 299 *value = rdev->config.r600.tile_config; 300 else { 301 DRM_DEBUG_KMS("tiling config is r6xx+ only!\n"); 302 return -EINVAL; 303 } 304 break; 305 case RADEON_INFO_WANT_HYPERZ: 306 /* The "value" here is both an input and output parameter. 307 * If the input value is 1, filp requests hyper-z access. 308 * If the input value is 0, filp revokes its hyper-z access. 309 * 310 * When returning, the value is 1 if filp owns hyper-z access, 311 * 0 otherwise. */ 312 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { 313 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); 314 return -EFAULT; 315 } 316 if (*value >= 2) { 317 DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", *value); 318 return -EINVAL; 319 } 320 radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, value); 321 break; 322 case RADEON_INFO_WANT_CMASK: 323 /* The same logic as Hyper-Z. */ 324 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { 325 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); 326 return -EFAULT; 327 } 328 if (*value >= 2) { 329 DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", *value); 330 return -EINVAL; 331 } 332 radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, value); 333 break; 334 case RADEON_INFO_CLOCK_CRYSTAL_FREQ: 335 /* return clock value in KHz */ 336 if (rdev->asic->get_xclk) 337 *value = radeon_get_xclk(rdev) * 10; 338 else 339 *value = rdev->clock.spll.reference_freq * 10; 340 break; 341 case RADEON_INFO_NUM_BACKENDS: 342 if (rdev->family >= CHIP_BONAIRE) 343 *value = rdev->config.cik.max_backends_per_se * 344 rdev->config.cik.max_shader_engines; 345 else if (rdev->family >= CHIP_TAHITI) 346 *value = rdev->config.si.max_backends_per_se * 347 rdev->config.si.max_shader_engines; 348 else if (rdev->family >= CHIP_CAYMAN) 349 *value = rdev->config.cayman.max_backends_per_se * 350 rdev->config.cayman.max_shader_engines; 351 else if (rdev->family >= CHIP_CEDAR) 352 *value = rdev->config.evergreen.max_backends; 353 else if (rdev->family >= CHIP_RV770) 354 *value = rdev->config.rv770.max_backends; 355 else if (rdev->family >= CHIP_R600) 356 *value = rdev->config.r600.max_backends; 357 else { 358 return -EINVAL; 359 } 360 break; 361 case RADEON_INFO_NUM_TILE_PIPES: 362 if (rdev->family >= CHIP_BONAIRE) 363 *value = rdev->config.cik.max_tile_pipes; 364 else if (rdev->family >= CHIP_TAHITI) 365 *value = rdev->config.si.max_tile_pipes; 366 else if (rdev->family >= CHIP_CAYMAN) 367 *value = rdev->config.cayman.max_tile_pipes; 368 else if (rdev->family >= CHIP_CEDAR) 369 *value = rdev->config.evergreen.max_tile_pipes; 370 else if (rdev->family >= CHIP_RV770) 371 *value = rdev->config.rv770.max_tile_pipes; 372 else if (rdev->family >= CHIP_R600) 373 *value = rdev->config.r600.max_tile_pipes; 374 else { 375 return -EINVAL; 376 } 377 break; 378 case RADEON_INFO_FUSION_GART_WORKING: 379 *value = 1; 380 break; 381 case RADEON_INFO_BACKEND_MAP: 382 if (rdev->family >= CHIP_BONAIRE) 383 *value = rdev->config.cik.backend_map; 384 else if (rdev->family >= CHIP_TAHITI) 385 *value = rdev->config.si.backend_map; 386 else if (rdev->family >= CHIP_CAYMAN) 387 *value = rdev->config.cayman.backend_map; 388 else if (rdev->family >= CHIP_CEDAR) 389 *value = rdev->config.evergreen.backend_map; 390 else if (rdev->family >= CHIP_RV770) 391 *value = rdev->config.rv770.backend_map; 392 else if (rdev->family >= CHIP_R600) 393 *value = rdev->config.r600.backend_map; 394 else { 395 return -EINVAL; 396 } 397 break; 398 case RADEON_INFO_VA_START: 399 /* this is where we report if vm is supported or not */ 400 if (rdev->family < CHIP_CAYMAN) 401 return -EINVAL; 402 *value = RADEON_VA_RESERVED_SIZE; 403 break; 404 case RADEON_INFO_IB_VM_MAX_SIZE: 405 /* this is where we report if vm is supported or not */ 406 if (rdev->family < CHIP_CAYMAN) 407 return -EINVAL; 408 *value = RADEON_IB_VM_MAX_SIZE; 409 break; 410 case RADEON_INFO_MAX_PIPES: 411 if (rdev->family >= CHIP_BONAIRE) 412 *value = rdev->config.cik.max_cu_per_sh; 413 else if (rdev->family >= CHIP_TAHITI) 414 *value = rdev->config.si.max_cu_per_sh; 415 else if (rdev->family >= CHIP_CAYMAN) 416 *value = rdev->config.cayman.max_pipes_per_simd; 417 else if (rdev->family >= CHIP_CEDAR) 418 *value = rdev->config.evergreen.max_pipes; 419 else if (rdev->family >= CHIP_RV770) 420 *value = rdev->config.rv770.max_pipes; 421 else if (rdev->family >= CHIP_R600) 422 *value = rdev->config.r600.max_pipes; 423 else { 424 return -EINVAL; 425 } 426 break; 427 case RADEON_INFO_TIMESTAMP: 428 if (rdev->family < CHIP_R600) { 429 DRM_DEBUG_KMS("timestamp is r6xx+ only!\n"); 430 return -EINVAL; 431 } 432 value = (uint32_t*)&value64; 433 value_size = sizeof(uint64_t); 434 value64 = radeon_get_gpu_clock_counter(rdev); 435 break; 436 case RADEON_INFO_MAX_SE: 437 if (rdev->family >= CHIP_BONAIRE) 438 *value = rdev->config.cik.max_shader_engines; 439 else if (rdev->family >= CHIP_TAHITI) 440 *value = rdev->config.si.max_shader_engines; 441 else if (rdev->family >= CHIP_CAYMAN) 442 *value = rdev->config.cayman.max_shader_engines; 443 else if (rdev->family >= CHIP_CEDAR) 444 *value = rdev->config.evergreen.num_ses; 445 else 446 *value = 1; 447 break; 448 case RADEON_INFO_MAX_SH_PER_SE: 449 if (rdev->family >= CHIP_BONAIRE) 450 *value = rdev->config.cik.max_sh_per_se; 451 else if (rdev->family >= CHIP_TAHITI) 452 *value = rdev->config.si.max_sh_per_se; 453 else 454 return -EINVAL; 455 break; 456 case RADEON_INFO_FASTFB_WORKING: 457 *value = rdev->fastfb_working; 458 break; 459 case RADEON_INFO_RING_WORKING: 460 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { 461 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); 462 return -EFAULT; 463 } 464 switch (*value) { 465 case RADEON_CS_RING_GFX: 466 case RADEON_CS_RING_COMPUTE: 467 *value = rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready; 468 break; 469 case RADEON_CS_RING_DMA: 470 *value = rdev->ring[R600_RING_TYPE_DMA_INDEX].ready; 471 *value |= rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready; 472 break; 473 case RADEON_CS_RING_UVD: 474 *value = rdev->ring[R600_RING_TYPE_UVD_INDEX].ready; 475 break; 476 case RADEON_CS_RING_VCE: 477 *value = rdev->ring[TN_RING_TYPE_VCE1_INDEX].ready; 478 break; 479 default: 480 return -EINVAL; 481 } 482 break; 483 case RADEON_INFO_SI_TILE_MODE_ARRAY: 484 if (rdev->family >= CHIP_BONAIRE) { 485 value = rdev->config.cik.tile_mode_array; 486 value_size = sizeof(uint32_t)*32; 487 } else if (rdev->family >= CHIP_TAHITI) { 488 value = rdev->config.si.tile_mode_array; 489 value_size = sizeof(uint32_t)*32; 490 } else { 491 DRM_DEBUG_KMS("tile mode array is si+ only!\n"); 492 return -EINVAL; 493 } 494 break; 495 case RADEON_INFO_CIK_MACROTILE_MODE_ARRAY: 496 if (rdev->family >= CHIP_BONAIRE) { 497 value = rdev->config.cik.macrotile_mode_array; 498 value_size = sizeof(uint32_t)*16; 499 } else { 500 DRM_DEBUG_KMS("macrotile mode array is cik+ only!\n"); 501 return -EINVAL; 502 } 503 break; 504 case RADEON_INFO_SI_CP_DMA_COMPUTE: 505 *value = 1; 506 break; 507 case RADEON_INFO_SI_BACKEND_ENABLED_MASK: 508 if (rdev->family >= CHIP_BONAIRE) { 509 *value = rdev->config.cik.backend_enable_mask; 510 } else if (rdev->family >= CHIP_TAHITI) { 511 *value = rdev->config.si.backend_enable_mask; 512 } else { 513 DRM_DEBUG_KMS("BACKEND_ENABLED_MASK is si+ only!\n"); 514 } 515 break; 516 case RADEON_INFO_MAX_SCLK: 517 if ((rdev->pm.pm_method == PM_METHOD_DPM) && 518 rdev->pm.dpm_enabled) 519 *value = rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10; 520 else 521 *value = rdev->pm.default_sclk * 10; 522 break; 523 case RADEON_INFO_VCE_FW_VERSION: 524 *value = rdev->vce.fw_version; 525 break; 526 case RADEON_INFO_VCE_FB_VERSION: 527 *value = rdev->vce.fb_version; 528 break; 529 case RADEON_INFO_NUM_BYTES_MOVED: 530 value = (uint32_t*)&value64; 531 value_size = sizeof(uint64_t); 532 value64 = atomic64_read(&rdev->num_bytes_moved); 533 break; 534 case RADEON_INFO_VRAM_USAGE: 535 value = (uint32_t*)&value64; 536 value_size = sizeof(uint64_t); 537 value64 = atomic64_read(&rdev->vram_usage); 538 break; 539 case RADEON_INFO_GTT_USAGE: 540 value = (uint32_t*)&value64; 541 value_size = sizeof(uint64_t); 542 value64 = atomic64_read(&rdev->gtt_usage); 543 break; 544 case RADEON_INFO_ACTIVE_CU_COUNT: 545 if (rdev->family >= CHIP_BONAIRE) 546 *value = rdev->config.cik.active_cus; 547 else if (rdev->family >= CHIP_TAHITI) 548 *value = rdev->config.si.active_cus; 549 else if (rdev->family >= CHIP_CAYMAN) 550 *value = rdev->config.cayman.active_simds; 551 else if (rdev->family >= CHIP_CEDAR) 552 *value = rdev->config.evergreen.active_simds; 553 else if (rdev->family >= CHIP_RV770) 554 *value = rdev->config.rv770.active_simds; 555 else if (rdev->family >= CHIP_R600) 556 *value = rdev->config.r600.active_simds; 557 else 558 *value = 1; 559 break; 560 case RADEON_INFO_CURRENT_GPU_TEMP: 561 /* get temperature in millidegrees C */ 562 if (rdev->asic->pm.get_temperature) 563 *value = radeon_get_temperature(rdev); 564 else 565 *value = 0; 566 break; 567 case RADEON_INFO_CURRENT_GPU_SCLK: 568 /* get sclk in Mhz */ 569 if (rdev->pm.dpm_enabled) 570 *value = radeon_dpm_get_current_sclk(rdev) / 100; 571 else 572 *value = rdev->pm.current_sclk / 100; 573 break; 574 case RADEON_INFO_CURRENT_GPU_MCLK: 575 /* get mclk in Mhz */ 576 if (rdev->pm.dpm_enabled) 577 *value = radeon_dpm_get_current_mclk(rdev) / 100; 578 else 579 *value = rdev->pm.current_mclk / 100; 580 break; 581 case RADEON_INFO_READ_REG: 582 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { 583 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); 584 return -EFAULT; 585 } 586 if (radeon_get_allowed_info_register(rdev, *value, value)) 587 return -EINVAL; 588 break; 589 case RADEON_INFO_VA_UNMAP_WORKING: 590 *value = true; 591 break; 592 case RADEON_INFO_GPU_RESET_COUNTER: 593 *value = atomic_read(&rdev->gpu_reset_counter); 594 break; 595 default: 596 DRM_DEBUG_KMS("Invalid request %d\n", info->request); 597 return -EINVAL; 598 } 599 if (copy_to_user(value_ptr, (char*)value, value_size)) { 600 DRM_ERROR("copy_to_user %s:%u\n", __func__, __LINE__); 601 return -EFAULT; 602 } 603 return 0; 604 } 605 606 607 /* 608 * Outdated mess for old drm with Xorg being in charge (void function now). 609 */ 610 /** 611 * radeon_driver_lastclose_kms - drm callback for last close 612 * 613 * @dev: drm dev pointer 614 * 615 * Switch vga_switcheroo state after last close (all asics). 616 */ 617 void radeon_driver_lastclose_kms(struct drm_device *dev) 618 { 619 drm_fb_helper_lastclose(dev); 620 vga_switcheroo_process_delayed_switch(); 621 } 622 623 /** 624 * radeon_driver_open_kms - drm callback for open 625 * 626 * @dev: drm dev pointer 627 * @file_priv: drm file 628 * 629 * On device open, init vm on cayman+ (all asics). 630 * Returns 0 on success, error on failure. 631 */ 632 int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) 633 { 634 struct radeon_device *rdev = dev->dev_private; 635 int r; 636 637 file_priv->driver_priv = NULL; 638 639 r = pm_runtime_get_sync(dev->dev); 640 if (r < 0) 641 return r; 642 643 /* new gpu have virtual address space support */ 644 if (rdev->family >= CHIP_CAYMAN) { 645 struct radeon_fpriv *fpriv; 646 struct radeon_vm *vm; 647 648 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); 649 if (unlikely(!fpriv)) { 650 r = -ENOMEM; 651 goto out_suspend; 652 } 653 654 if (rdev->accel_working) { 655 vm = &fpriv->vm; 656 r = radeon_vm_init(rdev, vm); 657 if (r) { 658 kfree(fpriv); 659 goto out_suspend; 660 } 661 662 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false); 663 if (r) { 664 radeon_vm_fini(rdev, vm); 665 kfree(fpriv); 666 goto out_suspend; 667 } 668 669 /* map the ib pool buffer read only into 670 * virtual address space */ 671 vm->ib_bo_va = radeon_vm_bo_add(rdev, vm, 672 rdev->ring_tmp_bo.bo); 673 r = radeon_vm_bo_set_addr(rdev, vm->ib_bo_va, 674 RADEON_VA_IB_OFFSET, 675 RADEON_VM_PAGE_READABLE | 676 RADEON_VM_PAGE_SNOOPED); 677 if (r) { 678 radeon_vm_fini(rdev, vm); 679 kfree(fpriv); 680 goto out_suspend; 681 } 682 } 683 file_priv->driver_priv = fpriv; 684 } 685 686 out_suspend: 687 pm_runtime_mark_last_busy(dev->dev); 688 pm_runtime_put_autosuspend(dev->dev); 689 return r; 690 } 691 692 /** 693 * radeon_driver_postclose_kms - drm callback for post close 694 * 695 * @dev: drm dev pointer 696 * @file_priv: drm file 697 * 698 * On device close, tear down hyperz and cmask filps on r1xx-r5xx 699 * (all asics). And tear down vm on cayman+ (all asics). 700 */ 701 void radeon_driver_postclose_kms(struct drm_device *dev, 702 struct drm_file *file_priv) 703 { 704 struct radeon_device *rdev = dev->dev_private; 705 706 pm_runtime_get_sync(dev->dev); 707 708 mutex_lock(&rdev->gem.mutex); 709 if (rdev->hyperz_filp == file_priv) 710 rdev->hyperz_filp = NULL; 711 if (rdev->cmask_filp == file_priv) 712 rdev->cmask_filp = NULL; 713 mutex_unlock(&rdev->gem.mutex); 714 715 radeon_uvd_free_handles(rdev, file_priv); 716 radeon_vce_free_handles(rdev, file_priv); 717 718 /* new gpu have virtual address space support */ 719 if (rdev->family >= CHIP_CAYMAN && file_priv->driver_priv) { 720 struct radeon_fpriv *fpriv = file_priv->driver_priv; 721 struct radeon_vm *vm = &fpriv->vm; 722 int r; 723 724 if (rdev->accel_working) { 725 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false); 726 if (!r) { 727 if (vm->ib_bo_va) 728 radeon_vm_bo_rmv(rdev, vm->ib_bo_va); 729 radeon_bo_unreserve(rdev->ring_tmp_bo.bo); 730 } 731 radeon_vm_fini(rdev, vm); 732 } 733 734 kfree(fpriv); 735 file_priv->driver_priv = NULL; 736 } 737 pm_runtime_mark_last_busy(dev->dev); 738 pm_runtime_put_autosuspend(dev->dev); 739 } 740 741 /* 742 * VBlank related functions. 743 */ 744 /** 745 * radeon_get_vblank_counter_kms - get frame count 746 * 747 * @dev: drm dev pointer 748 * @pipe: crtc to get the frame count from 749 * 750 * Gets the frame count on the requested crtc (all asics). 751 * Returns frame count on success, -EINVAL on failure. 752 */ 753 u32 radeon_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe) 754 { 755 int vpos, hpos, stat; 756 u32 count; 757 struct radeon_device *rdev = dev->dev_private; 758 759 if (pipe >= rdev->num_crtc) { 760 DRM_ERROR("Invalid crtc %u\n", pipe); 761 return -EINVAL; 762 } 763 764 /* The hw increments its frame counter at start of vsync, not at start 765 * of vblank, as is required by DRM core vblank counter handling. 766 * Cook the hw count here to make it appear to the caller as if it 767 * incremented at start of vblank. We measure distance to start of 768 * vblank in vpos. vpos therefore will be >= 0 between start of vblank 769 * and start of vsync, so vpos >= 0 means to bump the hw frame counter 770 * result by 1 to give the proper appearance to caller. 771 */ 772 if (rdev->mode_info.crtcs[pipe]) { 773 /* Repeat readout if needed to provide stable result if 774 * we cross start of vsync during the queries. 775 */ 776 do { 777 count = radeon_get_vblank_counter(rdev, pipe); 778 /* Ask radeon_get_crtc_scanoutpos to return vpos as 779 * distance to start of vblank, instead of regular 780 * vertical scanout pos. 781 */ 782 stat = radeon_get_crtc_scanoutpos( 783 dev, pipe, GET_DISTANCE_TO_VBLANKSTART, 784 &vpos, &hpos, NULL, NULL, 785 &rdev->mode_info.crtcs[pipe]->base.hwmode); 786 } while (count != radeon_get_vblank_counter(rdev, pipe)); 787 788 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != 789 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) { 790 DRM_DEBUG_VBL("Query failed! stat %d\n", stat); 791 } 792 else { 793 DRM_DEBUG_VBL("crtc %u: dist from vblank start %d\n", 794 pipe, vpos); 795 796 /* Bump counter if we are at >= leading edge of vblank, 797 * but before vsync where vpos would turn negative and 798 * the hw counter really increments. 799 */ 800 if (vpos >= 0) 801 count++; 802 } 803 } 804 else { 805 /* Fallback to use value as is. */ 806 count = radeon_get_vblank_counter(rdev, pipe); 807 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n"); 808 } 809 810 return count; 811 } 812 813 /** 814 * radeon_enable_vblank_kms - enable vblank interrupt 815 * 816 * @dev: drm dev pointer 817 * @crtc: crtc to enable vblank interrupt for 818 * 819 * Enable the interrupt on the requested crtc (all asics). 820 * Returns 0 on success, -EINVAL on failure. 821 */ 822 int radeon_enable_vblank_kms(struct drm_device *dev, int crtc) 823 { 824 struct radeon_device *rdev = dev->dev_private; 825 unsigned long irqflags; 826 int r; 827 828 if (crtc < 0 || crtc >= rdev->num_crtc) { 829 DRM_ERROR("Invalid crtc %d\n", crtc); 830 return -EINVAL; 831 } 832 833 spin_lock_irqsave(&rdev->irq.lock, irqflags); 834 rdev->irq.crtc_vblank_int[crtc] = true; 835 r = radeon_irq_set(rdev); 836 spin_unlock_irqrestore(&rdev->irq.lock, irqflags); 837 return r; 838 } 839 840 /** 841 * radeon_disable_vblank_kms - disable vblank interrupt 842 * 843 * @dev: drm dev pointer 844 * @crtc: crtc to disable vblank interrupt for 845 * 846 * Disable the interrupt on the requested crtc (all asics). 847 */ 848 void radeon_disable_vblank_kms(struct drm_device *dev, int crtc) 849 { 850 struct radeon_device *rdev = dev->dev_private; 851 unsigned long irqflags; 852 853 if (crtc < 0 || crtc >= rdev->num_crtc) { 854 DRM_ERROR("Invalid crtc %d\n", crtc); 855 return; 856 } 857 858 spin_lock_irqsave(&rdev->irq.lock, irqflags); 859 rdev->irq.crtc_vblank_int[crtc] = false; 860 radeon_irq_set(rdev); 861 spin_unlock_irqrestore(&rdev->irq.lock, irqflags); 862 } 863 864 const struct drm_ioctl_desc radeon_ioctls_kms[] = { 865 DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 866 DRM_IOCTL_DEF_DRV(RADEON_CP_START, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 867 DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 868 DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 869 DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, drm_invalid_op, DRM_AUTH), 870 DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, drm_invalid_op, DRM_AUTH), 871 DRM_IOCTL_DEF_DRV(RADEON_RESET, drm_invalid_op, DRM_AUTH), 872 DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, drm_invalid_op, DRM_AUTH), 873 DRM_IOCTL_DEF_DRV(RADEON_SWAP, drm_invalid_op, DRM_AUTH), 874 DRM_IOCTL_DEF_DRV(RADEON_CLEAR, drm_invalid_op, DRM_AUTH), 875 DRM_IOCTL_DEF_DRV(RADEON_VERTEX, drm_invalid_op, DRM_AUTH), 876 DRM_IOCTL_DEF_DRV(RADEON_INDICES, drm_invalid_op, DRM_AUTH), 877 DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, drm_invalid_op, DRM_AUTH), 878 DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, drm_invalid_op, DRM_AUTH), 879 DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 880 DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, drm_invalid_op, DRM_AUTH), 881 DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, drm_invalid_op, DRM_AUTH), 882 DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, drm_invalid_op, DRM_AUTH), 883 DRM_IOCTL_DEF_DRV(RADEON_FLIP, drm_invalid_op, DRM_AUTH), 884 DRM_IOCTL_DEF_DRV(RADEON_ALLOC, drm_invalid_op, DRM_AUTH), 885 DRM_IOCTL_DEF_DRV(RADEON_FREE, drm_invalid_op, DRM_AUTH), 886 DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 887 DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, drm_invalid_op, DRM_AUTH), 888 DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, drm_invalid_op, DRM_AUTH), 889 DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, drm_invalid_op, DRM_AUTH), 890 DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, drm_invalid_op, DRM_AUTH), 891 DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, drm_invalid_op, DRM_AUTH), 892 /* KMS */ 893 DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 894 DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 895 DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 896 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 897 DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH), 898 DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH), 899 DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 900 DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 901 DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 902 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 903 DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 904 DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 905 DRM_IOCTL_DEF_DRV(RADEON_GEM_VA, radeon_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 906 DRM_IOCTL_DEF_DRV(RADEON_GEM_OP, radeon_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 907 DRM_IOCTL_DEF_DRV(RADEON_GEM_USERPTR, radeon_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 908 }; 909 int radeon_max_kms_ioctl = ARRAY_SIZE(radeon_ioctls_kms); 910
Indexes created Wed Oct 22 00:09:40 GMT 2025