radeon_kms.c revision 1.3.18.1
1 /* $NetBSD: radeon_kms.c,v 1.3.18.1 2019/06/10 22:08:26 christos Exp $ */ 2 3 /* 4 * Copyright 2008 Advanced Micro Devices, Inc. 5 * Copyright 2008 Red Hat Inc. 6 * Copyright 2009 Jerome Glisse. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: Dave Airlie 27 * Alex Deucher 28 * Jerome Glisse 29 */ 30 #include <sys/cdefs.h> 31 __KERNEL_RCSID(0, "$NetBSD: radeon_kms.c,v 1.3.18.1 2019/06/10 22:08:26 christos Exp $"); 32 33 #include <drm/drmP.h> 34 #include "radeon.h" 35 #include <drm/radeon_drm.h> 36 #include "radeon_asic.h" 37 38 #include <linux/vga_switcheroo.h> 39 #include <linux/slab.h> 40 #include <linux/pm_runtime.h> 41 42 #include "radeon_kfd.h" 43 44 #if defined(CONFIG_VGA_SWITCHEROO) 45 bool radeon_has_atpx(void); 46 #else 47 static inline bool radeon_has_atpx(void) { return false; } 48 #endif 49 50 /** 51 * radeon_driver_unload_kms - Main unload function for KMS. 52 * 53 * @dev: drm dev pointer 54 * 55 * This is the main unload function for KMS (all asics). 56 * It calls radeon_modeset_fini() to tear down the 57 * displays, and radeon_device_fini() to tear down 58 * the rest of the device (CP, writeback, etc.). 59 * Returns 0 on success. 60 */ 61 int radeon_driver_unload_kms(struct drm_device *dev) 62 { 63 struct radeon_device *rdev = dev->dev_private; 64 65 if (rdev == NULL) 66 return 0; 67 68 #ifdef __NetBSD__ 69 /* XXX ugh */ 70 if (rdev->rmmio_size) 71 goto done_free; 72 #else 73 if (rdev->rmmio == NULL) 74 goto done_free; 75 #endif 76 77 pm_runtime_get_sync(dev->dev); 78 79 radeon_kfd_device_fini(rdev); 80 81 radeon_acpi_fini(rdev); 82 83 radeon_modeset_fini(rdev); 84 radeon_device_fini(rdev); 85 86 done_free: 87 kfree(rdev); 88 dev->dev_private = NULL; 89 return 0; 90 } 91 92 /** 93 * radeon_driver_load_kms - Main load function for KMS. 94 * 95 * @dev: drm dev pointer 96 * @flags: device flags 97 * 98 * This is the main load function for KMS (all asics). 99 * It calls radeon_device_init() to set up the non-display 100 * parts of the chip (asic init, CP, writeback, etc.), and 101 * radeon_modeset_init() to set up the display parts 102 * (crtcs, encoders, hotplug detect, etc.). 103 * Returns 0 on success, error on failure. 104 */ 105 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags) 106 { 107 struct radeon_device *rdev; 108 int r, acpi_status; 109 110 rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL); 111 if (rdev == NULL) { 112 return -ENOMEM; 113 } 114 dev->dev_private = (void *)rdev; 115 116 /* update BUS flag */ 117 if (drm_pci_device_is_agp(dev)) { 118 flags |= RADEON_IS_AGP; 119 } else if (pci_is_pcie(dev->pdev)) { 120 flags |= RADEON_IS_PCIE; 121 } else { 122 flags |= RADEON_IS_PCI; 123 } 124 125 if ((radeon_runtime_pm != 0) && 126 radeon_has_atpx() && 127 ((flags & RADEON_IS_IGP) == 0)) 128 flags |= RADEON_IS_PX; 129 130 /* radeon_device_init should report only fatal error 131 * like memory allocation failure or iomapping failure, 132 * or memory manager initialization failure, it must 133 * properly initialize the GPU MC controller and permit 134 * VRAM allocation 135 */ 136 r = radeon_device_init(rdev, dev, dev->pdev, flags); 137 if (r) { 138 dev_err(dev->dev, "Fatal error during GPU init\n"); 139 goto out; 140 } 141 142 /* Again modeset_init should fail only on fatal error 143 * otherwise it should provide enough functionalities 144 * for shadowfb to run 145 */ 146 r = radeon_modeset_init(rdev); 147 if (r) 148 dev_err(dev->dev, "Fatal error during modeset init\n"); 149 150 /* Call ACPI methods: require modeset init 151 * but failure is not fatal 152 */ 153 if (!r) { 154 acpi_status = radeon_acpi_init(rdev); 155 if (acpi_status) 156 dev_dbg(dev->dev, 157 "Error during ACPI methods call\n"); 158 } 159 160 radeon_kfd_device_probe(rdev); 161 radeon_kfd_device_init(rdev); 162 163 if (radeon_is_px(dev)) { 164 pm_runtime_use_autosuspend(dev->dev); 165 pm_runtime_set_autosuspend_delay(dev->dev, 5000); 166 pm_runtime_set_active(dev->dev); 167 pm_runtime_allow(dev->dev); 168 pm_runtime_mark_last_busy(dev->dev); 169 pm_runtime_put_autosuspend(dev->dev); 170 } 171 172 out: 173 if (r) 174 radeon_driver_unload_kms(dev); 175 176 177 return r; 178 } 179 180 /** 181 * radeon_set_filp_rights - Set filp right. 182 * 183 * @dev: drm dev pointer 184 * @owner: drm file 185 * @applier: drm file 186 * @value: value 187 * 188 * Sets the filp rights for the device (all asics). 189 */ 190 static void radeon_set_filp_rights(struct drm_device *dev, 191 struct drm_file **owner, 192 struct drm_file *applier, 193 uint32_t *value) 194 { 195 struct radeon_device *rdev = dev->dev_private; 196 197 mutex_lock(&rdev->gem.mutex); 198 if (*value == 1) { 199 /* wants rights */ 200 if (!*owner) 201 *owner = applier; 202 } else if (*value == 0) { 203 /* revokes rights */ 204 if (*owner == applier) 205 *owner = NULL; 206 } 207 *value = *owner == applier ? 1 : 0; 208 mutex_unlock(&rdev->gem.mutex); 209 } 210 211 /* 212 * Userspace get information ioctl 213 */ 214 /** 215 * radeon_info_ioctl - answer a device specific request. 216 * 217 * @rdev: radeon device pointer 218 * @data: request object 219 * @filp: drm filp 220 * 221 * This function is used to pass device specific parameters to the userspace 222 * drivers. Examples include: pci device id, pipeline parms, tiling params, 223 * etc. (all asics). 224 * Returns 0 on success, -EINVAL on failure. 225 */ 226 static int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 227 { 228 struct radeon_device *rdev = dev->dev_private; 229 struct drm_radeon_info *info = data; 230 struct radeon_mode_info *minfo = &rdev->mode_info; 231 uint32_t *value, value_tmp, *value_ptr, value_size; 232 uint64_t value64; 233 struct drm_crtc *crtc; 234 int i, found; 235 236 value_ptr = (uint32_t *)((unsigned long)info->value); 237 value = &value_tmp; 238 value_size = sizeof(uint32_t); 239 240 switch (info->request) { 241 case RADEON_INFO_DEVICE_ID: 242 *value = dev->pdev->device; 243 break; 244 case RADEON_INFO_NUM_GB_PIPES: 245 *value = rdev->num_gb_pipes; 246 break; 247 case RADEON_INFO_NUM_Z_PIPES: 248 *value = rdev->num_z_pipes; 249 break; 250 case RADEON_INFO_ACCEL_WORKING: 251 /* xf86-video-ati 6.13.0 relies on this being false for evergreen */ 252 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK)) 253 *value = false; 254 else 255 *value = rdev->accel_working; 256 break; 257 case RADEON_INFO_CRTC_FROM_ID: 258 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { 259 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); 260 return -EFAULT; 261 } 262 for (i = 0, found = 0; i < rdev->num_crtc; i++) { 263 crtc = (struct drm_crtc *)minfo->crtcs[i]; 264 if (crtc && crtc->base.id == *value) { 265 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 266 *value = radeon_crtc->crtc_id; 267 found = 1; 268 break; 269 } 270 } 271 if (!found) { 272 DRM_DEBUG_KMS("unknown crtc id %d\n", *value); 273 return -EINVAL; 274 } 275 break; 276 case RADEON_INFO_ACCEL_WORKING2: 277 if (rdev->family == CHIP_HAWAII) { 278 if (rdev->accel_working) { 279 if (rdev->new_fw) 280 *value = 3; 281 else 282 *value = 2; 283 } else { 284 *value = 0; 285 } 286 } else { 287 *value = rdev->accel_working; 288 } 289 break; 290 case RADEON_INFO_TILING_CONFIG: 291 if (rdev->family >= CHIP_BONAIRE) 292 *value = rdev->config.cik.tile_config; 293 else if (rdev->family >= CHIP_TAHITI) 294 *value = rdev->config.si.tile_config; 295 else if (rdev->family >= CHIP_CAYMAN) 296 *value = rdev->config.cayman.tile_config; 297 else if (rdev->family >= CHIP_CEDAR) 298 *value = rdev->config.evergreen.tile_config; 299 else if (rdev->family >= CHIP_RV770) 300 *value = rdev->config.rv770.tile_config; 301 else if (rdev->family >= CHIP_R600) 302 *value = rdev->config.r600.tile_config; 303 else { 304 DRM_DEBUG_KMS("tiling config is r6xx+ only!\n"); 305 return -EINVAL; 306 } 307 break; 308 case RADEON_INFO_WANT_HYPERZ: 309 /* The "value" here is both an input and output parameter. 310 * If the input value is 1, filp requests hyper-z access. 311 * If the input value is 0, filp revokes its hyper-z access. 312 * 313 * When returning, the value is 1 if filp owns hyper-z access, 314 * 0 otherwise. */ 315 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { 316 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); 317 return -EFAULT; 318 } 319 if (*value >= 2) { 320 DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", *value); 321 return -EINVAL; 322 } 323 radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, value); 324 break; 325 case RADEON_INFO_WANT_CMASK: 326 /* The same logic as Hyper-Z. */ 327 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { 328 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); 329 return -EFAULT; 330 } 331 if (*value >= 2) { 332 DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", *value); 333 return -EINVAL; 334 } 335 radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, value); 336 break; 337 case RADEON_INFO_CLOCK_CRYSTAL_FREQ: 338 /* return clock value in KHz */ 339 if (rdev->asic->get_xclk) 340 *value = radeon_get_xclk(rdev) * 10; 341 else 342 *value = rdev->clock.spll.reference_freq * 10; 343 break; 344 case RADEON_INFO_NUM_BACKENDS: 345 if (rdev->family >= CHIP_BONAIRE) 346 *value = rdev->config.cik.max_backends_per_se * 347 rdev->config.cik.max_shader_engines; 348 else if (rdev->family >= CHIP_TAHITI) 349 *value = rdev->config.si.max_backends_per_se * 350 rdev->config.si.max_shader_engines; 351 else if (rdev->family >= CHIP_CAYMAN) 352 *value = rdev->config.cayman.max_backends_per_se * 353 rdev->config.cayman.max_shader_engines; 354 else if (rdev->family >= CHIP_CEDAR) 355 *value = rdev->config.evergreen.max_backends; 356 else if (rdev->family >= CHIP_RV770) 357 *value = rdev->config.rv770.max_backends; 358 else if (rdev->family >= CHIP_R600) 359 *value = rdev->config.r600.max_backends; 360 else { 361 return -EINVAL; 362 } 363 break; 364 case RADEON_INFO_NUM_TILE_PIPES: 365 if (rdev->family >= CHIP_BONAIRE) 366 *value = rdev->config.cik.max_tile_pipes; 367 else if (rdev->family >= CHIP_TAHITI) 368 *value = rdev->config.si.max_tile_pipes; 369 else if (rdev->family >= CHIP_CAYMAN) 370 *value = rdev->config.cayman.max_tile_pipes; 371 else if (rdev->family >= CHIP_CEDAR) 372 *value = rdev->config.evergreen.max_tile_pipes; 373 else if (rdev->family >= CHIP_RV770) 374 *value = rdev->config.rv770.max_tile_pipes; 375 else if (rdev->family >= CHIP_R600) 376 *value = rdev->config.r600.max_tile_pipes; 377 else { 378 return -EINVAL; 379 } 380 break; 381 case RADEON_INFO_FUSION_GART_WORKING: 382 *value = 1; 383 break; 384 case RADEON_INFO_BACKEND_MAP: 385 if (rdev->family >= CHIP_BONAIRE) 386 *value = rdev->config.cik.backend_map; 387 else if (rdev->family >= CHIP_TAHITI) 388 *value = rdev->config.si.backend_map; 389 else if (rdev->family >= CHIP_CAYMAN) 390 *value = rdev->config.cayman.backend_map; 391 else if (rdev->family >= CHIP_CEDAR) 392 *value = rdev->config.evergreen.backend_map; 393 else if (rdev->family >= CHIP_RV770) 394 *value = rdev->config.rv770.backend_map; 395 else if (rdev->family >= CHIP_R600) 396 *value = rdev->config.r600.backend_map; 397 else { 398 return -EINVAL; 399 } 400 break; 401 case RADEON_INFO_VA_START: 402 /* this is where we report if vm is supported or not */ 403 if (rdev->family < CHIP_CAYMAN) 404 return -EINVAL; 405 *value = RADEON_VA_RESERVED_SIZE; 406 break; 407 case RADEON_INFO_IB_VM_MAX_SIZE: 408 /* this is where we report if vm is supported or not */ 409 if (rdev->family < CHIP_CAYMAN) 410 return -EINVAL; 411 *value = RADEON_IB_VM_MAX_SIZE; 412 break; 413 case RADEON_INFO_MAX_PIPES: 414 if (rdev->family >= CHIP_BONAIRE) 415 *value = rdev->config.cik.max_cu_per_sh; 416 else if (rdev->family >= CHIP_TAHITI) 417 *value = rdev->config.si.max_cu_per_sh; 418 else if (rdev->family >= CHIP_CAYMAN) 419 *value = rdev->config.cayman.max_pipes_per_simd; 420 else if (rdev->family >= CHIP_CEDAR) 421 *value = rdev->config.evergreen.max_pipes; 422 else if (rdev->family >= CHIP_RV770) 423 *value = rdev->config.rv770.max_pipes; 424 else if (rdev->family >= CHIP_R600) 425 *value = rdev->config.r600.max_pipes; 426 else { 427 return -EINVAL; 428 } 429 break; 430 case RADEON_INFO_TIMESTAMP: 431 if (rdev->family < CHIP_R600) { 432 DRM_DEBUG_KMS("timestamp is r6xx+ only!\n"); 433 return -EINVAL; 434 } 435 value = (uint32_t*)&value64; 436 value_size = sizeof(uint64_t); 437 value64 = radeon_get_gpu_clock_counter(rdev); 438 break; 439 case RADEON_INFO_MAX_SE: 440 if (rdev->family >= CHIP_BONAIRE) 441 *value = rdev->config.cik.max_shader_engines; 442 else if (rdev->family >= CHIP_TAHITI) 443 *value = rdev->config.si.max_shader_engines; 444 else if (rdev->family >= CHIP_CAYMAN) 445 *value = rdev->config.cayman.max_shader_engines; 446 else if (rdev->family >= CHIP_CEDAR) 447 *value = rdev->config.evergreen.num_ses; 448 else 449 *value = 1; 450 break; 451 case RADEON_INFO_MAX_SH_PER_SE: 452 if (rdev->family >= CHIP_BONAIRE) 453 *value = rdev->config.cik.max_sh_per_se; 454 else if (rdev->family >= CHIP_TAHITI) 455 *value = rdev->config.si.max_sh_per_se; 456 else 457 return -EINVAL; 458 break; 459 case RADEON_INFO_FASTFB_WORKING: 460 *value = rdev->fastfb_working; 461 break; 462 case RADEON_INFO_RING_WORKING: 463 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { 464 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); 465 return -EFAULT; 466 } 467 switch (*value) { 468 case RADEON_CS_RING_GFX: 469 case RADEON_CS_RING_COMPUTE: 470 *value = rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready; 471 break; 472 case RADEON_CS_RING_DMA: 473 *value = rdev->ring[R600_RING_TYPE_DMA_INDEX].ready; 474 *value |= rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready; 475 break; 476 case RADEON_CS_RING_UVD: 477 *value = rdev->ring[R600_RING_TYPE_UVD_INDEX].ready; 478 break; 479 case RADEON_CS_RING_VCE: 480 *value = rdev->ring[TN_RING_TYPE_VCE1_INDEX].ready; 481 break; 482 default: 483 return -EINVAL; 484 } 485 break; 486 case RADEON_INFO_SI_TILE_MODE_ARRAY: 487 if (rdev->family >= CHIP_BONAIRE) { 488 value = rdev->config.cik.tile_mode_array; 489 value_size = sizeof(uint32_t)*32; 490 } else if (rdev->family >= CHIP_TAHITI) { 491 value = rdev->config.si.tile_mode_array; 492 value_size = sizeof(uint32_t)*32; 493 } else { 494 DRM_DEBUG_KMS("tile mode array is si+ only!\n"); 495 return -EINVAL; 496 } 497 break; 498 case RADEON_INFO_CIK_MACROTILE_MODE_ARRAY: 499 if (rdev->family >= CHIP_BONAIRE) { 500 value = rdev->config.cik.macrotile_mode_array; 501 value_size = sizeof(uint32_t)*16; 502 } else { 503 DRM_DEBUG_KMS("macrotile mode array is cik+ only!\n"); 504 return -EINVAL; 505 } 506 break; 507 case RADEON_INFO_SI_CP_DMA_COMPUTE: 508 *value = 1; 509 break; 510 case RADEON_INFO_SI_BACKEND_ENABLED_MASK: 511 if (rdev->family >= CHIP_BONAIRE) { 512 *value = rdev->config.cik.backend_enable_mask; 513 } else if (rdev->family >= CHIP_TAHITI) { 514 *value = rdev->config.si.backend_enable_mask; 515 } else { 516 DRM_DEBUG_KMS("BACKEND_ENABLED_MASK is si+ only!\n"); 517 } 518 break; 519 case RADEON_INFO_MAX_SCLK: 520 if ((rdev->pm.pm_method == PM_METHOD_DPM) && 521 rdev->pm.dpm_enabled) 522 *value = rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10; 523 else 524 *value = rdev->pm.default_sclk * 10; 525 break; 526 case RADEON_INFO_VCE_FW_VERSION: 527 *value = rdev->vce.fw_version; 528 break; 529 case RADEON_INFO_VCE_FB_VERSION: 530 *value = rdev->vce.fb_version; 531 break; 532 case RADEON_INFO_NUM_BYTES_MOVED: 533 value = (uint32_t*)&value64; 534 value_size = sizeof(uint64_t); 535 value64 = atomic64_read(&rdev->num_bytes_moved); 536 break; 537 case RADEON_INFO_VRAM_USAGE: 538 value = (uint32_t*)&value64; 539 value_size = sizeof(uint64_t); 540 value64 = atomic64_read(&rdev->vram_usage); 541 break; 542 case RADEON_INFO_GTT_USAGE: 543 value = (uint32_t*)&value64; 544 value_size = sizeof(uint64_t); 545 value64 = atomic64_read(&rdev->gtt_usage); 546 break; 547 case RADEON_INFO_ACTIVE_CU_COUNT: 548 if (rdev->family >= CHIP_BONAIRE) 549 *value = rdev->config.cik.active_cus; 550 else if (rdev->family >= CHIP_TAHITI) 551 *value = rdev->config.si.active_cus; 552 else if (rdev->family >= CHIP_CAYMAN) 553 *value = rdev->config.cayman.active_simds; 554 else if (rdev->family >= CHIP_CEDAR) 555 *value = rdev->config.evergreen.active_simds; 556 else if (rdev->family >= CHIP_RV770) 557 *value = rdev->config.rv770.active_simds; 558 else if (rdev->family >= CHIP_R600) 559 *value = rdev->config.r600.active_simds; 560 else 561 *value = 1; 562 break; 563 case RADEON_INFO_CURRENT_GPU_TEMP: 564 /* get temperature in millidegrees C */ 565 if (rdev->asic->pm.get_temperature) 566 *value = radeon_get_temperature(rdev); 567 else 568 *value = 0; 569 break; 570 case RADEON_INFO_CURRENT_GPU_SCLK: 571 /* get sclk in Mhz */ 572 if (rdev->pm.dpm_enabled) 573 *value = radeon_dpm_get_current_sclk(rdev) / 100; 574 else 575 *value = rdev->pm.current_sclk / 100; 576 break; 577 case RADEON_INFO_CURRENT_GPU_MCLK: 578 /* get mclk in Mhz */ 579 if (rdev->pm.dpm_enabled) 580 *value = radeon_dpm_get_current_mclk(rdev) / 100; 581 else 582 *value = rdev->pm.current_mclk / 100; 583 break; 584 case RADEON_INFO_READ_REG: 585 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { 586 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); 587 return -EFAULT; 588 } 589 if (radeon_get_allowed_info_register(rdev, *value, value)) 590 return -EINVAL; 591 break; 592 case RADEON_INFO_VA_UNMAP_WORKING: 593 *value = true; 594 break; 595 case RADEON_INFO_GPU_RESET_COUNTER: 596 *value = atomic_read(&rdev->gpu_reset_counter); 597 break; 598 default: 599 DRM_DEBUG_KMS("Invalid request %d\n", info->request); 600 return -EINVAL; 601 } 602 if (copy_to_user(value_ptr, (char*)value, value_size)) { 603 DRM_ERROR("copy_to_user %s:%u\n", __func__, __LINE__); 604 return -EFAULT; 605 } 606 return 0; 607 } 608 609 610 /* 611 * Outdated mess for old drm with Xorg being in charge (void function now). 612 */ 613 /** 614 * radeon_driver_lastclose_kms - drm callback for last close 615 * 616 * @dev: drm dev pointer 617 * 618 * Switch vga_switcheroo state after last close (all asics). 619 */ 620 void radeon_driver_lastclose_kms(struct drm_device *dev) 621 { 622 struct radeon_device *rdev = dev->dev_private; 623 624 radeon_fbdev_restore_mode(rdev); 625 #ifndef __NetBSD__ /* XXX radeon vga */ 626 vga_switcheroo_process_delayed_switch(); 627 #endif 628 } 629 630 /** 631 * radeon_driver_open_kms - drm callback for open 632 * 633 * @dev: drm dev pointer 634 * @file_priv: drm file 635 * 636 * On device open, init vm on cayman+ (all asics). 637 * Returns 0 on success, error on failure. 638 */ 639 int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) 640 { 641 struct radeon_device *rdev = dev->dev_private; 642 int r; 643 644 file_priv->driver_priv = NULL; 645 646 r = pm_runtime_get_sync(dev->dev); 647 if (r < 0) 648 return r; 649 650 /* new gpu have virtual address space support */ 651 if (rdev->family >= CHIP_CAYMAN) { 652 struct radeon_fpriv *fpriv; 653 struct radeon_vm *vm; 654 int r; 655 656 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); 657 if (unlikely(!fpriv)) { 658 return -ENOMEM; 659 } 660 661 if (rdev->accel_working) { 662 vm = &fpriv->vm; 663 r = radeon_vm_init(rdev, vm); 664 if (r) { 665 kfree(fpriv); 666 return r; 667 } 668 669 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false); 670 if (r) { 671 radeon_vm_fini(rdev, vm); 672 kfree(fpriv); 673 return r; 674 } 675 676 /* map the ib pool buffer read only into 677 * virtual address space */ 678 vm->ib_bo_va = radeon_vm_bo_add(rdev, vm, 679 rdev->ring_tmp_bo.bo); 680 r = radeon_vm_bo_set_addr(rdev, vm->ib_bo_va, 681 RADEON_VA_IB_OFFSET, 682 RADEON_VM_PAGE_READABLE | 683 RADEON_VM_PAGE_SNOOPED); 684 if (r) { 685 radeon_vm_fini(rdev, vm); 686 kfree(fpriv); 687 return r; 688 } 689 } 690 file_priv->driver_priv = fpriv; 691 } 692 693 pm_runtime_mark_last_busy(dev->dev); 694 pm_runtime_put_autosuspend(dev->dev); 695 return 0; 696 } 697 698 /** 699 * radeon_driver_postclose_kms - drm callback for post close 700 * 701 * @dev: drm dev pointer 702 * @file_priv: drm file 703 * 704 * On device post close, tear down vm on cayman+ (all asics). 705 */ 706 void radeon_driver_postclose_kms(struct drm_device *dev, 707 struct drm_file *file_priv) 708 { 709 struct radeon_device *rdev = dev->dev_private; 710 711 /* new gpu have virtual address space support */ 712 if (rdev->family >= CHIP_CAYMAN && file_priv->driver_priv) { 713 struct radeon_fpriv *fpriv = file_priv->driver_priv; 714 struct radeon_vm *vm = &fpriv->vm; 715 int r; 716 717 if (rdev->accel_working) { 718 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false); 719 if (!r) { 720 if (vm->ib_bo_va) 721 radeon_vm_bo_rmv(rdev, vm->ib_bo_va); 722 radeon_bo_unreserve(rdev->ring_tmp_bo.bo); 723 } 724 radeon_vm_fini(rdev, vm); 725 } 726 727 kfree(fpriv); 728 file_priv->driver_priv = NULL; 729 } 730 } 731 732 /** 733 * radeon_driver_preclose_kms - drm callback for pre close 734 * 735 * @dev: drm dev pointer 736 * @file_priv: drm file 737 * 738 * On device pre close, tear down hyperz and cmask filps on r1xx-r5xx 739 * (all asics). 740 */ 741 void radeon_driver_preclose_kms(struct drm_device *dev, 742 struct drm_file *file_priv) 743 { 744 struct radeon_device *rdev = dev->dev_private; 745 746 mutex_lock(&rdev->gem.mutex); 747 if (rdev->hyperz_filp == file_priv) 748 rdev->hyperz_filp = NULL; 749 if (rdev->cmask_filp == file_priv) 750 rdev->cmask_filp = NULL; 751 mutex_unlock(&rdev->gem.mutex); 752 753 radeon_uvd_free_handles(rdev, file_priv); 754 radeon_vce_free_handles(rdev, file_priv); 755 } 756 757 /* 758 * VBlank related functions. 759 */ 760 /** 761 * radeon_get_vblank_counter_kms - get frame count 762 * 763 * @dev: drm dev pointer 764 * @crtc: crtc to get the frame count from 765 * 766 * Gets the frame count on the requested crtc (all asics). 767 * Returns frame count on success, -EINVAL on failure. 768 */ 769 u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc) 770 { 771 int vpos, hpos, stat; 772 u32 count; 773 struct radeon_device *rdev = dev->dev_private; 774 775 if (crtc < 0 || crtc >= rdev->num_crtc) { 776 DRM_ERROR("Invalid crtc %d\n", crtc); 777 return -EINVAL; 778 } 779 780 /* The hw increments its frame counter at start of vsync, not at start 781 * of vblank, as is required by DRM core vblank counter handling. 782 * Cook the hw count here to make it appear to the caller as if it 783 * incremented at start of vblank. We measure distance to start of 784 * vblank in vpos. vpos therefore will be >= 0 between start of vblank 785 * and start of vsync, so vpos >= 0 means to bump the hw frame counter 786 * result by 1 to give the proper appearance to caller. 787 */ 788 if (rdev->mode_info.crtcs[crtc]) { 789 /* Repeat readout if needed to provide stable result if 790 * we cross start of vsync during the queries. 791 */ 792 do { 793 count = radeon_get_vblank_counter(rdev, crtc); 794 /* Ask radeon_get_crtc_scanoutpos to return vpos as 795 * distance to start of vblank, instead of regular 796 * vertical scanout pos. 797 */ 798 stat = radeon_get_crtc_scanoutpos( 799 dev, crtc, GET_DISTANCE_TO_VBLANKSTART, 800 &vpos, &hpos, NULL, NULL, 801 &rdev->mode_info.crtcs[crtc]->base.hwmode); 802 } while (count != radeon_get_vblank_counter(rdev, crtc)); 803 804 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != 805 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) { 806 DRM_DEBUG_VBL("Query failed! stat %d\n", stat); 807 } 808 else { 809 DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n", 810 crtc, vpos); 811 812 /* Bump counter if we are at >= leading edge of vblank, 813 * but before vsync where vpos would turn negative and 814 * the hw counter really increments. 815 */ 816 if (vpos >= 0) 817 count++; 818 } 819 } 820 else { 821 /* Fallback to use value as is. */ 822 count = radeon_get_vblank_counter(rdev, crtc); 823 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n"); 824 } 825 826 return count; 827 } 828 829 /** 830 * radeon_enable_vblank_kms - enable vblank interrupt 831 * 832 * @dev: drm dev pointer 833 * @crtc: crtc to enable vblank interrupt for 834 * 835 * Enable the interrupt on the requested crtc (all asics). 836 * Returns 0 on success, -EINVAL on failure. 837 */ 838 int radeon_enable_vblank_kms(struct drm_device *dev, int crtc) 839 { 840 struct radeon_device *rdev = dev->dev_private; 841 unsigned long irqflags; 842 int r; 843 844 if (crtc < 0 || crtc >= rdev->num_crtc) { 845 DRM_ERROR("Invalid crtc %d\n", crtc); 846 return -EINVAL; 847 } 848 849 spin_lock_irqsave(&rdev->irq.lock, irqflags); 850 rdev->irq.crtc_vblank_int[crtc] = true; 851 r = radeon_irq_set(rdev); 852 spin_unlock_irqrestore(&rdev->irq.lock, irqflags); 853 return r; 854 } 855 856 /** 857 * radeon_disable_vblank_kms - disable vblank interrupt 858 * 859 * @dev: drm dev pointer 860 * @crtc: crtc to disable vblank interrupt for 861 * 862 * Disable the interrupt on the requested crtc (all asics). 863 */ 864 void radeon_disable_vblank_kms(struct drm_device *dev, int crtc) 865 { 866 struct radeon_device *rdev = dev->dev_private; 867 unsigned long irqflags; 868 869 if (crtc < 0 || crtc >= rdev->num_crtc) { 870 DRM_ERROR("Invalid crtc %d\n", crtc); 871 return; 872 } 873 874 spin_lock_irqsave(&rdev->irq.lock, irqflags); 875 rdev->irq.crtc_vblank_int[crtc] = false; 876 radeon_irq_set(rdev); 877 spin_unlock_irqrestore(&rdev->irq.lock, irqflags); 878 } 879 880 /** 881 * radeon_get_vblank_timestamp_kms - get vblank timestamp 882 * 883 * @dev: drm dev pointer 884 * @crtc: crtc to get the timestamp for 885 * @max_error: max error 886 * @vblank_time: time value 887 * @flags: flags passed to the driver 888 * 889 * Gets the timestamp on the requested crtc based on the 890 * scanout position. (all asics). 891 * Returns postive status flags on success, negative error on failure. 892 */ 893 int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc, 894 int *max_error, 895 struct timeval *vblank_time, 896 unsigned flags) 897 { 898 struct drm_crtc *drmcrtc; 899 struct radeon_device *rdev = dev->dev_private; 900 901 if (crtc < 0 || crtc >= dev->num_crtcs) { 902 DRM_ERROR("Invalid crtc %d\n", crtc); 903 return -EINVAL; 904 } 905 906 /* Get associated drm_crtc: */ 907 drmcrtc = &rdev->mode_info.crtcs[crtc]->base; 908 if (!drmcrtc) 909 return -EINVAL; 910 911 /* Helper routine in DRM core does all the work: */ 912 return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc, max_error, 913 vblank_time, flags, 914 &drmcrtc->hwmode); 915 } 916 917 const struct drm_ioctl_desc radeon_ioctls_kms[] = { 918 DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 919 DRM_IOCTL_DEF_DRV(RADEON_CP_START, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 920 DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 921 DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 922 DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, drm_invalid_op, DRM_AUTH), 923 DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, drm_invalid_op, DRM_AUTH), 924 DRM_IOCTL_DEF_DRV(RADEON_RESET, drm_invalid_op, DRM_AUTH), 925 DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, drm_invalid_op, DRM_AUTH), 926 DRM_IOCTL_DEF_DRV(RADEON_SWAP, drm_invalid_op, DRM_AUTH), 927 DRM_IOCTL_DEF_DRV(RADEON_CLEAR, drm_invalid_op, DRM_AUTH), 928 DRM_IOCTL_DEF_DRV(RADEON_VERTEX, drm_invalid_op, DRM_AUTH), 929 DRM_IOCTL_DEF_DRV(RADEON_INDICES, drm_invalid_op, DRM_AUTH), 930 DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, drm_invalid_op, DRM_AUTH), 931 DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, drm_invalid_op, DRM_AUTH), 932 DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 933 DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, drm_invalid_op, DRM_AUTH), 934 DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, drm_invalid_op, DRM_AUTH), 935 DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, drm_invalid_op, DRM_AUTH), 936 DRM_IOCTL_DEF_DRV(RADEON_FLIP, drm_invalid_op, DRM_AUTH), 937 DRM_IOCTL_DEF_DRV(RADEON_ALLOC, drm_invalid_op, DRM_AUTH), 938 DRM_IOCTL_DEF_DRV(RADEON_FREE, drm_invalid_op, DRM_AUTH), 939 DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 940 DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, drm_invalid_op, DRM_AUTH), 941 DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, drm_invalid_op, DRM_AUTH), 942 DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, drm_invalid_op, DRM_AUTH), 943 DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, drm_invalid_op, DRM_AUTH), 944 DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, drm_invalid_op, DRM_AUTH), 945 /* KMS */ 946 DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 947 DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 948 DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 949 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 950 DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH), 951 DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH), 952 DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 953 DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 954 DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 955 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 956 DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 957 DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 958 DRM_IOCTL_DEF_DRV(RADEON_GEM_VA, radeon_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 959 DRM_IOCTL_DEF_DRV(RADEON_GEM_OP, radeon_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 960 DRM_IOCTL_DEF_DRV(RADEON_GEM_USERPTR, radeon_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 961 }; 962 int radeon_max_kms_ioctl = ARRAY_SIZE(radeon_ioctls_kms); 963
Indexes created Tue Oct 21 07:10:13 GMT 2025