radeon_legacy_crtc.c revision 1.1.1.2
1 /* $NetBSD: radeon_legacy_crtc.c,v 1.1.1.2 2018/08/27 01:34:58 riastradh Exp $ */ 2 3 /* 4 * Copyright 2007-8 Advanced Micro Devices, Inc. 5 * Copyright 2008 Red Hat Inc. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 11 * and/or sell copies of the Software, and to permit persons to whom the 12 * Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 23 * OTHER DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: Dave Airlie 26 * Alex Deucher 27 */ 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: radeon_legacy_crtc.c,v 1.1.1.2 2018/08/27 01:34:58 riastradh Exp $"); 30 31 #include <drm/drmP.h> 32 #include <drm/drm_crtc_helper.h> 33 #include <drm/radeon_drm.h> 34 #include <drm/drm_fixed.h> 35 #include "radeon.h" 36 #include "atom.h" 37 38 static void radeon_overscan_setup(struct drm_crtc *crtc, 39 struct drm_display_mode *mode) 40 { 41 struct drm_device *dev = crtc->dev; 42 struct radeon_device *rdev = dev->dev_private; 43 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 44 45 WREG32(RADEON_OVR_CLR + radeon_crtc->crtc_offset, 0); 46 WREG32(RADEON_OVR_WID_LEFT_RIGHT + radeon_crtc->crtc_offset, 0); 47 WREG32(RADEON_OVR_WID_TOP_BOTTOM + radeon_crtc->crtc_offset, 0); 48 } 49 50 static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc, 51 struct drm_display_mode *mode) 52 { 53 struct drm_device *dev = crtc->dev; 54 struct radeon_device *rdev = dev->dev_private; 55 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 56 int xres = mode->hdisplay; 57 int yres = mode->vdisplay; 58 bool hscale = true, vscale = true; 59 int hsync_wid; 60 int vsync_wid; 61 int hsync_start; 62 int blank_width; 63 u32 scale, inc, crtc_more_cntl; 64 u32 fp_horz_stretch, fp_vert_stretch, fp_horz_vert_active; 65 u32 fp_h_sync_strt_wid, fp_crtc_h_total_disp; 66 u32 fp_v_sync_strt_wid, fp_crtc_v_total_disp; 67 struct drm_display_mode *native_mode = &radeon_crtc->native_mode; 68 69 fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH) & 70 (RADEON_VERT_STRETCH_RESERVED | 71 RADEON_VERT_AUTO_RATIO_INC); 72 fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH) & 73 (RADEON_HORZ_FP_LOOP_STRETCH | 74 RADEON_HORZ_AUTO_RATIO_INC); 75 76 crtc_more_cntl = 0; 77 if ((rdev->family == CHIP_RS100) || 78 (rdev->family == CHIP_RS200)) { 79 /* This is to workaround the asic bug for RMX, some versions 80 of BIOS dosen't have this register initialized correctly. */ 81 crtc_more_cntl |= RADEON_CRTC_H_CUTOFF_ACTIVE_EN; 82 } 83 84 85 fp_crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff) 86 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16)); 87 88 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8; 89 if (!hsync_wid) 90 hsync_wid = 1; 91 hsync_start = mode->crtc_hsync_start - 8; 92 93 fp_h_sync_strt_wid = ((hsync_start & 0x1fff) 94 | ((hsync_wid & 0x3f) << 16) 95 | ((mode->flags & DRM_MODE_FLAG_NHSYNC) 96 ? RADEON_CRTC_H_SYNC_POL 97 : 0)); 98 99 fp_crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff) 100 | ((mode->crtc_vdisplay - 1) << 16)); 101 102 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start; 103 if (!vsync_wid) 104 vsync_wid = 1; 105 106 fp_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff) 107 | ((vsync_wid & 0x1f) << 16) 108 | ((mode->flags & DRM_MODE_FLAG_NVSYNC) 109 ? RADEON_CRTC_V_SYNC_POL 110 : 0)); 111 112 fp_horz_vert_active = 0; 113 114 if (native_mode->hdisplay == 0 || 115 native_mode->vdisplay == 0) { 116 hscale = false; 117 vscale = false; 118 } else { 119 if (xres > native_mode->hdisplay) 120 xres = native_mode->hdisplay; 121 if (yres > native_mode->vdisplay) 122 yres = native_mode->vdisplay; 123 124 if (xres == native_mode->hdisplay) 125 hscale = false; 126 if (yres == native_mode->vdisplay) 127 vscale = false; 128 } 129 130 switch (radeon_crtc->rmx_type) { 131 case RMX_FULL: 132 case RMX_ASPECT: 133 if (!hscale) 134 fp_horz_stretch |= ((xres/8-1) << 16); 135 else { 136 inc = (fp_horz_stretch & RADEON_HORZ_AUTO_RATIO_INC) ? 1 : 0; 137 scale = ((xres + inc) * RADEON_HORZ_STRETCH_RATIO_MAX) 138 / native_mode->hdisplay + 1; 139 fp_horz_stretch |= (((scale) & RADEON_HORZ_STRETCH_RATIO_MASK) | 140 RADEON_HORZ_STRETCH_BLEND | 141 RADEON_HORZ_STRETCH_ENABLE | 142 ((native_mode->hdisplay/8-1) << 16)); 143 } 144 145 if (!vscale) 146 fp_vert_stretch |= ((yres-1) << 12); 147 else { 148 inc = (fp_vert_stretch & RADEON_VERT_AUTO_RATIO_INC) ? 1 : 0; 149 scale = ((yres + inc) * RADEON_VERT_STRETCH_RATIO_MAX) 150 / native_mode->vdisplay + 1; 151 fp_vert_stretch |= (((scale) & RADEON_VERT_STRETCH_RATIO_MASK) | 152 RADEON_VERT_STRETCH_ENABLE | 153 RADEON_VERT_STRETCH_BLEND | 154 ((native_mode->vdisplay-1) << 12)); 155 } 156 break; 157 case RMX_CENTER: 158 fp_horz_stretch |= ((xres/8-1) << 16); 159 fp_vert_stretch |= ((yres-1) << 12); 160 161 crtc_more_cntl |= (RADEON_CRTC_AUTO_HORZ_CENTER_EN | 162 RADEON_CRTC_AUTO_VERT_CENTER_EN); 163 164 blank_width = (mode->crtc_hblank_end - mode->crtc_hblank_start) / 8; 165 if (blank_width > 110) 166 blank_width = 110; 167 168 fp_crtc_h_total_disp = (((blank_width) & 0x3ff) 169 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16)); 170 171 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8; 172 if (!hsync_wid) 173 hsync_wid = 1; 174 175 fp_h_sync_strt_wid = ((((mode->crtc_hsync_start - mode->crtc_hblank_start) / 8) & 0x1fff) 176 | ((hsync_wid & 0x3f) << 16) 177 | ((mode->flags & DRM_MODE_FLAG_NHSYNC) 178 ? RADEON_CRTC_H_SYNC_POL 179 : 0)); 180 181 fp_crtc_v_total_disp = (((mode->crtc_vblank_end - mode->crtc_vblank_start) & 0xffff) 182 | ((mode->crtc_vdisplay - 1) << 16)); 183 184 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start; 185 if (!vsync_wid) 186 vsync_wid = 1; 187 188 fp_v_sync_strt_wid = ((((mode->crtc_vsync_start - mode->crtc_vblank_start) & 0xfff) 189 | ((vsync_wid & 0x1f) << 16) 190 | ((mode->flags & DRM_MODE_FLAG_NVSYNC) 191 ? RADEON_CRTC_V_SYNC_POL 192 : 0))); 193 194 fp_horz_vert_active = (((native_mode->vdisplay) & 0xfff) | 195 (((native_mode->hdisplay / 8) & 0x1ff) << 16)); 196 break; 197 case RMX_OFF: 198 default: 199 fp_horz_stretch |= ((xres/8-1) << 16); 200 fp_vert_stretch |= ((yres-1) << 12); 201 break; 202 } 203 204 WREG32(RADEON_FP_HORZ_STRETCH, fp_horz_stretch); 205 WREG32(RADEON_FP_VERT_STRETCH, fp_vert_stretch); 206 WREG32(RADEON_CRTC_MORE_CNTL, crtc_more_cntl); 207 WREG32(RADEON_FP_HORZ_VERT_ACTIVE, fp_horz_vert_active); 208 WREG32(RADEON_FP_H_SYNC_STRT_WID, fp_h_sync_strt_wid); 209 WREG32(RADEON_FP_V_SYNC_STRT_WID, fp_v_sync_strt_wid); 210 WREG32(RADEON_FP_CRTC_H_TOTAL_DISP, fp_crtc_h_total_disp); 211 WREG32(RADEON_FP_CRTC_V_TOTAL_DISP, fp_crtc_v_total_disp); 212 } 213 214 static void radeon_pll_wait_for_read_update_complete(struct drm_device *dev) 215 { 216 struct radeon_device *rdev = dev->dev_private; 217 int i = 0; 218 219 /* FIXME: Certain revisions of R300 can't recover here. Not sure of 220 the cause yet, but this workaround will mask the problem for now. 221 Other chips usually will pass at the very first test, so the 222 workaround shouldn't have any effect on them. */ 223 for (i = 0; 224 (i < 10000 && 225 RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R); 226 i++); 227 } 228 229 static void radeon_pll_write_update(struct drm_device *dev) 230 { 231 struct radeon_device *rdev = dev->dev_private; 232 233 while (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R); 234 235 WREG32_PLL_P(RADEON_PPLL_REF_DIV, 236 RADEON_PPLL_ATOMIC_UPDATE_W, 237 ~(RADEON_PPLL_ATOMIC_UPDATE_W)); 238 } 239 240 static void radeon_pll2_wait_for_read_update_complete(struct drm_device *dev) 241 { 242 struct radeon_device *rdev = dev->dev_private; 243 int i = 0; 244 245 246 /* FIXME: Certain revisions of R300 can't recover here. Not sure of 247 the cause yet, but this workaround will mask the problem for now. 248 Other chips usually will pass at the very first test, so the 249 workaround shouldn't have any effect on them. */ 250 for (i = 0; 251 (i < 10000 && 252 RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R); 253 i++); 254 } 255 256 static void radeon_pll2_write_update(struct drm_device *dev) 257 { 258 struct radeon_device *rdev = dev->dev_private; 259 260 while (RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R); 261 262 WREG32_PLL_P(RADEON_P2PLL_REF_DIV, 263 RADEON_P2PLL_ATOMIC_UPDATE_W, 264 ~(RADEON_P2PLL_ATOMIC_UPDATE_W)); 265 } 266 267 static uint8_t radeon_compute_pll_gain(uint16_t ref_freq, uint16_t ref_div, 268 uint16_t fb_div) 269 { 270 unsigned int vcoFreq; 271 272 if (!ref_div) 273 return 1; 274 275 vcoFreq = ((unsigned)ref_freq * fb_div) / ref_div; 276 277 /* 278 * This is horribly crude: the VCO frequency range is divided into 279 * 3 parts, each part having a fixed PLL gain value. 280 */ 281 if (vcoFreq >= 30000) 282 /* 283 * [300..max] MHz : 7 284 */ 285 return 7; 286 else if (vcoFreq >= 18000) 287 /* 288 * [180..300) MHz : 4 289 */ 290 return 4; 291 else 292 /* 293 * [0..180) MHz : 1 294 */ 295 return 1; 296 } 297 298 static void radeon_crtc_dpms(struct drm_crtc *crtc, int mode) 299 { 300 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 301 struct drm_device *dev = crtc->dev; 302 struct radeon_device *rdev = dev->dev_private; 303 uint32_t crtc_ext_cntl = 0; 304 uint32_t mask; 305 306 if (radeon_crtc->crtc_id) 307 mask = (RADEON_CRTC2_DISP_DIS | 308 RADEON_CRTC2_VSYNC_DIS | 309 RADEON_CRTC2_HSYNC_DIS | 310 RADEON_CRTC2_DISP_REQ_EN_B); 311 else 312 mask = (RADEON_CRTC_DISPLAY_DIS | 313 RADEON_CRTC_VSYNC_DIS | 314 RADEON_CRTC_HSYNC_DIS); 315 316 /* 317 * On all dual CRTC GPUs this bit controls the CRTC of the primary DAC. 318 * Therefore it is set in the DAC DMPS function. 319 * This is different for GPU's with a single CRTC but a primary and a 320 * TV DAC: here it controls the single CRTC no matter where it is 321 * routed. Therefore we set it here. 322 */ 323 if (rdev->flags & RADEON_SINGLE_CRTC) 324 crtc_ext_cntl = RADEON_CRTC_CRT_ON; 325 326 switch (mode) { 327 case DRM_MODE_DPMS_ON: 328 radeon_crtc->enabled = true; 329 /* adjust pm to dpms changes BEFORE enabling crtcs */ 330 radeon_pm_compute_clocks(rdev); 331 if (radeon_crtc->crtc_id) 332 WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~(RADEON_CRTC2_EN | mask)); 333 else { 334 WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN | 335 RADEON_CRTC_DISP_REQ_EN_B)); 336 WREG32_P(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl, ~(mask | crtc_ext_cntl)); 337 } 338 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id); 339 /* Make sure vblank interrupt is still enabled if needed */ 340 radeon_irq_set(rdev); 341 radeon_crtc_load_lut(crtc); 342 break; 343 case DRM_MODE_DPMS_STANDBY: 344 case DRM_MODE_DPMS_SUSPEND: 345 case DRM_MODE_DPMS_OFF: 346 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id); 347 if (radeon_crtc->crtc_id) 348 WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~(RADEON_CRTC2_EN | mask)); 349 else { 350 WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN | 351 RADEON_CRTC_DISP_REQ_EN_B)); 352 WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~(mask | crtc_ext_cntl)); 353 } 354 radeon_crtc->enabled = false; 355 /* adjust pm to dpms changes AFTER disabling crtcs */ 356 radeon_pm_compute_clocks(rdev); 357 break; 358 } 359 } 360 361 int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, 362 struct drm_framebuffer *old_fb) 363 { 364 return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0); 365 } 366 367 int radeon_crtc_set_base_atomic(struct drm_crtc *crtc, 368 struct drm_framebuffer *fb, 369 int x, int y, enum mode_set_atomic state) 370 { 371 return radeon_crtc_do_set_base(crtc, fb, x, y, 1); 372 } 373 374 int radeon_crtc_do_set_base(struct drm_crtc *crtc, 375 struct drm_framebuffer *fb, 376 int x, int y, int atomic) 377 { 378 struct drm_device *dev = crtc->dev; 379 struct radeon_device *rdev = dev->dev_private; 380 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 381 struct radeon_framebuffer *radeon_fb; 382 struct drm_framebuffer *target_fb; 383 struct drm_gem_object *obj; 384 struct radeon_bo *rbo; 385 uint64_t base; 386 uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0; 387 uint32_t crtc_pitch, pitch_pixels; 388 uint32_t tiling_flags; 389 int format; 390 uint32_t gen_cntl_reg, gen_cntl_val; 391 int r; 392 393 DRM_DEBUG_KMS("\n"); 394 /* no fb bound */ 395 if (!atomic && !crtc->primary->fb) { 396 DRM_DEBUG_KMS("No FB bound\n"); 397 return 0; 398 } 399 400 if (atomic) { 401 radeon_fb = to_radeon_framebuffer(fb); 402 target_fb = fb; 403 } 404 else { 405 radeon_fb = to_radeon_framebuffer(crtc->primary->fb); 406 target_fb = crtc->primary->fb; 407 } 408 409 switch (target_fb->bits_per_pixel) { 410 case 8: 411 format = 2; 412 break; 413 case 15: /* 555 */ 414 format = 3; 415 break; 416 case 16: /* 565 */ 417 format = 4; 418 break; 419 case 24: /* RGB */ 420 format = 5; 421 break; 422 case 32: /* xRGB */ 423 format = 6; 424 break; 425 default: 426 return false; 427 } 428 429 /* Pin framebuffer & get tilling informations */ 430 obj = radeon_fb->obj; 431 rbo = gem_to_radeon_bo(obj); 432 retry: 433 r = radeon_bo_reserve(rbo, false); 434 if (unlikely(r != 0)) 435 return r; 436 /* Only 27 bit offset for legacy CRTC */ 437 r = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM, 1 << 27, 438 &base); 439 if (unlikely(r != 0)) { 440 radeon_bo_unreserve(rbo); 441 442 /* On old GPU like RN50 with little vram pining can fails because 443 * current fb is taking all space needed. So instead of unpining 444 * the old buffer after pining the new one, first unpin old one 445 * and then retry pining new one. 446 * 447 * As only master can set mode only master can pin and it is 448 * unlikely the master client will race with itself especialy 449 * on those old gpu with single crtc. 450 * 451 * We don't shutdown the display controller because new buffer 452 * will end up in same spot. 453 */ 454 if (!atomic && fb && fb != crtc->primary->fb) { 455 struct radeon_bo *old_rbo; 456 unsigned long nsize, osize; 457 458 old_rbo = gem_to_radeon_bo(to_radeon_framebuffer(fb)->obj); 459 osize = radeon_bo_size(old_rbo); 460 nsize = radeon_bo_size(rbo); 461 if (nsize <= osize && !radeon_bo_reserve(old_rbo, false)) { 462 radeon_bo_unpin(old_rbo); 463 radeon_bo_unreserve(old_rbo); 464 fb = NULL; 465 goto retry; 466 } 467 } 468 return -EINVAL; 469 } 470 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); 471 radeon_bo_unreserve(rbo); 472 if (tiling_flags & RADEON_TILING_MICRO) 473 DRM_ERROR("trying to scanout microtiled buffer\n"); 474 475 /* if scanout was in GTT this really wouldn't work */ 476 /* crtc offset is from display base addr not FB location */ 477 radeon_crtc->legacy_display_base_addr = rdev->mc.vram_start; 478 479 base -= radeon_crtc->legacy_display_base_addr; 480 481 crtc_offset_cntl = 0; 482 483 pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8); 484 crtc_pitch = (((pitch_pixels * target_fb->bits_per_pixel) + 485 ((target_fb->bits_per_pixel * 8) - 1)) / 486 (target_fb->bits_per_pixel * 8)); 487 crtc_pitch |= crtc_pitch << 16; 488 489 crtc_offset_cntl |= RADEON_CRTC_GUI_TRIG_OFFSET_LEFT_EN; 490 if (tiling_flags & RADEON_TILING_MACRO) { 491 if (ASIC_IS_R300(rdev)) 492 crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN | 493 R300_CRTC_MICRO_TILE_BUFFER_DIS | 494 R300_CRTC_MACRO_TILE_EN); 495 else 496 crtc_offset_cntl |= RADEON_CRTC_TILE_EN; 497 } else { 498 if (ASIC_IS_R300(rdev)) 499 crtc_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN | 500 R300_CRTC_MICRO_TILE_BUFFER_DIS | 501 R300_CRTC_MACRO_TILE_EN); 502 else 503 crtc_offset_cntl &= ~RADEON_CRTC_TILE_EN; 504 } 505 506 if (tiling_flags & RADEON_TILING_MACRO) { 507 if (ASIC_IS_R300(rdev)) { 508 crtc_tile_x0_y0 = x | (y << 16); 509 base &= ~0x7ff; 510 } else { 511 int byteshift = target_fb->bits_per_pixel >> 4; 512 int tile_addr = (((y >> 3) * pitch_pixels + x) >> (8 - byteshift)) << 11; 513 base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8); 514 crtc_offset_cntl |= (y % 16); 515 } 516 } else { 517 int offset = y * pitch_pixels + x; 518 switch (target_fb->bits_per_pixel) { 519 case 8: 520 offset *= 1; 521 break; 522 case 15: 523 case 16: 524 offset *= 2; 525 break; 526 case 24: 527 offset *= 3; 528 break; 529 case 32: 530 offset *= 4; 531 break; 532 default: 533 return false; 534 } 535 base += offset; 536 } 537 538 base &= ~7; 539 540 if (radeon_crtc->crtc_id == 1) 541 gen_cntl_reg = RADEON_CRTC2_GEN_CNTL; 542 else 543 gen_cntl_reg = RADEON_CRTC_GEN_CNTL; 544 545 gen_cntl_val = RREG32(gen_cntl_reg); 546 gen_cntl_val &= ~(0xf << 8); 547 gen_cntl_val |= (format << 8); 548 gen_cntl_val &= ~RADEON_CRTC_VSTAT_MODE_MASK; 549 WREG32(gen_cntl_reg, gen_cntl_val); 550 551 crtc_offset = (u32)base; 552 553 WREG32(RADEON_DISPLAY_BASE_ADDR + radeon_crtc->crtc_offset, radeon_crtc->legacy_display_base_addr); 554 555 if (ASIC_IS_R300(rdev)) { 556 if (radeon_crtc->crtc_id) 557 WREG32(R300_CRTC2_TILE_X0_Y0, crtc_tile_x0_y0); 558 else 559 WREG32(R300_CRTC_TILE_X0_Y0, crtc_tile_x0_y0); 560 } 561 WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, crtc_offset_cntl); 562 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, crtc_offset); 563 WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch); 564 565 if (!atomic && fb && fb != crtc->primary->fb) { 566 radeon_fb = to_radeon_framebuffer(fb); 567 rbo = gem_to_radeon_bo(radeon_fb->obj); 568 r = radeon_bo_reserve(rbo, false); 569 if (unlikely(r != 0)) 570 return r; 571 radeon_bo_unpin(rbo); 572 radeon_bo_unreserve(rbo); 573 } 574 575 /* Bytes per pixel may have changed */ 576 radeon_bandwidth_update(rdev); 577 578 return 0; 579 } 580 581 static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mode *mode) 582 { 583 struct drm_device *dev = crtc->dev; 584 struct radeon_device *rdev = dev->dev_private; 585 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 586 struct drm_encoder *encoder; 587 int format; 588 int hsync_start; 589 int hsync_wid; 590 int vsync_wid; 591 uint32_t crtc_h_total_disp; 592 uint32_t crtc_h_sync_strt_wid; 593 uint32_t crtc_v_total_disp; 594 uint32_t crtc_v_sync_strt_wid; 595 bool is_tv = false; 596 597 DRM_DEBUG_KMS("\n"); 598 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 599 if (encoder->crtc == crtc) { 600 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 601 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { 602 is_tv = true; 603 DRM_INFO("crtc %d is connected to a TV\n", radeon_crtc->crtc_id); 604 break; 605 } 606 } 607 } 608 609 switch (crtc->primary->fb->bits_per_pixel) { 610 case 8: 611 format = 2; 612 break; 613 case 15: /* 555 */ 614 format = 3; 615 break; 616 case 16: /* 565 */ 617 format = 4; 618 break; 619 case 24: /* RGB */ 620 format = 5; 621 break; 622 case 32: /* xRGB */ 623 format = 6; 624 break; 625 default: 626 return false; 627 } 628 629 crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff) 630 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16)); 631 632 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8; 633 if (!hsync_wid) 634 hsync_wid = 1; 635 hsync_start = mode->crtc_hsync_start - 8; 636 637 crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) 638 | ((hsync_wid & 0x3f) << 16) 639 | ((mode->flags & DRM_MODE_FLAG_NHSYNC) 640 ? RADEON_CRTC_H_SYNC_POL 641 : 0)); 642 643 /* This works for double scan mode. */ 644 crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff) 645 | ((mode->crtc_vdisplay - 1) << 16)); 646 647 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start; 648 if (!vsync_wid) 649 vsync_wid = 1; 650 651 crtc_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff) 652 | ((vsync_wid & 0x1f) << 16) 653 | ((mode->flags & DRM_MODE_FLAG_NVSYNC) 654 ? RADEON_CRTC_V_SYNC_POL 655 : 0)); 656 657 if (radeon_crtc->crtc_id) { 658 uint32_t crtc2_gen_cntl; 659 uint32_t disp2_merge_cntl; 660 661 /* if TV DAC is enabled for another crtc and keep it enabled */ 662 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL) & 0x00718080; 663 crtc2_gen_cntl |= ((format << 8) 664 | RADEON_CRTC2_VSYNC_DIS 665 | RADEON_CRTC2_HSYNC_DIS 666 | RADEON_CRTC2_DISP_DIS 667 | RADEON_CRTC2_DISP_REQ_EN_B 668 | ((mode->flags & DRM_MODE_FLAG_DBLSCAN) 669 ? RADEON_CRTC2_DBL_SCAN_EN 670 : 0) 671 | ((mode->flags & DRM_MODE_FLAG_CSYNC) 672 ? RADEON_CRTC2_CSYNC_EN 673 : 0) 674 | ((mode->flags & DRM_MODE_FLAG_INTERLACE) 675 ? RADEON_CRTC2_INTERLACE_EN 676 : 0)); 677 678 /* rs4xx chips seem to like to have the crtc enabled when the timing is set */ 679 if ((rdev->family == CHIP_RS400) || (rdev->family == CHIP_RS480)) 680 crtc2_gen_cntl |= RADEON_CRTC2_EN; 681 682 disp2_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL); 683 disp2_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN; 684 685 WREG32(RADEON_DISP2_MERGE_CNTL, disp2_merge_cntl); 686 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); 687 688 WREG32(RADEON_FP_H2_SYNC_STRT_WID, crtc_h_sync_strt_wid); 689 WREG32(RADEON_FP_V2_SYNC_STRT_WID, crtc_v_sync_strt_wid); 690 } else { 691 uint32_t crtc_gen_cntl; 692 uint32_t crtc_ext_cntl; 693 uint32_t disp_merge_cntl; 694 695 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL) & 0x00718000; 696 crtc_gen_cntl |= (RADEON_CRTC_EXT_DISP_EN 697 | (format << 8) 698 | RADEON_CRTC_DISP_REQ_EN_B 699 | ((mode->flags & DRM_MODE_FLAG_DBLSCAN) 700 ? RADEON_CRTC_DBL_SCAN_EN 701 : 0) 702 | ((mode->flags & DRM_MODE_FLAG_CSYNC) 703 ? RADEON_CRTC_CSYNC_EN 704 : 0) 705 | ((mode->flags & DRM_MODE_FLAG_INTERLACE) 706 ? RADEON_CRTC_INTERLACE_EN 707 : 0)); 708 709 /* rs4xx chips seem to like to have the crtc enabled when the timing is set */ 710 if ((rdev->family == CHIP_RS400) || (rdev->family == CHIP_RS480)) 711 crtc_gen_cntl |= RADEON_CRTC_EN; 712 713 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); 714 crtc_ext_cntl |= (RADEON_XCRT_CNT_EN | 715 RADEON_CRTC_VSYNC_DIS | 716 RADEON_CRTC_HSYNC_DIS | 717 RADEON_CRTC_DISPLAY_DIS); 718 719 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL); 720 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN; 721 722 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl); 723 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl); 724 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); 725 } 726 727 if (is_tv) 728 radeon_legacy_tv_adjust_crtc_reg(encoder, &crtc_h_total_disp, 729 &crtc_h_sync_strt_wid, &crtc_v_total_disp, 730 &crtc_v_sync_strt_wid); 731 732 WREG32(RADEON_CRTC_H_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_h_total_disp); 733 WREG32(RADEON_CRTC_H_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_h_sync_strt_wid); 734 WREG32(RADEON_CRTC_V_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_v_total_disp); 735 WREG32(RADEON_CRTC_V_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_v_sync_strt_wid); 736 737 return true; 738 } 739 740 static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) 741 { 742 struct drm_device *dev = crtc->dev; 743 struct radeon_device *rdev = dev->dev_private; 744 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 745 struct drm_encoder *encoder; 746 uint32_t feedback_div = 0; 747 uint32_t frac_fb_div = 0; 748 uint32_t reference_div = 0; 749 uint32_t post_divider = 0; 750 uint32_t freq = 0; 751 uint8_t pll_gain; 752 bool use_bios_divs = false; 753 /* PLL registers */ 754 uint32_t pll_ref_div = 0; 755 uint32_t pll_fb_post_div = 0; 756 uint32_t htotal_cntl = 0; 757 bool is_tv = false; 758 struct radeon_pll *pll; 759 760 struct { 761 int divider; 762 int bitvalue; 763 } *post_div, post_divs[] = { 764 /* From RAGE 128 VR/RAGE 128 GL Register 765 * Reference Manual (Technical Reference 766 * Manual P/N RRG-G04100-C Rev. 0.04), page 767 * 3-17 (PLL_DIV_[3:0]). 768 */ 769 { 1, 0 }, /* VCLK_SRC */ 770 { 2, 1 }, /* VCLK_SRC/2 */ 771 { 4, 2 }, /* VCLK_SRC/4 */ 772 { 8, 3 }, /* VCLK_SRC/8 */ 773 { 3, 4 }, /* VCLK_SRC/3 */ 774 { 16, 5 }, /* VCLK_SRC/16 */ 775 { 6, 6 }, /* VCLK_SRC/6 */ 776 { 12, 7 }, /* VCLK_SRC/12 */ 777 { 0, 0 } 778 }; 779 780 if (radeon_crtc->crtc_id) 781 pll = &rdev->clock.p2pll; 782 else 783 pll = &rdev->clock.p1pll; 784 785 pll->flags = RADEON_PLL_LEGACY; 786 787 if (mode->clock > 200000) /* range limits??? */ 788 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; 789 else 790 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV; 791 792 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 793 if (encoder->crtc == crtc) { 794 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 795 796 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { 797 is_tv = true; 798 break; 799 } 800 801 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC) 802 pll->flags |= RADEON_PLL_NO_ODD_POST_DIV; 803 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) { 804 if (!rdev->is_atom_bios) { 805 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 806 struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv; 807 if (lvds) { 808 if (lvds->use_bios_dividers) { 809 pll_ref_div = lvds->panel_ref_divider; 810 pll_fb_post_div = (lvds->panel_fb_divider | 811 (lvds->panel_post_divider << 16)); 812 htotal_cntl = 0; 813 use_bios_divs = true; 814 } 815 } 816 } 817 pll->flags |= RADEON_PLL_USE_REF_DIV; 818 } 819 } 820 } 821 822 DRM_DEBUG_KMS("\n"); 823 824 if (!use_bios_divs) { 825 radeon_compute_pll_legacy(pll, mode->clock, 826 &freq, &feedback_div, &frac_fb_div, 827 &reference_div, &post_divider); 828 829 for (post_div = &post_divs[0]; post_div->divider; ++post_div) { 830 if (post_div->divider == post_divider) 831 break; 832 } 833 834 if (!post_div->divider) 835 post_div = &post_divs[0]; 836 837 DRM_DEBUG_KMS("dc=%u, fd=%d, rd=%d, pd=%d\n", 838 (unsigned)freq, 839 feedback_div, 840 reference_div, 841 post_divider); 842 843 pll_ref_div = reference_div; 844 #if defined(__powerpc__) && (0) /* TODO */ 845 /* apparently programming this otherwise causes a hang??? */ 846 if (info->MacModel == RADEON_MAC_IBOOK) 847 pll_fb_post_div = 0x000600ad; 848 else 849 #endif 850 pll_fb_post_div = (feedback_div | (post_div->bitvalue << 16)); 851 852 htotal_cntl = mode->htotal & 0x7; 853 854 } 855 856 pll_gain = radeon_compute_pll_gain(pll->reference_freq, 857 pll_ref_div & 0x3ff, 858 pll_fb_post_div & 0x7ff); 859 860 if (radeon_crtc->crtc_id) { 861 uint32_t pixclks_cntl = ((RREG32_PLL(RADEON_PIXCLKS_CNTL) & 862 ~(RADEON_PIX2CLK_SRC_SEL_MASK)) | 863 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK); 864 865 if (is_tv) { 866 radeon_legacy_tv_adjust_pll2(encoder, &htotal_cntl, 867 &pll_ref_div, &pll_fb_post_div, 868 &pixclks_cntl); 869 } 870 871 WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 872 RADEON_PIX2CLK_SRC_SEL_CPUCLK, 873 ~(RADEON_PIX2CLK_SRC_SEL_MASK)); 874 875 WREG32_PLL_P(RADEON_P2PLL_CNTL, 876 RADEON_P2PLL_RESET 877 | RADEON_P2PLL_ATOMIC_UPDATE_EN 878 | ((uint32_t)pll_gain << RADEON_P2PLL_PVG_SHIFT), 879 ~(RADEON_P2PLL_RESET 880 | RADEON_P2PLL_ATOMIC_UPDATE_EN 881 | RADEON_P2PLL_PVG_MASK)); 882 883 WREG32_PLL_P(RADEON_P2PLL_REF_DIV, 884 pll_ref_div, 885 ~RADEON_P2PLL_REF_DIV_MASK); 886 887 WREG32_PLL_P(RADEON_P2PLL_DIV_0, 888 pll_fb_post_div, 889 ~RADEON_P2PLL_FB0_DIV_MASK); 890 891 WREG32_PLL_P(RADEON_P2PLL_DIV_0, 892 pll_fb_post_div, 893 ~RADEON_P2PLL_POST0_DIV_MASK); 894 895 radeon_pll2_write_update(dev); 896 radeon_pll2_wait_for_read_update_complete(dev); 897 898 WREG32_PLL(RADEON_HTOTAL2_CNTL, htotal_cntl); 899 900 WREG32_PLL_P(RADEON_P2PLL_CNTL, 901 0, 902 ~(RADEON_P2PLL_RESET 903 | RADEON_P2PLL_SLEEP 904 | RADEON_P2PLL_ATOMIC_UPDATE_EN)); 905 906 DRM_DEBUG_KMS("Wrote2: 0x%08x 0x%08x 0x%08x (0x%08x)\n", 907 (unsigned)pll_ref_div, 908 (unsigned)pll_fb_post_div, 909 (unsigned)htotal_cntl, 910 RREG32_PLL(RADEON_P2PLL_CNTL)); 911 DRM_DEBUG_KMS("Wrote2: rd=%u, fd=%u, pd=%u\n", 912 (unsigned)pll_ref_div & RADEON_P2PLL_REF_DIV_MASK, 913 (unsigned)pll_fb_post_div & RADEON_P2PLL_FB0_DIV_MASK, 914 (unsigned)((pll_fb_post_div & 915 RADEON_P2PLL_POST0_DIV_MASK) >> 16)); 916 917 mdelay(50); /* Let the clock to lock */ 918 919 WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 920 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK, 921 ~(RADEON_PIX2CLK_SRC_SEL_MASK)); 922 923 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl); 924 } else { 925 uint32_t pixclks_cntl; 926 927 928 if (is_tv) { 929 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL); 930 radeon_legacy_tv_adjust_pll1(encoder, &htotal_cntl, &pll_ref_div, 931 &pll_fb_post_div, &pixclks_cntl); 932 } 933 934 if (rdev->flags & RADEON_IS_MOBILITY) { 935 /* A temporal workaround for the occasional blanking on certain laptop panels. 936 This appears to related to the PLL divider registers (fail to lock?). 937 It occurs even when all dividers are the same with their old settings. 938 In this case we really don't need to fiddle with PLL registers. 939 By doing this we can avoid the blanking problem with some panels. 940 */ 941 if ((pll_ref_div == (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) && 942 (pll_fb_post_div == (RREG32_PLL(RADEON_PPLL_DIV_3) & 943 (RADEON_PPLL_POST3_DIV_MASK | RADEON_PPLL_FB3_DIV_MASK)))) { 944 WREG32_P(RADEON_CLOCK_CNTL_INDEX, 945 RADEON_PLL_DIV_SEL, 946 ~(RADEON_PLL_DIV_SEL)); 947 r100_pll_errata_after_index(rdev); 948 return; 949 } 950 } 951 952 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL, 953 RADEON_VCLK_SRC_SEL_CPUCLK, 954 ~(RADEON_VCLK_SRC_SEL_MASK)); 955 WREG32_PLL_P(RADEON_PPLL_CNTL, 956 RADEON_PPLL_RESET 957 | RADEON_PPLL_ATOMIC_UPDATE_EN 958 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN 959 | ((uint32_t)pll_gain << RADEON_PPLL_PVG_SHIFT), 960 ~(RADEON_PPLL_RESET 961 | RADEON_PPLL_ATOMIC_UPDATE_EN 962 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN 963 | RADEON_PPLL_PVG_MASK)); 964 965 WREG32_P(RADEON_CLOCK_CNTL_INDEX, 966 RADEON_PLL_DIV_SEL, 967 ~(RADEON_PLL_DIV_SEL)); 968 r100_pll_errata_after_index(rdev); 969 970 if (ASIC_IS_R300(rdev) || 971 (rdev->family == CHIP_RS300) || 972 (rdev->family == CHIP_RS400) || 973 (rdev->family == CHIP_RS480)) { 974 if (pll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) { 975 /* When restoring console mode, use saved PPLL_REF_DIV 976 * setting. 977 */ 978 WREG32_PLL_P(RADEON_PPLL_REF_DIV, 979 pll_ref_div, 980 0); 981 } else { 982 /* R300 uses ref_div_acc field as real ref divider */ 983 WREG32_PLL_P(RADEON_PPLL_REF_DIV, 984 (pll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT), 985 ~R300_PPLL_REF_DIV_ACC_MASK); 986 } 987 } else 988 WREG32_PLL_P(RADEON_PPLL_REF_DIV, 989 pll_ref_div, 990 ~RADEON_PPLL_REF_DIV_MASK); 991 992 WREG32_PLL_P(RADEON_PPLL_DIV_3, 993 pll_fb_post_div, 994 ~RADEON_PPLL_FB3_DIV_MASK); 995 996 WREG32_PLL_P(RADEON_PPLL_DIV_3, 997 pll_fb_post_div, 998 ~RADEON_PPLL_POST3_DIV_MASK); 999 1000 radeon_pll_write_update(dev); 1001 radeon_pll_wait_for_read_update_complete(dev); 1002 1003 WREG32_PLL(RADEON_HTOTAL_CNTL, htotal_cntl); 1004 1005 WREG32_PLL_P(RADEON_PPLL_CNTL, 1006 0, 1007 ~(RADEON_PPLL_RESET 1008 | RADEON_PPLL_SLEEP 1009 | RADEON_PPLL_ATOMIC_UPDATE_EN 1010 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN)); 1011 1012 DRM_DEBUG_KMS("Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n", 1013 pll_ref_div, 1014 pll_fb_post_div, 1015 (unsigned)htotal_cntl, 1016 RREG32_PLL(RADEON_PPLL_CNTL)); 1017 DRM_DEBUG_KMS("Wrote: rd=%d, fd=%d, pd=%d\n", 1018 pll_ref_div & RADEON_PPLL_REF_DIV_MASK, 1019 pll_fb_post_div & RADEON_PPLL_FB3_DIV_MASK, 1020 (pll_fb_post_div & RADEON_PPLL_POST3_DIV_MASK) >> 16); 1021 1022 mdelay(50); /* Let the clock to lock */ 1023 1024 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL, 1025 RADEON_VCLK_SRC_SEL_PPLLCLK, 1026 ~(RADEON_VCLK_SRC_SEL_MASK)); 1027 1028 if (is_tv) 1029 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl); 1030 } 1031 } 1032 1033 static bool radeon_crtc_mode_fixup(struct drm_crtc *crtc, 1034 const struct drm_display_mode *mode, 1035 struct drm_display_mode *adjusted_mode) 1036 { 1037 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) 1038 return false; 1039 return true; 1040 } 1041 1042 static int radeon_crtc_mode_set(struct drm_crtc *crtc, 1043 struct drm_display_mode *mode, 1044 struct drm_display_mode *adjusted_mode, 1045 int x, int y, struct drm_framebuffer *old_fb) 1046 { 1047 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1048 1049 /* TODO TV */ 1050 radeon_crtc_set_base(crtc, x, y, old_fb); 1051 radeon_set_crtc_timing(crtc, adjusted_mode); 1052 radeon_set_pll(crtc, adjusted_mode); 1053 radeon_overscan_setup(crtc, adjusted_mode); 1054 if (radeon_crtc->crtc_id == 0) { 1055 radeon_legacy_rmx_mode_set(crtc, adjusted_mode); 1056 } else { 1057 if (radeon_crtc->rmx_type != RMX_OFF) { 1058 /* FIXME: only first crtc has rmx what should we 1059 * do ? 1060 */ 1061 DRM_ERROR("Mode need scaling but only first crtc can do that.\n"); 1062 } 1063 } 1064 radeon_cursor_reset(crtc); 1065 return 0; 1066 } 1067 1068 static void radeon_crtc_prepare(struct drm_crtc *crtc) 1069 { 1070 struct drm_device *dev = crtc->dev; 1071 struct drm_crtc *crtci; 1072 1073 /* 1074 * The hardware wedges sometimes if you reconfigure one CRTC 1075 * whilst another is running (see fdo bug #24611). 1076 */ 1077 list_for_each_entry(crtci, &dev->mode_config.crtc_list, head) 1078 radeon_crtc_dpms(crtci, DRM_MODE_DPMS_OFF); 1079 } 1080 1081 static void radeon_crtc_commit(struct drm_crtc *crtc) 1082 { 1083 struct drm_device *dev = crtc->dev; 1084 struct drm_crtc *crtci; 1085 1086 /* 1087 * Reenable the CRTCs that should be running. 1088 */ 1089 list_for_each_entry(crtci, &dev->mode_config.crtc_list, head) { 1090 if (crtci->enabled) 1091 radeon_crtc_dpms(crtci, DRM_MODE_DPMS_ON); 1092 } 1093 } 1094 1095 static void radeon_crtc_disable(struct drm_crtc *crtc) 1096 { 1097 radeon_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 1098 if (crtc->primary->fb) { 1099 int r; 1100 struct radeon_framebuffer *radeon_fb; 1101 struct radeon_bo *rbo; 1102 1103 radeon_fb = to_radeon_framebuffer(crtc->primary->fb); 1104 rbo = gem_to_radeon_bo(radeon_fb->obj); 1105 r = radeon_bo_reserve(rbo, false); 1106 if (unlikely(r)) 1107 DRM_ERROR("failed to reserve rbo before unpin\n"); 1108 else { 1109 radeon_bo_unpin(rbo); 1110 radeon_bo_unreserve(rbo); 1111 } 1112 } 1113 } 1114 1115 static const struct drm_crtc_helper_funcs legacy_helper_funcs = { 1116 .dpms = radeon_crtc_dpms, 1117 .mode_fixup = radeon_crtc_mode_fixup, 1118 .mode_set = radeon_crtc_mode_set, 1119 .mode_set_base = radeon_crtc_set_base, 1120 .mode_set_base_atomic = radeon_crtc_set_base_atomic, 1121 .prepare = radeon_crtc_prepare, 1122 .commit = radeon_crtc_commit, 1123 .load_lut = radeon_crtc_load_lut, 1124 .disable = radeon_crtc_disable 1125 }; 1126 1127 1128 void radeon_legacy_init_crtc(struct drm_device *dev, 1129 struct radeon_crtc *radeon_crtc) 1130 { 1131 if (radeon_crtc->crtc_id == 1) 1132 radeon_crtc->crtc_offset = RADEON_CRTC2_H_TOTAL_DISP - RADEON_CRTC_H_TOTAL_DISP; 1133 drm_crtc_helper_add(&radeon_crtc->base, &legacy_helper_funcs); 1134 } 1135
Indexes created Tue Oct 21 12:09:54 GMT 2025