radeon_legacy_crtc.c revision 1.1.1.3
1 /* $NetBSD: radeon_legacy_crtc.c,v 1.1.1.3 2021/12/18 20:15:49 riastradh Exp $ */ 2 3 /* 4 * Copyright 2007-8 Advanced Micro Devices, Inc. 5 * Copyright 2008 Red Hat Inc. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 11 * and/or sell copies of the Software, and to permit persons to whom the 12 * Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 23 * OTHER DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: Dave Airlie 26 * Alex Deucher 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: radeon_legacy_crtc.c,v 1.1.1.3 2021/12/18 20:15:49 riastradh Exp $"); 31 32 #include <drm/drm_crtc_helper.h> 33 #include <drm/drm_fb_helper.h> 34 #include <drm/drm_fixed.h> 35 #include <drm/drm_fourcc.h> 36 #include <drm/drm_vblank.h> 37 #include <drm/radeon_drm.h> 38 39 #include "atom.h" 40 #include "radeon.h" 41 42 static void radeon_overscan_setup(struct drm_crtc *crtc, 43 struct drm_display_mode *mode) 44 { 45 struct drm_device *dev = crtc->dev; 46 struct radeon_device *rdev = dev->dev_private; 47 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 48 49 WREG32(RADEON_OVR_CLR + radeon_crtc->crtc_offset, 0); 50 WREG32(RADEON_OVR_WID_LEFT_RIGHT + radeon_crtc->crtc_offset, 0); 51 WREG32(RADEON_OVR_WID_TOP_BOTTOM + radeon_crtc->crtc_offset, 0); 52 } 53 54 static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc, 55 struct drm_display_mode *mode) 56 { 57 struct drm_device *dev = crtc->dev; 58 struct radeon_device *rdev = dev->dev_private; 59 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 60 int xres = mode->hdisplay; 61 int yres = mode->vdisplay; 62 bool hscale = true, vscale = true; 63 int hsync_wid; 64 int vsync_wid; 65 int hsync_start; 66 int blank_width; 67 u32 scale, inc, crtc_more_cntl; 68 u32 fp_horz_stretch, fp_vert_stretch, fp_horz_vert_active; 69 u32 fp_h_sync_strt_wid, fp_crtc_h_total_disp; 70 u32 fp_v_sync_strt_wid, fp_crtc_v_total_disp; 71 struct drm_display_mode *native_mode = &radeon_crtc->native_mode; 72 73 fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH) & 74 (RADEON_VERT_STRETCH_RESERVED | 75 RADEON_VERT_AUTO_RATIO_INC); 76 fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH) & 77 (RADEON_HORZ_FP_LOOP_STRETCH | 78 RADEON_HORZ_AUTO_RATIO_INC); 79 80 crtc_more_cntl = 0; 81 if ((rdev->family == CHIP_RS100) || 82 (rdev->family == CHIP_RS200)) { 83 /* This is to workaround the asic bug for RMX, some versions 84 of BIOS dosen't have this register initialized correctly. */ 85 crtc_more_cntl |= RADEON_CRTC_H_CUTOFF_ACTIVE_EN; 86 } 87 88 89 fp_crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff) 90 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16)); 91 92 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8; 93 if (!hsync_wid) 94 hsync_wid = 1; 95 hsync_start = mode->crtc_hsync_start - 8; 96 97 fp_h_sync_strt_wid = ((hsync_start & 0x1fff) 98 | ((hsync_wid & 0x3f) << 16) 99 | ((mode->flags & DRM_MODE_FLAG_NHSYNC) 100 ? RADEON_CRTC_H_SYNC_POL 101 : 0)); 102 103 fp_crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff) 104 | ((mode->crtc_vdisplay - 1) << 16)); 105 106 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start; 107 if (!vsync_wid) 108 vsync_wid = 1; 109 110 fp_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff) 111 | ((vsync_wid & 0x1f) << 16) 112 | ((mode->flags & DRM_MODE_FLAG_NVSYNC) 113 ? RADEON_CRTC_V_SYNC_POL 114 : 0)); 115 116 fp_horz_vert_active = 0; 117 118 if (native_mode->hdisplay == 0 || 119 native_mode->vdisplay == 0) { 120 hscale = false; 121 vscale = false; 122 } else { 123 if (xres > native_mode->hdisplay) 124 xres = native_mode->hdisplay; 125 if (yres > native_mode->vdisplay) 126 yres = native_mode->vdisplay; 127 128 if (xres == native_mode->hdisplay) 129 hscale = false; 130 if (yres == native_mode->vdisplay) 131 vscale = false; 132 } 133 134 switch (radeon_crtc->rmx_type) { 135 case RMX_FULL: 136 case RMX_ASPECT: 137 if (!hscale) 138 fp_horz_stretch |= ((xres/8-1) << 16); 139 else { 140 inc = (fp_horz_stretch & RADEON_HORZ_AUTO_RATIO_INC) ? 1 : 0; 141 scale = ((xres + inc) * RADEON_HORZ_STRETCH_RATIO_MAX) 142 / native_mode->hdisplay + 1; 143 fp_horz_stretch |= (((scale) & RADEON_HORZ_STRETCH_RATIO_MASK) | 144 RADEON_HORZ_STRETCH_BLEND | 145 RADEON_HORZ_STRETCH_ENABLE | 146 ((native_mode->hdisplay/8-1) << 16)); 147 } 148 149 if (!vscale) 150 fp_vert_stretch |= ((yres-1) << 12); 151 else { 152 inc = (fp_vert_stretch & RADEON_VERT_AUTO_RATIO_INC) ? 1 : 0; 153 scale = ((yres + inc) * RADEON_VERT_STRETCH_RATIO_MAX) 154 / native_mode->vdisplay + 1; 155 fp_vert_stretch |= (((scale) & RADEON_VERT_STRETCH_RATIO_MASK) | 156 RADEON_VERT_STRETCH_ENABLE | 157 RADEON_VERT_STRETCH_BLEND | 158 ((native_mode->vdisplay-1) << 12)); 159 } 160 break; 161 case RMX_CENTER: 162 fp_horz_stretch |= ((xres/8-1) << 16); 163 fp_vert_stretch |= ((yres-1) << 12); 164 165 crtc_more_cntl |= (RADEON_CRTC_AUTO_HORZ_CENTER_EN | 166 RADEON_CRTC_AUTO_VERT_CENTER_EN); 167 168 blank_width = (mode->crtc_hblank_end - mode->crtc_hblank_start) / 8; 169 if (blank_width > 110) 170 blank_width = 110; 171 172 fp_crtc_h_total_disp = (((blank_width) & 0x3ff) 173 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16)); 174 175 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8; 176 if (!hsync_wid) 177 hsync_wid = 1; 178 179 fp_h_sync_strt_wid = ((((mode->crtc_hsync_start - mode->crtc_hblank_start) / 8) & 0x1fff) 180 | ((hsync_wid & 0x3f) << 16) 181 | ((mode->flags & DRM_MODE_FLAG_NHSYNC) 182 ? RADEON_CRTC_H_SYNC_POL 183 : 0)); 184 185 fp_crtc_v_total_disp = (((mode->crtc_vblank_end - mode->crtc_vblank_start) & 0xffff) 186 | ((mode->crtc_vdisplay - 1) << 16)); 187 188 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start; 189 if (!vsync_wid) 190 vsync_wid = 1; 191 192 fp_v_sync_strt_wid = ((((mode->crtc_vsync_start - mode->crtc_vblank_start) & 0xfff) 193 | ((vsync_wid & 0x1f) << 16) 194 | ((mode->flags & DRM_MODE_FLAG_NVSYNC) 195 ? RADEON_CRTC_V_SYNC_POL 196 : 0))); 197 198 fp_horz_vert_active = (((native_mode->vdisplay) & 0xfff) | 199 (((native_mode->hdisplay / 8) & 0x1ff) << 16)); 200 break; 201 case RMX_OFF: 202 default: 203 fp_horz_stretch |= ((xres/8-1) << 16); 204 fp_vert_stretch |= ((yres-1) << 12); 205 break; 206 } 207 208 WREG32(RADEON_FP_HORZ_STRETCH, fp_horz_stretch); 209 WREG32(RADEON_FP_VERT_STRETCH, fp_vert_stretch); 210 WREG32(RADEON_CRTC_MORE_CNTL, crtc_more_cntl); 211 WREG32(RADEON_FP_HORZ_VERT_ACTIVE, fp_horz_vert_active); 212 WREG32(RADEON_FP_H_SYNC_STRT_WID, fp_h_sync_strt_wid); 213 WREG32(RADEON_FP_V_SYNC_STRT_WID, fp_v_sync_strt_wid); 214 WREG32(RADEON_FP_CRTC_H_TOTAL_DISP, fp_crtc_h_total_disp); 215 WREG32(RADEON_FP_CRTC_V_TOTAL_DISP, fp_crtc_v_total_disp); 216 } 217 218 static void radeon_pll_wait_for_read_update_complete(struct drm_device *dev) 219 { 220 struct radeon_device *rdev = dev->dev_private; 221 int i = 0; 222 223 /* FIXME: Certain revisions of R300 can't recover here. Not sure of 224 the cause yet, but this workaround will mask the problem for now. 225 Other chips usually will pass at the very first test, so the 226 workaround shouldn't have any effect on them. */ 227 for (i = 0; 228 (i < 10000 && 229 RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R); 230 i++); 231 } 232 233 static void radeon_pll_write_update(struct drm_device *dev) 234 { 235 struct radeon_device *rdev = dev->dev_private; 236 237 while (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R); 238 239 WREG32_PLL_P(RADEON_PPLL_REF_DIV, 240 RADEON_PPLL_ATOMIC_UPDATE_W, 241 ~(RADEON_PPLL_ATOMIC_UPDATE_W)); 242 } 243 244 static void radeon_pll2_wait_for_read_update_complete(struct drm_device *dev) 245 { 246 struct radeon_device *rdev = dev->dev_private; 247 int i = 0; 248 249 250 /* FIXME: Certain revisions of R300 can't recover here. Not sure of 251 the cause yet, but this workaround will mask the problem for now. 252 Other chips usually will pass at the very first test, so the 253 workaround shouldn't have any effect on them. */ 254 for (i = 0; 255 (i < 10000 && 256 RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R); 257 i++); 258 } 259 260 static void radeon_pll2_write_update(struct drm_device *dev) 261 { 262 struct radeon_device *rdev = dev->dev_private; 263 264 while (RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R); 265 266 WREG32_PLL_P(RADEON_P2PLL_REF_DIV, 267 RADEON_P2PLL_ATOMIC_UPDATE_W, 268 ~(RADEON_P2PLL_ATOMIC_UPDATE_W)); 269 } 270 271 static uint8_t radeon_compute_pll_gain(uint16_t ref_freq, uint16_t ref_div, 272 uint16_t fb_div) 273 { 274 unsigned int vcoFreq; 275 276 if (!ref_div) 277 return 1; 278 279 vcoFreq = ((unsigned)ref_freq * fb_div) / ref_div; 280 281 /* 282 * This is horribly crude: the VCO frequency range is divided into 283 * 3 parts, each part having a fixed PLL gain value. 284 */ 285 if (vcoFreq >= 30000) 286 /* 287 * [300..max] MHz : 7 288 */ 289 return 7; 290 else if (vcoFreq >= 18000) 291 /* 292 * [180..300) MHz : 4 293 */ 294 return 4; 295 else 296 /* 297 * [0..180) MHz : 1 298 */ 299 return 1; 300 } 301 302 static void radeon_crtc_dpms(struct drm_crtc *crtc, int mode) 303 { 304 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 305 struct drm_device *dev = crtc->dev; 306 struct radeon_device *rdev = dev->dev_private; 307 uint32_t crtc_ext_cntl = 0; 308 uint32_t mask; 309 310 if (radeon_crtc->crtc_id) 311 mask = (RADEON_CRTC2_DISP_DIS | 312 RADEON_CRTC2_VSYNC_DIS | 313 RADEON_CRTC2_HSYNC_DIS | 314 RADEON_CRTC2_DISP_REQ_EN_B); 315 else 316 mask = (RADEON_CRTC_DISPLAY_DIS | 317 RADEON_CRTC_VSYNC_DIS | 318 RADEON_CRTC_HSYNC_DIS); 319 320 /* 321 * On all dual CRTC GPUs this bit controls the CRTC of the primary DAC. 322 * Therefore it is set in the DAC DMPS function. 323 * This is different for GPU's with a single CRTC but a primary and a 324 * TV DAC: here it controls the single CRTC no matter where it is 325 * routed. Therefore we set it here. 326 */ 327 if (rdev->flags & RADEON_SINGLE_CRTC) 328 crtc_ext_cntl = RADEON_CRTC_CRT_ON; 329 330 switch (mode) { 331 case DRM_MODE_DPMS_ON: 332 radeon_crtc->enabled = true; 333 /* adjust pm to dpms changes BEFORE enabling crtcs */ 334 radeon_pm_compute_clocks(rdev); 335 if (radeon_crtc->crtc_id) 336 WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~(RADEON_CRTC2_EN | mask)); 337 else { 338 WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN | 339 RADEON_CRTC_DISP_REQ_EN_B)); 340 WREG32_P(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl, ~(mask | crtc_ext_cntl)); 341 } 342 if (dev->num_crtcs > radeon_crtc->crtc_id) 343 drm_crtc_vblank_on(crtc); 344 radeon_crtc_load_lut(crtc); 345 break; 346 case DRM_MODE_DPMS_STANDBY: 347 case DRM_MODE_DPMS_SUSPEND: 348 case DRM_MODE_DPMS_OFF: 349 if (dev->num_crtcs > radeon_crtc->crtc_id) 350 drm_crtc_vblank_off(crtc); 351 if (radeon_crtc->crtc_id) 352 WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~(RADEON_CRTC2_EN | mask)); 353 else { 354 WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN | 355 RADEON_CRTC_DISP_REQ_EN_B)); 356 WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~(mask | crtc_ext_cntl)); 357 } 358 radeon_crtc->enabled = false; 359 /* adjust pm to dpms changes AFTER disabling crtcs */ 360 radeon_pm_compute_clocks(rdev); 361 break; 362 } 363 } 364 365 int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, 366 struct drm_framebuffer *old_fb) 367 { 368 return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0); 369 } 370 371 int radeon_crtc_set_base_atomic(struct drm_crtc *crtc, 372 struct drm_framebuffer *fb, 373 int x, int y, enum mode_set_atomic state) 374 { 375 return radeon_crtc_do_set_base(crtc, fb, x, y, 1); 376 } 377 378 int radeon_crtc_do_set_base(struct drm_crtc *crtc, 379 struct drm_framebuffer *fb, 380 int x, int y, int atomic) 381 { 382 struct drm_device *dev = crtc->dev; 383 struct radeon_device *rdev = dev->dev_private; 384 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 385 struct drm_framebuffer *target_fb; 386 struct drm_gem_object *obj; 387 struct radeon_bo *rbo; 388 uint64_t base; 389 uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0; 390 uint32_t crtc_pitch, pitch_pixels; 391 uint32_t tiling_flags; 392 int format; 393 uint32_t gen_cntl_reg, gen_cntl_val; 394 int r; 395 396 DRM_DEBUG_KMS("\n"); 397 /* no fb bound */ 398 if (!atomic && !crtc->primary->fb) { 399 DRM_DEBUG_KMS("No FB bound\n"); 400 return 0; 401 } 402 403 if (atomic) 404 target_fb = fb; 405 else 406 target_fb = crtc->primary->fb; 407 408 switch (target_fb->format->cpp[0] * 8) { 409 case 8: 410 format = 2; 411 break; 412 case 15: /* 555 */ 413 format = 3; 414 break; 415 case 16: /* 565 */ 416 format = 4; 417 break; 418 case 24: /* RGB */ 419 format = 5; 420 break; 421 case 32: /* xRGB */ 422 format = 6; 423 break; 424 default: 425 return false; 426 } 427 428 /* Pin framebuffer & get tilling informations */ 429 obj = target_fb->obj[0]; 430 rbo = gem_to_radeon_bo(obj); 431 retry: 432 r = radeon_bo_reserve(rbo, false); 433 if (unlikely(r != 0)) 434 return r; 435 /* Only 27 bit offset for legacy CRTC */ 436 r = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM, 1 << 27, 437 &base); 438 if (unlikely(r != 0)) { 439 radeon_bo_unreserve(rbo); 440 441 /* On old GPU like RN50 with little vram pining can fails because 442 * current fb is taking all space needed. So instead of unpining 443 * the old buffer after pining the new one, first unpin old one 444 * and then retry pining new one. 445 * 446 * As only master can set mode only master can pin and it is 447 * unlikely the master client will race with itself especialy 448 * on those old gpu with single crtc. 449 * 450 * We don't shutdown the display controller because new buffer 451 * will end up in same spot. 452 */ 453 if (!atomic && fb && fb != crtc->primary->fb) { 454 struct radeon_bo *old_rbo; 455 unsigned long nsize, osize; 456 457 old_rbo = gem_to_radeon_bo(fb->obj[0]); 458 osize = radeon_bo_size(old_rbo); 459 nsize = radeon_bo_size(rbo); 460 if (nsize <= osize && !radeon_bo_reserve(old_rbo, false)) { 461 radeon_bo_unpin(old_rbo); 462 radeon_bo_unreserve(old_rbo); 463 fb = NULL; 464 goto retry; 465 } 466 } 467 return -EINVAL; 468 } 469 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); 470 radeon_bo_unreserve(rbo); 471 if (tiling_flags & RADEON_TILING_MICRO) 472 DRM_ERROR("trying to scanout microtiled buffer\n"); 473 474 /* if scanout was in GTT this really wouldn't work */ 475 /* crtc offset is from display base addr not FB location */ 476 radeon_crtc->legacy_display_base_addr = rdev->mc.vram_start; 477 478 base -= radeon_crtc->legacy_display_base_addr; 479 480 crtc_offset_cntl = 0; 481 482 pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0]; 483 crtc_pitch = DIV_ROUND_UP(pitch_pixels * target_fb->format->cpp[0] * 8, 484 target_fb->format->cpp[0] * 8 * 8); 485 crtc_pitch |= crtc_pitch << 16; 486 487 crtc_offset_cntl |= RADEON_CRTC_GUI_TRIG_OFFSET_LEFT_EN; 488 if (tiling_flags & RADEON_TILING_MACRO) { 489 if (ASIC_IS_R300(rdev)) 490 crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN | 491 R300_CRTC_MICRO_TILE_BUFFER_DIS | 492 R300_CRTC_MACRO_TILE_EN); 493 else 494 crtc_offset_cntl |= RADEON_CRTC_TILE_EN; 495 } else { 496 if (ASIC_IS_R300(rdev)) 497 crtc_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN | 498 R300_CRTC_MICRO_TILE_BUFFER_DIS | 499 R300_CRTC_MACRO_TILE_EN); 500 else 501 crtc_offset_cntl &= ~RADEON_CRTC_TILE_EN; 502 } 503 504 if (tiling_flags & RADEON_TILING_MACRO) { 505 if (ASIC_IS_R300(rdev)) { 506 crtc_tile_x0_y0 = x | (y << 16); 507 base &= ~0x7ff; 508 } else { 509 int byteshift = target_fb->format->cpp[0] * 8 >> 4; 510 int tile_addr = (((y >> 3) * pitch_pixels + x) >> (8 - byteshift)) << 11; 511 base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8); 512 crtc_offset_cntl |= (y % 16); 513 } 514 } else { 515 int offset = y * pitch_pixels + x; 516 switch (target_fb->format->cpp[0] * 8) { 517 case 8: 518 offset *= 1; 519 break; 520 case 15: 521 case 16: 522 offset *= 2; 523 break; 524 case 24: 525 offset *= 3; 526 break; 527 case 32: 528 offset *= 4; 529 break; 530 default: 531 return false; 532 } 533 base += offset; 534 } 535 536 base &= ~7; 537 538 if (radeon_crtc->crtc_id == 1) 539 gen_cntl_reg = RADEON_CRTC2_GEN_CNTL; 540 else 541 gen_cntl_reg = RADEON_CRTC_GEN_CNTL; 542 543 gen_cntl_val = RREG32(gen_cntl_reg); 544 gen_cntl_val &= ~(0xf << 8); 545 gen_cntl_val |= (format << 8); 546 gen_cntl_val &= ~RADEON_CRTC_VSTAT_MODE_MASK; 547 WREG32(gen_cntl_reg, gen_cntl_val); 548 549 crtc_offset = (u32)base; 550 551 WREG32(RADEON_DISPLAY_BASE_ADDR + radeon_crtc->crtc_offset, radeon_crtc->legacy_display_base_addr); 552 553 if (ASIC_IS_R300(rdev)) { 554 if (radeon_crtc->crtc_id) 555 WREG32(R300_CRTC2_TILE_X0_Y0, crtc_tile_x0_y0); 556 else 557 WREG32(R300_CRTC_TILE_X0_Y0, crtc_tile_x0_y0); 558 } 559 WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, crtc_offset_cntl); 560 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, crtc_offset); 561 WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch); 562 563 if (!atomic && fb && fb != crtc->primary->fb) { 564 rbo = gem_to_radeon_bo(fb->obj[0]); 565 r = radeon_bo_reserve(rbo, false); 566 if (unlikely(r != 0)) 567 return r; 568 radeon_bo_unpin(rbo); 569 radeon_bo_unreserve(rbo); 570 } 571 572 /* Bytes per pixel may have changed */ 573 radeon_bandwidth_update(rdev); 574 575 return 0; 576 } 577 578 static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mode *mode) 579 { 580 struct drm_device *dev = crtc->dev; 581 struct radeon_device *rdev = dev->dev_private; 582 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 583 const struct drm_framebuffer *fb = crtc->primary->fb; 584 struct drm_encoder *encoder; 585 int format; 586 int hsync_start; 587 int hsync_wid; 588 int vsync_wid; 589 uint32_t crtc_h_total_disp; 590 uint32_t crtc_h_sync_strt_wid; 591 uint32_t crtc_v_total_disp; 592 uint32_t crtc_v_sync_strt_wid; 593 bool is_tv = false; 594 595 DRM_DEBUG_KMS("\n"); 596 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 597 if (encoder->crtc == crtc) { 598 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 599 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { 600 is_tv = true; 601 DRM_INFO("crtc %d is connected to a TV\n", radeon_crtc->crtc_id); 602 break; 603 } 604 } 605 } 606 607 switch (fb->format->cpp[0] * 8) { 608 case 8: 609 format = 2; 610 break; 611 case 15: /* 555 */ 612 format = 3; 613 break; 614 case 16: /* 565 */ 615 format = 4; 616 break; 617 case 24: /* RGB */ 618 format = 5; 619 break; 620 case 32: /* xRGB */ 621 format = 6; 622 break; 623 default: 624 return false; 625 } 626 627 crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff) 628 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16)); 629 630 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8; 631 if (!hsync_wid) 632 hsync_wid = 1; 633 hsync_start = mode->crtc_hsync_start - 8; 634 635 crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) 636 | ((hsync_wid & 0x3f) << 16) 637 | ((mode->flags & DRM_MODE_FLAG_NHSYNC) 638 ? RADEON_CRTC_H_SYNC_POL 639 : 0)); 640 641 /* This works for double scan mode. */ 642 crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff) 643 | ((mode->crtc_vdisplay - 1) << 16)); 644 645 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start; 646 if (!vsync_wid) 647 vsync_wid = 1; 648 649 crtc_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff) 650 | ((vsync_wid & 0x1f) << 16) 651 | ((mode->flags & DRM_MODE_FLAG_NVSYNC) 652 ? RADEON_CRTC_V_SYNC_POL 653 : 0)); 654 655 if (radeon_crtc->crtc_id) { 656 uint32_t crtc2_gen_cntl; 657 uint32_t disp2_merge_cntl; 658 659 /* if TV DAC is enabled for another crtc and keep it enabled */ 660 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL) & 0x00718080; 661 crtc2_gen_cntl |= ((format << 8) 662 | RADEON_CRTC2_VSYNC_DIS 663 | RADEON_CRTC2_HSYNC_DIS 664 | RADEON_CRTC2_DISP_DIS 665 | RADEON_CRTC2_DISP_REQ_EN_B 666 | ((mode->flags & DRM_MODE_FLAG_DBLSCAN) 667 ? RADEON_CRTC2_DBL_SCAN_EN 668 : 0) 669 | ((mode->flags & DRM_MODE_FLAG_CSYNC) 670 ? RADEON_CRTC2_CSYNC_EN 671 : 0) 672 | ((mode->flags & DRM_MODE_FLAG_INTERLACE) 673 ? RADEON_CRTC2_INTERLACE_EN 674 : 0)); 675 676 /* rs4xx chips seem to like to have the crtc enabled when the timing is set */ 677 if ((rdev->family == CHIP_RS400) || (rdev->family == CHIP_RS480)) 678 crtc2_gen_cntl |= RADEON_CRTC2_EN; 679 680 disp2_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL); 681 disp2_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN; 682 683 WREG32(RADEON_DISP2_MERGE_CNTL, disp2_merge_cntl); 684 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); 685 686 WREG32(RADEON_FP_H2_SYNC_STRT_WID, crtc_h_sync_strt_wid); 687 WREG32(RADEON_FP_V2_SYNC_STRT_WID, crtc_v_sync_strt_wid); 688 } else { 689 uint32_t crtc_gen_cntl; 690 uint32_t crtc_ext_cntl; 691 uint32_t disp_merge_cntl; 692 693 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL) & 0x00718000; 694 crtc_gen_cntl |= (RADEON_CRTC_EXT_DISP_EN 695 | (format << 8) 696 | RADEON_CRTC_DISP_REQ_EN_B 697 | ((mode->flags & DRM_MODE_FLAG_DBLSCAN) 698 ? RADEON_CRTC_DBL_SCAN_EN 699 : 0) 700 | ((mode->flags & DRM_MODE_FLAG_CSYNC) 701 ? RADEON_CRTC_CSYNC_EN 702 : 0) 703 | ((mode->flags & DRM_MODE_FLAG_INTERLACE) 704 ? RADEON_CRTC_INTERLACE_EN 705 : 0)); 706 707 /* rs4xx chips seem to like to have the crtc enabled when the timing is set */ 708 if ((rdev->family == CHIP_RS400) || (rdev->family == CHIP_RS480)) 709 crtc_gen_cntl |= RADEON_CRTC_EN; 710 711 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); 712 crtc_ext_cntl |= (RADEON_XCRT_CNT_EN | 713 RADEON_CRTC_VSYNC_DIS | 714 RADEON_CRTC_HSYNC_DIS | 715 RADEON_CRTC_DISPLAY_DIS); 716 717 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL); 718 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN; 719 720 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl); 721 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl); 722 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); 723 } 724 725 if (is_tv) 726 radeon_legacy_tv_adjust_crtc_reg(encoder, &crtc_h_total_disp, 727 &crtc_h_sync_strt_wid, &crtc_v_total_disp, 728 &crtc_v_sync_strt_wid); 729 730 WREG32(RADEON_CRTC_H_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_h_total_disp); 731 WREG32(RADEON_CRTC_H_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_h_sync_strt_wid); 732 WREG32(RADEON_CRTC_V_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_v_total_disp); 733 WREG32(RADEON_CRTC_V_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_v_sync_strt_wid); 734 735 return true; 736 } 737 738 static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) 739 { 740 struct drm_device *dev = crtc->dev; 741 struct radeon_device *rdev = dev->dev_private; 742 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 743 struct drm_encoder *encoder; 744 uint32_t feedback_div = 0; 745 uint32_t frac_fb_div = 0; 746 uint32_t reference_div = 0; 747 uint32_t post_divider = 0; 748 uint32_t freq = 0; 749 uint8_t pll_gain; 750 bool use_bios_divs = false; 751 /* PLL registers */ 752 uint32_t pll_ref_div = 0; 753 uint32_t pll_fb_post_div = 0; 754 uint32_t htotal_cntl = 0; 755 bool is_tv = false; 756 struct radeon_pll *pll; 757 758 struct { 759 int divider; 760 int bitvalue; 761 } *post_div, post_divs[] = { 762 /* From RAGE 128 VR/RAGE 128 GL Register 763 * Reference Manual (Technical Reference 764 * Manual P/N RRG-G04100-C Rev. 0.04), page 765 * 3-17 (PLL_DIV_[3:0]). 766 */ 767 { 1, 0 }, /* VCLK_SRC */ 768 { 2, 1 }, /* VCLK_SRC/2 */ 769 { 4, 2 }, /* VCLK_SRC/4 */ 770 { 8, 3 }, /* VCLK_SRC/8 */ 771 { 3, 4 }, /* VCLK_SRC/3 */ 772 { 16, 5 }, /* VCLK_SRC/16 */ 773 { 6, 6 }, /* VCLK_SRC/6 */ 774 { 12, 7 }, /* VCLK_SRC/12 */ 775 { 0, 0 } 776 }; 777 778 if (radeon_crtc->crtc_id) 779 pll = &rdev->clock.p2pll; 780 else 781 pll = &rdev->clock.p1pll; 782 783 pll->flags = RADEON_PLL_LEGACY; 784 785 if (mode->clock > 200000) /* range limits??? */ 786 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; 787 else 788 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV; 789 790 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 791 if (encoder->crtc == crtc) { 792 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 793 794 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { 795 is_tv = true; 796 break; 797 } 798 799 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC) 800 pll->flags |= RADEON_PLL_NO_ODD_POST_DIV; 801 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) { 802 if (!rdev->is_atom_bios) { 803 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 804 struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv; 805 if (lvds) { 806 if (lvds->use_bios_dividers) { 807 pll_ref_div = lvds->panel_ref_divider; 808 pll_fb_post_div = (lvds->panel_fb_divider | 809 (lvds->panel_post_divider << 16)); 810 htotal_cntl = 0; 811 use_bios_divs = true; 812 } 813 } 814 } 815 pll->flags |= RADEON_PLL_USE_REF_DIV; 816 } 817 } 818 } 819 820 DRM_DEBUG_KMS("\n"); 821 822 if (!use_bios_divs) { 823 radeon_compute_pll_legacy(pll, mode->clock, 824 &freq, &feedback_div, &frac_fb_div, 825 &reference_div, &post_divider); 826 827 for (post_div = &post_divs[0]; post_div->divider; ++post_div) { 828 if (post_div->divider == post_divider) 829 break; 830 } 831 832 if (!post_div->divider) 833 post_div = &post_divs[0]; 834 835 DRM_DEBUG_KMS("dc=%u, fd=%d, rd=%d, pd=%d\n", 836 (unsigned)freq, 837 feedback_div, 838 reference_div, 839 post_divider); 840 841 pll_ref_div = reference_div; 842 #if defined(__powerpc__) && (0) /* TODO */ 843 /* apparently programming this otherwise causes a hang??? */ 844 if (info->MacModel == RADEON_MAC_IBOOK) 845 pll_fb_post_div = 0x000600ad; 846 else 847 #endif 848 pll_fb_post_div = (feedback_div | (post_div->bitvalue << 16)); 849 850 htotal_cntl = mode->htotal & 0x7; 851 852 } 853 854 pll_gain = radeon_compute_pll_gain(pll->reference_freq, 855 pll_ref_div & 0x3ff, 856 pll_fb_post_div & 0x7ff); 857 858 if (radeon_crtc->crtc_id) { 859 uint32_t pixclks_cntl = ((RREG32_PLL(RADEON_PIXCLKS_CNTL) & 860 ~(RADEON_PIX2CLK_SRC_SEL_MASK)) | 861 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK); 862 863 if (is_tv) { 864 radeon_legacy_tv_adjust_pll2(encoder, &htotal_cntl, 865 &pll_ref_div, &pll_fb_post_div, 866 &pixclks_cntl); 867 } 868 869 WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 870 RADEON_PIX2CLK_SRC_SEL_CPUCLK, 871 ~(RADEON_PIX2CLK_SRC_SEL_MASK)); 872 873 WREG32_PLL_P(RADEON_P2PLL_CNTL, 874 RADEON_P2PLL_RESET 875 | RADEON_P2PLL_ATOMIC_UPDATE_EN 876 | ((uint32_t)pll_gain << RADEON_P2PLL_PVG_SHIFT), 877 ~(RADEON_P2PLL_RESET 878 | RADEON_P2PLL_ATOMIC_UPDATE_EN 879 | RADEON_P2PLL_PVG_MASK)); 880 881 WREG32_PLL_P(RADEON_P2PLL_REF_DIV, 882 pll_ref_div, 883 ~RADEON_P2PLL_REF_DIV_MASK); 884 885 WREG32_PLL_P(RADEON_P2PLL_DIV_0, 886 pll_fb_post_div, 887 ~RADEON_P2PLL_FB0_DIV_MASK); 888 889 WREG32_PLL_P(RADEON_P2PLL_DIV_0, 890 pll_fb_post_div, 891 ~RADEON_P2PLL_POST0_DIV_MASK); 892 893 radeon_pll2_write_update(dev); 894 radeon_pll2_wait_for_read_update_complete(dev); 895 896 WREG32_PLL(RADEON_HTOTAL2_CNTL, htotal_cntl); 897 898 WREG32_PLL_P(RADEON_P2PLL_CNTL, 899 0, 900 ~(RADEON_P2PLL_RESET 901 | RADEON_P2PLL_SLEEP 902 | RADEON_P2PLL_ATOMIC_UPDATE_EN)); 903 904 DRM_DEBUG_KMS("Wrote2: 0x%08x 0x%08x 0x%08x (0x%08x)\n", 905 (unsigned)pll_ref_div, 906 (unsigned)pll_fb_post_div, 907 (unsigned)htotal_cntl, 908 RREG32_PLL(RADEON_P2PLL_CNTL)); 909 DRM_DEBUG_KMS("Wrote2: rd=%u, fd=%u, pd=%u\n", 910 (unsigned)pll_ref_div & RADEON_P2PLL_REF_DIV_MASK, 911 (unsigned)pll_fb_post_div & RADEON_P2PLL_FB0_DIV_MASK, 912 (unsigned)((pll_fb_post_div & 913 RADEON_P2PLL_POST0_DIV_MASK) >> 16)); 914 915 mdelay(50); /* Let the clock to lock */ 916 917 WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 918 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK, 919 ~(RADEON_PIX2CLK_SRC_SEL_MASK)); 920 921 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl); 922 } else { 923 uint32_t pixclks_cntl; 924 925 926 if (is_tv) { 927 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL); 928 radeon_legacy_tv_adjust_pll1(encoder, &htotal_cntl, &pll_ref_div, 929 &pll_fb_post_div, &pixclks_cntl); 930 } 931 932 if (rdev->flags & RADEON_IS_MOBILITY) { 933 /* A temporal workaround for the occasional blanking on certain laptop panels. 934 This appears to related to the PLL divider registers (fail to lock?). 935 It occurs even when all dividers are the same with their old settings. 936 In this case we really don't need to fiddle with PLL registers. 937 By doing this we can avoid the blanking problem with some panels. 938 */ 939 if ((pll_ref_div == (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) && 940 (pll_fb_post_div == (RREG32_PLL(RADEON_PPLL_DIV_3) & 941 (RADEON_PPLL_POST3_DIV_MASK | RADEON_PPLL_FB3_DIV_MASK)))) { 942 WREG32_P(RADEON_CLOCK_CNTL_INDEX, 943 RADEON_PLL_DIV_SEL, 944 ~(RADEON_PLL_DIV_SEL)); 945 r100_pll_errata_after_index(rdev); 946 return; 947 } 948 } 949 950 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL, 951 RADEON_VCLK_SRC_SEL_CPUCLK, 952 ~(RADEON_VCLK_SRC_SEL_MASK)); 953 WREG32_PLL_P(RADEON_PPLL_CNTL, 954 RADEON_PPLL_RESET 955 | RADEON_PPLL_ATOMIC_UPDATE_EN 956 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN 957 | ((uint32_t)pll_gain << RADEON_PPLL_PVG_SHIFT), 958 ~(RADEON_PPLL_RESET 959 | RADEON_PPLL_ATOMIC_UPDATE_EN 960 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN 961 | RADEON_PPLL_PVG_MASK)); 962 963 WREG32_P(RADEON_CLOCK_CNTL_INDEX, 964 RADEON_PLL_DIV_SEL, 965 ~(RADEON_PLL_DIV_SEL)); 966 r100_pll_errata_after_index(rdev); 967 968 if (ASIC_IS_R300(rdev) || 969 (rdev->family == CHIP_RS300) || 970 (rdev->family == CHIP_RS400) || 971 (rdev->family == CHIP_RS480)) { 972 if (pll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) { 973 /* When restoring console mode, use saved PPLL_REF_DIV 974 * setting. 975 */ 976 WREG32_PLL_P(RADEON_PPLL_REF_DIV, 977 pll_ref_div, 978 0); 979 } else { 980 /* R300 uses ref_div_acc field as real ref divider */ 981 WREG32_PLL_P(RADEON_PPLL_REF_DIV, 982 (pll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT), 983 ~R300_PPLL_REF_DIV_ACC_MASK); 984 } 985 } else 986 WREG32_PLL_P(RADEON_PPLL_REF_DIV, 987 pll_ref_div, 988 ~RADEON_PPLL_REF_DIV_MASK); 989 990 WREG32_PLL_P(RADEON_PPLL_DIV_3, 991 pll_fb_post_div, 992 ~RADEON_PPLL_FB3_DIV_MASK); 993 994 WREG32_PLL_P(RADEON_PPLL_DIV_3, 995 pll_fb_post_div, 996 ~RADEON_PPLL_POST3_DIV_MASK); 997 998 radeon_pll_write_update(dev); 999 radeon_pll_wait_for_read_update_complete(dev); 1000 1001 WREG32_PLL(RADEON_HTOTAL_CNTL, htotal_cntl); 1002 1003 WREG32_PLL_P(RADEON_PPLL_CNTL, 1004 0, 1005 ~(RADEON_PPLL_RESET 1006 | RADEON_PPLL_SLEEP 1007 | RADEON_PPLL_ATOMIC_UPDATE_EN 1008 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN)); 1009 1010 DRM_DEBUG_KMS("Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n", 1011 pll_ref_div, 1012 pll_fb_post_div, 1013 (unsigned)htotal_cntl, 1014 RREG32_PLL(RADEON_PPLL_CNTL)); 1015 DRM_DEBUG_KMS("Wrote: rd=%d, fd=%d, pd=%d\n", 1016 pll_ref_div & RADEON_PPLL_REF_DIV_MASK, 1017 pll_fb_post_div & RADEON_PPLL_FB3_DIV_MASK, 1018 (pll_fb_post_div & RADEON_PPLL_POST3_DIV_MASK) >> 16); 1019 1020 mdelay(50); /* Let the clock to lock */ 1021 1022 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL, 1023 RADEON_VCLK_SRC_SEL_PPLLCLK, 1024 ~(RADEON_VCLK_SRC_SEL_MASK)); 1025 1026 if (is_tv) 1027 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl); 1028 } 1029 } 1030 1031 static bool radeon_crtc_mode_fixup(struct drm_crtc *crtc, 1032 const struct drm_display_mode *mode, 1033 struct drm_display_mode *adjusted_mode) 1034 { 1035 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) 1036 return false; 1037 return true; 1038 } 1039 1040 static int radeon_crtc_mode_set(struct drm_crtc *crtc, 1041 struct drm_display_mode *mode, 1042 struct drm_display_mode *adjusted_mode, 1043 int x, int y, struct drm_framebuffer *old_fb) 1044 { 1045 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1046 1047 /* TODO TV */ 1048 radeon_crtc_set_base(crtc, x, y, old_fb); 1049 radeon_set_crtc_timing(crtc, adjusted_mode); 1050 radeon_set_pll(crtc, adjusted_mode); 1051 radeon_overscan_setup(crtc, adjusted_mode); 1052 if (radeon_crtc->crtc_id == 0) { 1053 radeon_legacy_rmx_mode_set(crtc, adjusted_mode); 1054 } else { 1055 if (radeon_crtc->rmx_type != RMX_OFF) { 1056 /* FIXME: only first crtc has rmx what should we 1057 * do ? 1058 */ 1059 DRM_ERROR("Mode need scaling but only first crtc can do that.\n"); 1060 } 1061 } 1062 radeon_cursor_reset(crtc); 1063 return 0; 1064 } 1065 1066 static void radeon_crtc_prepare(struct drm_crtc *crtc) 1067 { 1068 struct drm_device *dev = crtc->dev; 1069 struct drm_crtc *crtci; 1070 1071 /* 1072 * The hardware wedges sometimes if you reconfigure one CRTC 1073 * whilst another is running (see fdo bug #24611). 1074 */ 1075 list_for_each_entry(crtci, &dev->mode_config.crtc_list, head) 1076 radeon_crtc_dpms(crtci, DRM_MODE_DPMS_OFF); 1077 } 1078 1079 static void radeon_crtc_commit(struct drm_crtc *crtc) 1080 { 1081 struct drm_device *dev = crtc->dev; 1082 struct drm_crtc *crtci; 1083 1084 /* 1085 * Reenable the CRTCs that should be running. 1086 */ 1087 list_for_each_entry(crtci, &dev->mode_config.crtc_list, head) { 1088 if (crtci->enabled) 1089 radeon_crtc_dpms(crtci, DRM_MODE_DPMS_ON); 1090 } 1091 } 1092 1093 static void radeon_crtc_disable(struct drm_crtc *crtc) 1094 { 1095 radeon_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 1096 if (crtc->primary->fb) { 1097 int r; 1098 struct radeon_bo *rbo; 1099 1100 rbo = gem_to_radeon_bo(crtc->primary->fb->obj[0]); 1101 r = radeon_bo_reserve(rbo, false); 1102 if (unlikely(r)) 1103 DRM_ERROR("failed to reserve rbo before unpin\n"); 1104 else { 1105 radeon_bo_unpin(rbo); 1106 radeon_bo_unreserve(rbo); 1107 } 1108 } 1109 } 1110 1111 static const struct drm_crtc_helper_funcs legacy_helper_funcs = { 1112 .dpms = radeon_crtc_dpms, 1113 .mode_fixup = radeon_crtc_mode_fixup, 1114 .mode_set = radeon_crtc_mode_set, 1115 .mode_set_base = radeon_crtc_set_base, 1116 .mode_set_base_atomic = radeon_crtc_set_base_atomic, 1117 .prepare = radeon_crtc_prepare, 1118 .commit = radeon_crtc_commit, 1119 .disable = radeon_crtc_disable 1120 }; 1121 1122 1123 void radeon_legacy_init_crtc(struct drm_device *dev, 1124 struct radeon_crtc *radeon_crtc) 1125 { 1126 if (radeon_crtc->crtc_id == 1) 1127 radeon_crtc->crtc_offset = RADEON_CRTC2_H_TOTAL_DISP - RADEON_CRTC_H_TOTAL_DISP; 1128 drm_crtc_helper_add(&radeon_crtc->base, &legacy_helper_funcs); 1129 } 1130
Indexes created Tue Oct 21 12:09:54 GMT 2025