radeon_legacy_encoders.c revision 1.3
1 /* $NetBSD: radeon_legacy_encoders.c,v 1.3 2018/08/27 04:58:36 riastradh Exp $ */ 2 3 /* 4 * Copyright 2007-8 Advanced Micro Devices, Inc. 5 * Copyright 2008 Red Hat Inc. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 11 * and/or sell copies of the Software, and to permit persons to whom the 12 * Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 23 * OTHER DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: Dave Airlie 26 * Alex Deucher 27 */ 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: radeon_legacy_encoders.c,v 1.3 2018/08/27 04:58:36 riastradh Exp $"); 30 31 #include <drm/drmP.h> 32 #include <drm/drm_crtc_helper.h> 33 #include <drm/radeon_drm.h> 34 #include "radeon.h" 35 #include "atom.h" 36 #include <linux/backlight.h> 37 #ifdef CONFIG_PMAC_BACKLIGHT 38 #include <asm/backlight.h> 39 #endif 40 41 static void radeon_legacy_encoder_disable(struct drm_encoder *encoder) 42 { 43 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 44 const struct drm_encoder_helper_funcs *encoder_funcs; 45 46 encoder_funcs = encoder->helper_private; 47 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF); 48 radeon_encoder->active_device = 0; 49 } 50 51 static void radeon_legacy_lvds_update(struct drm_encoder *encoder, int mode) 52 { 53 struct drm_device *dev = encoder->dev; 54 struct radeon_device *rdev = dev->dev_private; 55 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 56 uint32_t lvds_gen_cntl, lvds_pll_cntl, pixclks_cntl, disp_pwr_man; 57 int panel_pwr_delay = 2000; 58 bool is_mac = false; 59 uint8_t backlight_level; 60 DRM_DEBUG_KMS("\n"); 61 62 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); 63 backlight_level = (lvds_gen_cntl >> RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff; 64 65 if (radeon_encoder->enc_priv) { 66 if (rdev->is_atom_bios) { 67 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv; 68 panel_pwr_delay = lvds->panel_pwr_delay; 69 if (lvds->bl_dev) 70 backlight_level = lvds->backlight_level; 71 } else { 72 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv; 73 panel_pwr_delay = lvds->panel_pwr_delay; 74 if (lvds->bl_dev) 75 backlight_level = lvds->backlight_level; 76 } 77 } 78 79 /* macs (and possibly some x86 oem systems?) wire up LVDS strangely 80 * Taken from radeonfb. 81 */ 82 if ((rdev->mode_info.connector_table == CT_IBOOK) || 83 (rdev->mode_info.connector_table == CT_POWERBOOK_EXTERNAL) || 84 (rdev->mode_info.connector_table == CT_POWERBOOK_INTERNAL) || 85 (rdev->mode_info.connector_table == CT_POWERBOOK_VGA)) 86 is_mac = true; 87 88 switch (mode) { 89 case DRM_MODE_DPMS_ON: 90 disp_pwr_man = RREG32(RADEON_DISP_PWR_MAN); 91 disp_pwr_man |= RADEON_AUTO_PWRUP_EN; 92 WREG32(RADEON_DISP_PWR_MAN, disp_pwr_man); 93 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL); 94 lvds_pll_cntl |= RADEON_LVDS_PLL_EN; 95 WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl); 96 mdelay(1); 97 98 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL); 99 lvds_pll_cntl &= ~RADEON_LVDS_PLL_RESET; 100 WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl); 101 102 lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS | 103 RADEON_LVDS_BL_MOD_LEVEL_MASK); 104 lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_EN | 105 RADEON_LVDS_DIGON | RADEON_LVDS_BLON | 106 (backlight_level << RADEON_LVDS_BL_MOD_LEVEL_SHIFT)); 107 if (is_mac) 108 lvds_gen_cntl |= RADEON_LVDS_BL_MOD_EN; 109 mdelay(panel_pwr_delay); 110 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); 111 break; 112 case DRM_MODE_DPMS_STANDBY: 113 case DRM_MODE_DPMS_SUSPEND: 114 case DRM_MODE_DPMS_OFF: 115 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL); 116 WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb); 117 lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS; 118 if (is_mac) { 119 lvds_gen_cntl &= ~RADEON_LVDS_BL_MOD_EN; 120 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); 121 lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_EN); 122 } else { 123 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); 124 lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN | RADEON_LVDS_DIGON); 125 } 126 mdelay(panel_pwr_delay); 127 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); 128 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl); 129 mdelay(panel_pwr_delay); 130 break; 131 } 132 133 if (rdev->is_atom_bios) 134 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 135 else 136 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 137 138 } 139 140 static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode) 141 { 142 struct radeon_device *rdev = encoder->dev->dev_private; 143 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 144 DRM_DEBUG("\n"); 145 146 if (radeon_encoder->enc_priv) { 147 if (rdev->is_atom_bios) { 148 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv; 149 lvds->dpms_mode = mode; 150 } else { 151 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv; 152 lvds->dpms_mode = mode; 153 } 154 } 155 156 radeon_legacy_lvds_update(encoder, mode); 157 } 158 159 static void radeon_legacy_lvds_prepare(struct drm_encoder *encoder) 160 { 161 struct radeon_device *rdev = encoder->dev->dev_private; 162 163 if (rdev->is_atom_bios) 164 radeon_atom_output_lock(encoder, true); 165 else 166 radeon_combios_output_lock(encoder, true); 167 radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_OFF); 168 } 169 170 static void radeon_legacy_lvds_commit(struct drm_encoder *encoder) 171 { 172 struct radeon_device *rdev = encoder->dev->dev_private; 173 174 radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_ON); 175 if (rdev->is_atom_bios) 176 radeon_atom_output_lock(encoder, false); 177 else 178 radeon_combios_output_lock(encoder, false); 179 } 180 181 static void radeon_legacy_lvds_mode_set(struct drm_encoder *encoder, 182 struct drm_display_mode *mode, 183 struct drm_display_mode *adjusted_mode) 184 { 185 struct drm_device *dev = encoder->dev; 186 struct radeon_device *rdev = dev->dev_private; 187 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 188 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 189 uint32_t lvds_pll_cntl, lvds_gen_cntl, lvds_ss_gen_cntl; 190 191 DRM_DEBUG_KMS("\n"); 192 193 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL); 194 lvds_pll_cntl &= ~RADEON_LVDS_PLL_EN; 195 196 lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL); 197 if (rdev->is_atom_bios) { 198 /* LVDS_GEN_CNTL parameters are computed in LVDSEncoderControl 199 * need to call that on resume to set up the reg properly. 200 */ 201 radeon_encoder->pixel_clock = adjusted_mode->clock; 202 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE); 203 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); 204 } else { 205 struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv; 206 if (lvds) { 207 DRM_DEBUG_KMS("bios LVDS_GEN_CNTL: 0x%x\n", lvds->lvds_gen_cntl); 208 lvds_gen_cntl = lvds->lvds_gen_cntl; 209 lvds_ss_gen_cntl &= ~((0xf << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) | 210 (0xf << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT)); 211 lvds_ss_gen_cntl |= ((lvds->panel_digon_delay << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) | 212 (lvds->panel_blon_delay << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT)); 213 } else 214 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); 215 } 216 lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS; 217 lvds_gen_cntl &= ~(RADEON_LVDS_ON | 218 RADEON_LVDS_BLON | 219 RADEON_LVDS_EN | 220 RADEON_LVDS_RST_FM); 221 222 if (ASIC_IS_R300(rdev)) 223 lvds_pll_cntl &= ~(R300_LVDS_SRC_SEL_MASK); 224 225 if (radeon_crtc->crtc_id == 0) { 226 if (ASIC_IS_R300(rdev)) { 227 if (radeon_encoder->rmx_type != RMX_OFF) 228 lvds_pll_cntl |= R300_LVDS_SRC_SEL_RMX; 229 } else 230 lvds_gen_cntl &= ~RADEON_LVDS_SEL_CRTC2; 231 } else { 232 if (ASIC_IS_R300(rdev)) 233 lvds_pll_cntl |= R300_LVDS_SRC_SEL_CRTC2; 234 else 235 lvds_gen_cntl |= RADEON_LVDS_SEL_CRTC2; 236 } 237 238 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); 239 WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl); 240 WREG32(RADEON_LVDS_SS_GEN_CNTL, lvds_ss_gen_cntl); 241 242 if (rdev->family == CHIP_RV410) 243 WREG32(RADEON_CLOCK_CNTL_INDEX, 0); 244 245 if (rdev->is_atom_bios) 246 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); 247 else 248 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); 249 } 250 251 static bool radeon_legacy_mode_fixup(struct drm_encoder *encoder, 252 const struct drm_display_mode *mode, 253 struct drm_display_mode *adjusted_mode) 254 { 255 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 256 257 /* set the active encoder to connector routing */ 258 radeon_encoder_set_active_device(encoder); 259 drm_mode_set_crtcinfo(adjusted_mode, 0); 260 261 /* get the native mode for LVDS */ 262 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) 263 radeon_panel_mode_fixup(encoder, adjusted_mode); 264 265 return true; 266 } 267 268 static const struct drm_encoder_helper_funcs radeon_legacy_lvds_helper_funcs = { 269 .dpms = radeon_legacy_lvds_dpms, 270 .mode_fixup = radeon_legacy_mode_fixup, 271 .prepare = radeon_legacy_lvds_prepare, 272 .mode_set = radeon_legacy_lvds_mode_set, 273 .commit = radeon_legacy_lvds_commit, 274 .disable = radeon_legacy_encoder_disable, 275 }; 276 277 u8 278 radeon_legacy_get_backlight_level(struct radeon_encoder *radeon_encoder) 279 { 280 struct drm_device *dev = radeon_encoder->base.dev; 281 struct radeon_device *rdev = dev->dev_private; 282 u8 backlight_level; 283 284 backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >> 285 RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff; 286 287 return backlight_level; 288 } 289 290 void 291 radeon_legacy_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level) 292 { 293 struct drm_device *dev = radeon_encoder->base.dev; 294 struct radeon_device *rdev = dev->dev_private; 295 int dpms_mode = DRM_MODE_DPMS_ON; 296 297 if (radeon_encoder->enc_priv) { 298 if (rdev->is_atom_bios) { 299 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv; 300 if (lvds->backlight_level > 0) 301 dpms_mode = lvds->dpms_mode; 302 else 303 dpms_mode = DRM_MODE_DPMS_OFF; 304 lvds->backlight_level = level; 305 } else { 306 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv; 307 if (lvds->backlight_level > 0) 308 dpms_mode = lvds->dpms_mode; 309 else 310 dpms_mode = DRM_MODE_DPMS_OFF; 311 lvds->backlight_level = level; 312 } 313 } 314 315 radeon_legacy_lvds_update(&radeon_encoder->base, dpms_mode); 316 } 317 318 #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE) || IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 319 320 static uint8_t radeon_legacy_lvds_level(struct backlight_device *bd) 321 { 322 struct radeon_backlight_privdata *pdata = bl_get_data(bd); 323 uint8_t level; 324 325 /* Convert brightness to hardware level */ 326 if (bd->props.brightness < 0) 327 level = 0; 328 else if (bd->props.brightness > RADEON_MAX_BL_LEVEL) 329 level = RADEON_MAX_BL_LEVEL; 330 else 331 level = bd->props.brightness; 332 333 if (pdata->negative) 334 level = RADEON_MAX_BL_LEVEL - level; 335 336 return level; 337 } 338 339 static int radeon_legacy_backlight_update_status(struct backlight_device *bd) 340 { 341 struct radeon_backlight_privdata *pdata = bl_get_data(bd); 342 struct radeon_encoder *radeon_encoder = pdata->encoder; 343 344 radeon_legacy_set_backlight_level(radeon_encoder, 345 radeon_legacy_lvds_level(bd)); 346 347 return 0; 348 } 349 350 static int radeon_legacy_backlight_get_brightness(struct backlight_device *bd) 351 { 352 struct radeon_backlight_privdata *pdata = bl_get_data(bd); 353 struct radeon_encoder *radeon_encoder = pdata->encoder; 354 struct drm_device *dev = radeon_encoder->base.dev; 355 struct radeon_device *rdev = dev->dev_private; 356 uint8_t backlight_level; 357 358 backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >> 359 RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff; 360 361 return pdata->negative ? RADEON_MAX_BL_LEVEL - backlight_level : backlight_level; 362 } 363 364 static const struct backlight_ops radeon_backlight_ops = { 365 .get_brightness = radeon_legacy_backlight_get_brightness, 366 .update_status = radeon_legacy_backlight_update_status, 367 }; 368 369 void radeon_legacy_backlight_init(struct radeon_encoder *radeon_encoder, 370 struct drm_connector *drm_connector) 371 { 372 struct drm_device *dev = radeon_encoder->base.dev; 373 struct radeon_device *rdev = dev->dev_private; 374 struct backlight_device *bd; 375 struct backlight_properties props; 376 struct radeon_backlight_privdata *pdata; 377 uint8_t backlight_level; 378 char bl_name[16]; 379 380 if (!radeon_encoder->enc_priv) 381 return; 382 383 #ifdef CONFIG_PMAC_BACKLIGHT 384 if (!pmac_has_backlight_type("ati") && 385 !pmac_has_backlight_type("mnca")) 386 return; 387 #endif 388 389 pdata = kmalloc(sizeof(struct radeon_backlight_privdata), GFP_KERNEL); 390 if (!pdata) { 391 DRM_ERROR("Memory allocation failed\n"); 392 goto error; 393 } 394 395 memset(&props, 0, sizeof(props)); 396 props.max_brightness = RADEON_MAX_BL_LEVEL; 397 props.type = BACKLIGHT_RAW; 398 snprintf(bl_name, sizeof(bl_name), 399 "radeon_bl%d", dev->primary->index); 400 bd = backlight_device_register(bl_name, drm_connector->kdev, 401 pdata, &radeon_backlight_ops, &props); 402 if (IS_ERR(bd)) { 403 DRM_ERROR("Backlight registration failed\n"); 404 goto error; 405 } 406 407 pdata->encoder = radeon_encoder; 408 409 backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >> 410 RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff; 411 412 /* First, try to detect backlight level sense based on the assumption 413 * that firmware set it up at full brightness 414 */ 415 if (backlight_level == 0) 416 pdata->negative = true; 417 else if (backlight_level == 0xff) 418 pdata->negative = false; 419 else { 420 /* XXX hack... maybe some day we can figure out in what direction 421 * backlight should work on a given panel? 422 */ 423 pdata->negative = (rdev->family != CHIP_RV200 && 424 rdev->family != CHIP_RV250 && 425 rdev->family != CHIP_RV280 && 426 rdev->family != CHIP_RV350); 427 428 #ifdef CONFIG_PMAC_BACKLIGHT 429 pdata->negative = (pdata->negative || 430 of_machine_is_compatible("PowerBook4,3") || 431 of_machine_is_compatible("PowerBook6,3") || 432 of_machine_is_compatible("PowerBook6,5")); 433 #endif 434 } 435 436 if (rdev->is_atom_bios) { 437 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv; 438 lvds->bl_dev = bd; 439 } else { 440 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv; 441 lvds->bl_dev = bd; 442 } 443 444 bd->props.brightness = radeon_legacy_backlight_get_brightness(bd); 445 bd->props.power = FB_BLANK_UNBLANK; 446 backlight_update_status(bd); 447 448 DRM_INFO("radeon legacy LVDS backlight initialized\n"); 449 rdev->mode_info.bl_encoder = radeon_encoder; 450 451 return; 452 453 error: 454 kfree(pdata); 455 return; 456 } 457 458 static void radeon_legacy_backlight_exit(struct radeon_encoder *radeon_encoder) 459 { 460 struct drm_device *dev = radeon_encoder->base.dev; 461 struct radeon_device *rdev = dev->dev_private; 462 struct backlight_device *bd = NULL; 463 464 if (!radeon_encoder->enc_priv) 465 return; 466 467 if (rdev->is_atom_bios) { 468 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv; 469 bd = lvds->bl_dev; 470 lvds->bl_dev = NULL; 471 } else { 472 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv; 473 bd = lvds->bl_dev; 474 lvds->bl_dev = NULL; 475 } 476 477 if (bd) { 478 struct radeon_backlight_privdata *pdata; 479 480 pdata = bl_get_data(bd); 481 backlight_device_unregister(bd); 482 kfree(pdata); 483 484 DRM_INFO("radeon legacy LVDS backlight unloaded\n"); 485 } 486 } 487 488 #else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */ 489 490 void radeon_legacy_backlight_init(struct radeon_encoder *encoder) 491 { 492 } 493 494 static void radeon_legacy_backlight_exit(struct radeon_encoder *encoder) 495 { 496 } 497 498 #endif 499 500 501 static void radeon_lvds_enc_destroy(struct drm_encoder *encoder) 502 { 503 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 504 505 if (radeon_encoder->enc_priv) { 506 radeon_legacy_backlight_exit(radeon_encoder); 507 kfree(radeon_encoder->enc_priv); 508 } 509 drm_encoder_cleanup(encoder); 510 kfree(radeon_encoder); 511 } 512 513 static const struct drm_encoder_funcs radeon_legacy_lvds_enc_funcs = { 514 .destroy = radeon_lvds_enc_destroy, 515 }; 516 517 static void radeon_legacy_primary_dac_dpms(struct drm_encoder *encoder, int mode) 518 { 519 struct drm_device *dev = encoder->dev; 520 struct radeon_device *rdev = dev->dev_private; 521 uint32_t crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); 522 uint32_t dac_cntl = RREG32(RADEON_DAC_CNTL); 523 uint32_t dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL); 524 525 DRM_DEBUG_KMS("\n"); 526 527 switch (mode) { 528 case DRM_MODE_DPMS_ON: 529 crtc_ext_cntl |= RADEON_CRTC_CRT_ON; 530 dac_cntl &= ~RADEON_DAC_PDWN; 531 dac_macro_cntl &= ~(RADEON_DAC_PDWN_R | 532 RADEON_DAC_PDWN_G | 533 RADEON_DAC_PDWN_B); 534 break; 535 case DRM_MODE_DPMS_STANDBY: 536 case DRM_MODE_DPMS_SUSPEND: 537 case DRM_MODE_DPMS_OFF: 538 crtc_ext_cntl &= ~RADEON_CRTC_CRT_ON; 539 dac_cntl |= RADEON_DAC_PDWN; 540 dac_macro_cntl |= (RADEON_DAC_PDWN_R | 541 RADEON_DAC_PDWN_G | 542 RADEON_DAC_PDWN_B); 543 break; 544 } 545 546 /* handled in radeon_crtc_dpms() */ 547 if (!(rdev->flags & RADEON_SINGLE_CRTC)) 548 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); 549 WREG32(RADEON_DAC_CNTL, dac_cntl); 550 WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl); 551 552 if (rdev->is_atom_bios) 553 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 554 else 555 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 556 557 } 558 559 static void radeon_legacy_primary_dac_prepare(struct drm_encoder *encoder) 560 { 561 struct radeon_device *rdev = encoder->dev->dev_private; 562 563 if (rdev->is_atom_bios) 564 radeon_atom_output_lock(encoder, true); 565 else 566 radeon_combios_output_lock(encoder, true); 567 radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_OFF); 568 } 569 570 static void radeon_legacy_primary_dac_commit(struct drm_encoder *encoder) 571 { 572 struct radeon_device *rdev = encoder->dev->dev_private; 573 574 radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_ON); 575 576 if (rdev->is_atom_bios) 577 radeon_atom_output_lock(encoder, false); 578 else 579 radeon_combios_output_lock(encoder, false); 580 } 581 582 static void radeon_legacy_primary_dac_mode_set(struct drm_encoder *encoder, 583 struct drm_display_mode *mode, 584 struct drm_display_mode *adjusted_mode) 585 { 586 struct drm_device *dev = encoder->dev; 587 struct radeon_device *rdev = dev->dev_private; 588 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 589 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 590 uint32_t disp_output_cntl, dac_cntl, dac2_cntl, dac_macro_cntl; 591 592 DRM_DEBUG_KMS("\n"); 593 594 if (radeon_crtc->crtc_id == 0) { 595 if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) { 596 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) & 597 ~(RADEON_DISP_DAC_SOURCE_MASK); 598 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl); 599 } else { 600 dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~(RADEON_DAC2_DAC_CLK_SEL); 601 WREG32(RADEON_DAC_CNTL2, dac2_cntl); 602 } 603 } else { 604 if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) { 605 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) & 606 ~(RADEON_DISP_DAC_SOURCE_MASK); 607 disp_output_cntl |= RADEON_DISP_DAC_SOURCE_CRTC2; 608 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl); 609 } else { 610 dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC_CLK_SEL; 611 WREG32(RADEON_DAC_CNTL2, dac2_cntl); 612 } 613 } 614 615 dac_cntl = (RADEON_DAC_MASK_ALL | 616 RADEON_DAC_VGA_ADR_EN | 617 /* TODO 6-bits */ 618 RADEON_DAC_8BIT_EN); 619 620 WREG32_P(RADEON_DAC_CNTL, 621 dac_cntl, 622 RADEON_DAC_RANGE_CNTL | 623 RADEON_DAC_BLANKING); 624 625 if (radeon_encoder->enc_priv) { 626 struct radeon_encoder_primary_dac *p_dac = (struct radeon_encoder_primary_dac *)radeon_encoder->enc_priv; 627 dac_macro_cntl = p_dac->ps2_pdac_adj; 628 } else 629 dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL); 630 dac_macro_cntl |= RADEON_DAC_PDWN_R | RADEON_DAC_PDWN_G | RADEON_DAC_PDWN_B; 631 WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl); 632 633 if (rdev->is_atom_bios) 634 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); 635 else 636 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); 637 } 638 639 static enum drm_connector_status radeon_legacy_primary_dac_detect(struct drm_encoder *encoder, 640 struct drm_connector *connector) 641 { 642 struct drm_device *dev = encoder->dev; 643 struct radeon_device *rdev = dev->dev_private; 644 uint32_t vclk_ecp_cntl, crtc_ext_cntl; 645 uint32_t dac_ext_cntl, dac_cntl, dac_macro_cntl, tmp; 646 enum drm_connector_status found = connector_status_disconnected; 647 bool color = true; 648 649 /* just don't bother on RN50 those chip are often connected to remoting 650 * console hw and often we get failure to load detect those. So to make 651 * everyone happy report the encoder as always connected. 652 */ 653 if (ASIC_IS_RN50(rdev)) { 654 return connector_status_connected; 655 } 656 657 /* save the regs we need */ 658 vclk_ecp_cntl = RREG32_PLL(RADEON_VCLK_ECP_CNTL); 659 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); 660 dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL); 661 dac_cntl = RREG32(RADEON_DAC_CNTL); 662 dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL); 663 664 tmp = vclk_ecp_cntl & 665 ~(RADEON_PIXCLK_ALWAYS_ONb | RADEON_PIXCLK_DAC_ALWAYS_ONb); 666 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); 667 668 tmp = crtc_ext_cntl | RADEON_CRTC_CRT_ON; 669 WREG32(RADEON_CRTC_EXT_CNTL, tmp); 670 671 tmp = RADEON_DAC_FORCE_BLANK_OFF_EN | 672 RADEON_DAC_FORCE_DATA_EN; 673 674 if (color) 675 tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB; 676 else 677 tmp |= RADEON_DAC_FORCE_DATA_SEL_G; 678 679 if (ASIC_IS_R300(rdev)) 680 tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT); 681 else if (ASIC_IS_RV100(rdev)) 682 tmp |= (0x1ac << RADEON_DAC_FORCE_DATA_SHIFT); 683 else 684 tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT); 685 686 WREG32(RADEON_DAC_EXT_CNTL, tmp); 687 688 tmp = dac_cntl & ~(RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_PDWN); 689 tmp |= RADEON_DAC_RANGE_CNTL_PS2 | RADEON_DAC_CMP_EN; 690 WREG32(RADEON_DAC_CNTL, tmp); 691 692 tmp = dac_macro_cntl; 693 tmp &= ~(RADEON_DAC_PDWN_R | 694 RADEON_DAC_PDWN_G | 695 RADEON_DAC_PDWN_B); 696 697 WREG32(RADEON_DAC_MACRO_CNTL, tmp); 698 699 mdelay(2); 700 701 if (RREG32(RADEON_DAC_CNTL) & RADEON_DAC_CMP_OUTPUT) 702 found = connector_status_connected; 703 704 /* restore the regs we used */ 705 WREG32(RADEON_DAC_CNTL, dac_cntl); 706 WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl); 707 WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl); 708 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); 709 WREG32_PLL(RADEON_VCLK_ECP_CNTL, vclk_ecp_cntl); 710 711 return found; 712 } 713 714 static const struct drm_encoder_helper_funcs radeon_legacy_primary_dac_helper_funcs = { 715 .dpms = radeon_legacy_primary_dac_dpms, 716 .mode_fixup = radeon_legacy_mode_fixup, 717 .prepare = radeon_legacy_primary_dac_prepare, 718 .mode_set = radeon_legacy_primary_dac_mode_set, 719 .commit = radeon_legacy_primary_dac_commit, 720 .detect = radeon_legacy_primary_dac_detect, 721 .disable = radeon_legacy_encoder_disable, 722 }; 723 724 725 static const struct drm_encoder_funcs radeon_legacy_primary_dac_enc_funcs = { 726 .destroy = radeon_enc_destroy, 727 }; 728 729 static void radeon_legacy_tmds_int_dpms(struct drm_encoder *encoder, int mode) 730 { 731 struct drm_device *dev = encoder->dev; 732 struct radeon_device *rdev = dev->dev_private; 733 uint32_t fp_gen_cntl = RREG32(RADEON_FP_GEN_CNTL); 734 DRM_DEBUG_KMS("\n"); 735 736 switch (mode) { 737 case DRM_MODE_DPMS_ON: 738 fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN); 739 break; 740 case DRM_MODE_DPMS_STANDBY: 741 case DRM_MODE_DPMS_SUSPEND: 742 case DRM_MODE_DPMS_OFF: 743 fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN); 744 break; 745 } 746 747 WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl); 748 749 if (rdev->is_atom_bios) 750 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 751 else 752 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 753 754 } 755 756 static void radeon_legacy_tmds_int_prepare(struct drm_encoder *encoder) 757 { 758 struct radeon_device *rdev = encoder->dev->dev_private; 759 760 if (rdev->is_atom_bios) 761 radeon_atom_output_lock(encoder, true); 762 else 763 radeon_combios_output_lock(encoder, true); 764 radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_OFF); 765 } 766 767 static void radeon_legacy_tmds_int_commit(struct drm_encoder *encoder) 768 { 769 struct radeon_device *rdev = encoder->dev->dev_private; 770 771 radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_ON); 772 773 if (rdev->is_atom_bios) 774 radeon_atom_output_lock(encoder, true); 775 else 776 radeon_combios_output_lock(encoder, true); 777 } 778 779 static void radeon_legacy_tmds_int_mode_set(struct drm_encoder *encoder, 780 struct drm_display_mode *mode, 781 struct drm_display_mode *adjusted_mode) 782 { 783 struct drm_device *dev = encoder->dev; 784 struct radeon_device *rdev = dev->dev_private; 785 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 786 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 787 uint32_t tmp, tmds_pll_cntl, tmds_transmitter_cntl, fp_gen_cntl; 788 int i; 789 790 DRM_DEBUG_KMS("\n"); 791 792 tmp = tmds_pll_cntl = RREG32(RADEON_TMDS_PLL_CNTL); 793 tmp &= 0xfffff; 794 if (rdev->family == CHIP_RV280) { 795 /* bit 22 of TMDS_PLL_CNTL is read-back inverted */ 796 tmp ^= (1 << 22); 797 tmds_pll_cntl ^= (1 << 22); 798 } 799 800 if (radeon_encoder->enc_priv) { 801 struct radeon_encoder_int_tmds *tmds = (struct radeon_encoder_int_tmds *)radeon_encoder->enc_priv; 802 803 for (i = 0; i < 4; i++) { 804 if (tmds->tmds_pll[i].freq == 0) 805 break; 806 if ((uint32_t)(mode->clock / 10) < tmds->tmds_pll[i].freq) { 807 tmp = tmds->tmds_pll[i].value ; 808 break; 809 } 810 } 811 } 812 813 if (ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV280)) { 814 if (tmp & 0xfff00000) 815 tmds_pll_cntl = tmp; 816 else { 817 tmds_pll_cntl &= 0xfff00000; 818 tmds_pll_cntl |= tmp; 819 } 820 } else 821 tmds_pll_cntl = tmp; 822 823 tmds_transmitter_cntl = RREG32(RADEON_TMDS_TRANSMITTER_CNTL) & 824 ~(RADEON_TMDS_TRANSMITTER_PLLRST); 825 826 if (rdev->family == CHIP_R200 || 827 rdev->family == CHIP_R100 || 828 ASIC_IS_R300(rdev)) 829 tmds_transmitter_cntl &= ~(RADEON_TMDS_TRANSMITTER_PLLEN); 830 else /* RV chips got this bit reversed */ 831 tmds_transmitter_cntl |= RADEON_TMDS_TRANSMITTER_PLLEN; 832 833 fp_gen_cntl = (RREG32(RADEON_FP_GEN_CNTL) | 834 (RADEON_FP_CRTC_DONT_SHADOW_VPAR | 835 RADEON_FP_CRTC_DONT_SHADOW_HEND)); 836 837 fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN); 838 839 fp_gen_cntl &= ~(RADEON_FP_RMX_HVSYNC_CONTROL_EN | 840 RADEON_FP_DFP_SYNC_SEL | 841 RADEON_FP_CRT_SYNC_SEL | 842 RADEON_FP_CRTC_LOCK_8DOT | 843 RADEON_FP_USE_SHADOW_EN | 844 RADEON_FP_CRTC_USE_SHADOW_VEND | 845 RADEON_FP_CRT_SYNC_ALT); 846 847 if (1) /* FIXME rgbBits == 8 */ 848 fp_gen_cntl |= RADEON_FP_PANEL_FORMAT; /* 24 bit format */ 849 else 850 fp_gen_cntl &= ~RADEON_FP_PANEL_FORMAT;/* 18 bit format */ 851 852 if (radeon_crtc->crtc_id == 0) { 853 if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) { 854 fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK; 855 if (radeon_encoder->rmx_type != RMX_OFF) 856 fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX; 857 else 858 fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1; 859 } else 860 fp_gen_cntl &= ~RADEON_FP_SEL_CRTC2; 861 } else { 862 if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) { 863 fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK; 864 fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC2; 865 } else 866 fp_gen_cntl |= RADEON_FP_SEL_CRTC2; 867 } 868 869 WREG32(RADEON_TMDS_PLL_CNTL, tmds_pll_cntl); 870 WREG32(RADEON_TMDS_TRANSMITTER_CNTL, tmds_transmitter_cntl); 871 WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl); 872 873 if (rdev->is_atom_bios) 874 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); 875 else 876 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); 877 } 878 879 static const struct drm_encoder_helper_funcs radeon_legacy_tmds_int_helper_funcs = { 880 .dpms = radeon_legacy_tmds_int_dpms, 881 .mode_fixup = radeon_legacy_mode_fixup, 882 .prepare = radeon_legacy_tmds_int_prepare, 883 .mode_set = radeon_legacy_tmds_int_mode_set, 884 .commit = radeon_legacy_tmds_int_commit, 885 .disable = radeon_legacy_encoder_disable, 886 }; 887 888 889 static const struct drm_encoder_funcs radeon_legacy_tmds_int_enc_funcs = { 890 .destroy = radeon_enc_destroy, 891 }; 892 893 static void radeon_legacy_tmds_ext_dpms(struct drm_encoder *encoder, int mode) 894 { 895 struct drm_device *dev = encoder->dev; 896 struct radeon_device *rdev = dev->dev_private; 897 uint32_t fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); 898 DRM_DEBUG_KMS("\n"); 899 900 switch (mode) { 901 case DRM_MODE_DPMS_ON: 902 fp2_gen_cntl &= ~RADEON_FP2_BLANK_EN; 903 fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN); 904 break; 905 case DRM_MODE_DPMS_STANDBY: 906 case DRM_MODE_DPMS_SUSPEND: 907 case DRM_MODE_DPMS_OFF: 908 fp2_gen_cntl |= RADEON_FP2_BLANK_EN; 909 fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN); 910 break; 911 } 912 913 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); 914 915 if (rdev->is_atom_bios) 916 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 917 else 918 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 919 920 } 921 922 static void radeon_legacy_tmds_ext_prepare(struct drm_encoder *encoder) 923 { 924 struct radeon_device *rdev = encoder->dev->dev_private; 925 926 if (rdev->is_atom_bios) 927 radeon_atom_output_lock(encoder, true); 928 else 929 radeon_combios_output_lock(encoder, true); 930 radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_OFF); 931 } 932 933 static void radeon_legacy_tmds_ext_commit(struct drm_encoder *encoder) 934 { 935 struct radeon_device *rdev = encoder->dev->dev_private; 936 radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_ON); 937 938 if (rdev->is_atom_bios) 939 radeon_atom_output_lock(encoder, false); 940 else 941 radeon_combios_output_lock(encoder, false); 942 } 943 944 static void radeon_legacy_tmds_ext_mode_set(struct drm_encoder *encoder, 945 struct drm_display_mode *mode, 946 struct drm_display_mode *adjusted_mode) 947 { 948 struct drm_device *dev = encoder->dev; 949 struct radeon_device *rdev = dev->dev_private; 950 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 951 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 952 uint32_t fp2_gen_cntl; 953 954 DRM_DEBUG_KMS("\n"); 955 956 if (rdev->is_atom_bios) { 957 radeon_encoder->pixel_clock = adjusted_mode->clock; 958 atombios_dvo_setup(encoder, ATOM_ENABLE); 959 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); 960 } else { 961 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); 962 963 if (1) /* FIXME rgbBits == 8 */ 964 fp2_gen_cntl |= RADEON_FP2_PANEL_FORMAT; /* 24 bit format, */ 965 else 966 fp2_gen_cntl &= ~RADEON_FP2_PANEL_FORMAT;/* 18 bit format, */ 967 968 fp2_gen_cntl &= ~(RADEON_FP2_ON | 969 RADEON_FP2_DVO_EN | 970 RADEON_FP2_DVO_RATE_SEL_SDR); 971 972 /* XXX: these are oem specific */ 973 if (ASIC_IS_R300(rdev)) { 974 if ((dev->pdev->device == 0x4850) && 975 (dev->pdev->subsystem_vendor == 0x1028) && 976 (dev->pdev->subsystem_device == 0x2001)) /* Dell Inspiron 8600 */ 977 fp2_gen_cntl |= R300_FP2_DVO_CLOCK_MODE_SINGLE; 978 else 979 fp2_gen_cntl |= RADEON_FP2_PAD_FLOP_EN | R300_FP2_DVO_CLOCK_MODE_SINGLE; 980 981 /*if (mode->clock > 165000) 982 fp2_gen_cntl |= R300_FP2_DVO_DUAL_CHANNEL_EN;*/ 983 } 984 if (!radeon_combios_external_tmds_setup(encoder)) 985 radeon_external_tmds_setup(encoder); 986 } 987 988 if (radeon_crtc->crtc_id == 0) { 989 if ((rdev->family == CHIP_R200) || ASIC_IS_R300(rdev)) { 990 fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK; 991 if (radeon_encoder->rmx_type != RMX_OFF) 992 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_RMX; 993 else 994 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC1; 995 } else 996 fp2_gen_cntl &= ~RADEON_FP2_SRC_SEL_CRTC2; 997 } else { 998 if ((rdev->family == CHIP_R200) || ASIC_IS_R300(rdev)) { 999 fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK; 1000 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2; 1001 } else 1002 fp2_gen_cntl |= RADEON_FP2_SRC_SEL_CRTC2; 1003 } 1004 1005 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); 1006 1007 if (rdev->is_atom_bios) 1008 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); 1009 else 1010 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); 1011 } 1012 1013 static void radeon_ext_tmds_enc_destroy(struct drm_encoder *encoder) 1014 { 1015 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1016 /* don't destroy the i2c bus record here, this will be done in radeon_i2c_fini */ 1017 kfree(radeon_encoder->enc_priv); 1018 drm_encoder_cleanup(encoder); 1019 kfree(radeon_encoder); 1020 } 1021 1022 static const struct drm_encoder_helper_funcs radeon_legacy_tmds_ext_helper_funcs = { 1023 .dpms = radeon_legacy_tmds_ext_dpms, 1024 .mode_fixup = radeon_legacy_mode_fixup, 1025 .prepare = radeon_legacy_tmds_ext_prepare, 1026 .mode_set = radeon_legacy_tmds_ext_mode_set, 1027 .commit = radeon_legacy_tmds_ext_commit, 1028 .disable = radeon_legacy_encoder_disable, 1029 }; 1030 1031 1032 static const struct drm_encoder_funcs radeon_legacy_tmds_ext_enc_funcs = { 1033 .destroy = radeon_ext_tmds_enc_destroy, 1034 }; 1035 1036 static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode) 1037 { 1038 struct drm_device *dev = encoder->dev; 1039 struct radeon_device *rdev = dev->dev_private; 1040 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1041 uint32_t fp2_gen_cntl = 0, crtc2_gen_cntl = 0, tv_dac_cntl = 0; 1042 uint32_t tv_master_cntl = 0; 1043 bool is_tv; 1044 DRM_DEBUG_KMS("\n"); 1045 1046 is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false; 1047 1048 if (rdev->family == CHIP_R200) 1049 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); 1050 else { 1051 if (is_tv) 1052 tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL); 1053 else 1054 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); 1055 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); 1056 } 1057 1058 switch (mode) { 1059 case DRM_MODE_DPMS_ON: 1060 if (rdev->family == CHIP_R200) { 1061 fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN); 1062 } else { 1063 if (is_tv) 1064 tv_master_cntl |= RADEON_TV_ON; 1065 else 1066 crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON; 1067 1068 if (rdev->family == CHIP_R420 || 1069 rdev->family == CHIP_R423 || 1070 rdev->family == CHIP_RV410) 1071 tv_dac_cntl &= ~(R420_TV_DAC_RDACPD | 1072 R420_TV_DAC_GDACPD | 1073 R420_TV_DAC_BDACPD | 1074 RADEON_TV_DAC_BGSLEEP); 1075 else 1076 tv_dac_cntl &= ~(RADEON_TV_DAC_RDACPD | 1077 RADEON_TV_DAC_GDACPD | 1078 RADEON_TV_DAC_BDACPD | 1079 RADEON_TV_DAC_BGSLEEP); 1080 } 1081 break; 1082 case DRM_MODE_DPMS_STANDBY: 1083 case DRM_MODE_DPMS_SUSPEND: 1084 case DRM_MODE_DPMS_OFF: 1085 if (rdev->family == CHIP_R200) 1086 fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN); 1087 else { 1088 if (is_tv) 1089 tv_master_cntl &= ~RADEON_TV_ON; 1090 else 1091 crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON; 1092 1093 if (rdev->family == CHIP_R420 || 1094 rdev->family == CHIP_R423 || 1095 rdev->family == CHIP_RV410) 1096 tv_dac_cntl |= (R420_TV_DAC_RDACPD | 1097 R420_TV_DAC_GDACPD | 1098 R420_TV_DAC_BDACPD | 1099 RADEON_TV_DAC_BGSLEEP); 1100 else 1101 tv_dac_cntl |= (RADEON_TV_DAC_RDACPD | 1102 RADEON_TV_DAC_GDACPD | 1103 RADEON_TV_DAC_BDACPD | 1104 RADEON_TV_DAC_BGSLEEP); 1105 } 1106 break; 1107 } 1108 1109 if (rdev->family == CHIP_R200) { 1110 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); 1111 } else { 1112 if (is_tv) 1113 WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl); 1114 /* handled in radeon_crtc_dpms() */ 1115 else if (!(rdev->flags & RADEON_SINGLE_CRTC)) 1116 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); 1117 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); 1118 } 1119 1120 if (rdev->is_atom_bios) 1121 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 1122 else 1123 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 1124 1125 } 1126 1127 static void radeon_legacy_tv_dac_prepare(struct drm_encoder *encoder) 1128 { 1129 struct radeon_device *rdev = encoder->dev->dev_private; 1130 1131 if (rdev->is_atom_bios) 1132 radeon_atom_output_lock(encoder, true); 1133 else 1134 radeon_combios_output_lock(encoder, true); 1135 radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_OFF); 1136 } 1137 1138 static void radeon_legacy_tv_dac_commit(struct drm_encoder *encoder) 1139 { 1140 struct radeon_device *rdev = encoder->dev->dev_private; 1141 1142 radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_ON); 1143 1144 if (rdev->is_atom_bios) 1145 radeon_atom_output_lock(encoder, true); 1146 else 1147 radeon_combios_output_lock(encoder, true); 1148 } 1149 1150 static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder, 1151 struct drm_display_mode *mode, 1152 struct drm_display_mode *adjusted_mode) 1153 { 1154 struct drm_device *dev = encoder->dev; 1155 struct radeon_device *rdev = dev->dev_private; 1156 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1157 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1158 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv; 1159 uint32_t tv_dac_cntl, gpiopad_a = 0, dac2_cntl, disp_output_cntl = 0; 1160 uint32_t disp_hw_debug = 0, fp2_gen_cntl = 0, disp_tv_out_cntl = 0; 1161 bool is_tv = false; 1162 1163 DRM_DEBUG_KMS("\n"); 1164 1165 is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false; 1166 1167 if (rdev->family != CHIP_R200) { 1168 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); 1169 if (rdev->family == CHIP_R420 || 1170 rdev->family == CHIP_R423 || 1171 rdev->family == CHIP_RV410) { 1172 tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK | 1173 RADEON_TV_DAC_BGADJ_MASK | 1174 R420_TV_DAC_DACADJ_MASK | 1175 R420_TV_DAC_RDACPD | 1176 R420_TV_DAC_GDACPD | 1177 R420_TV_DAC_BDACPD | 1178 R420_TV_DAC_TVENABLE); 1179 } else { 1180 tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK | 1181 RADEON_TV_DAC_BGADJ_MASK | 1182 RADEON_TV_DAC_DACADJ_MASK | 1183 RADEON_TV_DAC_RDACPD | 1184 RADEON_TV_DAC_GDACPD | 1185 RADEON_TV_DAC_BDACPD); 1186 } 1187 1188 tv_dac_cntl |= RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD; 1189 1190 if (is_tv) { 1191 if (tv_dac->tv_std == TV_STD_NTSC || 1192 tv_dac->tv_std == TV_STD_NTSC_J || 1193 tv_dac->tv_std == TV_STD_PAL_M || 1194 tv_dac->tv_std == TV_STD_PAL_60) 1195 tv_dac_cntl |= tv_dac->ntsc_tvdac_adj; 1196 else 1197 tv_dac_cntl |= tv_dac->pal_tvdac_adj; 1198 1199 if (tv_dac->tv_std == TV_STD_NTSC || 1200 tv_dac->tv_std == TV_STD_NTSC_J) 1201 tv_dac_cntl |= RADEON_TV_DAC_STD_NTSC; 1202 else 1203 tv_dac_cntl |= RADEON_TV_DAC_STD_PAL; 1204 } else 1205 tv_dac_cntl |= (RADEON_TV_DAC_STD_PS2 | 1206 tv_dac->ps2_tvdac_adj); 1207 1208 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); 1209 } 1210 1211 if (ASIC_IS_R300(rdev)) { 1212 gpiopad_a = RREG32(RADEON_GPIOPAD_A) | 1; 1213 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL); 1214 } else if (rdev->family != CHIP_R200) 1215 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG); 1216 else if (rdev->family == CHIP_R200) 1217 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); 1218 1219 if (rdev->family >= CHIP_R200) 1220 disp_tv_out_cntl = RREG32(RADEON_DISP_TV_OUT_CNTL); 1221 1222 if (is_tv) { 1223 uint32_t dac_cntl; 1224 1225 dac_cntl = RREG32(RADEON_DAC_CNTL); 1226 dac_cntl &= ~RADEON_DAC_TVO_EN; 1227 WREG32(RADEON_DAC_CNTL, dac_cntl); 1228 1229 if (ASIC_IS_R300(rdev)) 1230 gpiopad_a = RREG32(RADEON_GPIOPAD_A) & ~1; 1231 1232 dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~RADEON_DAC2_DAC2_CLK_SEL; 1233 if (radeon_crtc->crtc_id == 0) { 1234 if (ASIC_IS_R300(rdev)) { 1235 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK; 1236 disp_output_cntl |= (RADEON_DISP_TVDAC_SOURCE_CRTC | 1237 RADEON_DISP_TV_SOURCE_CRTC); 1238 } 1239 if (rdev->family >= CHIP_R200) { 1240 disp_tv_out_cntl &= ~RADEON_DISP_TV_PATH_SRC_CRTC2; 1241 } else { 1242 disp_hw_debug |= RADEON_CRT2_DISP1_SEL; 1243 } 1244 } else { 1245 if (ASIC_IS_R300(rdev)) { 1246 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK; 1247 disp_output_cntl |= RADEON_DISP_TV_SOURCE_CRTC; 1248 } 1249 if (rdev->family >= CHIP_R200) { 1250 disp_tv_out_cntl |= RADEON_DISP_TV_PATH_SRC_CRTC2; 1251 } else { 1252 disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL; 1253 } 1254 } 1255 WREG32(RADEON_DAC_CNTL2, dac2_cntl); 1256 } else { 1257 1258 dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC2_CLK_SEL; 1259 1260 if (radeon_crtc->crtc_id == 0) { 1261 if (ASIC_IS_R300(rdev)) { 1262 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK; 1263 disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC; 1264 } else if (rdev->family == CHIP_R200) { 1265 fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK | 1266 RADEON_FP2_DVO_RATE_SEL_SDR); 1267 } else 1268 disp_hw_debug |= RADEON_CRT2_DISP1_SEL; 1269 } else { 1270 if (ASIC_IS_R300(rdev)) { 1271 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK; 1272 disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC2; 1273 } else if (rdev->family == CHIP_R200) { 1274 fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK | 1275 RADEON_FP2_DVO_RATE_SEL_SDR); 1276 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2; 1277 } else 1278 disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL; 1279 } 1280 WREG32(RADEON_DAC_CNTL2, dac2_cntl); 1281 } 1282 1283 if (ASIC_IS_R300(rdev)) { 1284 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1); 1285 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl); 1286 } else if (rdev->family != CHIP_R200) 1287 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug); 1288 else if (rdev->family == CHIP_R200) 1289 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); 1290 1291 if (rdev->family >= CHIP_R200) 1292 WREG32(RADEON_DISP_TV_OUT_CNTL, disp_tv_out_cntl); 1293 1294 if (is_tv) 1295 radeon_legacy_tv_mode_set(encoder, mode, adjusted_mode); 1296 1297 if (rdev->is_atom_bios) 1298 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); 1299 else 1300 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); 1301 1302 } 1303 1304 static bool r300_legacy_tv_detect(struct drm_encoder *encoder, 1305 struct drm_connector *connector) 1306 { 1307 struct drm_device *dev = encoder->dev; 1308 struct radeon_device *rdev = dev->dev_private; 1309 uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl; 1310 uint32_t disp_output_cntl, gpiopad_a, tmp; 1311 bool found = false; 1312 1313 /* save regs needed */ 1314 gpiopad_a = RREG32(RADEON_GPIOPAD_A); 1315 dac_cntl2 = RREG32(RADEON_DAC_CNTL2); 1316 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); 1317 dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL); 1318 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); 1319 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL); 1320 1321 WREG32_P(RADEON_GPIOPAD_A, 0, ~1); 1322 1323 WREG32(RADEON_DAC_CNTL2, RADEON_DAC2_DAC2_CLK_SEL); 1324 1325 WREG32(RADEON_CRTC2_GEN_CNTL, 1326 RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_VSYNC_TRISTAT); 1327 1328 tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK; 1329 tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2; 1330 WREG32(RADEON_DISP_OUTPUT_CNTL, tmp); 1331 1332 WREG32(RADEON_DAC_EXT_CNTL, 1333 RADEON_DAC2_FORCE_BLANK_OFF_EN | 1334 RADEON_DAC2_FORCE_DATA_EN | 1335 RADEON_DAC_FORCE_DATA_SEL_RGB | 1336 (0xec << RADEON_DAC_FORCE_DATA_SHIFT)); 1337 1338 WREG32(RADEON_TV_DAC_CNTL, 1339 RADEON_TV_DAC_STD_NTSC | 1340 (8 << RADEON_TV_DAC_BGADJ_SHIFT) | 1341 (6 << RADEON_TV_DAC_DACADJ_SHIFT)); 1342 1343 RREG32(RADEON_TV_DAC_CNTL); 1344 mdelay(4); 1345 1346 WREG32(RADEON_TV_DAC_CNTL, 1347 RADEON_TV_DAC_NBLANK | 1348 RADEON_TV_DAC_NHOLD | 1349 RADEON_TV_MONITOR_DETECT_EN | 1350 RADEON_TV_DAC_STD_NTSC | 1351 (8 << RADEON_TV_DAC_BGADJ_SHIFT) | 1352 (6 << RADEON_TV_DAC_DACADJ_SHIFT)); 1353 1354 RREG32(RADEON_TV_DAC_CNTL); 1355 mdelay(6); 1356 1357 tmp = RREG32(RADEON_TV_DAC_CNTL); 1358 if ((tmp & RADEON_TV_DAC_GDACDET) != 0) { 1359 found = true; 1360 DRM_DEBUG_KMS("S-video TV connection detected\n"); 1361 } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) { 1362 found = true; 1363 DRM_DEBUG_KMS("Composite TV connection detected\n"); 1364 } 1365 1366 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); 1367 WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl); 1368 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); 1369 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl); 1370 WREG32(RADEON_DAC_CNTL2, dac_cntl2); 1371 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1); 1372 return found; 1373 } 1374 1375 static bool radeon_legacy_tv_detect(struct drm_encoder *encoder, 1376 struct drm_connector *connector) 1377 { 1378 struct drm_device *dev = encoder->dev; 1379 struct radeon_device *rdev = dev->dev_private; 1380 uint32_t tv_dac_cntl, dac_cntl2; 1381 uint32_t config_cntl, tv_pre_dac_mux_cntl, tv_master_cntl, tmp; 1382 bool found = false; 1383 1384 if (ASIC_IS_R300(rdev)) 1385 return r300_legacy_tv_detect(encoder, connector); 1386 1387 dac_cntl2 = RREG32(RADEON_DAC_CNTL2); 1388 tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL); 1389 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); 1390 config_cntl = RREG32(RADEON_CONFIG_CNTL); 1391 tv_pre_dac_mux_cntl = RREG32(RADEON_TV_PRE_DAC_MUX_CNTL); 1392 1393 tmp = dac_cntl2 & ~RADEON_DAC2_DAC2_CLK_SEL; 1394 WREG32(RADEON_DAC_CNTL2, tmp); 1395 1396 tmp = tv_master_cntl | RADEON_TV_ON; 1397 tmp &= ~(RADEON_TV_ASYNC_RST | 1398 RADEON_RESTART_PHASE_FIX | 1399 RADEON_CRT_FIFO_CE_EN | 1400 RADEON_TV_FIFO_CE_EN | 1401 RADEON_RE_SYNC_NOW_SEL_MASK); 1402 tmp |= RADEON_TV_FIFO_ASYNC_RST | RADEON_CRT_ASYNC_RST; 1403 WREG32(RADEON_TV_MASTER_CNTL, tmp); 1404 1405 tmp = RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD | 1406 RADEON_TV_MONITOR_DETECT_EN | RADEON_TV_DAC_STD_NTSC | 1407 (8 << RADEON_TV_DAC_BGADJ_SHIFT); 1408 1409 if (config_cntl & RADEON_CFG_ATI_REV_ID_MASK) 1410 tmp |= (4 << RADEON_TV_DAC_DACADJ_SHIFT); 1411 else 1412 tmp |= (8 << RADEON_TV_DAC_DACADJ_SHIFT); 1413 WREG32(RADEON_TV_DAC_CNTL, tmp); 1414 1415 tmp = RADEON_C_GRN_EN | RADEON_CMP_BLU_EN | 1416 RADEON_RED_MX_FORCE_DAC_DATA | 1417 RADEON_GRN_MX_FORCE_DAC_DATA | 1418 RADEON_BLU_MX_FORCE_DAC_DATA | 1419 (0x109 << RADEON_TV_FORCE_DAC_DATA_SHIFT); 1420 WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tmp); 1421 1422 mdelay(3); 1423 tmp = RREG32(RADEON_TV_DAC_CNTL); 1424 if (tmp & RADEON_TV_DAC_GDACDET) { 1425 found = true; 1426 DRM_DEBUG_KMS("S-video TV connection detected\n"); 1427 } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) { 1428 found = true; 1429 DRM_DEBUG_KMS("Composite TV connection detected\n"); 1430 } 1431 1432 WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tv_pre_dac_mux_cntl); 1433 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); 1434 WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl); 1435 WREG32(RADEON_DAC_CNTL2, dac_cntl2); 1436 return found; 1437 } 1438 1439 static bool radeon_legacy_ext_dac_detect(struct drm_encoder *encoder, 1440 struct drm_connector *connector) 1441 { 1442 struct drm_device *dev = encoder->dev; 1443 struct radeon_device *rdev = dev->dev_private; 1444 uint32_t gpio_monid, fp2_gen_cntl, disp_output_cntl, crtc2_gen_cntl; 1445 uint32_t disp_lin_trans_grph_a, disp_lin_trans_grph_b, disp_lin_trans_grph_c; 1446 uint32_t disp_lin_trans_grph_d, disp_lin_trans_grph_e, disp_lin_trans_grph_f; 1447 uint32_t tmp, crtc2_h_total_disp, crtc2_v_total_disp; 1448 uint32_t crtc2_h_sync_strt_wid, crtc2_v_sync_strt_wid; 1449 bool found = false; 1450 int i; 1451 1452 /* save the regs we need */ 1453 gpio_monid = RREG32(RADEON_GPIO_MONID); 1454 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); 1455 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL); 1456 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); 1457 disp_lin_trans_grph_a = RREG32(RADEON_DISP_LIN_TRANS_GRPH_A); 1458 disp_lin_trans_grph_b = RREG32(RADEON_DISP_LIN_TRANS_GRPH_B); 1459 disp_lin_trans_grph_c = RREG32(RADEON_DISP_LIN_TRANS_GRPH_C); 1460 disp_lin_trans_grph_d = RREG32(RADEON_DISP_LIN_TRANS_GRPH_D); 1461 disp_lin_trans_grph_e = RREG32(RADEON_DISP_LIN_TRANS_GRPH_E); 1462 disp_lin_trans_grph_f = RREG32(RADEON_DISP_LIN_TRANS_GRPH_F); 1463 crtc2_h_total_disp = RREG32(RADEON_CRTC2_H_TOTAL_DISP); 1464 crtc2_v_total_disp = RREG32(RADEON_CRTC2_V_TOTAL_DISP); 1465 crtc2_h_sync_strt_wid = RREG32(RADEON_CRTC2_H_SYNC_STRT_WID); 1466 crtc2_v_sync_strt_wid = RREG32(RADEON_CRTC2_V_SYNC_STRT_WID); 1467 1468 tmp = RREG32(RADEON_GPIO_MONID); 1469 tmp &= ~RADEON_GPIO_A_0; 1470 WREG32(RADEON_GPIO_MONID, tmp); 1471 1472 WREG32(RADEON_FP2_GEN_CNTL, (RADEON_FP2_ON | 1473 RADEON_FP2_PANEL_FORMAT | 1474 R200_FP2_SOURCE_SEL_TRANS_UNIT | 1475 RADEON_FP2_DVO_EN | 1476 R200_FP2_DVO_RATE_SEL_SDR)); 1477 1478 WREG32(RADEON_DISP_OUTPUT_CNTL, (RADEON_DISP_DAC_SOURCE_RMX | 1479 RADEON_DISP_TRANS_MATRIX_GRAPHICS)); 1480 1481 WREG32(RADEON_CRTC2_GEN_CNTL, (RADEON_CRTC2_EN | 1482 RADEON_CRTC2_DISP_REQ_EN_B)); 1483 1484 WREG32(RADEON_DISP_LIN_TRANS_GRPH_A, 0x00000000); 1485 WREG32(RADEON_DISP_LIN_TRANS_GRPH_B, 0x000003f0); 1486 WREG32(RADEON_DISP_LIN_TRANS_GRPH_C, 0x00000000); 1487 WREG32(RADEON_DISP_LIN_TRANS_GRPH_D, 0x000003f0); 1488 WREG32(RADEON_DISP_LIN_TRANS_GRPH_E, 0x00000000); 1489 WREG32(RADEON_DISP_LIN_TRANS_GRPH_F, 0x000003f0); 1490 1491 WREG32(RADEON_CRTC2_H_TOTAL_DISP, 0x01000008); 1492 WREG32(RADEON_CRTC2_H_SYNC_STRT_WID, 0x00000800); 1493 WREG32(RADEON_CRTC2_V_TOTAL_DISP, 0x00080001); 1494 WREG32(RADEON_CRTC2_V_SYNC_STRT_WID, 0x00000080); 1495 1496 for (i = 0; i < 200; i++) { 1497 tmp = RREG32(RADEON_GPIO_MONID); 1498 if (tmp & RADEON_GPIO_Y_0) 1499 found = true; 1500 1501 if (found) 1502 break; 1503 1504 if (!drm_can_sleep()) 1505 mdelay(1); 1506 else 1507 msleep(1); 1508 } 1509 1510 /* restore the regs we used */ 1511 WREG32(RADEON_DISP_LIN_TRANS_GRPH_A, disp_lin_trans_grph_a); 1512 WREG32(RADEON_DISP_LIN_TRANS_GRPH_B, disp_lin_trans_grph_b); 1513 WREG32(RADEON_DISP_LIN_TRANS_GRPH_C, disp_lin_trans_grph_c); 1514 WREG32(RADEON_DISP_LIN_TRANS_GRPH_D, disp_lin_trans_grph_d); 1515 WREG32(RADEON_DISP_LIN_TRANS_GRPH_E, disp_lin_trans_grph_e); 1516 WREG32(RADEON_DISP_LIN_TRANS_GRPH_F, disp_lin_trans_grph_f); 1517 WREG32(RADEON_CRTC2_H_TOTAL_DISP, crtc2_h_total_disp); 1518 WREG32(RADEON_CRTC2_V_TOTAL_DISP, crtc2_v_total_disp); 1519 WREG32(RADEON_CRTC2_H_SYNC_STRT_WID, crtc2_h_sync_strt_wid); 1520 WREG32(RADEON_CRTC2_V_SYNC_STRT_WID, crtc2_v_sync_strt_wid); 1521 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); 1522 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl); 1523 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); 1524 WREG32(RADEON_GPIO_MONID, gpio_monid); 1525 1526 return found; 1527 } 1528 1529 static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder *encoder, 1530 struct drm_connector *connector) 1531 { 1532 struct drm_device *dev = encoder->dev; 1533 struct radeon_device *rdev = dev->dev_private; 1534 uint32_t crtc2_gen_cntl = 0, tv_dac_cntl, dac_cntl2, dac_ext_cntl; 1535 uint32_t gpiopad_a = 0, pixclks_cntl, tmp; 1536 uint32_t disp_output_cntl = 0, disp_hw_debug = 0, crtc_ext_cntl = 0; 1537 enum drm_connector_status found = connector_status_disconnected; 1538 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1539 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv; 1540 bool color = true; 1541 struct drm_crtc *crtc; 1542 1543 /* find out if crtc2 is in use or if this encoder is using it */ 1544 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 1545 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1546 if ((radeon_crtc->crtc_id == 1) && crtc->enabled) { 1547 if (encoder->crtc != crtc) { 1548 return connector_status_disconnected; 1549 } 1550 } 1551 } 1552 1553 if (connector->connector_type == DRM_MODE_CONNECTOR_SVIDEO || 1554 connector->connector_type == DRM_MODE_CONNECTOR_Composite || 1555 connector->connector_type == DRM_MODE_CONNECTOR_9PinDIN) { 1556 bool tv_detect; 1557 1558 if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT)) 1559 return connector_status_disconnected; 1560 1561 tv_detect = radeon_legacy_tv_detect(encoder, connector); 1562 if (tv_detect && tv_dac) 1563 found = connector_status_connected; 1564 return found; 1565 } 1566 1567 /* don't probe if the encoder is being used for something else not CRT related */ 1568 if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_CRT_SUPPORT)) { 1569 DRM_INFO("not detecting due to %08x\n", radeon_encoder->active_device); 1570 return connector_status_disconnected; 1571 } 1572 1573 /* R200 uses an external DAC for secondary DAC */ 1574 if (rdev->family == CHIP_R200) { 1575 if (radeon_legacy_ext_dac_detect(encoder, connector)) 1576 found = connector_status_connected; 1577 return found; 1578 } 1579 1580 /* save the regs we need */ 1581 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL); 1582 1583 if (rdev->flags & RADEON_SINGLE_CRTC) { 1584 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); 1585 } else { 1586 if (ASIC_IS_R300(rdev)) { 1587 gpiopad_a = RREG32(RADEON_GPIOPAD_A); 1588 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL); 1589 } else { 1590 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG); 1591 } 1592 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); 1593 } 1594 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); 1595 dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL); 1596 dac_cntl2 = RREG32(RADEON_DAC_CNTL2); 1597 1598 tmp = pixclks_cntl & ~(RADEON_PIX2CLK_ALWAYS_ONb 1599 | RADEON_PIX2CLK_DAC_ALWAYS_ONb); 1600 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); 1601 1602 if (rdev->flags & RADEON_SINGLE_CRTC) { 1603 tmp = crtc_ext_cntl | RADEON_CRTC_CRT_ON; 1604 WREG32(RADEON_CRTC_EXT_CNTL, tmp); 1605 } else { 1606 tmp = crtc2_gen_cntl & ~RADEON_CRTC2_PIX_WIDTH_MASK; 1607 tmp |= RADEON_CRTC2_CRT2_ON | 1608 (2 << RADEON_CRTC2_PIX_WIDTH_SHIFT); 1609 WREG32(RADEON_CRTC2_GEN_CNTL, tmp); 1610 1611 if (ASIC_IS_R300(rdev)) { 1612 WREG32_P(RADEON_GPIOPAD_A, 1, ~1); 1613 tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK; 1614 tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2; 1615 WREG32(RADEON_DISP_OUTPUT_CNTL, tmp); 1616 } else { 1617 tmp = disp_hw_debug & ~RADEON_CRT2_DISP1_SEL; 1618 WREG32(RADEON_DISP_HW_DEBUG, tmp); 1619 } 1620 } 1621 1622 tmp = RADEON_TV_DAC_NBLANK | 1623 RADEON_TV_DAC_NHOLD | 1624 RADEON_TV_MONITOR_DETECT_EN | 1625 RADEON_TV_DAC_STD_PS2; 1626 1627 WREG32(RADEON_TV_DAC_CNTL, tmp); 1628 1629 tmp = RADEON_DAC2_FORCE_BLANK_OFF_EN | 1630 RADEON_DAC2_FORCE_DATA_EN; 1631 1632 if (color) 1633 tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB; 1634 else 1635 tmp |= RADEON_DAC_FORCE_DATA_SEL_G; 1636 1637 if (ASIC_IS_R300(rdev)) 1638 tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT); 1639 else 1640 tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT); 1641 1642 WREG32(RADEON_DAC_EXT_CNTL, tmp); 1643 1644 tmp = dac_cntl2 | RADEON_DAC2_DAC2_CLK_SEL | RADEON_DAC2_CMP_EN; 1645 WREG32(RADEON_DAC_CNTL2, tmp); 1646 1647 mdelay(10); 1648 1649 if (ASIC_IS_R300(rdev)) { 1650 if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUT_B) 1651 found = connector_status_connected; 1652 } else { 1653 if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUTPUT) 1654 found = connector_status_connected; 1655 } 1656 1657 /* restore regs we used */ 1658 WREG32(RADEON_DAC_CNTL2, dac_cntl2); 1659 WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl); 1660 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); 1661 1662 if (rdev->flags & RADEON_SINGLE_CRTC) { 1663 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); 1664 } else { 1665 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); 1666 if (ASIC_IS_R300(rdev)) { 1667 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl); 1668 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1); 1669 } else { 1670 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug); 1671 } 1672 } 1673 1674 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl); 1675 1676 return found; 1677 1678 } 1679 1680 static const struct drm_encoder_helper_funcs radeon_legacy_tv_dac_helper_funcs = { 1681 .dpms = radeon_legacy_tv_dac_dpms, 1682 .mode_fixup = radeon_legacy_mode_fixup, 1683 .prepare = radeon_legacy_tv_dac_prepare, 1684 .mode_set = radeon_legacy_tv_dac_mode_set, 1685 .commit = radeon_legacy_tv_dac_commit, 1686 .detect = radeon_legacy_tv_dac_detect, 1687 .disable = radeon_legacy_encoder_disable, 1688 }; 1689 1690 1691 static const struct drm_encoder_funcs radeon_legacy_tv_dac_enc_funcs = { 1692 .destroy = radeon_enc_destroy, 1693 }; 1694 1695 1696 static struct radeon_encoder_int_tmds *radeon_legacy_get_tmds_info(struct radeon_encoder *encoder) 1697 { 1698 struct drm_device *dev = encoder->base.dev; 1699 struct radeon_device *rdev = dev->dev_private; 1700 struct radeon_encoder_int_tmds *tmds = NULL; 1701 bool ret; 1702 1703 tmds = kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL); 1704 1705 if (!tmds) 1706 return NULL; 1707 1708 if (rdev->is_atom_bios) 1709 ret = radeon_atombios_get_tmds_info(encoder, tmds); 1710 else 1711 ret = radeon_legacy_get_tmds_info_from_combios(encoder, tmds); 1712 1713 if (ret == false) 1714 radeon_legacy_get_tmds_info_from_table(encoder, tmds); 1715 1716 return tmds; 1717 } 1718 1719 static struct radeon_encoder_ext_tmds *radeon_legacy_get_ext_tmds_info(struct radeon_encoder *encoder) 1720 { 1721 struct drm_device *dev = encoder->base.dev; 1722 struct radeon_device *rdev = dev->dev_private; 1723 struct radeon_encoder_ext_tmds *tmds = NULL; 1724 bool ret; 1725 1726 if (rdev->is_atom_bios) 1727 return NULL; 1728 1729 tmds = kzalloc(sizeof(struct radeon_encoder_ext_tmds), GFP_KERNEL); 1730 1731 if (!tmds) 1732 return NULL; 1733 1734 ret = radeon_legacy_get_ext_tmds_info_from_combios(encoder, tmds); 1735 1736 if (ret == false) 1737 radeon_legacy_get_ext_tmds_info_from_table(encoder, tmds); 1738 1739 return tmds; 1740 } 1741 1742 void 1743 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum, uint32_t supported_device) 1744 { 1745 struct radeon_device *rdev = dev->dev_private; 1746 struct drm_encoder *encoder; 1747 struct radeon_encoder *radeon_encoder; 1748 1749 /* see if we already added it */ 1750 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1751 radeon_encoder = to_radeon_encoder(encoder); 1752 if (radeon_encoder->encoder_enum == encoder_enum) { 1753 radeon_encoder->devices |= supported_device; 1754 return; 1755 } 1756 1757 } 1758 1759 /* add a new one */ 1760 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL); 1761 if (!radeon_encoder) 1762 return; 1763 1764 encoder = &radeon_encoder->base; 1765 if (rdev->flags & RADEON_SINGLE_CRTC) 1766 encoder->possible_crtcs = 0x1; 1767 else 1768 encoder->possible_crtcs = 0x3; 1769 1770 radeon_encoder->enc_priv = NULL; 1771 1772 radeon_encoder->encoder_enum = encoder_enum; 1773 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 1774 radeon_encoder->devices = supported_device; 1775 radeon_encoder->rmx_type = RMX_OFF; 1776 1777 switch (radeon_encoder->encoder_id) { 1778 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1779 encoder->possible_crtcs = 0x1; 1780 drm_encoder_init(dev, encoder, &radeon_legacy_lvds_enc_funcs, DRM_MODE_ENCODER_LVDS); 1781 drm_encoder_helper_add(encoder, &radeon_legacy_lvds_helper_funcs); 1782 if (rdev->is_atom_bios) 1783 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); 1784 else 1785 radeon_encoder->enc_priv = radeon_combios_get_lvds_info(radeon_encoder); 1786 radeon_encoder->rmx_type = RMX_FULL; 1787 break; 1788 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1789 drm_encoder_init(dev, encoder, &radeon_legacy_tmds_int_enc_funcs, DRM_MODE_ENCODER_TMDS); 1790 drm_encoder_helper_add(encoder, &radeon_legacy_tmds_int_helper_funcs); 1791 radeon_encoder->enc_priv = radeon_legacy_get_tmds_info(radeon_encoder); 1792 break; 1793 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1794 drm_encoder_init(dev, encoder, &radeon_legacy_primary_dac_enc_funcs, DRM_MODE_ENCODER_DAC); 1795 drm_encoder_helper_add(encoder, &radeon_legacy_primary_dac_helper_funcs); 1796 if (rdev->is_atom_bios) 1797 radeon_encoder->enc_priv = radeon_atombios_get_primary_dac_info(radeon_encoder); 1798 else 1799 radeon_encoder->enc_priv = radeon_combios_get_primary_dac_info(radeon_encoder); 1800 break; 1801 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1802 drm_encoder_init(dev, encoder, &radeon_legacy_tv_dac_enc_funcs, DRM_MODE_ENCODER_TVDAC); 1803 drm_encoder_helper_add(encoder, &radeon_legacy_tv_dac_helper_funcs); 1804 if (rdev->is_atom_bios) 1805 radeon_encoder->enc_priv = radeon_atombios_get_tv_dac_info(radeon_encoder); 1806 else 1807 radeon_encoder->enc_priv = radeon_combios_get_tv_dac_info(radeon_encoder); 1808 break; 1809 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1810 drm_encoder_init(dev, encoder, &radeon_legacy_tmds_ext_enc_funcs, DRM_MODE_ENCODER_TMDS); 1811 drm_encoder_helper_add(encoder, &radeon_legacy_tmds_ext_helper_funcs); 1812 if (!rdev->is_atom_bios) 1813 radeon_encoder->enc_priv = radeon_legacy_get_ext_tmds_info(radeon_encoder); 1814 break; 1815 } 1816 } 1817
Indexes created Fri Oct 17 03:10:13 GMT 2025