radeon_legacy_tv.c revision 1.2.32.1
1 /* $NetBSD: radeon_legacy_tv.c,v 1.2.32.1 2019/06/10 22:08:26 christos Exp $ */ 2 3 #include <sys/cdefs.h> 4 __KERNEL_RCSID(0, "$NetBSD: radeon_legacy_tv.c,v 1.2.32.1 2019/06/10 22:08:26 christos Exp $"); 5 6 #include <drm/drmP.h> 7 #include <drm/drm_crtc_helper.h> 8 #include "radeon.h" 9 10 /* 11 * Integrated TV out support based on the GATOS code by 12 * Federico Ulivi <fulivi (at) lycos.com> 13 */ 14 15 16 /* 17 * Limits of h/v positions (hPos & vPos) 18 */ 19 #define MAX_H_POSITION 5 /* Range: [-5..5], negative is on the left, 0 is default, positive is on the right */ 20 #define MAX_V_POSITION 5 /* Range: [-5..5], negative is up, 0 is default, positive is down */ 21 22 /* 23 * Unit for hPos (in TV clock periods) 24 */ 25 #define H_POS_UNIT 10 26 27 /* 28 * Indexes in h. code timing table for horizontal line position adjustment 29 */ 30 #define H_TABLE_POS1 6 31 #define H_TABLE_POS2 8 32 33 /* 34 * Limits of hor. size (hSize) 35 */ 36 #define MAX_H_SIZE 5 /* Range: [-5..5], negative is smaller, positive is larger */ 37 38 /* tv standard constants */ 39 #define NTSC_TV_CLOCK_T 233 40 #define NTSC_TV_VFTOTAL 1 41 #define NTSC_TV_LINES_PER_FRAME 525 42 #define NTSC_TV_ZERO_H_SIZE 479166 43 #define NTSC_TV_H_SIZE_UNIT 9478 44 45 #define PAL_TV_CLOCK_T 188 46 #define PAL_TV_VFTOTAL 3 47 #define PAL_TV_LINES_PER_FRAME 625 48 #define PAL_TV_ZERO_H_SIZE 473200 49 #define PAL_TV_H_SIZE_UNIT 9360 50 51 /* tv pll setting for 27 mhz ref clk */ 52 #define NTSC_TV_PLL_M_27 22 53 #define NTSC_TV_PLL_N_27 175 54 #define NTSC_TV_PLL_P_27 5 55 56 #define PAL_TV_PLL_M_27 113 57 #define PAL_TV_PLL_N_27 668 58 #define PAL_TV_PLL_P_27 3 59 60 /* tv pll setting for 14 mhz ref clk */ 61 #define NTSC_TV_PLL_M_14 33 62 #define NTSC_TV_PLL_N_14 693 63 #define NTSC_TV_PLL_P_14 7 64 65 #define PAL_TV_PLL_M_14 19 66 #define PAL_TV_PLL_N_14 353 67 #define PAL_TV_PLL_P_14 5 68 69 #define VERT_LEAD_IN_LINES 2 70 #define FRAC_BITS 0xe 71 #define FRAC_MASK 0x3fff 72 73 struct radeon_tv_mode_constants { 74 uint16_t hor_resolution; 75 uint16_t ver_resolution; 76 enum radeon_tv_std standard; 77 uint16_t hor_total; 78 uint16_t ver_total; 79 uint16_t hor_start; 80 uint16_t hor_syncstart; 81 uint16_t ver_syncstart; 82 unsigned def_restart; 83 uint16_t crtcPLL_N; 84 uint8_t crtcPLL_M; 85 uint8_t crtcPLL_post_div; 86 unsigned pix_to_tv; 87 }; 88 89 static const uint16_t hor_timing_NTSC[MAX_H_CODE_TIMING_LEN] = { 90 0x0007, 91 0x003f, 92 0x0263, 93 0x0a24, 94 0x2a6b, 95 0x0a36, 96 0x126d, /* H_TABLE_POS1 */ 97 0x1bfe, 98 0x1a8f, /* H_TABLE_POS2 */ 99 0x1ec7, 100 0x3863, 101 0x1bfe, 102 0x1bfe, 103 0x1a2a, 104 0x1e95, 105 0x0e31, 106 0x201b, 107 0 108 }; 109 110 static const uint16_t vert_timing_NTSC[MAX_V_CODE_TIMING_LEN] = { 111 0x2001, 112 0x200d, 113 0x1006, 114 0x0c06, 115 0x1006, 116 0x1818, 117 0x21e3, 118 0x1006, 119 0x0c06, 120 0x1006, 121 0x1817, 122 0x21d4, 123 0x0002, 124 0 125 }; 126 127 static const uint16_t hor_timing_PAL[MAX_H_CODE_TIMING_LEN] = { 128 0x0007, 129 0x0058, 130 0x027c, 131 0x0a31, 132 0x2a77, 133 0x0a95, 134 0x124f, /* H_TABLE_POS1 */ 135 0x1bfe, 136 0x1b22, /* H_TABLE_POS2 */ 137 0x1ef9, 138 0x387c, 139 0x1bfe, 140 0x1bfe, 141 0x1b31, 142 0x1eb5, 143 0x0e43, 144 0x201b, 145 0 146 }; 147 148 static const uint16_t vert_timing_PAL[MAX_V_CODE_TIMING_LEN] = { 149 0x2001, 150 0x200c, 151 0x1005, 152 0x0c05, 153 0x1005, 154 0x1401, 155 0x1821, 156 0x2240, 157 0x1005, 158 0x0c05, 159 0x1005, 160 0x1401, 161 0x1822, 162 0x2230, 163 0x0002, 164 0 165 }; 166 167 /********************************************************************** 168 * 169 * availableModes 170 * 171 * Table of all allowed modes for tv output 172 * 173 **********************************************************************/ 174 static const struct radeon_tv_mode_constants available_tv_modes[] = { 175 { /* NTSC timing for 27 Mhz ref clk */ 176 800, /* horResolution */ 177 600, /* verResolution */ 178 TV_STD_NTSC, /* standard */ 179 990, /* horTotal */ 180 740, /* verTotal */ 181 813, /* horStart */ 182 824, /* horSyncStart */ 183 632, /* verSyncStart */ 184 625592, /* defRestart */ 185 592, /* crtcPLL_N */ 186 91, /* crtcPLL_M */ 187 4, /* crtcPLL_postDiv */ 188 1022, /* pixToTV */ 189 }, 190 { /* PAL timing for 27 Mhz ref clk */ 191 800, /* horResolution */ 192 600, /* verResolution */ 193 TV_STD_PAL, /* standard */ 194 1144, /* horTotal */ 195 706, /* verTotal */ 196 812, /* horStart */ 197 824, /* horSyncStart */ 198 669, /* verSyncStart */ 199 696700, /* defRestart */ 200 1382, /* crtcPLL_N */ 201 231, /* crtcPLL_M */ 202 4, /* crtcPLL_postDiv */ 203 759, /* pixToTV */ 204 }, 205 { /* NTSC timing for 14 Mhz ref clk */ 206 800, /* horResolution */ 207 600, /* verResolution */ 208 TV_STD_NTSC, /* standard */ 209 1018, /* horTotal */ 210 727, /* verTotal */ 211 813, /* horStart */ 212 840, /* horSyncStart */ 213 633, /* verSyncStart */ 214 630627, /* defRestart */ 215 347, /* crtcPLL_N */ 216 14, /* crtcPLL_M */ 217 8, /* crtcPLL_postDiv */ 218 1022, /* pixToTV */ 219 }, 220 { /* PAL timing for 14 Mhz ref clk */ 221 800, /* horResolution */ 222 600, /* verResolution */ 223 TV_STD_PAL, /* standard */ 224 1131, /* horTotal */ 225 742, /* verTotal */ 226 813, /* horStart */ 227 840, /* horSyncStart */ 228 633, /* verSyncStart */ 229 708369, /* defRestart */ 230 211, /* crtcPLL_N */ 231 9, /* crtcPLL_M */ 232 8, /* crtcPLL_postDiv */ 233 759, /* pixToTV */ 234 }, 235 }; 236 237 #define N_AVAILABLE_MODES ARRAY_SIZE(available_tv_modes) 238 239 static const struct radeon_tv_mode_constants *radeon_legacy_tv_get_std_mode(struct radeon_encoder *radeon_encoder, 240 uint16_t *pll_ref_freq) 241 { 242 struct drm_device *dev = radeon_encoder->base.dev; 243 struct radeon_device *rdev = dev->dev_private; 244 struct radeon_crtc *radeon_crtc; 245 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv; 246 const struct radeon_tv_mode_constants *const_ptr; 247 struct radeon_pll *pll; 248 249 radeon_crtc = to_radeon_crtc(radeon_encoder->base.crtc); 250 if (radeon_crtc->crtc_id == 1) 251 pll = &rdev->clock.p2pll; 252 else 253 pll = &rdev->clock.p1pll; 254 255 if (pll_ref_freq) 256 *pll_ref_freq = pll->reference_freq; 257 258 if (tv_dac->tv_std == TV_STD_NTSC || 259 tv_dac->tv_std == TV_STD_NTSC_J || 260 tv_dac->tv_std == TV_STD_PAL_M) { 261 if (pll->reference_freq == 2700) 262 const_ptr = &available_tv_modes[0]; 263 else 264 const_ptr = &available_tv_modes[2]; 265 } else { 266 if (pll->reference_freq == 2700) 267 const_ptr = &available_tv_modes[1]; 268 else 269 const_ptr = &available_tv_modes[3]; 270 } 271 return const_ptr; 272 } 273 274 static long YCOEF_value[5] = { 2, 2, 0, 4, 0 }; 275 static long YCOEF_EN_value[5] = { 1, 1, 0, 1, 0 }; 276 static long SLOPE_value[5] = { 1, 2, 2, 4, 8 }; 277 static long SLOPE_limit[5] = { 6, 5, 4, 3, 2 }; 278 279 static void radeon_wait_pll_lock(struct drm_encoder *encoder, unsigned n_tests, 280 unsigned n_wait_loops, unsigned cnt_threshold) 281 { 282 struct drm_device *dev = encoder->dev; 283 struct radeon_device *rdev = dev->dev_private; 284 uint32_t save_pll_test; 285 unsigned int i, j; 286 287 WREG32(RADEON_TEST_DEBUG_MUX, (RREG32(RADEON_TEST_DEBUG_MUX) & 0xffff60ff) | 0x100); 288 save_pll_test = RREG32_PLL(RADEON_PLL_TEST_CNTL); 289 WREG32_PLL(RADEON_PLL_TEST_CNTL, save_pll_test & ~RADEON_PLL_MASK_READ_B); 290 291 WREG8(RADEON_CLOCK_CNTL_INDEX, RADEON_PLL_TEST_CNTL); 292 for (i = 0; i < n_tests; i++) { 293 WREG8(RADEON_CLOCK_CNTL_DATA + 3, 0); 294 for (j = 0; j < n_wait_loops; j++) 295 if (RREG8(RADEON_CLOCK_CNTL_DATA + 3) >= cnt_threshold) 296 break; 297 } 298 WREG32_PLL(RADEON_PLL_TEST_CNTL, save_pll_test); 299 WREG32(RADEON_TEST_DEBUG_MUX, RREG32(RADEON_TEST_DEBUG_MUX) & 0xffffe0ff); 300 } 301 302 303 static void radeon_legacy_tv_write_fifo(struct radeon_encoder *radeon_encoder, 304 uint16_t addr, uint32_t value) 305 { 306 struct drm_device *dev = radeon_encoder->base.dev; 307 struct radeon_device *rdev = dev->dev_private; 308 uint32_t tmp; 309 int i = 0; 310 311 WREG32(RADEON_TV_HOST_WRITE_DATA, value); 312 313 WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr); 314 WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr | RADEON_HOST_FIFO_WT); 315 316 do { 317 tmp = RREG32(RADEON_TV_HOST_RD_WT_CNTL); 318 if ((tmp & RADEON_HOST_FIFO_WT_ACK) == 0) 319 break; 320 i++; 321 } while (i < 10000); 322 WREG32(RADEON_TV_HOST_RD_WT_CNTL, 0); 323 } 324 325 #if 0 /* included for completeness */ 326 static uint32_t radeon_legacy_tv_read_fifo(struct radeon_encoder *radeon_encoder, uint16_t addr) 327 { 328 struct drm_device *dev = radeon_encoder->base.dev; 329 struct radeon_device *rdev = dev->dev_private; 330 uint32_t tmp; 331 int i = 0; 332 333 WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr); 334 WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr | RADEON_HOST_FIFO_RD); 335 336 do { 337 tmp = RREG32(RADEON_TV_HOST_RD_WT_CNTL); 338 if ((tmp & RADEON_HOST_FIFO_RD_ACK) == 0) 339 break; 340 i++; 341 } while (i < 10000); 342 WREG32(RADEON_TV_HOST_RD_WT_CNTL, 0); 343 return RREG32(RADEON_TV_HOST_READ_DATA); 344 } 345 #endif 346 347 static uint16_t radeon_get_htiming_tables_addr(uint32_t tv_uv_adr) 348 { 349 uint16_t h_table; 350 351 switch ((tv_uv_adr & RADEON_HCODE_TABLE_SEL_MASK) >> RADEON_HCODE_TABLE_SEL_SHIFT) { 352 case 0: 353 h_table = RADEON_TV_MAX_FIFO_ADDR_INTERNAL; 354 break; 355 case 1: 356 h_table = ((tv_uv_adr & RADEON_TABLE1_BOT_ADR_MASK) >> RADEON_TABLE1_BOT_ADR_SHIFT) * 2; 357 break; 358 case 2: 359 h_table = ((tv_uv_adr & RADEON_TABLE3_TOP_ADR_MASK) >> RADEON_TABLE3_TOP_ADR_SHIFT) * 2; 360 break; 361 default: 362 h_table = 0; 363 break; 364 } 365 return h_table; 366 } 367 368 static uint16_t radeon_get_vtiming_tables_addr(uint32_t tv_uv_adr) 369 { 370 uint16_t v_table; 371 372 switch ((tv_uv_adr & RADEON_VCODE_TABLE_SEL_MASK) >> RADEON_VCODE_TABLE_SEL_SHIFT) { 373 case 0: 374 v_table = ((tv_uv_adr & RADEON_MAX_UV_ADR_MASK) >> RADEON_MAX_UV_ADR_SHIFT) * 2 + 1; 375 break; 376 case 1: 377 v_table = ((tv_uv_adr & RADEON_TABLE1_BOT_ADR_MASK) >> RADEON_TABLE1_BOT_ADR_SHIFT) * 2 + 1; 378 break; 379 case 2: 380 v_table = ((tv_uv_adr & RADEON_TABLE3_TOP_ADR_MASK) >> RADEON_TABLE3_TOP_ADR_SHIFT) * 2 + 1; 381 break; 382 default: 383 v_table = 0; 384 break; 385 } 386 return v_table; 387 } 388 389 static void radeon_restore_tv_timing_tables(struct radeon_encoder *radeon_encoder) 390 { 391 struct drm_device *dev = radeon_encoder->base.dev; 392 struct radeon_device *rdev = dev->dev_private; 393 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv; 394 uint16_t h_table, v_table; 395 uint32_t tmp; 396 int i; 397 398 WREG32(RADEON_TV_UV_ADR, tv_dac->tv.tv_uv_adr); 399 h_table = radeon_get_htiming_tables_addr(tv_dac->tv.tv_uv_adr); 400 v_table = radeon_get_vtiming_tables_addr(tv_dac->tv.tv_uv_adr); 401 402 for (i = 0; i < MAX_H_CODE_TIMING_LEN; i += 2, h_table--) { 403 tmp = ((uint32_t)tv_dac->tv.h_code_timing[i] << 14) | ((uint32_t)tv_dac->tv.h_code_timing[i+1]); 404 radeon_legacy_tv_write_fifo(radeon_encoder, h_table, tmp); 405 if (tv_dac->tv.h_code_timing[i] == 0 || tv_dac->tv.h_code_timing[i + 1] == 0) 406 break; 407 } 408 for (i = 0; i < MAX_V_CODE_TIMING_LEN; i += 2, v_table++) { 409 tmp = ((uint32_t)tv_dac->tv.v_code_timing[i+1] << 14) | ((uint32_t)tv_dac->tv.v_code_timing[i]); 410 radeon_legacy_tv_write_fifo(radeon_encoder, v_table, tmp); 411 if (tv_dac->tv.v_code_timing[i] == 0 || tv_dac->tv.v_code_timing[i + 1] == 0) 412 break; 413 } 414 } 415 416 static void radeon_legacy_write_tv_restarts(struct radeon_encoder *radeon_encoder) 417 { 418 struct drm_device *dev = radeon_encoder->base.dev; 419 struct radeon_device *rdev = dev->dev_private; 420 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv; 421 WREG32(RADEON_TV_FRESTART, tv_dac->tv.frestart); 422 WREG32(RADEON_TV_HRESTART, tv_dac->tv.hrestart); 423 WREG32(RADEON_TV_VRESTART, tv_dac->tv.vrestart); 424 } 425 426 static bool radeon_legacy_tv_init_restarts(struct drm_encoder *encoder) 427 { 428 struct drm_device *dev = encoder->dev; 429 struct radeon_device *rdev = dev->dev_private; 430 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 431 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv; 432 struct radeon_crtc *radeon_crtc; 433 int restart; 434 unsigned int h_total, v_total, f_total; 435 int v_offset, h_offset; 436 u16 p1, p2, h_inc; 437 bool h_changed; 438 const struct radeon_tv_mode_constants *const_ptr; 439 struct radeon_pll *pll __unused; 440 441 radeon_crtc = to_radeon_crtc(radeon_encoder->base.crtc); 442 if (radeon_crtc->crtc_id == 1) 443 pll = &rdev->clock.p2pll; 444 else 445 pll = &rdev->clock.p1pll; 446 447 const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, NULL); 448 if (!const_ptr) 449 return false; 450 451 h_total = const_ptr->hor_total; 452 v_total = const_ptr->ver_total; 453 454 if (tv_dac->tv_std == TV_STD_NTSC || 455 tv_dac->tv_std == TV_STD_NTSC_J || 456 tv_dac->tv_std == TV_STD_PAL_M || 457 tv_dac->tv_std == TV_STD_PAL_60) 458 f_total = NTSC_TV_VFTOTAL + 1; 459 else 460 f_total = PAL_TV_VFTOTAL + 1; 461 462 /* adjust positions 1&2 in hor. cod timing table */ 463 h_offset = tv_dac->h_pos * H_POS_UNIT; 464 465 if (tv_dac->tv_std == TV_STD_NTSC || 466 tv_dac->tv_std == TV_STD_NTSC_J || 467 tv_dac->tv_std == TV_STD_PAL_M) { 468 h_offset -= 50; 469 p1 = hor_timing_NTSC[H_TABLE_POS1]; 470 p2 = hor_timing_NTSC[H_TABLE_POS2]; 471 } else { 472 p1 = hor_timing_PAL[H_TABLE_POS1]; 473 p2 = hor_timing_PAL[H_TABLE_POS2]; 474 } 475 476 p1 = (u16)((int)p1 + h_offset); 477 p2 = (u16)((int)p2 - h_offset); 478 479 h_changed = (p1 != tv_dac->tv.h_code_timing[H_TABLE_POS1] || 480 p2 != tv_dac->tv.h_code_timing[H_TABLE_POS2]); 481 482 tv_dac->tv.h_code_timing[H_TABLE_POS1] = p1; 483 tv_dac->tv.h_code_timing[H_TABLE_POS2] = p2; 484 485 /* Convert hOffset from n. of TV clock periods to n. of CRTC clock periods (CRTC pixels) */ 486 h_offset = (h_offset * (int)(const_ptr->pix_to_tv)) / 1000; 487 488 /* adjust restart */ 489 restart = const_ptr->def_restart; 490 491 /* 492 * convert v_pos TV lines to n. of CRTC pixels 493 */ 494 if (tv_dac->tv_std == TV_STD_NTSC || 495 tv_dac->tv_std == TV_STD_NTSC_J || 496 tv_dac->tv_std == TV_STD_PAL_M || 497 tv_dac->tv_std == TV_STD_PAL_60) 498 v_offset = ((int)(v_total * h_total) * 2 * tv_dac->v_pos) / (int)(NTSC_TV_LINES_PER_FRAME); 499 else 500 v_offset = ((int)(v_total * h_total) * 2 * tv_dac->v_pos) / (int)(PAL_TV_LINES_PER_FRAME); 501 502 restart -= v_offset + h_offset; 503 504 DRM_DEBUG_KMS("compute_restarts: def = %u h = %d v = %d, p1 = %04x, p2 = %04x, restart = %d\n", 505 const_ptr->def_restart, tv_dac->h_pos, tv_dac->v_pos, p1, p2, restart); 506 507 tv_dac->tv.hrestart = restart % h_total; 508 restart /= h_total; 509 tv_dac->tv.vrestart = restart % v_total; 510 restart /= v_total; 511 tv_dac->tv.frestart = restart % f_total; 512 513 DRM_DEBUG_KMS("compute_restart: F/H/V=%u,%u,%u\n", 514 (unsigned)tv_dac->tv.frestart, 515 (unsigned)tv_dac->tv.vrestart, 516 (unsigned)tv_dac->tv.hrestart); 517 518 /* compute h_inc from hsize */ 519 if (tv_dac->tv_std == TV_STD_NTSC || 520 tv_dac->tv_std == TV_STD_NTSC_J || 521 tv_dac->tv_std == TV_STD_PAL_M) 522 h_inc = (u16)((int)(const_ptr->hor_resolution * 4096 * NTSC_TV_CLOCK_T) / 523 (tv_dac->h_size * (int)(NTSC_TV_H_SIZE_UNIT) + (int)(NTSC_TV_ZERO_H_SIZE))); 524 else 525 h_inc = (u16)((int)(const_ptr->hor_resolution * 4096 * PAL_TV_CLOCK_T) / 526 (tv_dac->h_size * (int)(PAL_TV_H_SIZE_UNIT) + (int)(PAL_TV_ZERO_H_SIZE))); 527 528 tv_dac->tv.timing_cntl = (tv_dac->tv.timing_cntl & ~RADEON_H_INC_MASK) | 529 ((u32)h_inc << RADEON_H_INC_SHIFT); 530 531 DRM_DEBUG_KMS("compute_restart: h_size = %d h_inc = %d\n", tv_dac->h_size, h_inc); 532 533 return h_changed; 534 } 535 536 void radeon_legacy_tv_mode_set(struct drm_encoder *encoder, 537 struct drm_display_mode *mode, 538 struct drm_display_mode *adjusted_mode) 539 { 540 struct drm_device *dev = encoder->dev; 541 struct radeon_device *rdev = dev->dev_private; 542 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 543 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv; 544 const struct radeon_tv_mode_constants *const_ptr; 545 struct radeon_crtc *radeon_crtc; 546 int i; 547 uint16_t pll_ref_freq; 548 uint32_t vert_space, flicker_removal, tmp; 549 uint32_t tv_master_cntl, tv_rgb_cntl, tv_dac_cntl; 550 uint32_t tv_modulator_cntl1, tv_modulator_cntl2; 551 uint32_t tv_vscaler_cntl1, tv_vscaler_cntl2; 552 uint32_t tv_pll_cntl, tv_pll_cntl1 __unused, tv_ftotal; 553 uint32_t tv_y_fall_cntl, tv_y_rise_cntl, tv_y_saw_tooth_cntl; 554 uint32_t m, n, p; 555 const uint16_t *hor_timing; 556 const uint16_t *vert_timing; 557 558 const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, &pll_ref_freq); 559 if (!const_ptr) 560 return; 561 562 radeon_crtc = to_radeon_crtc(encoder->crtc); 563 564 tv_master_cntl = (RADEON_VIN_ASYNC_RST | 565 RADEON_CRT_FIFO_CE_EN | 566 RADEON_TV_FIFO_CE_EN | 567 RADEON_TV_ON); 568 569 if (!ASIC_IS_R300(rdev)) 570 tv_master_cntl |= RADEON_TVCLK_ALWAYS_ONb; 571 572 if (tv_dac->tv_std == TV_STD_NTSC || 573 tv_dac->tv_std == TV_STD_NTSC_J) 574 tv_master_cntl |= RADEON_RESTART_PHASE_FIX; 575 576 tv_modulator_cntl1 = (RADEON_SLEW_RATE_LIMIT | 577 RADEON_SYNC_TIP_LEVEL | 578 RADEON_YFLT_EN | 579 RADEON_UVFLT_EN | 580 (6 << RADEON_CY_FILT_BLEND_SHIFT)); 581 582 if (tv_dac->tv_std == TV_STD_NTSC || 583 tv_dac->tv_std == TV_STD_NTSC_J) { 584 tv_modulator_cntl1 |= (0x46 << RADEON_SET_UP_LEVEL_SHIFT) | 585 (0x3b << RADEON_BLANK_LEVEL_SHIFT); 586 tv_modulator_cntl2 = (-111 & RADEON_TV_U_BURST_LEVEL_MASK) | 587 ((0 & RADEON_TV_V_BURST_LEVEL_MASK) << RADEON_TV_V_BURST_LEVEL_SHIFT); 588 } else if (tv_dac->tv_std == TV_STD_SCART_PAL) { 589 tv_modulator_cntl1 |= RADEON_ALT_PHASE_EN; 590 tv_modulator_cntl2 = (0 & RADEON_TV_U_BURST_LEVEL_MASK) | 591 ((0 & RADEON_TV_V_BURST_LEVEL_MASK) << RADEON_TV_V_BURST_LEVEL_SHIFT); 592 } else { 593 tv_modulator_cntl1 |= RADEON_ALT_PHASE_EN | 594 (0x3b << RADEON_SET_UP_LEVEL_SHIFT) | 595 (0x3b << RADEON_BLANK_LEVEL_SHIFT); 596 tv_modulator_cntl2 = (-78 & RADEON_TV_U_BURST_LEVEL_MASK) | 597 ((62 & RADEON_TV_V_BURST_LEVEL_MASK) << RADEON_TV_V_BURST_LEVEL_SHIFT); 598 } 599 600 601 tv_rgb_cntl = (RADEON_RGB_DITHER_EN 602 | RADEON_TVOUT_SCALE_EN 603 | (0x0b << RADEON_UVRAM_READ_MARGIN_SHIFT) 604 | (0x07 << RADEON_FIFORAM_FFMACRO_READ_MARGIN_SHIFT) 605 | RADEON_RGB_ATTEN_SEL(0x3) 606 | RADEON_RGB_ATTEN_VAL(0xc)); 607 608 if (radeon_crtc->crtc_id == 1) 609 tv_rgb_cntl |= RADEON_RGB_SRC_SEL_CRTC2; 610 else { 611 if (radeon_crtc->rmx_type != RMX_OFF) 612 tv_rgb_cntl |= RADEON_RGB_SRC_SEL_RMX; 613 else 614 tv_rgb_cntl |= RADEON_RGB_SRC_SEL_CRTC1; 615 } 616 617 if (tv_dac->tv_std == TV_STD_NTSC || 618 tv_dac->tv_std == TV_STD_NTSC_J || 619 tv_dac->tv_std == TV_STD_PAL_M || 620 tv_dac->tv_std == TV_STD_PAL_60) 621 vert_space = const_ptr->ver_total * 2 * 10000 / NTSC_TV_LINES_PER_FRAME; 622 else 623 vert_space = const_ptr->ver_total * 2 * 10000 / PAL_TV_LINES_PER_FRAME; 624 625 tmp = RREG32(RADEON_TV_VSCALER_CNTL1); 626 tmp &= 0xe3ff0000; 627 tmp |= (vert_space * (1 << FRAC_BITS) / 10000); 628 tv_vscaler_cntl1 = tmp; 629 630 if (pll_ref_freq == 2700) 631 tv_vscaler_cntl1 |= RADEON_RESTART_FIELD; 632 633 if (const_ptr->hor_resolution == 1024) 634 tv_vscaler_cntl1 |= (4 << RADEON_Y_DEL_W_SIG_SHIFT); 635 else 636 tv_vscaler_cntl1 |= (2 << RADEON_Y_DEL_W_SIG_SHIFT); 637 638 /* scale up for int divide */ 639 tmp = const_ptr->ver_total * 2 * 1000; 640 if (tv_dac->tv_std == TV_STD_NTSC || 641 tv_dac->tv_std == TV_STD_NTSC_J || 642 tv_dac->tv_std == TV_STD_PAL_M || 643 tv_dac->tv_std == TV_STD_PAL_60) { 644 tmp /= NTSC_TV_LINES_PER_FRAME; 645 } else { 646 tmp /= PAL_TV_LINES_PER_FRAME; 647 } 648 flicker_removal = (tmp + 500) / 1000; 649 650 if (flicker_removal < 3) 651 flicker_removal = 3; 652 for (i = 0; i < ARRAY_SIZE(SLOPE_limit); ++i) { 653 if (flicker_removal == SLOPE_limit[i]) 654 break; 655 } 656 657 tv_y_saw_tooth_cntl = (vert_space * SLOPE_value[i] * (1 << (FRAC_BITS - 1)) + 658 5001) / 10000 / 8 | ((SLOPE_value[i] * 659 (1 << (FRAC_BITS - 1)) / 8) << 16); 660 tv_y_fall_cntl = 661 (YCOEF_EN_value[i] << 17) | ((YCOEF_value[i] * (1 << 8) / 8) << 24) | 662 RADEON_Y_FALL_PING_PONG | (272 * SLOPE_value[i] / 8) * (1 << (FRAC_BITS - 1)) / 663 1024; 664 tv_y_rise_cntl = RADEON_Y_RISE_PING_PONG| 665 (flicker_removal * 1024 - 272) * SLOPE_value[i] / 8 * (1 << (FRAC_BITS - 1)) / 1024; 666 667 tv_vscaler_cntl2 = RREG32(RADEON_TV_VSCALER_CNTL2) & 0x00fffff0; 668 tv_vscaler_cntl2 |= (0x10 << 24) | 669 RADEON_DITHER_MODE | 670 RADEON_Y_OUTPUT_DITHER_EN | 671 RADEON_UV_OUTPUT_DITHER_EN | 672 RADEON_UV_TO_BUF_DITHER_EN; 673 674 tmp = (tv_vscaler_cntl1 >> RADEON_UV_INC_SHIFT) & RADEON_UV_INC_MASK; 675 tmp = ((16384 * 256 * 10) / tmp + 5) / 10; 676 tmp = (tmp << RADEON_UV_OUTPUT_POST_SCALE_SHIFT) | 0x000b0000; 677 tv_dac->tv.timing_cntl = tmp; 678 679 if (tv_dac->tv_std == TV_STD_NTSC || 680 tv_dac->tv_std == TV_STD_NTSC_J || 681 tv_dac->tv_std == TV_STD_PAL_M || 682 tv_dac->tv_std == TV_STD_PAL_60) 683 tv_dac_cntl = tv_dac->ntsc_tvdac_adj; 684 else 685 tv_dac_cntl = tv_dac->pal_tvdac_adj; 686 687 tv_dac_cntl |= RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD; 688 689 if (tv_dac->tv_std == TV_STD_NTSC || 690 tv_dac->tv_std == TV_STD_NTSC_J) 691 tv_dac_cntl |= RADEON_TV_DAC_STD_NTSC; 692 else 693 tv_dac_cntl |= RADEON_TV_DAC_STD_PAL; 694 695 if (tv_dac->tv_std == TV_STD_NTSC || 696 tv_dac->tv_std == TV_STD_NTSC_J) { 697 if (pll_ref_freq == 2700) { 698 m = NTSC_TV_PLL_M_27; 699 n = NTSC_TV_PLL_N_27; 700 p = NTSC_TV_PLL_P_27; 701 } else { 702 m = NTSC_TV_PLL_M_14; 703 n = NTSC_TV_PLL_N_14; 704 p = NTSC_TV_PLL_P_14; 705 } 706 } else { 707 if (pll_ref_freq == 2700) { 708 m = PAL_TV_PLL_M_27; 709 n = PAL_TV_PLL_N_27; 710 p = PAL_TV_PLL_P_27; 711 } else { 712 m = PAL_TV_PLL_M_14; 713 n = PAL_TV_PLL_N_14; 714 p = PAL_TV_PLL_P_14; 715 } 716 } 717 718 tv_pll_cntl = (m & RADEON_TV_M0LO_MASK) | 719 (((m >> 8) & RADEON_TV_M0HI_MASK) << RADEON_TV_M0HI_SHIFT) | 720 ((n & RADEON_TV_N0LO_MASK) << RADEON_TV_N0LO_SHIFT) | 721 (((n >> 9) & RADEON_TV_N0HI_MASK) << RADEON_TV_N0HI_SHIFT) | 722 ((p & RADEON_TV_P_MASK) << RADEON_TV_P_SHIFT); 723 724 tv_pll_cntl1 = (((4 & RADEON_TVPCP_MASK) << RADEON_TVPCP_SHIFT) | 725 ((4 & RADEON_TVPVG_MASK) << RADEON_TVPVG_SHIFT) | 726 ((1 & RADEON_TVPDC_MASK) << RADEON_TVPDC_SHIFT) | 727 RADEON_TVCLK_SRC_SEL_TVPLL | 728 RADEON_TVPLL_TEST_DIS); 729 730 tv_dac->tv.tv_uv_adr = 0xc8; 731 732 if (tv_dac->tv_std == TV_STD_NTSC || 733 tv_dac->tv_std == TV_STD_NTSC_J || 734 tv_dac->tv_std == TV_STD_PAL_M || 735 tv_dac->tv_std == TV_STD_PAL_60) { 736 tv_ftotal = NTSC_TV_VFTOTAL; 737 hor_timing = hor_timing_NTSC; 738 vert_timing = vert_timing_NTSC; 739 } else { 740 hor_timing = hor_timing_PAL; 741 vert_timing = vert_timing_PAL; 742 tv_ftotal = PAL_TV_VFTOTAL; 743 } 744 745 for (i = 0; i < MAX_H_CODE_TIMING_LEN; i++) { 746 if ((tv_dac->tv.h_code_timing[i] = hor_timing[i]) == 0) 747 break; 748 } 749 750 for (i = 0; i < MAX_V_CODE_TIMING_LEN; i++) { 751 if ((tv_dac->tv.v_code_timing[i] = vert_timing[i]) == 0) 752 break; 753 } 754 755 radeon_legacy_tv_init_restarts(encoder); 756 757 /* play with DAC_CNTL */ 758 /* play with GPIOPAD_A */ 759 /* DISP_OUTPUT_CNTL */ 760 /* use reference freq */ 761 762 /* program the TV registers */ 763 WREG32(RADEON_TV_MASTER_CNTL, (tv_master_cntl | RADEON_TV_ASYNC_RST | 764 RADEON_CRT_ASYNC_RST | RADEON_TV_FIFO_ASYNC_RST)); 765 766 tmp = RREG32(RADEON_TV_DAC_CNTL); 767 tmp &= ~RADEON_TV_DAC_NBLANK; 768 tmp |= RADEON_TV_DAC_BGSLEEP | 769 RADEON_TV_DAC_RDACPD | 770 RADEON_TV_DAC_GDACPD | 771 RADEON_TV_DAC_BDACPD; 772 WREG32(RADEON_TV_DAC_CNTL, tmp); 773 774 /* TV PLL */ 775 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~RADEON_TVCLK_SRC_SEL_TVPLL); 776 WREG32_PLL(RADEON_TV_PLL_CNTL, tv_pll_cntl); 777 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, RADEON_TVPLL_RESET, ~RADEON_TVPLL_RESET); 778 779 radeon_wait_pll_lock(encoder, 200, 800, 135); 780 781 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~RADEON_TVPLL_RESET); 782 783 radeon_wait_pll_lock(encoder, 300, 160, 27); 784 radeon_wait_pll_lock(encoder, 200, 800, 135); 785 786 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~0xf); 787 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, RADEON_TVCLK_SRC_SEL_TVPLL, ~RADEON_TVCLK_SRC_SEL_TVPLL); 788 789 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, (1 << RADEON_TVPDC_SHIFT), ~RADEON_TVPDC_MASK); 790 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~RADEON_TVPLL_SLEEP); 791 792 /* TV HV */ 793 WREG32(RADEON_TV_RGB_CNTL, tv_rgb_cntl); 794 WREG32(RADEON_TV_HTOTAL, const_ptr->hor_total - 1); 795 WREG32(RADEON_TV_HDISP, const_ptr->hor_resolution - 1); 796 WREG32(RADEON_TV_HSTART, const_ptr->hor_start); 797 798 WREG32(RADEON_TV_VTOTAL, const_ptr->ver_total - 1); 799 WREG32(RADEON_TV_VDISP, const_ptr->ver_resolution - 1); 800 WREG32(RADEON_TV_FTOTAL, tv_ftotal); 801 WREG32(RADEON_TV_VSCALER_CNTL1, tv_vscaler_cntl1); 802 WREG32(RADEON_TV_VSCALER_CNTL2, tv_vscaler_cntl2); 803 804 WREG32(RADEON_TV_Y_FALL_CNTL, tv_y_fall_cntl); 805 WREG32(RADEON_TV_Y_RISE_CNTL, tv_y_rise_cntl); 806 WREG32(RADEON_TV_Y_SAW_TOOTH_CNTL, tv_y_saw_tooth_cntl); 807 808 WREG32(RADEON_TV_MASTER_CNTL, (tv_master_cntl | RADEON_TV_ASYNC_RST | 809 RADEON_CRT_ASYNC_RST)); 810 811 /* TV restarts */ 812 radeon_legacy_write_tv_restarts(radeon_encoder); 813 814 /* tv timings */ 815 radeon_restore_tv_timing_tables(radeon_encoder); 816 817 WREG32(RADEON_TV_MASTER_CNTL, (tv_master_cntl | RADEON_TV_ASYNC_RST)); 818 819 /* tv std */ 820 WREG32(RADEON_TV_SYNC_CNTL, (RADEON_SYNC_PUB | RADEON_TV_SYNC_IO_DRIVE)); 821 WREG32(RADEON_TV_TIMING_CNTL, tv_dac->tv.timing_cntl); 822 WREG32(RADEON_TV_MODULATOR_CNTL1, tv_modulator_cntl1); 823 WREG32(RADEON_TV_MODULATOR_CNTL2, tv_modulator_cntl2); 824 WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, (RADEON_Y_RED_EN | 825 RADEON_C_GRN_EN | 826 RADEON_CMP_BLU_EN | 827 RADEON_DAC_DITHER_EN)); 828 829 WREG32(RADEON_TV_CRC_CNTL, 0); 830 831 WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl); 832 833 WREG32(RADEON_TV_GAIN_LIMIT_SETTINGS, ((0x17f << RADEON_UV_GAIN_LIMIT_SHIFT) | 834 (0x5ff << RADEON_Y_GAIN_LIMIT_SHIFT))); 835 WREG32(RADEON_TV_LINEAR_GAIN_SETTINGS, ((0x100 << RADEON_UV_GAIN_SHIFT) | 836 (0x100 << RADEON_Y_GAIN_SHIFT))); 837 838 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); 839 840 } 841 842 void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder, 843 uint32_t *h_total_disp, uint32_t *h_sync_strt_wid, 844 uint32_t *v_total_disp, uint32_t *v_sync_strt_wid) 845 { 846 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 847 const struct radeon_tv_mode_constants *const_ptr; 848 uint32_t tmp; 849 850 const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, NULL); 851 if (!const_ptr) 852 return; 853 854 *h_total_disp = (((const_ptr->hor_resolution / 8) - 1) << RADEON_CRTC_H_DISP_SHIFT) | 855 (((const_ptr->hor_total / 8) - 1) << RADEON_CRTC_H_TOTAL_SHIFT); 856 857 tmp = *h_sync_strt_wid; 858 tmp &= ~(RADEON_CRTC_H_SYNC_STRT_PIX | RADEON_CRTC_H_SYNC_STRT_CHAR); 859 tmp |= (((const_ptr->hor_syncstart / 8) - 1) << RADEON_CRTC_H_SYNC_STRT_CHAR_SHIFT) | 860 (const_ptr->hor_syncstart & 7); 861 *h_sync_strt_wid = tmp; 862 863 *v_total_disp = ((const_ptr->ver_resolution - 1) << RADEON_CRTC_V_DISP_SHIFT) | 864 ((const_ptr->ver_total - 1) << RADEON_CRTC_V_TOTAL_SHIFT); 865 866 tmp = *v_sync_strt_wid; 867 tmp &= ~RADEON_CRTC_V_SYNC_STRT; 868 tmp |= ((const_ptr->ver_syncstart - 1) << RADEON_CRTC_V_SYNC_STRT_SHIFT); 869 *v_sync_strt_wid = tmp; 870 } 871 872 static int get_post_div(int value) 873 { 874 int post_div; 875 switch (value) { 876 case 1: post_div = 0; break; 877 case 2: post_div = 1; break; 878 case 3: post_div = 4; break; 879 case 4: post_div = 2; break; 880 case 6: post_div = 6; break; 881 case 8: post_div = 3; break; 882 case 12: post_div = 7; break; 883 case 16: 884 default: post_div = 5; break; 885 } 886 return post_div; 887 } 888 889 void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder, 890 uint32_t *htotal_cntl, uint32_t *ppll_ref_div, 891 uint32_t *ppll_div_3, uint32_t *pixclks_cntl) 892 { 893 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 894 const struct radeon_tv_mode_constants *const_ptr; 895 896 const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, NULL); 897 if (!const_ptr) 898 return; 899 900 *htotal_cntl = (const_ptr->hor_total & 0x7) | RADEON_HTOT_CNTL_VGA_EN; 901 902 *ppll_ref_div = const_ptr->crtcPLL_M; 903 904 *ppll_div_3 = (const_ptr->crtcPLL_N & 0x7ff) | (get_post_div(const_ptr->crtcPLL_post_div) << 16); 905 *pixclks_cntl &= ~(RADEON_PIX2CLK_SRC_SEL_MASK | RADEON_PIXCLK_TV_SRC_SEL); 906 *pixclks_cntl |= RADEON_PIX2CLK_SRC_SEL_P2PLLCLK; 907 } 908 909 void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder, 910 uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div, 911 uint32_t *p2pll_div_0, uint32_t *pixclks_cntl) 912 { 913 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 914 const struct radeon_tv_mode_constants *const_ptr; 915 916 const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, NULL); 917 if (!const_ptr) 918 return; 919 920 *htotal2_cntl = (const_ptr->hor_total & 0x7); 921 922 *p2pll_ref_div = const_ptr->crtcPLL_M; 923 924 *p2pll_div_0 = (const_ptr->crtcPLL_N & 0x7ff) | (get_post_div(const_ptr->crtcPLL_post_div) << 16); 925 *pixclks_cntl &= ~RADEON_PIX2CLK_SRC_SEL_MASK; 926 *pixclks_cntl |= RADEON_PIX2CLK_SRC_SEL_P2PLLCLK | RADEON_PIXCLK_TV_SRC_SEL; 927 } 928 929
Indexes created Wed Oct 29 01:09:52 GMT 2025