radeon_ni.c revision 1.1.1.1
1 /* $NetBSD: radeon_ni.c,v 1.1.1.1 2021/12/18 20:15:49 riastradh Exp $ */ 2 3 /* 4 * Copyright 2010 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Alex Deucher 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: radeon_ni.c,v 1.1.1.1 2021/12/18 20:15:49 riastradh Exp $"); 29 30 #include <linux/firmware.h> 31 #include <linux/module.h> 32 #include <linux/pci.h> 33 #include <linux/slab.h> 34 35 #include <drm/radeon_drm.h> 36 37 #include "atom.h" 38 #include "cayman_blit_shaders.h" 39 #include "clearstate_cayman.h" 40 #include "ni_reg.h" 41 #include "nid.h" 42 #include "radeon.h" 43 #include "radeon_asic.h" 44 #include "radeon_audio.h" 45 #include "radeon_ucode.h" 46 47 /* 48 * Indirect registers accessor 49 */ 50 u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg) 51 { 52 unsigned long flags; 53 u32 r; 54 55 spin_lock_irqsave(&rdev->smc_idx_lock, flags); 56 WREG32(TN_SMC_IND_INDEX_0, (reg)); 57 r = RREG32(TN_SMC_IND_DATA_0); 58 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags); 59 return r; 60 } 61 62 void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v) 63 { 64 unsigned long flags; 65 66 spin_lock_irqsave(&rdev->smc_idx_lock, flags); 67 WREG32(TN_SMC_IND_INDEX_0, (reg)); 68 WREG32(TN_SMC_IND_DATA_0, (v)); 69 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags); 70 } 71 72 static const u32 tn_rlc_save_restore_register_list[] = 73 { 74 0x98fc, 75 0x98f0, 76 0x9834, 77 0x9838, 78 0x9870, 79 0x9874, 80 0x8a14, 81 0x8b24, 82 0x8bcc, 83 0x8b10, 84 0x8c30, 85 0x8d00, 86 0x8d04, 87 0x8c00, 88 0x8c04, 89 0x8c10, 90 0x8c14, 91 0x8d8c, 92 0x8cf0, 93 0x8e38, 94 0x9508, 95 0x9688, 96 0x9608, 97 0x960c, 98 0x9610, 99 0x9614, 100 0x88c4, 101 0x8978, 102 0x88d4, 103 0x900c, 104 0x9100, 105 0x913c, 106 0x90e8, 107 0x9354, 108 0xa008, 109 0x98f8, 110 0x9148, 111 0x914c, 112 0x3f94, 113 0x98f4, 114 0x9b7c, 115 0x3f8c, 116 0x8950, 117 0x8954, 118 0x8a18, 119 0x8b28, 120 0x9144, 121 0x3f90, 122 0x915c, 123 0x9160, 124 0x9178, 125 0x917c, 126 0x9180, 127 0x918c, 128 0x9190, 129 0x9194, 130 0x9198, 131 0x919c, 132 0x91a8, 133 0x91ac, 134 0x91b0, 135 0x91b4, 136 0x91b8, 137 0x91c4, 138 0x91c8, 139 0x91cc, 140 0x91d0, 141 0x91d4, 142 0x91e0, 143 0x91e4, 144 0x91ec, 145 0x91f0, 146 0x91f4, 147 0x9200, 148 0x9204, 149 0x929c, 150 0x8030, 151 0x9150, 152 0x9a60, 153 0x920c, 154 0x9210, 155 0x9228, 156 0x922c, 157 0x9244, 158 0x9248, 159 0x91e8, 160 0x9294, 161 0x9208, 162 0x9224, 163 0x9240, 164 0x9220, 165 0x923c, 166 0x9258, 167 0x9744, 168 0xa200, 169 0xa204, 170 0xa208, 171 0xa20c, 172 0x8d58, 173 0x9030, 174 0x9034, 175 0x9038, 176 0x903c, 177 0x9040, 178 0x9654, 179 0x897c, 180 0xa210, 181 0xa214, 182 0x9868, 183 0xa02c, 184 0x9664, 185 0x9698, 186 0x949c, 187 0x8e10, 188 0x8e18, 189 0x8c50, 190 0x8c58, 191 0x8c60, 192 0x8c68, 193 0x89b4, 194 0x9830, 195 0x802c, 196 }; 197 198 extern bool evergreen_is_display_hung(struct radeon_device *rdev); 199 extern void evergreen_print_gpu_status_regs(struct radeon_device *rdev); 200 extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save); 201 extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save); 202 extern int evergreen_mc_wait_for_idle(struct radeon_device *rdev); 203 extern void evergreen_mc_program(struct radeon_device *rdev); 204 extern void evergreen_irq_suspend(struct radeon_device *rdev); 205 extern int evergreen_mc_init(struct radeon_device *rdev); 206 extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev); 207 extern void evergreen_pcie_gen2_enable(struct radeon_device *rdev); 208 extern void evergreen_program_aspm(struct radeon_device *rdev); 209 extern void sumo_rlc_fini(struct radeon_device *rdev); 210 extern int sumo_rlc_init(struct radeon_device *rdev); 211 extern void evergreen_gpu_pci_config_reset(struct radeon_device *rdev); 212 213 /* Firmware Names */ 214 MODULE_FIRMWARE("radeon/BARTS_pfp.bin"); 215 MODULE_FIRMWARE("radeon/BARTS_me.bin"); 216 MODULE_FIRMWARE("radeon/BARTS_mc.bin"); 217 MODULE_FIRMWARE("radeon/BARTS_smc.bin"); 218 MODULE_FIRMWARE("radeon/BTC_rlc.bin"); 219 MODULE_FIRMWARE("radeon/TURKS_pfp.bin"); 220 MODULE_FIRMWARE("radeon/TURKS_me.bin"); 221 MODULE_FIRMWARE("radeon/TURKS_mc.bin"); 222 MODULE_FIRMWARE("radeon/TURKS_smc.bin"); 223 MODULE_FIRMWARE("radeon/CAICOS_pfp.bin"); 224 MODULE_FIRMWARE("radeon/CAICOS_me.bin"); 225 MODULE_FIRMWARE("radeon/CAICOS_mc.bin"); 226 MODULE_FIRMWARE("radeon/CAICOS_smc.bin"); 227 MODULE_FIRMWARE("radeon/CAYMAN_pfp.bin"); 228 MODULE_FIRMWARE("radeon/CAYMAN_me.bin"); 229 MODULE_FIRMWARE("radeon/CAYMAN_mc.bin"); 230 MODULE_FIRMWARE("radeon/CAYMAN_rlc.bin"); 231 MODULE_FIRMWARE("radeon/CAYMAN_smc.bin"); 232 MODULE_FIRMWARE("radeon/ARUBA_pfp.bin"); 233 MODULE_FIRMWARE("radeon/ARUBA_me.bin"); 234 MODULE_FIRMWARE("radeon/ARUBA_rlc.bin"); 235 236 237 static const u32 cayman_golden_registers2[] = 238 { 239 0x3e5c, 0xffffffff, 0x00000000, 240 0x3e48, 0xffffffff, 0x00000000, 241 0x3e4c, 0xffffffff, 0x00000000, 242 0x3e64, 0xffffffff, 0x00000000, 243 0x3e50, 0xffffffff, 0x00000000, 244 0x3e60, 0xffffffff, 0x00000000 245 }; 246 247 static const u32 cayman_golden_registers[] = 248 { 249 0x5eb4, 0xffffffff, 0x00000002, 250 0x5e78, 0x8f311ff1, 0x001000f0, 251 0x3f90, 0xffff0000, 0xff000000, 252 0x9148, 0xffff0000, 0xff000000, 253 0x3f94, 0xffff0000, 0xff000000, 254 0x914c, 0xffff0000, 0xff000000, 255 0xc78, 0x00000080, 0x00000080, 256 0xbd4, 0x70073777, 0x00011003, 257 0xd02c, 0xbfffff1f, 0x08421000, 258 0xd0b8, 0x73773777, 0x02011003, 259 0x5bc0, 0x00200000, 0x50100000, 260 0x98f8, 0x33773777, 0x02011003, 261 0x98fc, 0xffffffff, 0x76541032, 262 0x7030, 0x31000311, 0x00000011, 263 0x2f48, 0x33773777, 0x42010001, 264 0x6b28, 0x00000010, 0x00000012, 265 0x7728, 0x00000010, 0x00000012, 266 0x10328, 0x00000010, 0x00000012, 267 0x10f28, 0x00000010, 0x00000012, 268 0x11b28, 0x00000010, 0x00000012, 269 0x12728, 0x00000010, 0x00000012, 270 0x240c, 0x000007ff, 0x00000000, 271 0x8a14, 0xf000001f, 0x00000007, 272 0x8b24, 0x3fff3fff, 0x00ff0fff, 273 0x8b10, 0x0000ff0f, 0x00000000, 274 0x28a4c, 0x07ffffff, 0x06000000, 275 0x10c, 0x00000001, 0x00010003, 276 0xa02c, 0xffffffff, 0x0000009b, 277 0x913c, 0x0000010f, 0x01000100, 278 0x8c04, 0xf8ff00ff, 0x40600060, 279 0x28350, 0x00000f01, 0x00000000, 280 0x9508, 0x3700001f, 0x00000002, 281 0x960c, 0xffffffff, 0x54763210, 282 0x88c4, 0x001f3ae3, 0x00000082, 283 0x88d0, 0xffffffff, 0x0f40df40, 284 0x88d4, 0x0000001f, 0x00000010, 285 0x8974, 0xffffffff, 0x00000000 286 }; 287 288 static const u32 dvst_golden_registers2[] = 289 { 290 0x8f8, 0xffffffff, 0, 291 0x8fc, 0x00380000, 0, 292 0x8f8, 0xffffffff, 1, 293 0x8fc, 0x0e000000, 0 294 }; 295 296 static const u32 dvst_golden_registers[] = 297 { 298 0x690, 0x3fff3fff, 0x20c00033, 299 0x918c, 0x0fff0fff, 0x00010006, 300 0x91a8, 0x0fff0fff, 0x00010006, 301 0x9150, 0xffffdfff, 0x6e944040, 302 0x917c, 0x0fff0fff, 0x00030002, 303 0x9198, 0x0fff0fff, 0x00030002, 304 0x915c, 0x0fff0fff, 0x00010000, 305 0x3f90, 0xffff0001, 0xff000000, 306 0x9178, 0x0fff0fff, 0x00070000, 307 0x9194, 0x0fff0fff, 0x00070000, 308 0x9148, 0xffff0001, 0xff000000, 309 0x9190, 0x0fff0fff, 0x00090008, 310 0x91ac, 0x0fff0fff, 0x00090008, 311 0x3f94, 0xffff0000, 0xff000000, 312 0x914c, 0xffff0000, 0xff000000, 313 0x929c, 0x00000fff, 0x00000001, 314 0x55e4, 0xff607fff, 0xfc000100, 315 0x8a18, 0xff000fff, 0x00000100, 316 0x8b28, 0xff000fff, 0x00000100, 317 0x9144, 0xfffc0fff, 0x00000100, 318 0x6ed8, 0x00010101, 0x00010000, 319 0x9830, 0xffffffff, 0x00000000, 320 0x9834, 0xf00fffff, 0x00000400, 321 0x9838, 0xfffffffe, 0x00000000, 322 0xd0c0, 0xff000fff, 0x00000100, 323 0xd02c, 0xbfffff1f, 0x08421000, 324 0xd0b8, 0x73773777, 0x12010001, 325 0x5bb0, 0x000000f0, 0x00000070, 326 0x98f8, 0x73773777, 0x12010001, 327 0x98fc, 0xffffffff, 0x00000010, 328 0x9b7c, 0x00ff0000, 0x00fc0000, 329 0x8030, 0x00001f0f, 0x0000100a, 330 0x2f48, 0x73773777, 0x12010001, 331 0x2408, 0x00030000, 0x000c007f, 332 0x8a14, 0xf000003f, 0x00000007, 333 0x8b24, 0x3fff3fff, 0x00ff0fff, 334 0x8b10, 0x0000ff0f, 0x00000000, 335 0x28a4c, 0x07ffffff, 0x06000000, 336 0x4d8, 0x00000fff, 0x00000100, 337 0xa008, 0xffffffff, 0x00010000, 338 0x913c, 0xffff03ff, 0x01000100, 339 0x8c00, 0x000000ff, 0x00000003, 340 0x8c04, 0xf8ff00ff, 0x40600060, 341 0x8cf0, 0x1fff1fff, 0x08e00410, 342 0x28350, 0x00000f01, 0x00000000, 343 0x9508, 0xf700071f, 0x00000002, 344 0x960c, 0xffffffff, 0x54763210, 345 0x20ef8, 0x01ff01ff, 0x00000002, 346 0x20e98, 0xfffffbff, 0x00200000, 347 0x2015c, 0xffffffff, 0x00000f40, 348 0x88c4, 0x001f3ae3, 0x00000082, 349 0x8978, 0x3fffffff, 0x04050140, 350 0x88d4, 0x0000001f, 0x00000010, 351 0x8974, 0xffffffff, 0x00000000 352 }; 353 354 static const u32 scrapper_golden_registers[] = 355 { 356 0x690, 0x3fff3fff, 0x20c00033, 357 0x918c, 0x0fff0fff, 0x00010006, 358 0x918c, 0x0fff0fff, 0x00010006, 359 0x91a8, 0x0fff0fff, 0x00010006, 360 0x91a8, 0x0fff0fff, 0x00010006, 361 0x9150, 0xffffdfff, 0x6e944040, 362 0x9150, 0xffffdfff, 0x6e944040, 363 0x917c, 0x0fff0fff, 0x00030002, 364 0x917c, 0x0fff0fff, 0x00030002, 365 0x9198, 0x0fff0fff, 0x00030002, 366 0x9198, 0x0fff0fff, 0x00030002, 367 0x915c, 0x0fff0fff, 0x00010000, 368 0x915c, 0x0fff0fff, 0x00010000, 369 0x3f90, 0xffff0001, 0xff000000, 370 0x3f90, 0xffff0001, 0xff000000, 371 0x9178, 0x0fff0fff, 0x00070000, 372 0x9178, 0x0fff0fff, 0x00070000, 373 0x9194, 0x0fff0fff, 0x00070000, 374 0x9194, 0x0fff0fff, 0x00070000, 375 0x9148, 0xffff0001, 0xff000000, 376 0x9148, 0xffff0001, 0xff000000, 377 0x9190, 0x0fff0fff, 0x00090008, 378 0x9190, 0x0fff0fff, 0x00090008, 379 0x91ac, 0x0fff0fff, 0x00090008, 380 0x91ac, 0x0fff0fff, 0x00090008, 381 0x3f94, 0xffff0000, 0xff000000, 382 0x3f94, 0xffff0000, 0xff000000, 383 0x914c, 0xffff0000, 0xff000000, 384 0x914c, 0xffff0000, 0xff000000, 385 0x929c, 0x00000fff, 0x00000001, 386 0x929c, 0x00000fff, 0x00000001, 387 0x55e4, 0xff607fff, 0xfc000100, 388 0x8a18, 0xff000fff, 0x00000100, 389 0x8a18, 0xff000fff, 0x00000100, 390 0x8b28, 0xff000fff, 0x00000100, 391 0x8b28, 0xff000fff, 0x00000100, 392 0x9144, 0xfffc0fff, 0x00000100, 393 0x9144, 0xfffc0fff, 0x00000100, 394 0x6ed8, 0x00010101, 0x00010000, 395 0x9830, 0xffffffff, 0x00000000, 396 0x9830, 0xffffffff, 0x00000000, 397 0x9834, 0xf00fffff, 0x00000400, 398 0x9834, 0xf00fffff, 0x00000400, 399 0x9838, 0xfffffffe, 0x00000000, 400 0x9838, 0xfffffffe, 0x00000000, 401 0xd0c0, 0xff000fff, 0x00000100, 402 0xd02c, 0xbfffff1f, 0x08421000, 403 0xd02c, 0xbfffff1f, 0x08421000, 404 0xd0b8, 0x73773777, 0x12010001, 405 0xd0b8, 0x73773777, 0x12010001, 406 0x5bb0, 0x000000f0, 0x00000070, 407 0x98f8, 0x73773777, 0x12010001, 408 0x98f8, 0x73773777, 0x12010001, 409 0x98fc, 0xffffffff, 0x00000010, 410 0x98fc, 0xffffffff, 0x00000010, 411 0x9b7c, 0x00ff0000, 0x00fc0000, 412 0x9b7c, 0x00ff0000, 0x00fc0000, 413 0x8030, 0x00001f0f, 0x0000100a, 414 0x8030, 0x00001f0f, 0x0000100a, 415 0x2f48, 0x73773777, 0x12010001, 416 0x2f48, 0x73773777, 0x12010001, 417 0x2408, 0x00030000, 0x000c007f, 418 0x8a14, 0xf000003f, 0x00000007, 419 0x8a14, 0xf000003f, 0x00000007, 420 0x8b24, 0x3fff3fff, 0x00ff0fff, 421 0x8b24, 0x3fff3fff, 0x00ff0fff, 422 0x8b10, 0x0000ff0f, 0x00000000, 423 0x8b10, 0x0000ff0f, 0x00000000, 424 0x28a4c, 0x07ffffff, 0x06000000, 425 0x28a4c, 0x07ffffff, 0x06000000, 426 0x4d8, 0x00000fff, 0x00000100, 427 0x4d8, 0x00000fff, 0x00000100, 428 0xa008, 0xffffffff, 0x00010000, 429 0xa008, 0xffffffff, 0x00010000, 430 0x913c, 0xffff03ff, 0x01000100, 431 0x913c, 0xffff03ff, 0x01000100, 432 0x90e8, 0x001fffff, 0x010400c0, 433 0x8c00, 0x000000ff, 0x00000003, 434 0x8c00, 0x000000ff, 0x00000003, 435 0x8c04, 0xf8ff00ff, 0x40600060, 436 0x8c04, 0xf8ff00ff, 0x40600060, 437 0x8c30, 0x0000000f, 0x00040005, 438 0x8cf0, 0x1fff1fff, 0x08e00410, 439 0x8cf0, 0x1fff1fff, 0x08e00410, 440 0x900c, 0x00ffffff, 0x0017071f, 441 0x28350, 0x00000f01, 0x00000000, 442 0x28350, 0x00000f01, 0x00000000, 443 0x9508, 0xf700071f, 0x00000002, 444 0x9508, 0xf700071f, 0x00000002, 445 0x9688, 0x00300000, 0x0017000f, 446 0x960c, 0xffffffff, 0x54763210, 447 0x960c, 0xffffffff, 0x54763210, 448 0x20ef8, 0x01ff01ff, 0x00000002, 449 0x20e98, 0xfffffbff, 0x00200000, 450 0x2015c, 0xffffffff, 0x00000f40, 451 0x88c4, 0x001f3ae3, 0x00000082, 452 0x88c4, 0x001f3ae3, 0x00000082, 453 0x8978, 0x3fffffff, 0x04050140, 454 0x8978, 0x3fffffff, 0x04050140, 455 0x88d4, 0x0000001f, 0x00000010, 456 0x88d4, 0x0000001f, 0x00000010, 457 0x8974, 0xffffffff, 0x00000000, 458 0x8974, 0xffffffff, 0x00000000 459 }; 460 461 static void ni_init_golden_registers(struct radeon_device *rdev) 462 { 463 switch (rdev->family) { 464 case CHIP_CAYMAN: 465 radeon_program_register_sequence(rdev, 466 cayman_golden_registers, 467 (const u32)ARRAY_SIZE(cayman_golden_registers)); 468 radeon_program_register_sequence(rdev, 469 cayman_golden_registers2, 470 (const u32)ARRAY_SIZE(cayman_golden_registers2)); 471 break; 472 case CHIP_ARUBA: 473 if ((rdev->pdev->device == 0x9900) || 474 (rdev->pdev->device == 0x9901) || 475 (rdev->pdev->device == 0x9903) || 476 (rdev->pdev->device == 0x9904) || 477 (rdev->pdev->device == 0x9905) || 478 (rdev->pdev->device == 0x9906) || 479 (rdev->pdev->device == 0x9907) || 480 (rdev->pdev->device == 0x9908) || 481 (rdev->pdev->device == 0x9909) || 482 (rdev->pdev->device == 0x990A) || 483 (rdev->pdev->device == 0x990B) || 484 (rdev->pdev->device == 0x990C) || 485 (rdev->pdev->device == 0x990D) || 486 (rdev->pdev->device == 0x990E) || 487 (rdev->pdev->device == 0x990F) || 488 (rdev->pdev->device == 0x9910) || 489 (rdev->pdev->device == 0x9913) || 490 (rdev->pdev->device == 0x9917) || 491 (rdev->pdev->device == 0x9918)) { 492 radeon_program_register_sequence(rdev, 493 dvst_golden_registers, 494 (const u32)ARRAY_SIZE(dvst_golden_registers)); 495 radeon_program_register_sequence(rdev, 496 dvst_golden_registers2, 497 (const u32)ARRAY_SIZE(dvst_golden_registers2)); 498 } else { 499 radeon_program_register_sequence(rdev, 500 scrapper_golden_registers, 501 (const u32)ARRAY_SIZE(scrapper_golden_registers)); 502 radeon_program_register_sequence(rdev, 503 dvst_golden_registers2, 504 (const u32)ARRAY_SIZE(dvst_golden_registers2)); 505 } 506 break; 507 default: 508 break; 509 } 510 } 511 512 #define BTC_IO_MC_REGS_SIZE 29 513 514 static const u32 barts_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = { 515 {0x00000077, 0xff010100}, 516 {0x00000078, 0x00000000}, 517 {0x00000079, 0x00001434}, 518 {0x0000007a, 0xcc08ec08}, 519 {0x0000007b, 0x00040000}, 520 {0x0000007c, 0x000080c0}, 521 {0x0000007d, 0x09000000}, 522 {0x0000007e, 0x00210404}, 523 {0x00000081, 0x08a8e800}, 524 {0x00000082, 0x00030444}, 525 {0x00000083, 0x00000000}, 526 {0x00000085, 0x00000001}, 527 {0x00000086, 0x00000002}, 528 {0x00000087, 0x48490000}, 529 {0x00000088, 0x20244647}, 530 {0x00000089, 0x00000005}, 531 {0x0000008b, 0x66030000}, 532 {0x0000008c, 0x00006603}, 533 {0x0000008d, 0x00000100}, 534 {0x0000008f, 0x00001c0a}, 535 {0x00000090, 0xff000001}, 536 {0x00000094, 0x00101101}, 537 {0x00000095, 0x00000fff}, 538 {0x00000096, 0x00116fff}, 539 {0x00000097, 0x60010000}, 540 {0x00000098, 0x10010000}, 541 {0x00000099, 0x00006000}, 542 {0x0000009a, 0x00001000}, 543 {0x0000009f, 0x00946a00} 544 }; 545 546 static const u32 turks_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = { 547 {0x00000077, 0xff010100}, 548 {0x00000078, 0x00000000}, 549 {0x00000079, 0x00001434}, 550 {0x0000007a, 0xcc08ec08}, 551 {0x0000007b, 0x00040000}, 552 {0x0000007c, 0x000080c0}, 553 {0x0000007d, 0x09000000}, 554 {0x0000007e, 0x00210404}, 555 {0x00000081, 0x08a8e800}, 556 {0x00000082, 0x00030444}, 557 {0x00000083, 0x00000000}, 558 {0x00000085, 0x00000001}, 559 {0x00000086, 0x00000002}, 560 {0x00000087, 0x48490000}, 561 {0x00000088, 0x20244647}, 562 {0x00000089, 0x00000005}, 563 {0x0000008b, 0x66030000}, 564 {0x0000008c, 0x00006603}, 565 {0x0000008d, 0x00000100}, 566 {0x0000008f, 0x00001c0a}, 567 {0x00000090, 0xff000001}, 568 {0x00000094, 0x00101101}, 569 {0x00000095, 0x00000fff}, 570 {0x00000096, 0x00116fff}, 571 {0x00000097, 0x60010000}, 572 {0x00000098, 0x10010000}, 573 {0x00000099, 0x00006000}, 574 {0x0000009a, 0x00001000}, 575 {0x0000009f, 0x00936a00} 576 }; 577 578 static const u32 caicos_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = { 579 {0x00000077, 0xff010100}, 580 {0x00000078, 0x00000000}, 581 {0x00000079, 0x00001434}, 582 {0x0000007a, 0xcc08ec08}, 583 {0x0000007b, 0x00040000}, 584 {0x0000007c, 0x000080c0}, 585 {0x0000007d, 0x09000000}, 586 {0x0000007e, 0x00210404}, 587 {0x00000081, 0x08a8e800}, 588 {0x00000082, 0x00030444}, 589 {0x00000083, 0x00000000}, 590 {0x00000085, 0x00000001}, 591 {0x00000086, 0x00000002}, 592 {0x00000087, 0x48490000}, 593 {0x00000088, 0x20244647}, 594 {0x00000089, 0x00000005}, 595 {0x0000008b, 0x66030000}, 596 {0x0000008c, 0x00006603}, 597 {0x0000008d, 0x00000100}, 598 {0x0000008f, 0x00001c0a}, 599 {0x00000090, 0xff000001}, 600 {0x00000094, 0x00101101}, 601 {0x00000095, 0x00000fff}, 602 {0x00000096, 0x00116fff}, 603 {0x00000097, 0x60010000}, 604 {0x00000098, 0x10010000}, 605 {0x00000099, 0x00006000}, 606 {0x0000009a, 0x00001000}, 607 {0x0000009f, 0x00916a00} 608 }; 609 610 static const u32 cayman_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = { 611 {0x00000077, 0xff010100}, 612 {0x00000078, 0x00000000}, 613 {0x00000079, 0x00001434}, 614 {0x0000007a, 0xcc08ec08}, 615 {0x0000007b, 0x00040000}, 616 {0x0000007c, 0x000080c0}, 617 {0x0000007d, 0x09000000}, 618 {0x0000007e, 0x00210404}, 619 {0x00000081, 0x08a8e800}, 620 {0x00000082, 0x00030444}, 621 {0x00000083, 0x00000000}, 622 {0x00000085, 0x00000001}, 623 {0x00000086, 0x00000002}, 624 {0x00000087, 0x48490000}, 625 {0x00000088, 0x20244647}, 626 {0x00000089, 0x00000005}, 627 {0x0000008b, 0x66030000}, 628 {0x0000008c, 0x00006603}, 629 {0x0000008d, 0x00000100}, 630 {0x0000008f, 0x00001c0a}, 631 {0x00000090, 0xff000001}, 632 {0x00000094, 0x00101101}, 633 {0x00000095, 0x00000fff}, 634 {0x00000096, 0x00116fff}, 635 {0x00000097, 0x60010000}, 636 {0x00000098, 0x10010000}, 637 {0x00000099, 0x00006000}, 638 {0x0000009a, 0x00001000}, 639 {0x0000009f, 0x00976b00} 640 }; 641 642 int ni_mc_load_microcode(struct radeon_device *rdev) 643 { 644 const __be32 *fw_data; 645 u32 mem_type, running, blackout = 0; 646 u32 *io_mc_regs; 647 int i, ucode_size, regs_size; 648 649 if (!rdev->mc_fw) 650 return -EINVAL; 651 652 switch (rdev->family) { 653 case CHIP_BARTS: 654 io_mc_regs = (u32 *)&barts_io_mc_regs; 655 ucode_size = BTC_MC_UCODE_SIZE; 656 regs_size = BTC_IO_MC_REGS_SIZE; 657 break; 658 case CHIP_TURKS: 659 io_mc_regs = (u32 *)&turks_io_mc_regs; 660 ucode_size = BTC_MC_UCODE_SIZE; 661 regs_size = BTC_IO_MC_REGS_SIZE; 662 break; 663 case CHIP_CAICOS: 664 default: 665 io_mc_regs = (u32 *)&caicos_io_mc_regs; 666 ucode_size = BTC_MC_UCODE_SIZE; 667 regs_size = BTC_IO_MC_REGS_SIZE; 668 break; 669 case CHIP_CAYMAN: 670 io_mc_regs = (u32 *)&cayman_io_mc_regs; 671 ucode_size = CAYMAN_MC_UCODE_SIZE; 672 regs_size = BTC_IO_MC_REGS_SIZE; 673 break; 674 } 675 676 mem_type = (RREG32(MC_SEQ_MISC0) & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT; 677 running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK; 678 679 if ((mem_type == MC_SEQ_MISC0_GDDR5_VALUE) && (running == 0)) { 680 if (running) { 681 blackout = RREG32(MC_SHARED_BLACKOUT_CNTL); 682 WREG32(MC_SHARED_BLACKOUT_CNTL, 1); 683 } 684 685 /* reset the engine and set to writable */ 686 WREG32(MC_SEQ_SUP_CNTL, 0x00000008); 687 WREG32(MC_SEQ_SUP_CNTL, 0x00000010); 688 689 /* load mc io regs */ 690 for (i = 0; i < regs_size; i++) { 691 WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]); 692 WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]); 693 } 694 /* load the MC ucode */ 695 fw_data = (const __be32 *)rdev->mc_fw->data; 696 for (i = 0; i < ucode_size; i++) 697 WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++)); 698 699 /* put the engine back into the active state */ 700 WREG32(MC_SEQ_SUP_CNTL, 0x00000008); 701 WREG32(MC_SEQ_SUP_CNTL, 0x00000004); 702 WREG32(MC_SEQ_SUP_CNTL, 0x00000001); 703 704 /* wait for training to complete */ 705 for (i = 0; i < rdev->usec_timeout; i++) { 706 if (RREG32(MC_IO_PAD_CNTL_D0) & MEM_FALL_OUT_CMD) 707 break; 708 udelay(1); 709 } 710 711 if (running) 712 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout); 713 } 714 715 return 0; 716 } 717 718 int ni_init_microcode(struct radeon_device *rdev) 719 { 720 const char *chip_name; 721 const char *rlc_chip_name; 722 size_t pfp_req_size, me_req_size, rlc_req_size, mc_req_size; 723 size_t smc_req_size = 0; 724 char fw_name[30]; 725 int err; 726 727 DRM_DEBUG("\n"); 728 729 switch (rdev->family) { 730 case CHIP_BARTS: 731 chip_name = "BARTS"; 732 rlc_chip_name = "BTC"; 733 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4; 734 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4; 735 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4; 736 mc_req_size = BTC_MC_UCODE_SIZE * 4; 737 smc_req_size = ALIGN(BARTS_SMC_UCODE_SIZE, 4); 738 break; 739 case CHIP_TURKS: 740 chip_name = "TURKS"; 741 rlc_chip_name = "BTC"; 742 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4; 743 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4; 744 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4; 745 mc_req_size = BTC_MC_UCODE_SIZE * 4; 746 smc_req_size = ALIGN(TURKS_SMC_UCODE_SIZE, 4); 747 break; 748 case CHIP_CAICOS: 749 chip_name = "CAICOS"; 750 rlc_chip_name = "BTC"; 751 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4; 752 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4; 753 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4; 754 mc_req_size = BTC_MC_UCODE_SIZE * 4; 755 smc_req_size = ALIGN(CAICOS_SMC_UCODE_SIZE, 4); 756 break; 757 case CHIP_CAYMAN: 758 chip_name = "CAYMAN"; 759 rlc_chip_name = "CAYMAN"; 760 pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4; 761 me_req_size = CAYMAN_PM4_UCODE_SIZE * 4; 762 rlc_req_size = CAYMAN_RLC_UCODE_SIZE * 4; 763 mc_req_size = CAYMAN_MC_UCODE_SIZE * 4; 764 smc_req_size = ALIGN(CAYMAN_SMC_UCODE_SIZE, 4); 765 break; 766 case CHIP_ARUBA: 767 chip_name = "ARUBA"; 768 rlc_chip_name = "ARUBA"; 769 /* pfp/me same size as CAYMAN */ 770 pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4; 771 me_req_size = CAYMAN_PM4_UCODE_SIZE * 4; 772 rlc_req_size = ARUBA_RLC_UCODE_SIZE * 4; 773 mc_req_size = 0; 774 break; 775 default: BUG(); 776 } 777 778 DRM_INFO("Loading %s Microcode\n", chip_name); 779 780 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name); 781 err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev); 782 if (err) 783 goto out; 784 if (rdev->pfp_fw->size != pfp_req_size) { 785 pr_err("ni_cp: Bogus length %zu in firmware \"%s\"\n", 786 rdev->pfp_fw->size, fw_name); 787 err = -EINVAL; 788 goto out; 789 } 790 791 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name); 792 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev); 793 if (err) 794 goto out; 795 if (rdev->me_fw->size != me_req_size) { 796 pr_err("ni_cp: Bogus length %zu in firmware \"%s\"\n", 797 rdev->me_fw->size, fw_name); 798 err = -EINVAL; 799 } 800 801 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name); 802 err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev); 803 if (err) 804 goto out; 805 if (rdev->rlc_fw->size != rlc_req_size) { 806 pr_err("ni_rlc: Bogus length %zu in firmware \"%s\"\n", 807 rdev->rlc_fw->size, fw_name); 808 err = -EINVAL; 809 } 810 811 /* no MC ucode on TN */ 812 if (!(rdev->flags & RADEON_IS_IGP)) { 813 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name); 814 err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev); 815 if (err) 816 goto out; 817 if (rdev->mc_fw->size != mc_req_size) { 818 pr_err("ni_mc: Bogus length %zu in firmware \"%s\"\n", 819 rdev->mc_fw->size, fw_name); 820 err = -EINVAL; 821 } 822 } 823 824 if ((rdev->family >= CHIP_BARTS) && (rdev->family <= CHIP_CAYMAN)) { 825 snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", chip_name); 826 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev); 827 if (err) { 828 pr_err("smc: error loading firmware \"%s\"\n", fw_name); 829 release_firmware(rdev->smc_fw); 830 rdev->smc_fw = NULL; 831 err = 0; 832 } else if (rdev->smc_fw->size != smc_req_size) { 833 pr_err("ni_mc: Bogus length %zu in firmware \"%s\"\n", 834 rdev->mc_fw->size, fw_name); 835 err = -EINVAL; 836 } 837 } 838 839 out: 840 if (err) { 841 if (err != -EINVAL) 842 pr_err("ni_cp: Failed to load firmware \"%s\"\n", 843 fw_name); 844 release_firmware(rdev->pfp_fw); 845 rdev->pfp_fw = NULL; 846 release_firmware(rdev->me_fw); 847 rdev->me_fw = NULL; 848 release_firmware(rdev->rlc_fw); 849 rdev->rlc_fw = NULL; 850 release_firmware(rdev->mc_fw); 851 rdev->mc_fw = NULL; 852 } 853 return err; 854 } 855 856 /** 857 * cayman_get_allowed_info_register - fetch the register for the info ioctl 858 * 859 * @rdev: radeon_device pointer 860 * @reg: register offset in bytes 861 * @val: register value 862 * 863 * Returns 0 for success or -EINVAL for an invalid register 864 * 865 */ 866 int cayman_get_allowed_info_register(struct radeon_device *rdev, 867 u32 reg, u32 *val) 868 { 869 switch (reg) { 870 case GRBM_STATUS: 871 case GRBM_STATUS_SE0: 872 case GRBM_STATUS_SE1: 873 case SRBM_STATUS: 874 case SRBM_STATUS2: 875 case (DMA_STATUS_REG + DMA0_REGISTER_OFFSET): 876 case (DMA_STATUS_REG + DMA1_REGISTER_OFFSET): 877 case UVD_STATUS: 878 *val = RREG32(reg); 879 return 0; 880 default: 881 return -EINVAL; 882 } 883 } 884 885 int tn_get_temp(struct radeon_device *rdev) 886 { 887 u32 temp = RREG32_SMC(TN_CURRENT_GNB_TEMP) & 0x7ff; 888 int actual_temp = (temp / 8) - 49; 889 890 return actual_temp * 1000; 891 } 892 893 /* 894 * Core functions 895 */ 896 static void cayman_gpu_init(struct radeon_device *rdev) 897 { 898 u32 gb_addr_config = 0; 899 u32 mc_shared_chmap, mc_arb_ramcfg; 900 u32 cgts_tcc_disable; 901 u32 sx_debug_1; 902 u32 smx_dc_ctl0; 903 u32 cgts_sm_ctrl_reg; 904 u32 hdp_host_path_cntl; 905 u32 tmp; 906 u32 disabled_rb_mask; 907 int i, j; 908 909 switch (rdev->family) { 910 case CHIP_CAYMAN: 911 rdev->config.cayman.max_shader_engines = 2; 912 rdev->config.cayman.max_pipes_per_simd = 4; 913 rdev->config.cayman.max_tile_pipes = 8; 914 rdev->config.cayman.max_simds_per_se = 12; 915 rdev->config.cayman.max_backends_per_se = 4; 916 rdev->config.cayman.max_texture_channel_caches = 8; 917 rdev->config.cayman.max_gprs = 256; 918 rdev->config.cayman.max_threads = 256; 919 rdev->config.cayman.max_gs_threads = 32; 920 rdev->config.cayman.max_stack_entries = 512; 921 rdev->config.cayman.sx_num_of_sets = 8; 922 rdev->config.cayman.sx_max_export_size = 256; 923 rdev->config.cayman.sx_max_export_pos_size = 64; 924 rdev->config.cayman.sx_max_export_smx_size = 192; 925 rdev->config.cayman.max_hw_contexts = 8; 926 rdev->config.cayman.sq_num_cf_insts = 2; 927 928 rdev->config.cayman.sc_prim_fifo_size = 0x100; 929 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30; 930 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130; 931 gb_addr_config = CAYMAN_GB_ADDR_CONFIG_GOLDEN; 932 break; 933 case CHIP_ARUBA: 934 default: 935 rdev->config.cayman.max_shader_engines = 1; 936 rdev->config.cayman.max_pipes_per_simd = 4; 937 rdev->config.cayman.max_tile_pipes = 2; 938 if ((rdev->pdev->device == 0x9900) || 939 (rdev->pdev->device == 0x9901) || 940 (rdev->pdev->device == 0x9905) || 941 (rdev->pdev->device == 0x9906) || 942 (rdev->pdev->device == 0x9907) || 943 (rdev->pdev->device == 0x9908) || 944 (rdev->pdev->device == 0x9909) || 945 (rdev->pdev->device == 0x990B) || 946 (rdev->pdev->device == 0x990C) || 947 (rdev->pdev->device == 0x990F) || 948 (rdev->pdev->device == 0x9910) || 949 (rdev->pdev->device == 0x9917) || 950 (rdev->pdev->device == 0x9999) || 951 (rdev->pdev->device == 0x999C)) { 952 rdev->config.cayman.max_simds_per_se = 6; 953 rdev->config.cayman.max_backends_per_se = 2; 954 rdev->config.cayman.max_hw_contexts = 8; 955 rdev->config.cayman.sx_max_export_size = 256; 956 rdev->config.cayman.sx_max_export_pos_size = 64; 957 rdev->config.cayman.sx_max_export_smx_size = 192; 958 } else if ((rdev->pdev->device == 0x9903) || 959 (rdev->pdev->device == 0x9904) || 960 (rdev->pdev->device == 0x990A) || 961 (rdev->pdev->device == 0x990D) || 962 (rdev->pdev->device == 0x990E) || 963 (rdev->pdev->device == 0x9913) || 964 (rdev->pdev->device == 0x9918) || 965 (rdev->pdev->device == 0x999D)) { 966 rdev->config.cayman.max_simds_per_se = 4; 967 rdev->config.cayman.max_backends_per_se = 2; 968 rdev->config.cayman.max_hw_contexts = 8; 969 rdev->config.cayman.sx_max_export_size = 256; 970 rdev->config.cayman.sx_max_export_pos_size = 64; 971 rdev->config.cayman.sx_max_export_smx_size = 192; 972 } else if ((rdev->pdev->device == 0x9919) || 973 (rdev->pdev->device == 0x9990) || 974 (rdev->pdev->device == 0x9991) || 975 (rdev->pdev->device == 0x9994) || 976 (rdev->pdev->device == 0x9995) || 977 (rdev->pdev->device == 0x9996) || 978 (rdev->pdev->device == 0x999A) || 979 (rdev->pdev->device == 0x99A0)) { 980 rdev->config.cayman.max_simds_per_se = 3; 981 rdev->config.cayman.max_backends_per_se = 1; 982 rdev->config.cayman.max_hw_contexts = 4; 983 rdev->config.cayman.sx_max_export_size = 128; 984 rdev->config.cayman.sx_max_export_pos_size = 32; 985 rdev->config.cayman.sx_max_export_smx_size = 96; 986 } else { 987 rdev->config.cayman.max_simds_per_se = 2; 988 rdev->config.cayman.max_backends_per_se = 1; 989 rdev->config.cayman.max_hw_contexts = 4; 990 rdev->config.cayman.sx_max_export_size = 128; 991 rdev->config.cayman.sx_max_export_pos_size = 32; 992 rdev->config.cayman.sx_max_export_smx_size = 96; 993 } 994 rdev->config.cayman.max_texture_channel_caches = 2; 995 rdev->config.cayman.max_gprs = 256; 996 rdev->config.cayman.max_threads = 256; 997 rdev->config.cayman.max_gs_threads = 32; 998 rdev->config.cayman.max_stack_entries = 512; 999 rdev->config.cayman.sx_num_of_sets = 8; 1000 rdev->config.cayman.sq_num_cf_insts = 2; 1001 1002 rdev->config.cayman.sc_prim_fifo_size = 0x40; 1003 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30; 1004 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130; 1005 gb_addr_config = ARUBA_GB_ADDR_CONFIG_GOLDEN; 1006 break; 1007 } 1008 1009 /* Initialize HDP */ 1010 for (i = 0, j = 0; i < 32; i++, j += 0x18) { 1011 WREG32((0x2c14 + j), 0x00000000); 1012 WREG32((0x2c18 + j), 0x00000000); 1013 WREG32((0x2c1c + j), 0x00000000); 1014 WREG32((0x2c20 + j), 0x00000000); 1015 WREG32((0x2c24 + j), 0x00000000); 1016 } 1017 1018 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); 1019 WREG32(SRBM_INT_CNTL, 0x1); 1020 WREG32(SRBM_INT_ACK, 0x1); 1021 1022 evergreen_fix_pci_max_read_req_size(rdev); 1023 1024 mc_shared_chmap = RREG32(MC_SHARED_CHMAP); 1025 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG); 1026 1027 tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT; 1028 rdev->config.cayman.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; 1029 if (rdev->config.cayman.mem_row_size_in_kb > 4) 1030 rdev->config.cayman.mem_row_size_in_kb = 4; 1031 /* XXX use MC settings? */ 1032 rdev->config.cayman.shader_engine_tile_size = 32; 1033 rdev->config.cayman.num_gpus = 1; 1034 rdev->config.cayman.multi_gpu_tile_size = 64; 1035 1036 tmp = (gb_addr_config & NUM_PIPES_MASK) >> NUM_PIPES_SHIFT; 1037 rdev->config.cayman.num_tile_pipes = (1 << tmp); 1038 tmp = (gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT; 1039 rdev->config.cayman.mem_max_burst_length_bytes = (tmp + 1) * 256; 1040 tmp = (gb_addr_config & NUM_SHADER_ENGINES_MASK) >> NUM_SHADER_ENGINES_SHIFT; 1041 rdev->config.cayman.num_shader_engines = tmp + 1; 1042 tmp = (gb_addr_config & NUM_GPUS_MASK) >> NUM_GPUS_SHIFT; 1043 rdev->config.cayman.num_gpus = tmp + 1; 1044 tmp = (gb_addr_config & MULTI_GPU_TILE_SIZE_MASK) >> MULTI_GPU_TILE_SIZE_SHIFT; 1045 rdev->config.cayman.multi_gpu_tile_size = 1 << tmp; 1046 tmp = (gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT; 1047 rdev->config.cayman.mem_row_size_in_kb = 1 << tmp; 1048 1049 1050 /* setup tiling info dword. gb_addr_config is not adequate since it does 1051 * not have bank info, so create a custom tiling dword. 1052 * bits 3:0 num_pipes 1053 * bits 7:4 num_banks 1054 * bits 11:8 group_size 1055 * bits 15:12 row_size 1056 */ 1057 rdev->config.cayman.tile_config = 0; 1058 switch (rdev->config.cayman.num_tile_pipes) { 1059 case 1: 1060 default: 1061 rdev->config.cayman.tile_config |= (0 << 0); 1062 break; 1063 case 2: 1064 rdev->config.cayman.tile_config |= (1 << 0); 1065 break; 1066 case 4: 1067 rdev->config.cayman.tile_config |= (2 << 0); 1068 break; 1069 case 8: 1070 rdev->config.cayman.tile_config |= (3 << 0); 1071 break; 1072 } 1073 1074 /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */ 1075 if (rdev->flags & RADEON_IS_IGP) 1076 rdev->config.cayman.tile_config |= 1 << 4; 1077 else { 1078 switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) { 1079 case 0: /* four banks */ 1080 rdev->config.cayman.tile_config |= 0 << 4; 1081 break; 1082 case 1: /* eight banks */ 1083 rdev->config.cayman.tile_config |= 1 << 4; 1084 break; 1085 case 2: /* sixteen banks */ 1086 default: 1087 rdev->config.cayman.tile_config |= 2 << 4; 1088 break; 1089 } 1090 } 1091 rdev->config.cayman.tile_config |= 1092 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8; 1093 rdev->config.cayman.tile_config |= 1094 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12; 1095 1096 tmp = 0; 1097 for (i = (rdev->config.cayman.max_shader_engines - 1); i >= 0; i--) { 1098 u32 rb_disable_bitmap; 1099 1100 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i)); 1101 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i)); 1102 rb_disable_bitmap = (RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000) >> 16; 1103 tmp <<= 4; 1104 tmp |= rb_disable_bitmap; 1105 } 1106 /* enabled rb are just the one not disabled :) */ 1107 disabled_rb_mask = tmp; 1108 tmp = 0; 1109 for (i = 0; i < (rdev->config.cayman.max_backends_per_se * rdev->config.cayman.max_shader_engines); i++) 1110 tmp |= (1 << i); 1111 /* if all the backends are disabled, fix it up here */ 1112 if ((disabled_rb_mask & tmp) == tmp) { 1113 for (i = 0; i < (rdev->config.cayman.max_backends_per_se * rdev->config.cayman.max_shader_engines); i++) 1114 disabled_rb_mask &= ~(1 << i); 1115 } 1116 1117 for (i = 0; i < rdev->config.cayman.max_shader_engines; i++) { 1118 u32 simd_disable_bitmap; 1119 1120 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i)); 1121 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i)); 1122 simd_disable_bitmap = (RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffff0000) >> 16; 1123 simd_disable_bitmap |= 0xffffffff << rdev->config.cayman.max_simds_per_se; 1124 tmp <<= 16; 1125 tmp |= simd_disable_bitmap; 1126 } 1127 rdev->config.cayman.active_simds = hweight32(~tmp); 1128 1129 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES); 1130 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES); 1131 1132 WREG32(GB_ADDR_CONFIG, gb_addr_config); 1133 WREG32(DMIF_ADDR_CONFIG, gb_addr_config); 1134 if (ASIC_IS_DCE6(rdev)) 1135 WREG32(DMIF_ADDR_CALC, gb_addr_config); 1136 WREG32(HDP_ADDR_CONFIG, gb_addr_config); 1137 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config); 1138 WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config); 1139 WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config); 1140 WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config); 1141 WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config); 1142 1143 if ((rdev->config.cayman.max_backends_per_se == 1) && 1144 (rdev->flags & RADEON_IS_IGP)) { 1145 if ((disabled_rb_mask & 3) == 2) { 1146 /* RB1 disabled, RB0 enabled */ 1147 tmp = 0x00000000; 1148 } else { 1149 /* RB0 disabled, RB1 enabled */ 1150 tmp = 0x11111111; 1151 } 1152 } else { 1153 tmp = gb_addr_config & NUM_PIPES_MASK; 1154 tmp = r6xx_remap_render_backend(rdev, tmp, 1155 rdev->config.cayman.max_backends_per_se * 1156 rdev->config.cayman.max_shader_engines, 1157 CAYMAN_MAX_BACKENDS, disabled_rb_mask); 1158 } 1159 rdev->config.cayman.backend_map = tmp; 1160 WREG32(GB_BACKEND_MAP, tmp); 1161 1162 cgts_tcc_disable = 0xffff0000; 1163 for (i = 0; i < rdev->config.cayman.max_texture_channel_caches; i++) 1164 cgts_tcc_disable &= ~(1 << (16 + i)); 1165 WREG32(CGTS_TCC_DISABLE, cgts_tcc_disable); 1166 WREG32(CGTS_SYS_TCC_DISABLE, cgts_tcc_disable); 1167 WREG32(CGTS_USER_SYS_TCC_DISABLE, cgts_tcc_disable); 1168 WREG32(CGTS_USER_TCC_DISABLE, cgts_tcc_disable); 1169 1170 /* reprogram the shader complex */ 1171 cgts_sm_ctrl_reg = RREG32(CGTS_SM_CTRL_REG); 1172 for (i = 0; i < 16; i++) 1173 WREG32(CGTS_SM_CTRL_REG, OVERRIDE); 1174 WREG32(CGTS_SM_CTRL_REG, cgts_sm_ctrl_reg); 1175 1176 /* set HW defaults for 3D engine */ 1177 WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60)); 1178 1179 sx_debug_1 = RREG32(SX_DEBUG_1); 1180 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS; 1181 WREG32(SX_DEBUG_1, sx_debug_1); 1182 1183 smx_dc_ctl0 = RREG32(SMX_DC_CTL0); 1184 smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff); 1185 smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.cayman.sx_num_of_sets); 1186 WREG32(SMX_DC_CTL0, smx_dc_ctl0); 1187 1188 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4) | CRC_SIMD_ID_WADDR_DISABLE); 1189 1190 /* need to be explicitly zero-ed */ 1191 WREG32(VGT_OFFCHIP_LDS_BASE, 0); 1192 WREG32(SQ_LSTMP_RING_BASE, 0); 1193 WREG32(SQ_HSTMP_RING_BASE, 0); 1194 WREG32(SQ_ESTMP_RING_BASE, 0); 1195 WREG32(SQ_GSTMP_RING_BASE, 0); 1196 WREG32(SQ_VSTMP_RING_BASE, 0); 1197 WREG32(SQ_PSTMP_RING_BASE, 0); 1198 1199 WREG32(TA_CNTL_AUX, DISABLE_CUBE_ANISO); 1200 1201 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.cayman.sx_max_export_size / 4) - 1) | 1202 POSITION_BUFFER_SIZE((rdev->config.cayman.sx_max_export_pos_size / 4) - 1) | 1203 SMX_BUFFER_SIZE((rdev->config.cayman.sx_max_export_smx_size / 4) - 1))); 1204 1205 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.cayman.sc_prim_fifo_size) | 1206 SC_HIZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_hiz_tile_fifo_size) | 1207 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_earlyz_tile_fifo_size))); 1208 1209 1210 WREG32(VGT_NUM_INSTANCES, 1); 1211 1212 WREG32(CP_PERFMON_CNTL, 0); 1213 1214 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.cayman.sq_num_cf_insts) | 1215 FETCH_FIFO_HIWATER(0x4) | 1216 DONE_FIFO_HIWATER(0xe0) | 1217 ALU_UPDATE_FIFO_HIWATER(0x8))); 1218 1219 WREG32(SQ_GPR_RESOURCE_MGMT_1, NUM_CLAUSE_TEMP_GPRS(4)); 1220 WREG32(SQ_CONFIG, (VC_ENABLE | 1221 EXPORT_SRC_C | 1222 GFX_PRIO(0) | 1223 CS1_PRIO(0) | 1224 CS2_PRIO(1))); 1225 WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, DYN_GPR_ENABLE); 1226 1227 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) | 1228 FORCE_EOV_MAX_REZ_CNT(255))); 1229 1230 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) | 1231 AUTO_INVLD_EN(ES_AND_GS_AUTO)); 1232 1233 WREG32(VGT_GS_VERTEX_REUSE, 16); 1234 WREG32(PA_SC_LINE_STIPPLE_STATE, 0); 1235 1236 WREG32(CB_PERF_CTR0_SEL_0, 0); 1237 WREG32(CB_PERF_CTR0_SEL_1, 0); 1238 WREG32(CB_PERF_CTR1_SEL_0, 0); 1239 WREG32(CB_PERF_CTR1_SEL_1, 0); 1240 WREG32(CB_PERF_CTR2_SEL_0, 0); 1241 WREG32(CB_PERF_CTR2_SEL_1, 0); 1242 WREG32(CB_PERF_CTR3_SEL_0, 0); 1243 WREG32(CB_PERF_CTR3_SEL_1, 0); 1244 1245 tmp = RREG32(HDP_MISC_CNTL); 1246 tmp |= HDP_FLUSH_INVALIDATE_CACHE; 1247 WREG32(HDP_MISC_CNTL, tmp); 1248 1249 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL); 1250 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl); 1251 1252 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3)); 1253 1254 udelay(50); 1255 1256 /* set clockgating golden values on TN */ 1257 if (rdev->family == CHIP_ARUBA) { 1258 tmp = RREG32_CG(CG_CGTT_LOCAL_0); 1259 tmp &= ~0x00380000; 1260 WREG32_CG(CG_CGTT_LOCAL_0, tmp); 1261 tmp = RREG32_CG(CG_CGTT_LOCAL_1); 1262 tmp &= ~0x0e000000; 1263 WREG32_CG(CG_CGTT_LOCAL_1, tmp); 1264 } 1265 } 1266 1267 /* 1268 * GART 1269 */ 1270 void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev) 1271 { 1272 /* flush hdp cache */ 1273 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); 1274 1275 /* bits 0-7 are the VM contexts0-7 */ 1276 WREG32(VM_INVALIDATE_REQUEST, 1); 1277 } 1278 1279 static int cayman_pcie_gart_enable(struct radeon_device *rdev) 1280 { 1281 int i, r; 1282 1283 if (rdev->gart.robj == NULL) { 1284 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); 1285 return -EINVAL; 1286 } 1287 r = radeon_gart_table_vram_pin(rdev); 1288 if (r) 1289 return r; 1290 /* Setup TLB control */ 1291 WREG32(MC_VM_MX_L1_TLB_CNTL, 1292 (0xA << 7) | 1293 ENABLE_L1_TLB | 1294 ENABLE_L1_FRAGMENT_PROCESSING | 1295 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 1296 ENABLE_ADVANCED_DRIVER_MODEL | 1297 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU); 1298 /* Setup L2 cache */ 1299 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | 1300 ENABLE_L2_FRAGMENT_PROCESSING | 1301 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 1302 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE | 1303 EFFECTIVE_L2_QUEUE_SIZE(7) | 1304 CONTEXT1_IDENTITY_ACCESS_MODE(1)); 1305 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE); 1306 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | 1307 BANK_SELECT(6) | 1308 L2_CACHE_BIGK_FRAGMENT_SIZE(6)); 1309 /* setup context0 */ 1310 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); 1311 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); 1312 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); 1313 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 1314 (u32)(rdev->dummy_page.addr >> 12)); 1315 WREG32(VM_CONTEXT0_CNTL2, 0); 1316 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | 1317 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); 1318 1319 WREG32(0x15D4, 0); 1320 WREG32(0x15D8, 0); 1321 WREG32(0x15DC, 0); 1322 1323 /* empty context1-7 */ 1324 /* Assign the pt base to something valid for now; the pts used for 1325 * the VMs are determined by the application and setup and assigned 1326 * on the fly in the vm part of radeon_gart.c 1327 */ 1328 for (i = 1; i < 8; i++) { 1329 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (i << 2), 0); 1330 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (i << 2), 1331 rdev->vm_manager.max_pfn - 1); 1332 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2), 1333 rdev->vm_manager.saved_table_addr[i]); 1334 } 1335 1336 /* enable context1-7 */ 1337 WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, 1338 (u32)(rdev->dummy_page.addr >> 12)); 1339 WREG32(VM_CONTEXT1_CNTL2, 4); 1340 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) | 1341 PAGE_TABLE_BLOCK_SIZE(radeon_vm_block_size - 9) | 1342 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT | 1343 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT | 1344 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT | 1345 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT | 1346 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT | 1347 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT | 1348 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT | 1349 VALID_PROTECTION_FAULT_ENABLE_DEFAULT | 1350 READ_PROTECTION_FAULT_ENABLE_INTERRUPT | 1351 READ_PROTECTION_FAULT_ENABLE_DEFAULT | 1352 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT | 1353 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT); 1354 1355 cayman_pcie_gart_tlb_flush(rdev); 1356 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 1357 (unsigned)(rdev->mc.gtt_size >> 20), 1358 (unsigned long long)rdev->gart.table_addr); 1359 rdev->gart.ready = true; 1360 return 0; 1361 } 1362 1363 static void cayman_pcie_gart_disable(struct radeon_device *rdev) 1364 { 1365 unsigned i; 1366 1367 for (i = 1; i < 8; ++i) { 1368 rdev->vm_manager.saved_table_addr[i] = RREG32( 1369 VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2)); 1370 } 1371 1372 /* Disable all tables */ 1373 WREG32(VM_CONTEXT0_CNTL, 0); 1374 WREG32(VM_CONTEXT1_CNTL, 0); 1375 /* Setup TLB control */ 1376 WREG32(MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING | 1377 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 1378 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU); 1379 /* Setup L2 cache */ 1380 WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 1381 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE | 1382 EFFECTIVE_L2_QUEUE_SIZE(7) | 1383 CONTEXT1_IDENTITY_ACCESS_MODE(1)); 1384 WREG32(VM_L2_CNTL2, 0); 1385 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | 1386 L2_CACHE_BIGK_FRAGMENT_SIZE(6)); 1387 radeon_gart_table_vram_unpin(rdev); 1388 } 1389 1390 static void cayman_pcie_gart_fini(struct radeon_device *rdev) 1391 { 1392 cayman_pcie_gart_disable(rdev); 1393 radeon_gart_table_vram_free(rdev); 1394 radeon_gart_fini(rdev); 1395 } 1396 1397 void cayman_cp_int_cntl_setup(struct radeon_device *rdev, 1398 int ring, u32 cp_int_cntl) 1399 { 1400 WREG32(SRBM_GFX_CNTL, RINGID(ring)); 1401 WREG32(CP_INT_CNTL, cp_int_cntl); 1402 } 1403 1404 /* 1405 * CP. 1406 */ 1407 void cayman_fence_ring_emit(struct radeon_device *rdev, 1408 struct radeon_fence *fence) 1409 { 1410 struct radeon_ring *ring = &rdev->ring[fence->ring]; 1411 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; 1412 u32 cp_coher_cntl = PACKET3_FULL_CACHE_ENA | PACKET3_TC_ACTION_ENA | 1413 PACKET3_SH_ACTION_ENA; 1414 1415 /* flush read cache over gart for this vmid */ 1416 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 1417 radeon_ring_write(ring, PACKET3_ENGINE_ME | cp_coher_cntl); 1418 radeon_ring_write(ring, 0xFFFFFFFF); 1419 radeon_ring_write(ring, 0); 1420 radeon_ring_write(ring, 10); /* poll interval */ 1421 /* EVENT_WRITE_EOP - flush caches, send int */ 1422 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); 1423 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5)); 1424 radeon_ring_write(ring, lower_32_bits(addr)); 1425 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); 1426 radeon_ring_write(ring, fence->seq); 1427 radeon_ring_write(ring, 0); 1428 } 1429 1430 void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) 1431 { 1432 struct radeon_ring *ring = &rdev->ring[ib->ring]; 1433 unsigned vm_id = ib->vm ? ib->vm->ids[ib->ring].id : 0; 1434 u32 cp_coher_cntl = PACKET3_FULL_CACHE_ENA | PACKET3_TC_ACTION_ENA | 1435 PACKET3_SH_ACTION_ENA; 1436 1437 /* set to DX10/11 mode */ 1438 radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0)); 1439 radeon_ring_write(ring, 1); 1440 1441 if (ring->rptr_save_reg) { 1442 uint32_t next_rptr = ring->wptr + 3 + 4 + 8; 1443 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 1444 radeon_ring_write(ring, ((ring->rptr_save_reg - 1445 PACKET3_SET_CONFIG_REG_START) >> 2)); 1446 radeon_ring_write(ring, next_rptr); 1447 } 1448 1449 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 1450 radeon_ring_write(ring, 1451 #ifdef __BIG_ENDIAN 1452 (2 << 0) | 1453 #endif 1454 (ib->gpu_addr & 0xFFFFFFFC)); 1455 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF); 1456 radeon_ring_write(ring, ib->length_dw | (vm_id << 24)); 1457 1458 /* flush read cache over gart for this vmid */ 1459 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 1460 radeon_ring_write(ring, PACKET3_ENGINE_ME | cp_coher_cntl); 1461 radeon_ring_write(ring, 0xFFFFFFFF); 1462 radeon_ring_write(ring, 0); 1463 radeon_ring_write(ring, (vm_id << 24) | 10); /* poll interval */ 1464 } 1465 1466 static void cayman_cp_enable(struct radeon_device *rdev, bool enable) 1467 { 1468 if (enable) 1469 WREG32(CP_ME_CNTL, 0); 1470 else { 1471 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX) 1472 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 1473 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT)); 1474 WREG32(SCRATCH_UMSK, 0); 1475 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; 1476 } 1477 } 1478 1479 u32 cayman_gfx_get_rptr(struct radeon_device *rdev, 1480 struct radeon_ring *ring) 1481 { 1482 u32 rptr; 1483 1484 if (rdev->wb.enabled) 1485 rptr = rdev->wb.wb[ring->rptr_offs/4]; 1486 else { 1487 if (ring->idx == RADEON_RING_TYPE_GFX_INDEX) 1488 rptr = RREG32(CP_RB0_RPTR); 1489 else if (ring->idx == CAYMAN_RING_TYPE_CP1_INDEX) 1490 rptr = RREG32(CP_RB1_RPTR); 1491 else 1492 rptr = RREG32(CP_RB2_RPTR); 1493 } 1494 1495 return rptr; 1496 } 1497 1498 u32 cayman_gfx_get_wptr(struct radeon_device *rdev, 1499 struct radeon_ring *ring) 1500 { 1501 u32 wptr; 1502 1503 if (ring->idx == RADEON_RING_TYPE_GFX_INDEX) 1504 wptr = RREG32(CP_RB0_WPTR); 1505 else if (ring->idx == CAYMAN_RING_TYPE_CP1_INDEX) 1506 wptr = RREG32(CP_RB1_WPTR); 1507 else 1508 wptr = RREG32(CP_RB2_WPTR); 1509 1510 return wptr; 1511 } 1512 1513 void cayman_gfx_set_wptr(struct radeon_device *rdev, 1514 struct radeon_ring *ring) 1515 { 1516 if (ring->idx == RADEON_RING_TYPE_GFX_INDEX) { 1517 WREG32(CP_RB0_WPTR, ring->wptr); 1518 (void)RREG32(CP_RB0_WPTR); 1519 } else if (ring->idx == CAYMAN_RING_TYPE_CP1_INDEX) { 1520 WREG32(CP_RB1_WPTR, ring->wptr); 1521 (void)RREG32(CP_RB1_WPTR); 1522 } else { 1523 WREG32(CP_RB2_WPTR, ring->wptr); 1524 (void)RREG32(CP_RB2_WPTR); 1525 } 1526 } 1527 1528 static int cayman_cp_load_microcode(struct radeon_device *rdev) 1529 { 1530 const __be32 *fw_data; 1531 int i; 1532 1533 if (!rdev->me_fw || !rdev->pfp_fw) 1534 return -EINVAL; 1535 1536 cayman_cp_enable(rdev, false); 1537 1538 fw_data = (const __be32 *)rdev->pfp_fw->data; 1539 WREG32(CP_PFP_UCODE_ADDR, 0); 1540 for (i = 0; i < CAYMAN_PFP_UCODE_SIZE; i++) 1541 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++)); 1542 WREG32(CP_PFP_UCODE_ADDR, 0); 1543 1544 fw_data = (const __be32 *)rdev->me_fw->data; 1545 WREG32(CP_ME_RAM_WADDR, 0); 1546 for (i = 0; i < CAYMAN_PM4_UCODE_SIZE; i++) 1547 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++)); 1548 1549 WREG32(CP_PFP_UCODE_ADDR, 0); 1550 WREG32(CP_ME_RAM_WADDR, 0); 1551 WREG32(CP_ME_RAM_RADDR, 0); 1552 return 0; 1553 } 1554 1555 static int cayman_cp_start(struct radeon_device *rdev) 1556 { 1557 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 1558 int r, i; 1559 1560 r = radeon_ring_lock(rdev, ring, 7); 1561 if (r) { 1562 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); 1563 return r; 1564 } 1565 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); 1566 radeon_ring_write(ring, 0x1); 1567 radeon_ring_write(ring, 0x0); 1568 radeon_ring_write(ring, rdev->config.cayman.max_hw_contexts - 1); 1569 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); 1570 radeon_ring_write(ring, 0); 1571 radeon_ring_write(ring, 0); 1572 radeon_ring_unlock_commit(rdev, ring, false); 1573 1574 cayman_cp_enable(rdev, true); 1575 1576 r = radeon_ring_lock(rdev, ring, cayman_default_size + 19); 1577 if (r) { 1578 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); 1579 return r; 1580 } 1581 1582 /* setup clear context state */ 1583 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 1584 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 1585 1586 for (i = 0; i < cayman_default_size; i++) 1587 radeon_ring_write(ring, cayman_default_state[i]); 1588 1589 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 1590 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 1591 1592 /* set clear context state */ 1593 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 1594 radeon_ring_write(ring, 0); 1595 1596 /* SQ_VTX_BASE_VTX_LOC */ 1597 radeon_ring_write(ring, 0xc0026f00); 1598 radeon_ring_write(ring, 0x00000000); 1599 radeon_ring_write(ring, 0x00000000); 1600 radeon_ring_write(ring, 0x00000000); 1601 1602 /* Clear consts */ 1603 radeon_ring_write(ring, 0xc0036f00); 1604 radeon_ring_write(ring, 0x00000bc4); 1605 radeon_ring_write(ring, 0xffffffff); 1606 radeon_ring_write(ring, 0xffffffff); 1607 radeon_ring_write(ring, 0xffffffff); 1608 1609 radeon_ring_write(ring, 0xc0026900); 1610 radeon_ring_write(ring, 0x00000316); 1611 radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */ 1612 radeon_ring_write(ring, 0x00000010); /* */ 1613 1614 radeon_ring_unlock_commit(rdev, ring, false); 1615 1616 /* XXX init other rings */ 1617 1618 return 0; 1619 } 1620 1621 static void cayman_cp_fini(struct radeon_device *rdev) 1622 { 1623 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 1624 cayman_cp_enable(rdev, false); 1625 radeon_ring_fini(rdev, ring); 1626 radeon_scratch_free(rdev, ring->rptr_save_reg); 1627 } 1628 1629 static int cayman_cp_resume(struct radeon_device *rdev) 1630 { 1631 static const int ridx[] = { 1632 RADEON_RING_TYPE_GFX_INDEX, 1633 CAYMAN_RING_TYPE_CP1_INDEX, 1634 CAYMAN_RING_TYPE_CP2_INDEX 1635 }; 1636 static const unsigned cp_rb_cntl[] = { 1637 CP_RB0_CNTL, 1638 CP_RB1_CNTL, 1639 CP_RB2_CNTL, 1640 }; 1641 static const unsigned cp_rb_rptr_addr[] = { 1642 CP_RB0_RPTR_ADDR, 1643 CP_RB1_RPTR_ADDR, 1644 CP_RB2_RPTR_ADDR 1645 }; 1646 static const unsigned cp_rb_rptr_addr_hi[] = { 1647 CP_RB0_RPTR_ADDR_HI, 1648 CP_RB1_RPTR_ADDR_HI, 1649 CP_RB2_RPTR_ADDR_HI 1650 }; 1651 static const unsigned cp_rb_base[] = { 1652 CP_RB0_BASE, 1653 CP_RB1_BASE, 1654 CP_RB2_BASE 1655 }; 1656 static const unsigned cp_rb_rptr[] = { 1657 CP_RB0_RPTR, 1658 CP_RB1_RPTR, 1659 CP_RB2_RPTR 1660 }; 1661 static const unsigned cp_rb_wptr[] = { 1662 CP_RB0_WPTR, 1663 CP_RB1_WPTR, 1664 CP_RB2_WPTR 1665 }; 1666 struct radeon_ring *ring; 1667 int i, r; 1668 1669 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */ 1670 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP | 1671 SOFT_RESET_PA | 1672 SOFT_RESET_SH | 1673 SOFT_RESET_VGT | 1674 SOFT_RESET_SPI | 1675 SOFT_RESET_SX)); 1676 RREG32(GRBM_SOFT_RESET); 1677 mdelay(15); 1678 WREG32(GRBM_SOFT_RESET, 0); 1679 RREG32(GRBM_SOFT_RESET); 1680 1681 WREG32(CP_SEM_WAIT_TIMER, 0x0); 1682 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0); 1683 1684 /* Set the write pointer delay */ 1685 WREG32(CP_RB_WPTR_DELAY, 0); 1686 1687 WREG32(CP_DEBUG, (1 << 27)); 1688 1689 /* set the wb address whether it's enabled or not */ 1690 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); 1691 WREG32(SCRATCH_UMSK, 0xff); 1692 1693 for (i = 0; i < 3; ++i) { 1694 uint32_t rb_cntl; 1695 uint64_t addr; 1696 1697 /* Set ring buffer size */ 1698 ring = &rdev->ring[ridx[i]]; 1699 rb_cntl = order_base_2(ring->ring_size / 8); 1700 rb_cntl |= order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8; 1701 #ifdef __BIG_ENDIAN 1702 rb_cntl |= BUF_SWAP_32BIT; 1703 #endif 1704 WREG32(cp_rb_cntl[i], rb_cntl); 1705 1706 /* set the wb address whether it's enabled or not */ 1707 addr = rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET; 1708 WREG32(cp_rb_rptr_addr[i], addr & 0xFFFFFFFC); 1709 WREG32(cp_rb_rptr_addr_hi[i], upper_32_bits(addr) & 0xFF); 1710 } 1711 1712 /* set the rb base addr, this causes an internal reset of ALL rings */ 1713 for (i = 0; i < 3; ++i) { 1714 ring = &rdev->ring[ridx[i]]; 1715 WREG32(cp_rb_base[i], ring->gpu_addr >> 8); 1716 } 1717 1718 for (i = 0; i < 3; ++i) { 1719 /* Initialize the ring buffer's read and write pointers */ 1720 ring = &rdev->ring[ridx[i]]; 1721 WREG32_P(cp_rb_cntl[i], RB_RPTR_WR_ENA, ~RB_RPTR_WR_ENA); 1722 1723 ring->wptr = 0; 1724 WREG32(cp_rb_rptr[i], 0); 1725 WREG32(cp_rb_wptr[i], ring->wptr); 1726 1727 mdelay(1); 1728 WREG32_P(cp_rb_cntl[i], 0, ~RB_RPTR_WR_ENA); 1729 } 1730 1731 /* start the rings */ 1732 cayman_cp_start(rdev); 1733 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true; 1734 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false; 1735 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false; 1736 /* this only test cp0 */ 1737 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); 1738 if (r) { 1739 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; 1740 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false; 1741 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false; 1742 return r; 1743 } 1744 1745 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX) 1746 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); 1747 1748 return 0; 1749 } 1750 1751 u32 cayman_gpu_check_soft_reset(struct radeon_device *rdev) 1752 { 1753 u32 reset_mask = 0; 1754 u32 tmp; 1755 1756 /* GRBM_STATUS */ 1757 tmp = RREG32(GRBM_STATUS); 1758 if (tmp & (PA_BUSY | SC_BUSY | 1759 SH_BUSY | SX_BUSY | 1760 TA_BUSY | VGT_BUSY | 1761 DB_BUSY | CB_BUSY | 1762 GDS_BUSY | SPI_BUSY | 1763 IA_BUSY | IA_BUSY_NO_DMA)) 1764 reset_mask |= RADEON_RESET_GFX; 1765 1766 if (tmp & (CF_RQ_PENDING | PF_RQ_PENDING | 1767 CP_BUSY | CP_COHERENCY_BUSY)) 1768 reset_mask |= RADEON_RESET_CP; 1769 1770 if (tmp & GRBM_EE_BUSY) 1771 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP; 1772 1773 /* DMA_STATUS_REG 0 */ 1774 tmp = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET); 1775 if (!(tmp & DMA_IDLE)) 1776 reset_mask |= RADEON_RESET_DMA; 1777 1778 /* DMA_STATUS_REG 1 */ 1779 tmp = RREG32(DMA_STATUS_REG + DMA1_REGISTER_OFFSET); 1780 if (!(tmp & DMA_IDLE)) 1781 reset_mask |= RADEON_RESET_DMA1; 1782 1783 /* SRBM_STATUS2 */ 1784 tmp = RREG32(SRBM_STATUS2); 1785 if (tmp & DMA_BUSY) 1786 reset_mask |= RADEON_RESET_DMA; 1787 1788 if (tmp & DMA1_BUSY) 1789 reset_mask |= RADEON_RESET_DMA1; 1790 1791 /* SRBM_STATUS */ 1792 tmp = RREG32(SRBM_STATUS); 1793 if (tmp & (RLC_RQ_PENDING | RLC_BUSY)) 1794 reset_mask |= RADEON_RESET_RLC; 1795 1796 if (tmp & IH_BUSY) 1797 reset_mask |= RADEON_RESET_IH; 1798 1799 if (tmp & SEM_BUSY) 1800 reset_mask |= RADEON_RESET_SEM; 1801 1802 if (tmp & GRBM_RQ_PENDING) 1803 reset_mask |= RADEON_RESET_GRBM; 1804 1805 if (tmp & VMC_BUSY) 1806 reset_mask |= RADEON_RESET_VMC; 1807 1808 if (tmp & (MCB_BUSY | MCB_NON_DISPLAY_BUSY | 1809 MCC_BUSY | MCD_BUSY)) 1810 reset_mask |= RADEON_RESET_MC; 1811 1812 if (evergreen_is_display_hung(rdev)) 1813 reset_mask |= RADEON_RESET_DISPLAY; 1814 1815 /* VM_L2_STATUS */ 1816 tmp = RREG32(VM_L2_STATUS); 1817 if (tmp & L2_BUSY) 1818 reset_mask |= RADEON_RESET_VMC; 1819 1820 /* Skip MC reset as it's mostly likely not hung, just busy */ 1821 if (reset_mask & RADEON_RESET_MC) { 1822 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask); 1823 reset_mask &= ~RADEON_RESET_MC; 1824 } 1825 1826 return reset_mask; 1827 } 1828 1829 static void cayman_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask) 1830 { 1831 struct evergreen_mc_save save; 1832 u32 grbm_soft_reset = 0, srbm_soft_reset = 0; 1833 u32 tmp; 1834 1835 if (reset_mask == 0) 1836 return; 1837 1838 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask); 1839 1840 evergreen_print_gpu_status_regs(rdev); 1841 dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_ADDR 0x%08X\n", 1842 RREG32(0x14F8)); 1843 dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_STATUS 0x%08X\n", 1844 RREG32(0x14D8)); 1845 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", 1846 RREG32(0x14FC)); 1847 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", 1848 RREG32(0x14DC)); 1849 1850 /* Disable CP parsing/prefetching */ 1851 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT); 1852 1853 if (reset_mask & RADEON_RESET_DMA) { 1854 /* dma0 */ 1855 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); 1856 tmp &= ~DMA_RB_ENABLE; 1857 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp); 1858 } 1859 1860 if (reset_mask & RADEON_RESET_DMA1) { 1861 /* dma1 */ 1862 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET); 1863 tmp &= ~DMA_RB_ENABLE; 1864 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp); 1865 } 1866 1867 udelay(50); 1868 1869 evergreen_mc_stop(rdev, &save); 1870 if (evergreen_mc_wait_for_idle(rdev)) { 1871 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1872 } 1873 1874 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) { 1875 grbm_soft_reset = SOFT_RESET_CB | 1876 SOFT_RESET_DB | 1877 SOFT_RESET_GDS | 1878 SOFT_RESET_PA | 1879 SOFT_RESET_SC | 1880 SOFT_RESET_SPI | 1881 SOFT_RESET_SH | 1882 SOFT_RESET_SX | 1883 SOFT_RESET_TC | 1884 SOFT_RESET_TA | 1885 SOFT_RESET_VGT | 1886 SOFT_RESET_IA; 1887 } 1888 1889 if (reset_mask & RADEON_RESET_CP) { 1890 grbm_soft_reset |= SOFT_RESET_CP | SOFT_RESET_VGT; 1891 1892 srbm_soft_reset |= SOFT_RESET_GRBM; 1893 } 1894 1895 if (reset_mask & RADEON_RESET_DMA) 1896 srbm_soft_reset |= SOFT_RESET_DMA; 1897 1898 if (reset_mask & RADEON_RESET_DMA1) 1899 srbm_soft_reset |= SOFT_RESET_DMA1; 1900 1901 if (reset_mask & RADEON_RESET_DISPLAY) 1902 srbm_soft_reset |= SOFT_RESET_DC; 1903 1904 if (reset_mask & RADEON_RESET_RLC) 1905 srbm_soft_reset |= SOFT_RESET_RLC; 1906 1907 if (reset_mask & RADEON_RESET_SEM) 1908 srbm_soft_reset |= SOFT_RESET_SEM; 1909 1910 if (reset_mask & RADEON_RESET_IH) 1911 srbm_soft_reset |= SOFT_RESET_IH; 1912 1913 if (reset_mask & RADEON_RESET_GRBM) 1914 srbm_soft_reset |= SOFT_RESET_GRBM; 1915 1916 if (reset_mask & RADEON_RESET_VMC) 1917 srbm_soft_reset |= SOFT_RESET_VMC; 1918 1919 if (!(rdev->flags & RADEON_IS_IGP)) { 1920 if (reset_mask & RADEON_RESET_MC) 1921 srbm_soft_reset |= SOFT_RESET_MC; 1922 } 1923 1924 if (grbm_soft_reset) { 1925 tmp = RREG32(GRBM_SOFT_RESET); 1926 tmp |= grbm_soft_reset; 1927 dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 1928 WREG32(GRBM_SOFT_RESET, tmp); 1929 tmp = RREG32(GRBM_SOFT_RESET); 1930 1931 udelay(50); 1932 1933 tmp &= ~grbm_soft_reset; 1934 WREG32(GRBM_SOFT_RESET, tmp); 1935 tmp = RREG32(GRBM_SOFT_RESET); 1936 } 1937 1938 if (srbm_soft_reset) { 1939 tmp = RREG32(SRBM_SOFT_RESET); 1940 tmp |= srbm_soft_reset; 1941 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1942 WREG32(SRBM_SOFT_RESET, tmp); 1943 tmp = RREG32(SRBM_SOFT_RESET); 1944 1945 udelay(50); 1946 1947 tmp &= ~srbm_soft_reset; 1948 WREG32(SRBM_SOFT_RESET, tmp); 1949 tmp = RREG32(SRBM_SOFT_RESET); 1950 } 1951 1952 /* Wait a little for things to settle down */ 1953 udelay(50); 1954 1955 evergreen_mc_resume(rdev, &save); 1956 udelay(50); 1957 1958 evergreen_print_gpu_status_regs(rdev); 1959 } 1960 1961 int cayman_asic_reset(struct radeon_device *rdev, bool hard) 1962 { 1963 u32 reset_mask; 1964 1965 if (hard) { 1966 evergreen_gpu_pci_config_reset(rdev); 1967 return 0; 1968 } 1969 1970 reset_mask = cayman_gpu_check_soft_reset(rdev); 1971 1972 if (reset_mask) 1973 r600_set_bios_scratch_engine_hung(rdev, true); 1974 1975 cayman_gpu_soft_reset(rdev, reset_mask); 1976 1977 reset_mask = cayman_gpu_check_soft_reset(rdev); 1978 1979 if (reset_mask) 1980 evergreen_gpu_pci_config_reset(rdev); 1981 1982 r600_set_bios_scratch_engine_hung(rdev, false); 1983 1984 return 0; 1985 } 1986 1987 /** 1988 * cayman_gfx_is_lockup - Check if the GFX engine is locked up 1989 * 1990 * @rdev: radeon_device pointer 1991 * @ring: radeon_ring structure holding ring information 1992 * 1993 * Check if the GFX engine is locked up. 1994 * Returns true if the engine appears to be locked up, false if not. 1995 */ 1996 bool cayman_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) 1997 { 1998 u32 reset_mask = cayman_gpu_check_soft_reset(rdev); 1999 2000 if (!(reset_mask & (RADEON_RESET_GFX | 2001 RADEON_RESET_COMPUTE | 2002 RADEON_RESET_CP))) { 2003 radeon_ring_lockup_update(rdev, ring); 2004 return false; 2005 } 2006 return radeon_ring_test_lockup(rdev, ring); 2007 } 2008 2009 static void cayman_uvd_init(struct radeon_device *rdev) 2010 { 2011 int r; 2012 2013 if (!rdev->has_uvd) 2014 return; 2015 2016 r = radeon_uvd_init(rdev); 2017 if (r) { 2018 dev_err(rdev->dev, "failed UVD (%d) init.\n", r); 2019 /* 2020 * At this point rdev->uvd.vcpu_bo is NULL which trickles down 2021 * to early fails uvd_v2_2_resume() and thus nothing happens 2022 * there. So it is pointless to try to go through that code 2023 * hence why we disable uvd here. 2024 */ 2025 rdev->has_uvd = false; 2026 return; 2027 } 2028 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL; 2029 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX], 4096); 2030 } 2031 2032 static void cayman_uvd_start(struct radeon_device *rdev) 2033 { 2034 int r; 2035 2036 if (!rdev->has_uvd) 2037 return; 2038 2039 r = uvd_v2_2_resume(rdev); 2040 if (r) { 2041 dev_err(rdev->dev, "failed UVD resume (%d).\n", r); 2042 goto error; 2043 } 2044 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_UVD_INDEX); 2045 if (r) { 2046 dev_err(rdev->dev, "failed initializing UVD fences (%d).\n", r); 2047 goto error; 2048 } 2049 return; 2050 2051 error: 2052 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0; 2053 } 2054 2055 static void cayman_uvd_resume(struct radeon_device *rdev) 2056 { 2057 struct radeon_ring *ring; 2058 int r; 2059 2060 if (!rdev->has_uvd || !rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size) 2061 return; 2062 2063 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; 2064 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, PACKET0(UVD_NO_OP, 0)); 2065 if (r) { 2066 dev_err(rdev->dev, "failed initializing UVD ring (%d).\n", r); 2067 return; 2068 } 2069 r = uvd_v1_0_init(rdev); 2070 if (r) { 2071 dev_err(rdev->dev, "failed initializing UVD (%d).\n", r); 2072 return; 2073 } 2074 } 2075 2076 static void cayman_vce_init(struct radeon_device *rdev) 2077 { 2078 int r; 2079 2080 /* Only set for CHIP_ARUBA */ 2081 if (!rdev->has_vce) 2082 return; 2083 2084 r = radeon_vce_init(rdev); 2085 if (r) { 2086 dev_err(rdev->dev, "failed VCE (%d) init.\n", r); 2087 /* 2088 * At this point rdev->vce.vcpu_bo is NULL which trickles down 2089 * to early fails cayman_vce_start() and thus nothing happens 2090 * there. So it is pointless to try to go through that code 2091 * hence why we disable vce here. 2092 */ 2093 rdev->has_vce = false; 2094 return; 2095 } 2096 rdev->ring[TN_RING_TYPE_VCE1_INDEX].ring_obj = NULL; 2097 r600_ring_init(rdev, &rdev->ring[TN_RING_TYPE_VCE1_INDEX], 4096); 2098 rdev->ring[TN_RING_TYPE_VCE2_INDEX].ring_obj = NULL; 2099 r600_ring_init(rdev, &rdev->ring[TN_RING_TYPE_VCE2_INDEX], 4096); 2100 } 2101 2102 static void cayman_vce_start(struct radeon_device *rdev) 2103 { 2104 int r; 2105 2106 if (!rdev->has_vce) 2107 return; 2108 2109 r = radeon_vce_resume(rdev); 2110 if (r) { 2111 dev_err(rdev->dev, "failed VCE resume (%d).\n", r); 2112 goto error; 2113 } 2114 r = vce_v1_0_resume(rdev); 2115 if (r) { 2116 dev_err(rdev->dev, "failed VCE resume (%d).\n", r); 2117 goto error; 2118 } 2119 r = radeon_fence_driver_start_ring(rdev, TN_RING_TYPE_VCE1_INDEX); 2120 if (r) { 2121 dev_err(rdev->dev, "failed initializing VCE1 fences (%d).\n", r); 2122 goto error; 2123 } 2124 r = radeon_fence_driver_start_ring(rdev, TN_RING_TYPE_VCE2_INDEX); 2125 if (r) { 2126 dev_err(rdev->dev, "failed initializing VCE2 fences (%d).\n", r); 2127 goto error; 2128 } 2129 return; 2130 2131 error: 2132 rdev->ring[TN_RING_TYPE_VCE1_INDEX].ring_size = 0; 2133 rdev->ring[TN_RING_TYPE_VCE2_INDEX].ring_size = 0; 2134 } 2135 2136 static void cayman_vce_resume(struct radeon_device *rdev) 2137 { 2138 struct radeon_ring *ring; 2139 int r; 2140 2141 if (!rdev->has_vce || !rdev->ring[TN_RING_TYPE_VCE1_INDEX].ring_size) 2142 return; 2143 2144 ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX]; 2145 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, 0x0); 2146 if (r) { 2147 dev_err(rdev->dev, "failed initializing VCE1 ring (%d).\n", r); 2148 return; 2149 } 2150 ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX]; 2151 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, 0x0); 2152 if (r) { 2153 dev_err(rdev->dev, "failed initializing VCE1 ring (%d).\n", r); 2154 return; 2155 } 2156 r = vce_v1_0_init(rdev); 2157 if (r) { 2158 dev_err(rdev->dev, "failed initializing VCE (%d).\n", r); 2159 return; 2160 } 2161 } 2162 2163 static int cayman_startup(struct radeon_device *rdev) 2164 { 2165 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2166 int r; 2167 2168 /* enable pcie gen2 link */ 2169 evergreen_pcie_gen2_enable(rdev); 2170 /* enable aspm */ 2171 evergreen_program_aspm(rdev); 2172 2173 /* scratch needs to be initialized before MC */ 2174 r = r600_vram_scratch_init(rdev); 2175 if (r) 2176 return r; 2177 2178 evergreen_mc_program(rdev); 2179 2180 if (!(rdev->flags & RADEON_IS_IGP) && !rdev->pm.dpm_enabled) { 2181 r = ni_mc_load_microcode(rdev); 2182 if (r) { 2183 DRM_ERROR("Failed to load MC firmware!\n"); 2184 return r; 2185 } 2186 } 2187 2188 r = cayman_pcie_gart_enable(rdev); 2189 if (r) 2190 return r; 2191 cayman_gpu_init(rdev); 2192 2193 /* allocate rlc buffers */ 2194 if (rdev->flags & RADEON_IS_IGP) { 2195 rdev->rlc.reg_list = tn_rlc_save_restore_register_list; 2196 rdev->rlc.reg_list_size = 2197 (u32)ARRAY_SIZE(tn_rlc_save_restore_register_list); 2198 rdev->rlc.cs_data = cayman_cs_data; 2199 r = sumo_rlc_init(rdev); 2200 if (r) { 2201 DRM_ERROR("Failed to init rlc BOs!\n"); 2202 return r; 2203 } 2204 } 2205 2206 /* allocate wb buffer */ 2207 r = radeon_wb_init(rdev); 2208 if (r) 2209 return r; 2210 2211 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 2212 if (r) { 2213 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 2214 return r; 2215 } 2216 2217 cayman_uvd_start(rdev); 2218 cayman_vce_start(rdev); 2219 2220 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP1_INDEX); 2221 if (r) { 2222 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 2223 return r; 2224 } 2225 2226 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP2_INDEX); 2227 if (r) { 2228 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 2229 return r; 2230 } 2231 2232 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX); 2233 if (r) { 2234 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r); 2235 return r; 2236 } 2237 2238 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_DMA1_INDEX); 2239 if (r) { 2240 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r); 2241 return r; 2242 } 2243 2244 /* Enable IRQ */ 2245 if (!rdev->irq.installed) { 2246 r = radeon_irq_kms_init(rdev); 2247 if (r) 2248 return r; 2249 } 2250 2251 r = r600_irq_init(rdev); 2252 if (r) { 2253 DRM_ERROR("radeon: IH init failed (%d).\n", r); 2254 radeon_irq_kms_fini(rdev); 2255 return r; 2256 } 2257 evergreen_irq_set(rdev); 2258 2259 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, 2260 RADEON_CP_PACKET2); 2261 if (r) 2262 return r; 2263 2264 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; 2265 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET, 2266 DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0)); 2267 if (r) 2268 return r; 2269 2270 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]; 2271 r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET, 2272 DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0)); 2273 if (r) 2274 return r; 2275 2276 r = cayman_cp_load_microcode(rdev); 2277 if (r) 2278 return r; 2279 r = cayman_cp_resume(rdev); 2280 if (r) 2281 return r; 2282 2283 r = cayman_dma_resume(rdev); 2284 if (r) 2285 return r; 2286 2287 cayman_uvd_resume(rdev); 2288 cayman_vce_resume(rdev); 2289 2290 r = radeon_ib_pool_init(rdev); 2291 if (r) { 2292 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 2293 return r; 2294 } 2295 2296 r = radeon_vm_manager_init(rdev); 2297 if (r) { 2298 dev_err(rdev->dev, "vm manager initialization failed (%d).\n", r); 2299 return r; 2300 } 2301 2302 r = radeon_audio_init(rdev); 2303 if (r) 2304 return r; 2305 2306 return 0; 2307 } 2308 2309 int cayman_resume(struct radeon_device *rdev) 2310 { 2311 int r; 2312 2313 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw, 2314 * posting will perform necessary task to bring back GPU into good 2315 * shape. 2316 */ 2317 /* post card */ 2318 atom_asic_init(rdev->mode_info.atom_context); 2319 2320 /* init golden registers */ 2321 ni_init_golden_registers(rdev); 2322 2323 if (rdev->pm.pm_method == PM_METHOD_DPM) 2324 radeon_pm_resume(rdev); 2325 2326 rdev->accel_working = true; 2327 r = cayman_startup(rdev); 2328 if (r) { 2329 DRM_ERROR("cayman startup failed on resume\n"); 2330 rdev->accel_working = false; 2331 return r; 2332 } 2333 return r; 2334 } 2335 2336 int cayman_suspend(struct radeon_device *rdev) 2337 { 2338 radeon_pm_suspend(rdev); 2339 radeon_audio_fini(rdev); 2340 radeon_vm_manager_fini(rdev); 2341 cayman_cp_enable(rdev, false); 2342 cayman_dma_stop(rdev); 2343 if (rdev->has_uvd) { 2344 uvd_v1_0_fini(rdev); 2345 radeon_uvd_suspend(rdev); 2346 } 2347 evergreen_irq_suspend(rdev); 2348 radeon_wb_disable(rdev); 2349 cayman_pcie_gart_disable(rdev); 2350 return 0; 2351 } 2352 2353 /* Plan is to move initialization in that function and use 2354 * helper function so that radeon_device_init pretty much 2355 * do nothing more than calling asic specific function. This 2356 * should also allow to remove a bunch of callback function 2357 * like vram_info. 2358 */ 2359 int cayman_init(struct radeon_device *rdev) 2360 { 2361 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2362 int r; 2363 2364 /* Read BIOS */ 2365 if (!radeon_get_bios(rdev)) { 2366 if (ASIC_IS_AVIVO(rdev)) 2367 return -EINVAL; 2368 } 2369 /* Must be an ATOMBIOS */ 2370 if (!rdev->is_atom_bios) { 2371 dev_err(rdev->dev, "Expecting atombios for cayman GPU\n"); 2372 return -EINVAL; 2373 } 2374 r = radeon_atombios_init(rdev); 2375 if (r) 2376 return r; 2377 2378 /* Post card if necessary */ 2379 if (!radeon_card_posted(rdev)) { 2380 if (!rdev->bios) { 2381 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); 2382 return -EINVAL; 2383 } 2384 DRM_INFO("GPU not posted. posting now...\n"); 2385 atom_asic_init(rdev->mode_info.atom_context); 2386 } 2387 /* init golden registers */ 2388 ni_init_golden_registers(rdev); 2389 /* Initialize scratch registers */ 2390 r600_scratch_init(rdev); 2391 /* Initialize surface registers */ 2392 radeon_surface_init(rdev); 2393 /* Initialize clocks */ 2394 radeon_get_clock_info(rdev->ddev); 2395 /* Fence driver */ 2396 r = radeon_fence_driver_init(rdev); 2397 if (r) 2398 return r; 2399 /* initialize memory controller */ 2400 r = evergreen_mc_init(rdev); 2401 if (r) 2402 return r; 2403 /* Memory manager */ 2404 r = radeon_bo_init(rdev); 2405 if (r) 2406 return r; 2407 2408 if (rdev->flags & RADEON_IS_IGP) { 2409 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { 2410 r = ni_init_microcode(rdev); 2411 if (r) { 2412 DRM_ERROR("Failed to load firmware!\n"); 2413 return r; 2414 } 2415 } 2416 } else { 2417 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) { 2418 r = ni_init_microcode(rdev); 2419 if (r) { 2420 DRM_ERROR("Failed to load firmware!\n"); 2421 return r; 2422 } 2423 } 2424 } 2425 2426 /* Initialize power management */ 2427 radeon_pm_init(rdev); 2428 2429 ring->ring_obj = NULL; 2430 r600_ring_init(rdev, ring, 1024 * 1024); 2431 2432 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; 2433 ring->ring_obj = NULL; 2434 r600_ring_init(rdev, ring, 64 * 1024); 2435 2436 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]; 2437 ring->ring_obj = NULL; 2438 r600_ring_init(rdev, ring, 64 * 1024); 2439 2440 cayman_uvd_init(rdev); 2441 cayman_vce_init(rdev); 2442 2443 rdev->ih.ring_obj = NULL; 2444 r600_ih_ring_init(rdev, 64 * 1024); 2445 2446 r = r600_pcie_gart_init(rdev); 2447 if (r) 2448 return r; 2449 2450 rdev->accel_working = true; 2451 r = cayman_startup(rdev); 2452 if (r) { 2453 dev_err(rdev->dev, "disabling GPU acceleration\n"); 2454 cayman_cp_fini(rdev); 2455 cayman_dma_fini(rdev); 2456 r600_irq_fini(rdev); 2457 if (rdev->flags & RADEON_IS_IGP) 2458 sumo_rlc_fini(rdev); 2459 radeon_wb_fini(rdev); 2460 radeon_ib_pool_fini(rdev); 2461 radeon_vm_manager_fini(rdev); 2462 radeon_irq_kms_fini(rdev); 2463 cayman_pcie_gart_fini(rdev); 2464 rdev->accel_working = false; 2465 } 2466 2467 /* Don't start up if the MC ucode is missing. 2468 * The default clocks and voltages before the MC ucode 2469 * is loaded are not suffient for advanced operations. 2470 * 2471 * We can skip this check for TN, because there is no MC 2472 * ucode. 2473 */ 2474 if (!rdev->mc_fw && !(rdev->flags & RADEON_IS_IGP)) { 2475 DRM_ERROR("radeon: MC ucode required for NI+.\n"); 2476 return -EINVAL; 2477 } 2478 2479 return 0; 2480 } 2481 2482 void cayman_fini(struct radeon_device *rdev) 2483 { 2484 radeon_pm_fini(rdev); 2485 cayman_cp_fini(rdev); 2486 cayman_dma_fini(rdev); 2487 r600_irq_fini(rdev); 2488 if (rdev->flags & RADEON_IS_IGP) 2489 sumo_rlc_fini(rdev); 2490 radeon_wb_fini(rdev); 2491 radeon_vm_manager_fini(rdev); 2492 radeon_ib_pool_fini(rdev); 2493 radeon_irq_kms_fini(rdev); 2494 uvd_v1_0_fini(rdev); 2495 radeon_uvd_fini(rdev); 2496 if (rdev->has_vce) 2497 radeon_vce_fini(rdev); 2498 cayman_pcie_gart_fini(rdev); 2499 r600_vram_scratch_fini(rdev); 2500 radeon_gem_fini(rdev); 2501 radeon_fence_driver_fini(rdev); 2502 radeon_bo_fini(rdev); 2503 radeon_atombios_fini(rdev); 2504 kfree(rdev->bios); 2505 rdev->bios = NULL; 2506 } 2507 2508 /* 2509 * vm 2510 */ 2511 int cayman_vm_init(struct radeon_device *rdev) 2512 { 2513 /* number of VMs */ 2514 rdev->vm_manager.nvm = 8; 2515 /* base offset of vram pages */ 2516 if (rdev->flags & RADEON_IS_IGP) { 2517 u64 tmp = RREG32(FUS_MC_VM_FB_OFFSET); 2518 tmp <<= 22; 2519 rdev->vm_manager.vram_base_offset = tmp; 2520 } else 2521 rdev->vm_manager.vram_base_offset = 0; 2522 return 0; 2523 } 2524 2525 void cayman_vm_fini(struct radeon_device *rdev) 2526 { 2527 } 2528 2529 /** 2530 * cayman_vm_decode_fault - print human readable fault info 2531 * 2532 * @rdev: radeon_device pointer 2533 * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value 2534 * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value 2535 * 2536 * Print human readable fault information (cayman/TN). 2537 */ 2538 void cayman_vm_decode_fault(struct radeon_device *rdev, 2539 u32 status, u32 addr) 2540 { 2541 u32 mc_id = (status & MEMORY_CLIENT_ID_MASK) >> MEMORY_CLIENT_ID_SHIFT; 2542 u32 vmid = (status & FAULT_VMID_MASK) >> FAULT_VMID_SHIFT; 2543 u32 protections = (status & PROTECTIONS_MASK) >> PROTECTIONS_SHIFT; 2544 char *block; 2545 2546 switch (mc_id) { 2547 case 32: 2548 case 16: 2549 case 96: 2550 case 80: 2551 case 160: 2552 case 144: 2553 case 224: 2554 case 208: 2555 block = "CB"; 2556 break; 2557 case 33: 2558 case 17: 2559 case 97: 2560 case 81: 2561 case 161: 2562 case 145: 2563 case 225: 2564 case 209: 2565 block = "CB_FMASK"; 2566 break; 2567 case 34: 2568 case 18: 2569 case 98: 2570 case 82: 2571 case 162: 2572 case 146: 2573 case 226: 2574 case 210: 2575 block = "CB_CMASK"; 2576 break; 2577 case 35: 2578 case 19: 2579 case 99: 2580 case 83: 2581 case 163: 2582 case 147: 2583 case 227: 2584 case 211: 2585 block = "CB_IMMED"; 2586 break; 2587 case 36: 2588 case 20: 2589 case 100: 2590 case 84: 2591 case 164: 2592 case 148: 2593 case 228: 2594 case 212: 2595 block = "DB"; 2596 break; 2597 case 37: 2598 case 21: 2599 case 101: 2600 case 85: 2601 case 165: 2602 case 149: 2603 case 229: 2604 case 213: 2605 block = "DB_HTILE"; 2606 break; 2607 case 38: 2608 case 22: 2609 case 102: 2610 case 86: 2611 case 166: 2612 case 150: 2613 case 230: 2614 case 214: 2615 block = "SX"; 2616 break; 2617 case 39: 2618 case 23: 2619 case 103: 2620 case 87: 2621 case 167: 2622 case 151: 2623 case 231: 2624 case 215: 2625 block = "DB_STEN"; 2626 break; 2627 case 40: 2628 case 24: 2629 case 104: 2630 case 88: 2631 case 232: 2632 case 216: 2633 case 168: 2634 case 152: 2635 block = "TC_TFETCH"; 2636 break; 2637 case 41: 2638 case 25: 2639 case 105: 2640 case 89: 2641 case 233: 2642 case 217: 2643 case 169: 2644 case 153: 2645 block = "TC_VFETCH"; 2646 break; 2647 case 42: 2648 case 26: 2649 case 106: 2650 case 90: 2651 case 234: 2652 case 218: 2653 case 170: 2654 case 154: 2655 block = "VC"; 2656 break; 2657 case 112: 2658 block = "CP"; 2659 break; 2660 case 113: 2661 case 114: 2662 block = "SH"; 2663 break; 2664 case 115: 2665 block = "VGT"; 2666 break; 2667 case 178: 2668 block = "IH"; 2669 break; 2670 case 51: 2671 block = "RLC"; 2672 break; 2673 case 55: 2674 block = "DMA"; 2675 break; 2676 case 56: 2677 block = "HDP"; 2678 break; 2679 default: 2680 block = "unknown"; 2681 break; 2682 } 2683 2684 printk("VM fault (0x%02x, vmid %d) at page %u, %s from %s (%d)\n", 2685 protections, vmid, addr, 2686 (status & MEMORY_CLIENT_RW_MASK) ? "write" : "read", 2687 block, mc_id); 2688 } 2689 2690 /** 2691 * cayman_vm_flush - vm flush using the CP 2692 * 2693 * @rdev: radeon_device pointer 2694 * 2695 * Update the page table base and flush the VM TLB 2696 * using the CP (cayman-si). 2697 */ 2698 void cayman_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring, 2699 unsigned vm_id, uint64_t pd_addr) 2700 { 2701 radeon_ring_write(ring, PACKET0(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm_id << 2), 0)); 2702 radeon_ring_write(ring, pd_addr >> 12); 2703 2704 /* flush hdp cache */ 2705 radeon_ring_write(ring, PACKET0(HDP_MEM_COHERENCY_FLUSH_CNTL, 0)); 2706 radeon_ring_write(ring, 0x1); 2707 2708 /* bits 0-7 are the VM contexts0-7 */ 2709 radeon_ring_write(ring, PACKET0(VM_INVALIDATE_REQUEST, 0)); 2710 radeon_ring_write(ring, 1 << vm_id); 2711 2712 /* wait for the invalidate to complete */ 2713 radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 2714 radeon_ring_write(ring, (WAIT_REG_MEM_FUNCTION(0) | /* always */ 2715 WAIT_REG_MEM_ENGINE(0))); /* me */ 2716 radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2); 2717 radeon_ring_write(ring, 0); 2718 radeon_ring_write(ring, 0); /* ref */ 2719 radeon_ring_write(ring, 0); /* mask */ 2720 radeon_ring_write(ring, 0x20); /* poll interval */ 2721 2722 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 2723 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 2724 radeon_ring_write(ring, 0x0); 2725 } 2726 2727 int tn_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk) 2728 { 2729 struct atom_clock_dividers dividers; 2730 int r, i; 2731 2732 r = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 2733 ecclk, false, ÷rs); 2734 if (r) 2735 return r; 2736 2737 for (i = 0; i < 100; i++) { 2738 if (RREG32(CG_ECLK_STATUS) & ECLK_STATUS) 2739 break; 2740 mdelay(10); 2741 } 2742 if (i == 100) 2743 return -ETIMEDOUT; 2744 2745 WREG32_P(CG_ECLK_CNTL, dividers.post_div, ~(ECLK_DIR_CNTL_EN|ECLK_DIVIDER_MASK)); 2746 2747 for (i = 0; i < 100; i++) { 2748 if (RREG32(CG_ECLK_STATUS) & ECLK_STATUS) 2749 break; 2750 mdelay(10); 2751 } 2752 if (i == 100) 2753 return -ETIMEDOUT; 2754 2755 return 0; 2756 } 2757
Indexes created Wed Oct 22 13:09:56 GMT 2025