radeon_ni.c revision 1.1.6.2
1 /* $NetBSD: radeon_ni.c,v 1.1.6.2 2019/06/10 22:08:26 christos Exp $ */ 2 3 /* 4 * Copyright 2010 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Alex Deucher 25 */ 26 #include <sys/cdefs.h> 27 __KERNEL_RCSID(0, "$NetBSD: radeon_ni.c,v 1.1.6.2 2019/06/10 22:08:26 christos Exp $"); 28 29 #include <linux/firmware.h> 30 #include <linux/slab.h> 31 #include <linux/module.h> 32 #include <drm/drmP.h> 33 #include "radeon.h" 34 #include "radeon_asic.h" 35 #include "radeon_audio.h" 36 #include <drm/radeon_drm.h> 37 #include "nid.h" 38 #include "atom.h" 39 #include "ni_reg.h" 40 #include "cayman_blit_shaders.h" 41 #include "radeon_ucode.h" 42 #include "clearstate_cayman.h" 43 44 /* 45 * Indirect registers accessor 46 */ 47 u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg) 48 { 49 unsigned long flags; 50 u32 r; 51 52 spin_lock_irqsave(&rdev->smc_idx_lock, flags); 53 WREG32(TN_SMC_IND_INDEX_0, (reg)); 54 r = RREG32(TN_SMC_IND_DATA_0); 55 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags); 56 return r; 57 } 58 59 void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v) 60 { 61 unsigned long flags; 62 63 spin_lock_irqsave(&rdev->smc_idx_lock, flags); 64 WREG32(TN_SMC_IND_INDEX_0, (reg)); 65 WREG32(TN_SMC_IND_DATA_0, (v)); 66 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags); 67 } 68 69 static const u32 tn_rlc_save_restore_register_list[] = 70 { 71 0x98fc, 72 0x98f0, 73 0x9834, 74 0x9838, 75 0x9870, 76 0x9874, 77 0x8a14, 78 0x8b24, 79 0x8bcc, 80 0x8b10, 81 0x8c30, 82 0x8d00, 83 0x8d04, 84 0x8c00, 85 0x8c04, 86 0x8c10, 87 0x8c14, 88 0x8d8c, 89 0x8cf0, 90 0x8e38, 91 0x9508, 92 0x9688, 93 0x9608, 94 0x960c, 95 0x9610, 96 0x9614, 97 0x88c4, 98 0x8978, 99 0x88d4, 100 0x900c, 101 0x9100, 102 0x913c, 103 0x90e8, 104 0x9354, 105 0xa008, 106 0x98f8, 107 0x9148, 108 0x914c, 109 0x3f94, 110 0x98f4, 111 0x9b7c, 112 0x3f8c, 113 0x8950, 114 0x8954, 115 0x8a18, 116 0x8b28, 117 0x9144, 118 0x3f90, 119 0x915c, 120 0x9160, 121 0x9178, 122 0x917c, 123 0x9180, 124 0x918c, 125 0x9190, 126 0x9194, 127 0x9198, 128 0x919c, 129 0x91a8, 130 0x91ac, 131 0x91b0, 132 0x91b4, 133 0x91b8, 134 0x91c4, 135 0x91c8, 136 0x91cc, 137 0x91d0, 138 0x91d4, 139 0x91e0, 140 0x91e4, 141 0x91ec, 142 0x91f0, 143 0x91f4, 144 0x9200, 145 0x9204, 146 0x929c, 147 0x8030, 148 0x9150, 149 0x9a60, 150 0x920c, 151 0x9210, 152 0x9228, 153 0x922c, 154 0x9244, 155 0x9248, 156 0x91e8, 157 0x9294, 158 0x9208, 159 0x9224, 160 0x9240, 161 0x9220, 162 0x923c, 163 0x9258, 164 0x9744, 165 0xa200, 166 0xa204, 167 0xa208, 168 0xa20c, 169 0x8d58, 170 0x9030, 171 0x9034, 172 0x9038, 173 0x903c, 174 0x9040, 175 0x9654, 176 0x897c, 177 0xa210, 178 0xa214, 179 0x9868, 180 0xa02c, 181 0x9664, 182 0x9698, 183 0x949c, 184 0x8e10, 185 0x8e18, 186 0x8c50, 187 0x8c58, 188 0x8c60, 189 0x8c68, 190 0x89b4, 191 0x9830, 192 0x802c, 193 }; 194 195 extern bool evergreen_is_display_hung(struct radeon_device *rdev); 196 extern void evergreen_print_gpu_status_regs(struct radeon_device *rdev); 197 extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save); 198 extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save); 199 extern int evergreen_mc_wait_for_idle(struct radeon_device *rdev); 200 extern void evergreen_mc_program(struct radeon_device *rdev); 201 extern void evergreen_irq_suspend(struct radeon_device *rdev); 202 extern int evergreen_mc_init(struct radeon_device *rdev); 203 extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev); 204 extern void evergreen_pcie_gen2_enable(struct radeon_device *rdev); 205 extern void evergreen_program_aspm(struct radeon_device *rdev); 206 extern void sumo_rlc_fini(struct radeon_device *rdev); 207 extern int sumo_rlc_init(struct radeon_device *rdev); 208 extern void evergreen_gpu_pci_config_reset(struct radeon_device *rdev); 209 210 /* Firmware Names */ 211 MODULE_FIRMWARE("radeon/BARTS_pfp.bin"); 212 MODULE_FIRMWARE("radeon/BARTS_me.bin"); 213 MODULE_FIRMWARE("radeon/BARTS_mc.bin"); 214 MODULE_FIRMWARE("radeon/BARTS_smc.bin"); 215 MODULE_FIRMWARE("radeon/BTC_rlc.bin"); 216 MODULE_FIRMWARE("radeon/TURKS_pfp.bin"); 217 MODULE_FIRMWARE("radeon/TURKS_me.bin"); 218 MODULE_FIRMWARE("radeon/TURKS_mc.bin"); 219 MODULE_FIRMWARE("radeon/TURKS_smc.bin"); 220 MODULE_FIRMWARE("radeon/CAICOS_pfp.bin"); 221 MODULE_FIRMWARE("radeon/CAICOS_me.bin"); 222 MODULE_FIRMWARE("radeon/CAICOS_mc.bin"); 223 MODULE_FIRMWARE("radeon/CAICOS_smc.bin"); 224 MODULE_FIRMWARE("radeon/CAYMAN_pfp.bin"); 225 MODULE_FIRMWARE("radeon/CAYMAN_me.bin"); 226 MODULE_FIRMWARE("radeon/CAYMAN_mc.bin"); 227 MODULE_FIRMWARE("radeon/CAYMAN_rlc.bin"); 228 MODULE_FIRMWARE("radeon/CAYMAN_smc.bin"); 229 MODULE_FIRMWARE("radeon/ARUBA_pfp.bin"); 230 MODULE_FIRMWARE("radeon/ARUBA_me.bin"); 231 MODULE_FIRMWARE("radeon/ARUBA_rlc.bin"); 232 233 234 static const u32 cayman_golden_registers2[] = 235 { 236 0x3e5c, 0xffffffff, 0x00000000, 237 0x3e48, 0xffffffff, 0x00000000, 238 0x3e4c, 0xffffffff, 0x00000000, 239 0x3e64, 0xffffffff, 0x00000000, 240 0x3e50, 0xffffffff, 0x00000000, 241 0x3e60, 0xffffffff, 0x00000000 242 }; 243 244 static const u32 cayman_golden_registers[] = 245 { 246 0x5eb4, 0xffffffff, 0x00000002, 247 0x5e78, 0x8f311ff1, 0x001000f0, 248 0x3f90, 0xffff0000, 0xff000000, 249 0x9148, 0xffff0000, 0xff000000, 250 0x3f94, 0xffff0000, 0xff000000, 251 0x914c, 0xffff0000, 0xff000000, 252 0xc78, 0x00000080, 0x00000080, 253 0xbd4, 0x70073777, 0x00011003, 254 0xd02c, 0xbfffff1f, 0x08421000, 255 0xd0b8, 0x73773777, 0x02011003, 256 0x5bc0, 0x00200000, 0x50100000, 257 0x98f8, 0x33773777, 0x02011003, 258 0x98fc, 0xffffffff, 0x76541032, 259 0x7030, 0x31000311, 0x00000011, 260 0x2f48, 0x33773777, 0x42010001, 261 0x6b28, 0x00000010, 0x00000012, 262 0x7728, 0x00000010, 0x00000012, 263 0x10328, 0x00000010, 0x00000012, 264 0x10f28, 0x00000010, 0x00000012, 265 0x11b28, 0x00000010, 0x00000012, 266 0x12728, 0x00000010, 0x00000012, 267 0x240c, 0x000007ff, 0x00000000, 268 0x8a14, 0xf000001f, 0x00000007, 269 0x8b24, 0x3fff3fff, 0x00ff0fff, 270 0x8b10, 0x0000ff0f, 0x00000000, 271 0x28a4c, 0x07ffffff, 0x06000000, 272 0x10c, 0x00000001, 0x00010003, 273 0xa02c, 0xffffffff, 0x0000009b, 274 0x913c, 0x0000010f, 0x01000100, 275 0x8c04, 0xf8ff00ff, 0x40600060, 276 0x28350, 0x00000f01, 0x00000000, 277 0x9508, 0x3700001f, 0x00000002, 278 0x960c, 0xffffffff, 0x54763210, 279 0x88c4, 0x001f3ae3, 0x00000082, 280 0x88d0, 0xffffffff, 0x0f40df40, 281 0x88d4, 0x0000001f, 0x00000010, 282 0x8974, 0xffffffff, 0x00000000 283 }; 284 285 static const u32 dvst_golden_registers2[] = 286 { 287 0x8f8, 0xffffffff, 0, 288 0x8fc, 0x00380000, 0, 289 0x8f8, 0xffffffff, 1, 290 0x8fc, 0x0e000000, 0 291 }; 292 293 static const u32 dvst_golden_registers[] = 294 { 295 0x690, 0x3fff3fff, 0x20c00033, 296 0x918c, 0x0fff0fff, 0x00010006, 297 0x91a8, 0x0fff0fff, 0x00010006, 298 0x9150, 0xffffdfff, 0x6e944040, 299 0x917c, 0x0fff0fff, 0x00030002, 300 0x9198, 0x0fff0fff, 0x00030002, 301 0x915c, 0x0fff0fff, 0x00010000, 302 0x3f90, 0xffff0001, 0xff000000, 303 0x9178, 0x0fff0fff, 0x00070000, 304 0x9194, 0x0fff0fff, 0x00070000, 305 0x9148, 0xffff0001, 0xff000000, 306 0x9190, 0x0fff0fff, 0x00090008, 307 0x91ac, 0x0fff0fff, 0x00090008, 308 0x3f94, 0xffff0000, 0xff000000, 309 0x914c, 0xffff0000, 0xff000000, 310 0x929c, 0x00000fff, 0x00000001, 311 0x55e4, 0xff607fff, 0xfc000100, 312 0x8a18, 0xff000fff, 0x00000100, 313 0x8b28, 0xff000fff, 0x00000100, 314 0x9144, 0xfffc0fff, 0x00000100, 315 0x6ed8, 0x00010101, 0x00010000, 316 0x9830, 0xffffffff, 0x00000000, 317 0x9834, 0xf00fffff, 0x00000400, 318 0x9838, 0xfffffffe, 0x00000000, 319 0xd0c0, 0xff000fff, 0x00000100, 320 0xd02c, 0xbfffff1f, 0x08421000, 321 0xd0b8, 0x73773777, 0x12010001, 322 0x5bb0, 0x000000f0, 0x00000070, 323 0x98f8, 0x73773777, 0x12010001, 324 0x98fc, 0xffffffff, 0x00000010, 325 0x9b7c, 0x00ff0000, 0x00fc0000, 326 0x8030, 0x00001f0f, 0x0000100a, 327 0x2f48, 0x73773777, 0x12010001, 328 0x2408, 0x00030000, 0x000c007f, 329 0x8a14, 0xf000003f, 0x00000007, 330 0x8b24, 0x3fff3fff, 0x00ff0fff, 331 0x8b10, 0x0000ff0f, 0x00000000, 332 0x28a4c, 0x07ffffff, 0x06000000, 333 0x4d8, 0x00000fff, 0x00000100, 334 0xa008, 0xffffffff, 0x00010000, 335 0x913c, 0xffff03ff, 0x01000100, 336 0x8c00, 0x000000ff, 0x00000003, 337 0x8c04, 0xf8ff00ff, 0x40600060, 338 0x8cf0, 0x1fff1fff, 0x08e00410, 339 0x28350, 0x00000f01, 0x00000000, 340 0x9508, 0xf700071f, 0x00000002, 341 0x960c, 0xffffffff, 0x54763210, 342 0x20ef8, 0x01ff01ff, 0x00000002, 343 0x20e98, 0xfffffbff, 0x00200000, 344 0x2015c, 0xffffffff, 0x00000f40, 345 0x88c4, 0x001f3ae3, 0x00000082, 346 0x8978, 0x3fffffff, 0x04050140, 347 0x88d4, 0x0000001f, 0x00000010, 348 0x8974, 0xffffffff, 0x00000000 349 }; 350 351 static const u32 scrapper_golden_registers[] = 352 { 353 0x690, 0x3fff3fff, 0x20c00033, 354 0x918c, 0x0fff0fff, 0x00010006, 355 0x918c, 0x0fff0fff, 0x00010006, 356 0x91a8, 0x0fff0fff, 0x00010006, 357 0x91a8, 0x0fff0fff, 0x00010006, 358 0x9150, 0xffffdfff, 0x6e944040, 359 0x9150, 0xffffdfff, 0x6e944040, 360 0x917c, 0x0fff0fff, 0x00030002, 361 0x917c, 0x0fff0fff, 0x00030002, 362 0x9198, 0x0fff0fff, 0x00030002, 363 0x9198, 0x0fff0fff, 0x00030002, 364 0x915c, 0x0fff0fff, 0x00010000, 365 0x915c, 0x0fff0fff, 0x00010000, 366 0x3f90, 0xffff0001, 0xff000000, 367 0x3f90, 0xffff0001, 0xff000000, 368 0x9178, 0x0fff0fff, 0x00070000, 369 0x9178, 0x0fff0fff, 0x00070000, 370 0x9194, 0x0fff0fff, 0x00070000, 371 0x9194, 0x0fff0fff, 0x00070000, 372 0x9148, 0xffff0001, 0xff000000, 373 0x9148, 0xffff0001, 0xff000000, 374 0x9190, 0x0fff0fff, 0x00090008, 375 0x9190, 0x0fff0fff, 0x00090008, 376 0x91ac, 0x0fff0fff, 0x00090008, 377 0x91ac, 0x0fff0fff, 0x00090008, 378 0x3f94, 0xffff0000, 0xff000000, 379 0x3f94, 0xffff0000, 0xff000000, 380 0x914c, 0xffff0000, 0xff000000, 381 0x914c, 0xffff0000, 0xff000000, 382 0x929c, 0x00000fff, 0x00000001, 383 0x929c, 0x00000fff, 0x00000001, 384 0x55e4, 0xff607fff, 0xfc000100, 385 0x8a18, 0xff000fff, 0x00000100, 386 0x8a18, 0xff000fff, 0x00000100, 387 0x8b28, 0xff000fff, 0x00000100, 388 0x8b28, 0xff000fff, 0x00000100, 389 0x9144, 0xfffc0fff, 0x00000100, 390 0x9144, 0xfffc0fff, 0x00000100, 391 0x6ed8, 0x00010101, 0x00010000, 392 0x9830, 0xffffffff, 0x00000000, 393 0x9830, 0xffffffff, 0x00000000, 394 0x9834, 0xf00fffff, 0x00000400, 395 0x9834, 0xf00fffff, 0x00000400, 396 0x9838, 0xfffffffe, 0x00000000, 397 0x9838, 0xfffffffe, 0x00000000, 398 0xd0c0, 0xff000fff, 0x00000100, 399 0xd02c, 0xbfffff1f, 0x08421000, 400 0xd02c, 0xbfffff1f, 0x08421000, 401 0xd0b8, 0x73773777, 0x12010001, 402 0xd0b8, 0x73773777, 0x12010001, 403 0x5bb0, 0x000000f0, 0x00000070, 404 0x98f8, 0x73773777, 0x12010001, 405 0x98f8, 0x73773777, 0x12010001, 406 0x98fc, 0xffffffff, 0x00000010, 407 0x98fc, 0xffffffff, 0x00000010, 408 0x9b7c, 0x00ff0000, 0x00fc0000, 409 0x9b7c, 0x00ff0000, 0x00fc0000, 410 0x8030, 0x00001f0f, 0x0000100a, 411 0x8030, 0x00001f0f, 0x0000100a, 412 0x2f48, 0x73773777, 0x12010001, 413 0x2f48, 0x73773777, 0x12010001, 414 0x2408, 0x00030000, 0x000c007f, 415 0x8a14, 0xf000003f, 0x00000007, 416 0x8a14, 0xf000003f, 0x00000007, 417 0x8b24, 0x3fff3fff, 0x00ff0fff, 418 0x8b24, 0x3fff3fff, 0x00ff0fff, 419 0x8b10, 0x0000ff0f, 0x00000000, 420 0x8b10, 0x0000ff0f, 0x00000000, 421 0x28a4c, 0x07ffffff, 0x06000000, 422 0x28a4c, 0x07ffffff, 0x06000000, 423 0x4d8, 0x00000fff, 0x00000100, 424 0x4d8, 0x00000fff, 0x00000100, 425 0xa008, 0xffffffff, 0x00010000, 426 0xa008, 0xffffffff, 0x00010000, 427 0x913c, 0xffff03ff, 0x01000100, 428 0x913c, 0xffff03ff, 0x01000100, 429 0x90e8, 0x001fffff, 0x010400c0, 430 0x8c00, 0x000000ff, 0x00000003, 431 0x8c00, 0x000000ff, 0x00000003, 432 0x8c04, 0xf8ff00ff, 0x40600060, 433 0x8c04, 0xf8ff00ff, 0x40600060, 434 0x8c30, 0x0000000f, 0x00040005, 435 0x8cf0, 0x1fff1fff, 0x08e00410, 436 0x8cf0, 0x1fff1fff, 0x08e00410, 437 0x900c, 0x00ffffff, 0x0017071f, 438 0x28350, 0x00000f01, 0x00000000, 439 0x28350, 0x00000f01, 0x00000000, 440 0x9508, 0xf700071f, 0x00000002, 441 0x9508, 0xf700071f, 0x00000002, 442 0x9688, 0x00300000, 0x0017000f, 443 0x960c, 0xffffffff, 0x54763210, 444 0x960c, 0xffffffff, 0x54763210, 445 0x20ef8, 0x01ff01ff, 0x00000002, 446 0x20e98, 0xfffffbff, 0x00200000, 447 0x2015c, 0xffffffff, 0x00000f40, 448 0x88c4, 0x001f3ae3, 0x00000082, 449 0x88c4, 0x001f3ae3, 0x00000082, 450 0x8978, 0x3fffffff, 0x04050140, 451 0x8978, 0x3fffffff, 0x04050140, 452 0x88d4, 0x0000001f, 0x00000010, 453 0x88d4, 0x0000001f, 0x00000010, 454 0x8974, 0xffffffff, 0x00000000, 455 0x8974, 0xffffffff, 0x00000000 456 }; 457 458 static void ni_init_golden_registers(struct radeon_device *rdev) 459 { 460 switch (rdev->family) { 461 case CHIP_CAYMAN: 462 radeon_program_register_sequence(rdev, 463 cayman_golden_registers, 464 (const u32)ARRAY_SIZE(cayman_golden_registers)); 465 radeon_program_register_sequence(rdev, 466 cayman_golden_registers2, 467 (const u32)ARRAY_SIZE(cayman_golden_registers2)); 468 break; 469 case CHIP_ARUBA: 470 if ((rdev->pdev->device == 0x9900) || 471 (rdev->pdev->device == 0x9901) || 472 (rdev->pdev->device == 0x9903) || 473 (rdev->pdev->device == 0x9904) || 474 (rdev->pdev->device == 0x9905) || 475 (rdev->pdev->device == 0x9906) || 476 (rdev->pdev->device == 0x9907) || 477 (rdev->pdev->device == 0x9908) || 478 (rdev->pdev->device == 0x9909) || 479 (rdev->pdev->device == 0x990A) || 480 (rdev->pdev->device == 0x990B) || 481 (rdev->pdev->device == 0x990C) || 482 (rdev->pdev->device == 0x990D) || 483 (rdev->pdev->device == 0x990E) || 484 (rdev->pdev->device == 0x990F) || 485 (rdev->pdev->device == 0x9910) || 486 (rdev->pdev->device == 0x9913) || 487 (rdev->pdev->device == 0x9917) || 488 (rdev->pdev->device == 0x9918)) { 489 radeon_program_register_sequence(rdev, 490 dvst_golden_registers, 491 (const u32)ARRAY_SIZE(dvst_golden_registers)); 492 radeon_program_register_sequence(rdev, 493 dvst_golden_registers2, 494 (const u32)ARRAY_SIZE(dvst_golden_registers2)); 495 } else { 496 radeon_program_register_sequence(rdev, 497 scrapper_golden_registers, 498 (const u32)ARRAY_SIZE(scrapper_golden_registers)); 499 radeon_program_register_sequence(rdev, 500 dvst_golden_registers2, 501 (const u32)ARRAY_SIZE(dvst_golden_registers2)); 502 } 503 break; 504 default: 505 break; 506 } 507 } 508 509 #define BTC_IO_MC_REGS_SIZE 29 510 511 static const u32 barts_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = { 512 {0x00000077, 0xff010100}, 513 {0x00000078, 0x00000000}, 514 {0x00000079, 0x00001434}, 515 {0x0000007a, 0xcc08ec08}, 516 {0x0000007b, 0x00040000}, 517 {0x0000007c, 0x000080c0}, 518 {0x0000007d, 0x09000000}, 519 {0x0000007e, 0x00210404}, 520 {0x00000081, 0x08a8e800}, 521 {0x00000082, 0x00030444}, 522 {0x00000083, 0x00000000}, 523 {0x00000085, 0x00000001}, 524 {0x00000086, 0x00000002}, 525 {0x00000087, 0x48490000}, 526 {0x00000088, 0x20244647}, 527 {0x00000089, 0x00000005}, 528 {0x0000008b, 0x66030000}, 529 {0x0000008c, 0x00006603}, 530 {0x0000008d, 0x00000100}, 531 {0x0000008f, 0x00001c0a}, 532 {0x00000090, 0xff000001}, 533 {0x00000094, 0x00101101}, 534 {0x00000095, 0x00000fff}, 535 {0x00000096, 0x00116fff}, 536 {0x00000097, 0x60010000}, 537 {0x00000098, 0x10010000}, 538 {0x00000099, 0x00006000}, 539 {0x0000009a, 0x00001000}, 540 {0x0000009f, 0x00946a00} 541 }; 542 543 static const u32 turks_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = { 544 {0x00000077, 0xff010100}, 545 {0x00000078, 0x00000000}, 546 {0x00000079, 0x00001434}, 547 {0x0000007a, 0xcc08ec08}, 548 {0x0000007b, 0x00040000}, 549 {0x0000007c, 0x000080c0}, 550 {0x0000007d, 0x09000000}, 551 {0x0000007e, 0x00210404}, 552 {0x00000081, 0x08a8e800}, 553 {0x00000082, 0x00030444}, 554 {0x00000083, 0x00000000}, 555 {0x00000085, 0x00000001}, 556 {0x00000086, 0x00000002}, 557 {0x00000087, 0x48490000}, 558 {0x00000088, 0x20244647}, 559 {0x00000089, 0x00000005}, 560 {0x0000008b, 0x66030000}, 561 {0x0000008c, 0x00006603}, 562 {0x0000008d, 0x00000100}, 563 {0x0000008f, 0x00001c0a}, 564 {0x00000090, 0xff000001}, 565 {0x00000094, 0x00101101}, 566 {0x00000095, 0x00000fff}, 567 {0x00000096, 0x00116fff}, 568 {0x00000097, 0x60010000}, 569 {0x00000098, 0x10010000}, 570 {0x00000099, 0x00006000}, 571 {0x0000009a, 0x00001000}, 572 {0x0000009f, 0x00936a00} 573 }; 574 575 static const u32 caicos_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = { 576 {0x00000077, 0xff010100}, 577 {0x00000078, 0x00000000}, 578 {0x00000079, 0x00001434}, 579 {0x0000007a, 0xcc08ec08}, 580 {0x0000007b, 0x00040000}, 581 {0x0000007c, 0x000080c0}, 582 {0x0000007d, 0x09000000}, 583 {0x0000007e, 0x00210404}, 584 {0x00000081, 0x08a8e800}, 585 {0x00000082, 0x00030444}, 586 {0x00000083, 0x00000000}, 587 {0x00000085, 0x00000001}, 588 {0x00000086, 0x00000002}, 589 {0x00000087, 0x48490000}, 590 {0x00000088, 0x20244647}, 591 {0x00000089, 0x00000005}, 592 {0x0000008b, 0x66030000}, 593 {0x0000008c, 0x00006603}, 594 {0x0000008d, 0x00000100}, 595 {0x0000008f, 0x00001c0a}, 596 {0x00000090, 0xff000001}, 597 {0x00000094, 0x00101101}, 598 {0x00000095, 0x00000fff}, 599 {0x00000096, 0x00116fff}, 600 {0x00000097, 0x60010000}, 601 {0x00000098, 0x10010000}, 602 {0x00000099, 0x00006000}, 603 {0x0000009a, 0x00001000}, 604 {0x0000009f, 0x00916a00} 605 }; 606 607 static const u32 cayman_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = { 608 {0x00000077, 0xff010100}, 609 {0x00000078, 0x00000000}, 610 {0x00000079, 0x00001434}, 611 {0x0000007a, 0xcc08ec08}, 612 {0x0000007b, 0x00040000}, 613 {0x0000007c, 0x000080c0}, 614 {0x0000007d, 0x09000000}, 615 {0x0000007e, 0x00210404}, 616 {0x00000081, 0x08a8e800}, 617 {0x00000082, 0x00030444}, 618 {0x00000083, 0x00000000}, 619 {0x00000085, 0x00000001}, 620 {0x00000086, 0x00000002}, 621 {0x00000087, 0x48490000}, 622 {0x00000088, 0x20244647}, 623 {0x00000089, 0x00000005}, 624 {0x0000008b, 0x66030000}, 625 {0x0000008c, 0x00006603}, 626 {0x0000008d, 0x00000100}, 627 {0x0000008f, 0x00001c0a}, 628 {0x00000090, 0xff000001}, 629 {0x00000094, 0x00101101}, 630 {0x00000095, 0x00000fff}, 631 {0x00000096, 0x00116fff}, 632 {0x00000097, 0x60010000}, 633 {0x00000098, 0x10010000}, 634 {0x00000099, 0x00006000}, 635 {0x0000009a, 0x00001000}, 636 {0x0000009f, 0x00976b00} 637 }; 638 639 int ni_mc_load_microcode(struct radeon_device *rdev) 640 { 641 const __be32 *fw_data; 642 u32 mem_type, running, blackout = 0; 643 const u32 *io_mc_regs; 644 int i, ucode_size, regs_size; 645 646 if (!rdev->mc_fw) 647 return -EINVAL; 648 649 switch (rdev->family) { 650 case CHIP_BARTS: 651 io_mc_regs = &barts_io_mc_regs[0][0]; 652 ucode_size = BTC_MC_UCODE_SIZE; 653 regs_size = BTC_IO_MC_REGS_SIZE; 654 break; 655 case CHIP_TURKS: 656 io_mc_regs = &turks_io_mc_regs[0][0]; 657 ucode_size = BTC_MC_UCODE_SIZE; 658 regs_size = BTC_IO_MC_REGS_SIZE; 659 break; 660 case CHIP_CAICOS: 661 default: 662 io_mc_regs = &caicos_io_mc_regs[0][0]; 663 ucode_size = BTC_MC_UCODE_SIZE; 664 regs_size = BTC_IO_MC_REGS_SIZE; 665 break; 666 case CHIP_CAYMAN: 667 io_mc_regs = &cayman_io_mc_regs[0][0]; 668 ucode_size = CAYMAN_MC_UCODE_SIZE; 669 regs_size = BTC_IO_MC_REGS_SIZE; 670 break; 671 } 672 673 mem_type = (RREG32(MC_SEQ_MISC0) & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT; 674 running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK; 675 676 if ((mem_type == MC_SEQ_MISC0_GDDR5_VALUE) && (running == 0)) { 677 if (running) { 678 blackout = RREG32(MC_SHARED_BLACKOUT_CNTL); 679 WREG32(MC_SHARED_BLACKOUT_CNTL, 1); 680 } 681 682 /* reset the engine and set to writable */ 683 WREG32(MC_SEQ_SUP_CNTL, 0x00000008); 684 WREG32(MC_SEQ_SUP_CNTL, 0x00000010); 685 686 /* load mc io regs */ 687 for (i = 0; i < regs_size; i++) { 688 WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]); 689 WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]); 690 } 691 /* load the MC ucode */ 692 fw_data = (const __be32 *)rdev->mc_fw->data; 693 for (i = 0; i < ucode_size; i++) 694 WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++)); 695 696 /* put the engine back into the active state */ 697 WREG32(MC_SEQ_SUP_CNTL, 0x00000008); 698 WREG32(MC_SEQ_SUP_CNTL, 0x00000004); 699 WREG32(MC_SEQ_SUP_CNTL, 0x00000001); 700 701 /* wait for training to complete */ 702 for (i = 0; i < rdev->usec_timeout; i++) { 703 if (RREG32(MC_IO_PAD_CNTL_D0) & MEM_FALL_OUT_CMD) 704 break; 705 udelay(1); 706 } 707 708 if (running) 709 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout); 710 } 711 712 return 0; 713 } 714 715 int ni_init_microcode(struct radeon_device *rdev) 716 { 717 const char *chip_name; 718 const char *rlc_chip_name; 719 size_t pfp_req_size, me_req_size, rlc_req_size, mc_req_size; 720 size_t smc_req_size = 0; 721 char fw_name[30]; 722 int err; 723 724 DRM_DEBUG("\n"); 725 726 switch (rdev->family) { 727 case CHIP_BARTS: 728 chip_name = "BARTS"; 729 rlc_chip_name = "BTC"; 730 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4; 731 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4; 732 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4; 733 mc_req_size = BTC_MC_UCODE_SIZE * 4; 734 #ifdef __NetBSD__ /* XXX ALIGN means something else. */ 735 smc_req_size = round_up(BARTS_SMC_UCODE_SIZE, 4); 736 #else 737 smc_req_size = ALIGN(BARTS_SMC_UCODE_SIZE, 4); 738 #endif 739 break; 740 case CHIP_TURKS: 741 chip_name = "TURKS"; 742 rlc_chip_name = "BTC"; 743 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4; 744 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4; 745 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4; 746 mc_req_size = BTC_MC_UCODE_SIZE * 4; 747 #ifdef __NetBSD__ /* XXX ALIGN means something else. */ 748 smc_req_size = round_up(TURKS_SMC_UCODE_SIZE, 4); 749 #else 750 smc_req_size = ALIGN(TURKS_SMC_UCODE_SIZE, 4); 751 #endif 752 break; 753 case CHIP_CAICOS: 754 chip_name = "CAICOS"; 755 rlc_chip_name = "BTC"; 756 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4; 757 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4; 758 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4; 759 mc_req_size = BTC_MC_UCODE_SIZE * 4; 760 #ifdef __NetBSD__ /* XXX ALIGN means something else. */ 761 smc_req_size = round_up(CAICOS_SMC_UCODE_SIZE, 4); 762 #else 763 smc_req_size = ALIGN(CAICOS_SMC_UCODE_SIZE, 4); 764 #endif 765 break; 766 case CHIP_CAYMAN: 767 chip_name = "CAYMAN"; 768 rlc_chip_name = "CAYMAN"; 769 pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4; 770 me_req_size = CAYMAN_PM4_UCODE_SIZE * 4; 771 rlc_req_size = CAYMAN_RLC_UCODE_SIZE * 4; 772 mc_req_size = CAYMAN_MC_UCODE_SIZE * 4; 773 #ifdef __NetBSD__ /* XXX ALIGN means something else. */ 774 smc_req_size = round_up(CAYMAN_SMC_UCODE_SIZE, 4); 775 #else 776 smc_req_size = ALIGN(CAYMAN_SMC_UCODE_SIZE, 4); 777 #endif 778 break; 779 case CHIP_ARUBA: 780 chip_name = "ARUBA"; 781 rlc_chip_name = "ARUBA"; 782 /* pfp/me same size as CAYMAN */ 783 pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4; 784 me_req_size = CAYMAN_PM4_UCODE_SIZE * 4; 785 rlc_req_size = ARUBA_RLC_UCODE_SIZE * 4; 786 mc_req_size = 0; 787 break; 788 default: BUG(); 789 } 790 791 DRM_INFO("Loading %s Microcode\n", chip_name); 792 793 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name); 794 err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev); 795 if (err) 796 goto out; 797 if (rdev->pfp_fw->size != pfp_req_size) { 798 printk(KERN_ERR 799 "ni_cp: Bogus length %zu in firmware \"%s\"\n", 800 rdev->pfp_fw->size, fw_name); 801 err = -EINVAL; 802 goto out; 803 } 804 805 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name); 806 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev); 807 if (err) 808 goto out; 809 if (rdev->me_fw->size != me_req_size) { 810 printk(KERN_ERR 811 "ni_cp: Bogus length %zu in firmware \"%s\"\n", 812 rdev->me_fw->size, fw_name); 813 err = -EINVAL; 814 } 815 816 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name); 817 err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev); 818 if (err) 819 goto out; 820 if (rdev->rlc_fw->size != rlc_req_size) { 821 printk(KERN_ERR 822 "ni_rlc: Bogus length %zu in firmware \"%s\"\n", 823 rdev->rlc_fw->size, fw_name); 824 err = -EINVAL; 825 } 826 827 /* no MC ucode on TN */ 828 if (!(rdev->flags & RADEON_IS_IGP)) { 829 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name); 830 err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev); 831 if (err) 832 goto out; 833 if (rdev->mc_fw->size != mc_req_size) { 834 printk(KERN_ERR 835 "ni_mc: Bogus length %zu in firmware \"%s\"\n", 836 rdev->mc_fw->size, fw_name); 837 err = -EINVAL; 838 } 839 } 840 841 if ((rdev->family >= CHIP_BARTS) && (rdev->family <= CHIP_CAYMAN)) { 842 snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", chip_name); 843 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev); 844 if (err) { 845 printk(KERN_ERR 846 "smc: error loading firmware \"%s\"\n", 847 fw_name); 848 release_firmware(rdev->smc_fw); 849 rdev->smc_fw = NULL; 850 err = 0; 851 } else if (rdev->smc_fw->size != smc_req_size) { 852 printk(KERN_ERR 853 "ni_mc: Bogus length %zu in firmware \"%s\"\n", 854 rdev->mc_fw->size, fw_name); 855 err = -EINVAL; 856 } 857 } 858 859 out: 860 if (err) { 861 if (err != -EINVAL) 862 printk(KERN_ERR 863 "ni_cp: Failed to load firmware \"%s\"\n", 864 fw_name); 865 release_firmware(rdev->pfp_fw); 866 rdev->pfp_fw = NULL; 867 release_firmware(rdev->me_fw); 868 rdev->me_fw = NULL; 869 release_firmware(rdev->rlc_fw); 870 rdev->rlc_fw = NULL; 871 release_firmware(rdev->mc_fw); 872 rdev->mc_fw = NULL; 873 } 874 return err; 875 } 876 877 /** 878 * cayman_get_allowed_info_register - fetch the register for the info ioctl 879 * 880 * @rdev: radeon_device pointer 881 * @reg: register offset in bytes 882 * @val: register value 883 * 884 * Returns 0 for success or -EINVAL for an invalid register 885 * 886 */ 887 int cayman_get_allowed_info_register(struct radeon_device *rdev, 888 u32 reg, u32 *val) 889 { 890 switch (reg) { 891 case GRBM_STATUS: 892 case GRBM_STATUS_SE0: 893 case GRBM_STATUS_SE1: 894 case SRBM_STATUS: 895 case SRBM_STATUS2: 896 case (DMA_STATUS_REG + DMA0_REGISTER_OFFSET): 897 case (DMA_STATUS_REG + DMA1_REGISTER_OFFSET): 898 case UVD_STATUS: 899 *val = RREG32(reg); 900 return 0; 901 default: 902 return -EINVAL; 903 } 904 } 905 906 int tn_get_temp(struct radeon_device *rdev) 907 { 908 u32 temp = RREG32_SMC(TN_CURRENT_GNB_TEMP) & 0x7ff; 909 int actual_temp = (temp / 8) - 49; 910 911 return actual_temp * 1000; 912 } 913 914 /* 915 * Core functions 916 */ 917 static void cayman_gpu_init(struct radeon_device *rdev) 918 { 919 u32 gb_addr_config = 0; 920 u32 mc_shared_chmap __unused, mc_arb_ramcfg; 921 u32 cgts_tcc_disable; 922 u32 sx_debug_1; 923 u32 smx_dc_ctl0; 924 u32 cgts_sm_ctrl_reg; 925 u32 hdp_host_path_cntl; 926 u32 tmp; 927 u32 disabled_rb_mask; 928 int i, j; 929 930 switch (rdev->family) { 931 case CHIP_CAYMAN: 932 rdev->config.cayman.max_shader_engines = 2; 933 rdev->config.cayman.max_pipes_per_simd = 4; 934 rdev->config.cayman.max_tile_pipes = 8; 935 rdev->config.cayman.max_simds_per_se = 12; 936 rdev->config.cayman.max_backends_per_se = 4; 937 rdev->config.cayman.max_texture_channel_caches = 8; 938 rdev->config.cayman.max_gprs = 256; 939 rdev->config.cayman.max_threads = 256; 940 rdev->config.cayman.max_gs_threads = 32; 941 rdev->config.cayman.max_stack_entries = 512; 942 rdev->config.cayman.sx_num_of_sets = 8; 943 rdev->config.cayman.sx_max_export_size = 256; 944 rdev->config.cayman.sx_max_export_pos_size = 64; 945 rdev->config.cayman.sx_max_export_smx_size = 192; 946 rdev->config.cayman.max_hw_contexts = 8; 947 rdev->config.cayman.sq_num_cf_insts = 2; 948 949 rdev->config.cayman.sc_prim_fifo_size = 0x100; 950 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30; 951 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130; 952 gb_addr_config = CAYMAN_GB_ADDR_CONFIG_GOLDEN; 953 break; 954 case CHIP_ARUBA: 955 default: 956 rdev->config.cayman.max_shader_engines = 1; 957 rdev->config.cayman.max_pipes_per_simd = 4; 958 rdev->config.cayman.max_tile_pipes = 2; 959 if ((rdev->pdev->device == 0x9900) || 960 (rdev->pdev->device == 0x9901) || 961 (rdev->pdev->device == 0x9905) || 962 (rdev->pdev->device == 0x9906) || 963 (rdev->pdev->device == 0x9907) || 964 (rdev->pdev->device == 0x9908) || 965 (rdev->pdev->device == 0x9909) || 966 (rdev->pdev->device == 0x990B) || 967 (rdev->pdev->device == 0x990C) || 968 (rdev->pdev->device == 0x990F) || 969 (rdev->pdev->device == 0x9910) || 970 (rdev->pdev->device == 0x9917) || 971 (rdev->pdev->device == 0x9999) || 972 (rdev->pdev->device == 0x999C)) { 973 rdev->config.cayman.max_simds_per_se = 6; 974 rdev->config.cayman.max_backends_per_se = 2; 975 rdev->config.cayman.max_hw_contexts = 8; 976 rdev->config.cayman.sx_max_export_size = 256; 977 rdev->config.cayman.sx_max_export_pos_size = 64; 978 rdev->config.cayman.sx_max_export_smx_size = 192; 979 } else if ((rdev->pdev->device == 0x9903) || 980 (rdev->pdev->device == 0x9904) || 981 (rdev->pdev->device == 0x990A) || 982 (rdev->pdev->device == 0x990D) || 983 (rdev->pdev->device == 0x990E) || 984 (rdev->pdev->device == 0x9913) || 985 (rdev->pdev->device == 0x9918) || 986 (rdev->pdev->device == 0x999D)) { 987 rdev->config.cayman.max_simds_per_se = 4; 988 rdev->config.cayman.max_backends_per_se = 2; 989 rdev->config.cayman.max_hw_contexts = 8; 990 rdev->config.cayman.sx_max_export_size = 256; 991 rdev->config.cayman.sx_max_export_pos_size = 64; 992 rdev->config.cayman.sx_max_export_smx_size = 192; 993 } else if ((rdev->pdev->device == 0x9919) || 994 (rdev->pdev->device == 0x9990) || 995 (rdev->pdev->device == 0x9991) || 996 (rdev->pdev->device == 0x9994) || 997 (rdev->pdev->device == 0x9995) || 998 (rdev->pdev->device == 0x9996) || 999 (rdev->pdev->device == 0x999A) || 1000 (rdev->pdev->device == 0x99A0)) { 1001 rdev->config.cayman.max_simds_per_se = 3; 1002 rdev->config.cayman.max_backends_per_se = 1; 1003 rdev->config.cayman.max_hw_contexts = 4; 1004 rdev->config.cayman.sx_max_export_size = 128; 1005 rdev->config.cayman.sx_max_export_pos_size = 32; 1006 rdev->config.cayman.sx_max_export_smx_size = 96; 1007 } else { 1008 rdev->config.cayman.max_simds_per_se = 2; 1009 rdev->config.cayman.max_backends_per_se = 1; 1010 rdev->config.cayman.max_hw_contexts = 4; 1011 rdev->config.cayman.sx_max_export_size = 128; 1012 rdev->config.cayman.sx_max_export_pos_size = 32; 1013 rdev->config.cayman.sx_max_export_smx_size = 96; 1014 } 1015 rdev->config.cayman.max_texture_channel_caches = 2; 1016 rdev->config.cayman.max_gprs = 256; 1017 rdev->config.cayman.max_threads = 256; 1018 rdev->config.cayman.max_gs_threads = 32; 1019 rdev->config.cayman.max_stack_entries = 512; 1020 rdev->config.cayman.sx_num_of_sets = 8; 1021 rdev->config.cayman.sq_num_cf_insts = 2; 1022 1023 rdev->config.cayman.sc_prim_fifo_size = 0x40; 1024 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30; 1025 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130; 1026 gb_addr_config = ARUBA_GB_ADDR_CONFIG_GOLDEN; 1027 break; 1028 } 1029 1030 /* Initialize HDP */ 1031 for (i = 0, j = 0; i < 32; i++, j += 0x18) { 1032 WREG32((0x2c14 + j), 0x00000000); 1033 WREG32((0x2c18 + j), 0x00000000); 1034 WREG32((0x2c1c + j), 0x00000000); 1035 WREG32((0x2c20 + j), 0x00000000); 1036 WREG32((0x2c24 + j), 0x00000000); 1037 } 1038 1039 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); 1040 WREG32(SRBM_INT_CNTL, 0x1); 1041 WREG32(SRBM_INT_ACK, 0x1); 1042 1043 evergreen_fix_pci_max_read_req_size(rdev); 1044 1045 mc_shared_chmap = RREG32(MC_SHARED_CHMAP); 1046 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG); 1047 1048 tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT; 1049 rdev->config.cayman.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; 1050 if (rdev->config.cayman.mem_row_size_in_kb > 4) 1051 rdev->config.cayman.mem_row_size_in_kb = 4; 1052 /* XXX use MC settings? */ 1053 rdev->config.cayman.shader_engine_tile_size = 32; 1054 rdev->config.cayman.num_gpus = 1; 1055 rdev->config.cayman.multi_gpu_tile_size = 64; 1056 1057 tmp = (gb_addr_config & NUM_PIPES_MASK) >> NUM_PIPES_SHIFT; 1058 rdev->config.cayman.num_tile_pipes = (1 << tmp); 1059 tmp = (gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT; 1060 rdev->config.cayman.mem_max_burst_length_bytes = (tmp + 1) * 256; 1061 tmp = (gb_addr_config & NUM_SHADER_ENGINES_MASK) >> NUM_SHADER_ENGINES_SHIFT; 1062 rdev->config.cayman.num_shader_engines = tmp + 1; 1063 tmp = (gb_addr_config & NUM_GPUS_MASK) >> NUM_GPUS_SHIFT; 1064 rdev->config.cayman.num_gpus = tmp + 1; 1065 tmp = (gb_addr_config & MULTI_GPU_TILE_SIZE_MASK) >> MULTI_GPU_TILE_SIZE_SHIFT; 1066 rdev->config.cayman.multi_gpu_tile_size = 1 << tmp; 1067 tmp = (gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT; 1068 rdev->config.cayman.mem_row_size_in_kb = 1 << tmp; 1069 1070 1071 /* setup tiling info dword. gb_addr_config is not adequate since it does 1072 * not have bank info, so create a custom tiling dword. 1073 * bits 3:0 num_pipes 1074 * bits 7:4 num_banks 1075 * bits 11:8 group_size 1076 * bits 15:12 row_size 1077 */ 1078 rdev->config.cayman.tile_config = 0; 1079 switch (rdev->config.cayman.num_tile_pipes) { 1080 case 1: 1081 default: 1082 rdev->config.cayman.tile_config |= (0 << 0); 1083 break; 1084 case 2: 1085 rdev->config.cayman.tile_config |= (1 << 0); 1086 break; 1087 case 4: 1088 rdev->config.cayman.tile_config |= (2 << 0); 1089 break; 1090 case 8: 1091 rdev->config.cayman.tile_config |= (3 << 0); 1092 break; 1093 } 1094 1095 /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */ 1096 if (rdev->flags & RADEON_IS_IGP) 1097 rdev->config.cayman.tile_config |= 1 << 4; 1098 else { 1099 switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) { 1100 case 0: /* four banks */ 1101 rdev->config.cayman.tile_config |= 0 << 4; 1102 break; 1103 case 1: /* eight banks */ 1104 rdev->config.cayman.tile_config |= 1 << 4; 1105 break; 1106 case 2: /* sixteen banks */ 1107 default: 1108 rdev->config.cayman.tile_config |= 2 << 4; 1109 break; 1110 } 1111 } 1112 rdev->config.cayman.tile_config |= 1113 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8; 1114 rdev->config.cayman.tile_config |= 1115 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12; 1116 1117 tmp = 0; 1118 for (i = (rdev->config.cayman.max_shader_engines - 1); i >= 0; i--) { 1119 u32 rb_disable_bitmap; 1120 1121 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i)); 1122 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i)); 1123 rb_disable_bitmap = (RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000) >> 16; 1124 tmp <<= 4; 1125 tmp |= rb_disable_bitmap; 1126 } 1127 /* enabled rb are just the one not disabled :) */ 1128 disabled_rb_mask = tmp; 1129 tmp = 0; 1130 for (i = 0; i < (rdev->config.cayman.max_backends_per_se * rdev->config.cayman.max_shader_engines); i++) 1131 tmp |= (1 << i); 1132 /* if all the backends are disabled, fix it up here */ 1133 if ((disabled_rb_mask & tmp) == tmp) { 1134 for (i = 0; i < (rdev->config.cayman.max_backends_per_se * rdev->config.cayman.max_shader_engines); i++) 1135 disabled_rb_mask &= ~(1 << i); 1136 } 1137 1138 for (i = 0; i < rdev->config.cayman.max_shader_engines; i++) { 1139 u32 simd_disable_bitmap; 1140 1141 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i)); 1142 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i)); 1143 simd_disable_bitmap = (RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffff0000) >> 16; 1144 simd_disable_bitmap |= 0xffffffff << rdev->config.cayman.max_simds_per_se; 1145 tmp <<= 16; 1146 tmp |= simd_disable_bitmap; 1147 } 1148 rdev->config.cayman.active_simds = hweight32(~tmp); 1149 1150 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES); 1151 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES); 1152 1153 WREG32(GB_ADDR_CONFIG, gb_addr_config); 1154 WREG32(DMIF_ADDR_CONFIG, gb_addr_config); 1155 if (ASIC_IS_DCE6(rdev)) 1156 WREG32(DMIF_ADDR_CALC, gb_addr_config); 1157 WREG32(HDP_ADDR_CONFIG, gb_addr_config); 1158 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config); 1159 WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config); 1160 WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config); 1161 WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config); 1162 WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config); 1163 1164 if ((rdev->config.cayman.max_backends_per_se == 1) && 1165 (rdev->flags & RADEON_IS_IGP)) { 1166 if ((disabled_rb_mask & 3) == 2) { 1167 /* RB1 disabled, RB0 enabled */ 1168 tmp = 0x00000000; 1169 } else { 1170 /* RB0 disabled, RB1 enabled */ 1171 tmp = 0x11111111; 1172 } 1173 } else { 1174 tmp = gb_addr_config & NUM_PIPES_MASK; 1175 tmp = r6xx_remap_render_backend(rdev, tmp, 1176 rdev->config.cayman.max_backends_per_se * 1177 rdev->config.cayman.max_shader_engines, 1178 CAYMAN_MAX_BACKENDS, disabled_rb_mask); 1179 } 1180 WREG32(GB_BACKEND_MAP, tmp); 1181 1182 cgts_tcc_disable = 0xffff0000; 1183 for (i = 0; i < rdev->config.cayman.max_texture_channel_caches; i++) 1184 cgts_tcc_disable &= ~(1 << (16 + i)); 1185 WREG32(CGTS_TCC_DISABLE, cgts_tcc_disable); 1186 WREG32(CGTS_SYS_TCC_DISABLE, cgts_tcc_disable); 1187 WREG32(CGTS_USER_SYS_TCC_DISABLE, cgts_tcc_disable); 1188 WREG32(CGTS_USER_TCC_DISABLE, cgts_tcc_disable); 1189 1190 /* reprogram the shader complex */ 1191 cgts_sm_ctrl_reg = RREG32(CGTS_SM_CTRL_REG); 1192 for (i = 0; i < 16; i++) 1193 WREG32(CGTS_SM_CTRL_REG, OVERRIDE); 1194 WREG32(CGTS_SM_CTRL_REG, cgts_sm_ctrl_reg); 1195 1196 /* set HW defaults for 3D engine */ 1197 WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60)); 1198 1199 sx_debug_1 = RREG32(SX_DEBUG_1); 1200 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS; 1201 WREG32(SX_DEBUG_1, sx_debug_1); 1202 1203 smx_dc_ctl0 = RREG32(SMX_DC_CTL0); 1204 smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff); 1205 smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.cayman.sx_num_of_sets); 1206 WREG32(SMX_DC_CTL0, smx_dc_ctl0); 1207 1208 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4) | CRC_SIMD_ID_WADDR_DISABLE); 1209 1210 /* need to be explicitly zero-ed */ 1211 WREG32(VGT_OFFCHIP_LDS_BASE, 0); 1212 WREG32(SQ_LSTMP_RING_BASE, 0); 1213 WREG32(SQ_HSTMP_RING_BASE, 0); 1214 WREG32(SQ_ESTMP_RING_BASE, 0); 1215 WREG32(SQ_GSTMP_RING_BASE, 0); 1216 WREG32(SQ_VSTMP_RING_BASE, 0); 1217 WREG32(SQ_PSTMP_RING_BASE, 0); 1218 1219 WREG32(TA_CNTL_AUX, DISABLE_CUBE_ANISO); 1220 1221 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.cayman.sx_max_export_size / 4) - 1) | 1222 POSITION_BUFFER_SIZE((rdev->config.cayman.sx_max_export_pos_size / 4) - 1) | 1223 SMX_BUFFER_SIZE((rdev->config.cayman.sx_max_export_smx_size / 4) - 1))); 1224 1225 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.cayman.sc_prim_fifo_size) | 1226 SC_HIZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_hiz_tile_fifo_size) | 1227 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_earlyz_tile_fifo_size))); 1228 1229 1230 WREG32(VGT_NUM_INSTANCES, 1); 1231 1232 WREG32(CP_PERFMON_CNTL, 0); 1233 1234 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.cayman.sq_num_cf_insts) | 1235 FETCH_FIFO_HIWATER(0x4) | 1236 DONE_FIFO_HIWATER(0xe0) | 1237 ALU_UPDATE_FIFO_HIWATER(0x8))); 1238 1239 WREG32(SQ_GPR_RESOURCE_MGMT_1, NUM_CLAUSE_TEMP_GPRS(4)); 1240 WREG32(SQ_CONFIG, (VC_ENABLE | 1241 EXPORT_SRC_C | 1242 GFX_PRIO(0) | 1243 CS1_PRIO(0) | 1244 CS2_PRIO(1))); 1245 WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, DYN_GPR_ENABLE); 1246 1247 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) | 1248 FORCE_EOV_MAX_REZ_CNT(255))); 1249 1250 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) | 1251 AUTO_INVLD_EN(ES_AND_GS_AUTO)); 1252 1253 WREG32(VGT_GS_VERTEX_REUSE, 16); 1254 WREG32(PA_SC_LINE_STIPPLE_STATE, 0); 1255 1256 WREG32(CB_PERF_CTR0_SEL_0, 0); 1257 WREG32(CB_PERF_CTR0_SEL_1, 0); 1258 WREG32(CB_PERF_CTR1_SEL_0, 0); 1259 WREG32(CB_PERF_CTR1_SEL_1, 0); 1260 WREG32(CB_PERF_CTR2_SEL_0, 0); 1261 WREG32(CB_PERF_CTR2_SEL_1, 0); 1262 WREG32(CB_PERF_CTR3_SEL_0, 0); 1263 WREG32(CB_PERF_CTR3_SEL_1, 0); 1264 1265 tmp = RREG32(HDP_MISC_CNTL); 1266 tmp |= HDP_FLUSH_INVALIDATE_CACHE; 1267 WREG32(HDP_MISC_CNTL, tmp); 1268 1269 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL); 1270 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl); 1271 1272 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3)); 1273 1274 udelay(50); 1275 1276 /* set clockgating golden values on TN */ 1277 if (rdev->family == CHIP_ARUBA) { 1278 tmp = RREG32_CG(CG_CGTT_LOCAL_0); 1279 tmp &= ~0x00380000; 1280 WREG32_CG(CG_CGTT_LOCAL_0, tmp); 1281 tmp = RREG32_CG(CG_CGTT_LOCAL_1); 1282 tmp &= ~0x0e000000; 1283 WREG32_CG(CG_CGTT_LOCAL_1, tmp); 1284 } 1285 } 1286 1287 /* 1288 * GART 1289 */ 1290 void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev) 1291 { 1292 /* flush hdp cache */ 1293 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); 1294 1295 /* bits 0-7 are the VM contexts0-7 */ 1296 WREG32(VM_INVALIDATE_REQUEST, 1); 1297 } 1298 1299 static int cayman_pcie_gart_enable(struct radeon_device *rdev) 1300 { 1301 int i, r; 1302 1303 if (rdev->gart.robj == NULL) { 1304 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); 1305 return -EINVAL; 1306 } 1307 r = radeon_gart_table_vram_pin(rdev); 1308 if (r) 1309 return r; 1310 /* Setup TLB control */ 1311 WREG32(MC_VM_MX_L1_TLB_CNTL, 1312 (0xA << 7) | 1313 ENABLE_L1_TLB | 1314 ENABLE_L1_FRAGMENT_PROCESSING | 1315 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 1316 ENABLE_ADVANCED_DRIVER_MODEL | 1317 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU); 1318 /* Setup L2 cache */ 1319 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | 1320 ENABLE_L2_FRAGMENT_PROCESSING | 1321 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 1322 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE | 1323 EFFECTIVE_L2_QUEUE_SIZE(7) | 1324 CONTEXT1_IDENTITY_ACCESS_MODE(1)); 1325 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE); 1326 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | 1327 BANK_SELECT(6) | 1328 L2_CACHE_BIGK_FRAGMENT_SIZE(6)); 1329 /* setup context0 */ 1330 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); 1331 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); 1332 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); 1333 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 1334 (u32)(rdev->dummy_page.addr >> 12)); 1335 WREG32(VM_CONTEXT0_CNTL2, 0); 1336 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | 1337 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); 1338 1339 WREG32(0x15D4, 0); 1340 WREG32(0x15D8, 0); 1341 WREG32(0x15DC, 0); 1342 1343 /* empty context1-7 */ 1344 /* Assign the pt base to something valid for now; the pts used for 1345 * the VMs are determined by the application and setup and assigned 1346 * on the fly in the vm part of radeon_gart.c 1347 */ 1348 for (i = 1; i < 8; i++) { 1349 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (i << 2), 0); 1350 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (i << 2), 1351 rdev->vm_manager.max_pfn - 1); 1352 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2), 1353 rdev->vm_manager.saved_table_addr[i]); 1354 } 1355 1356 /* enable context1-7 */ 1357 WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, 1358 (u32)(rdev->dummy_page.addr >> 12)); 1359 WREG32(VM_CONTEXT1_CNTL2, 4); 1360 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) | 1361 PAGE_TABLE_BLOCK_SIZE(radeon_vm_block_size - 9) | 1362 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT | 1363 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT | 1364 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT | 1365 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT | 1366 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT | 1367 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT | 1368 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT | 1369 VALID_PROTECTION_FAULT_ENABLE_DEFAULT | 1370 READ_PROTECTION_FAULT_ENABLE_INTERRUPT | 1371 READ_PROTECTION_FAULT_ENABLE_DEFAULT | 1372 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT | 1373 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT); 1374 1375 cayman_pcie_gart_tlb_flush(rdev); 1376 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 1377 (unsigned)(rdev->mc.gtt_size >> 20), 1378 (unsigned long long)rdev->gart.table_addr); 1379 rdev->gart.ready = true; 1380 return 0; 1381 } 1382 1383 static void cayman_pcie_gart_disable(struct radeon_device *rdev) 1384 { 1385 unsigned i; 1386 1387 for (i = 1; i < 8; ++i) { 1388 rdev->vm_manager.saved_table_addr[i] = RREG32( 1389 VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2)); 1390 } 1391 1392 /* Disable all tables */ 1393 WREG32(VM_CONTEXT0_CNTL, 0); 1394 WREG32(VM_CONTEXT1_CNTL, 0); 1395 /* Setup TLB control */ 1396 WREG32(MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING | 1397 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 1398 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU); 1399 /* Setup L2 cache */ 1400 WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 1401 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE | 1402 EFFECTIVE_L2_QUEUE_SIZE(7) | 1403 CONTEXT1_IDENTITY_ACCESS_MODE(1)); 1404 WREG32(VM_L2_CNTL2, 0); 1405 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | 1406 L2_CACHE_BIGK_FRAGMENT_SIZE(6)); 1407 radeon_gart_table_vram_unpin(rdev); 1408 } 1409 1410 static void cayman_pcie_gart_fini(struct radeon_device *rdev) 1411 { 1412 cayman_pcie_gart_disable(rdev); 1413 radeon_gart_table_vram_free(rdev); 1414 radeon_gart_fini(rdev); 1415 } 1416 1417 void cayman_cp_int_cntl_setup(struct radeon_device *rdev, 1418 int ring, u32 cp_int_cntl) 1419 { 1420 WREG32(SRBM_GFX_CNTL, RINGID(ring)); 1421 WREG32(CP_INT_CNTL, cp_int_cntl); 1422 } 1423 1424 /* 1425 * CP. 1426 */ 1427 void cayman_fence_ring_emit(struct radeon_device *rdev, 1428 struct radeon_fence *fence) 1429 { 1430 struct radeon_ring *ring = &rdev->ring[fence->ring]; 1431 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; 1432 u32 cp_coher_cntl = PACKET3_FULL_CACHE_ENA | PACKET3_TC_ACTION_ENA | 1433 PACKET3_SH_ACTION_ENA; 1434 1435 /* flush read cache over gart for this vmid */ 1436 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 1437 radeon_ring_write(ring, PACKET3_ENGINE_ME | cp_coher_cntl); 1438 radeon_ring_write(ring, 0xFFFFFFFF); 1439 radeon_ring_write(ring, 0); 1440 radeon_ring_write(ring, 10); /* poll interval */ 1441 /* EVENT_WRITE_EOP - flush caches, send int */ 1442 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); 1443 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5)); 1444 radeon_ring_write(ring, lower_32_bits(addr)); 1445 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); 1446 radeon_ring_write(ring, fence->seq); 1447 radeon_ring_write(ring, 0); 1448 } 1449 1450 void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) 1451 { 1452 struct radeon_ring *ring = &rdev->ring[ib->ring]; 1453 unsigned vm_id = ib->vm ? ib->vm->ids[ib->ring].id : 0; 1454 u32 cp_coher_cntl = PACKET3_FULL_CACHE_ENA | PACKET3_TC_ACTION_ENA | 1455 PACKET3_SH_ACTION_ENA; 1456 1457 /* set to DX10/11 mode */ 1458 radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0)); 1459 radeon_ring_write(ring, 1); 1460 1461 if (ring->rptr_save_reg) { 1462 uint32_t next_rptr = ring->wptr + 3 + 4 + 8; 1463 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 1464 radeon_ring_write(ring, ((ring->rptr_save_reg - 1465 PACKET3_SET_CONFIG_REG_START) >> 2)); 1466 radeon_ring_write(ring, next_rptr); 1467 } 1468 1469 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 1470 radeon_ring_write(ring, 1471 #ifdef __BIG_ENDIAN 1472 (2 << 0) | 1473 #endif 1474 (ib->gpu_addr & 0xFFFFFFFC)); 1475 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF); 1476 radeon_ring_write(ring, ib->length_dw | (vm_id << 24)); 1477 1478 /* flush read cache over gart for this vmid */ 1479 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 1480 radeon_ring_write(ring, PACKET3_ENGINE_ME | cp_coher_cntl); 1481 radeon_ring_write(ring, 0xFFFFFFFF); 1482 radeon_ring_write(ring, 0); 1483 radeon_ring_write(ring, (vm_id << 24) | 10); /* poll interval */ 1484 } 1485 1486 static void cayman_cp_enable(struct radeon_device *rdev, bool enable) 1487 { 1488 if (enable) 1489 WREG32(CP_ME_CNTL, 0); 1490 else { 1491 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX) 1492 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 1493 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT)); 1494 WREG32(SCRATCH_UMSK, 0); 1495 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; 1496 } 1497 } 1498 1499 u32 cayman_gfx_get_rptr(struct radeon_device *rdev, 1500 struct radeon_ring *ring) 1501 { 1502 u32 rptr; 1503 1504 if (rdev->wb.enabled) 1505 rptr = rdev->wb.wb[ring->rptr_offs/4]; 1506 else { 1507 if (ring->idx == RADEON_RING_TYPE_GFX_INDEX) 1508 rptr = RREG32(CP_RB0_RPTR); 1509 else if (ring->idx == CAYMAN_RING_TYPE_CP1_INDEX) 1510 rptr = RREG32(CP_RB1_RPTR); 1511 else 1512 rptr = RREG32(CP_RB2_RPTR); 1513 } 1514 1515 return rptr; 1516 } 1517 1518 u32 cayman_gfx_get_wptr(struct radeon_device *rdev, 1519 struct radeon_ring *ring) 1520 { 1521 u32 wptr; 1522 1523 if (ring->idx == RADEON_RING_TYPE_GFX_INDEX) 1524 wptr = RREG32(CP_RB0_WPTR); 1525 else if (ring->idx == CAYMAN_RING_TYPE_CP1_INDEX) 1526 wptr = RREG32(CP_RB1_WPTR); 1527 else 1528 wptr = RREG32(CP_RB2_WPTR); 1529 1530 return wptr; 1531 } 1532 1533 void cayman_gfx_set_wptr(struct radeon_device *rdev, 1534 struct radeon_ring *ring) 1535 { 1536 if (ring->idx == RADEON_RING_TYPE_GFX_INDEX) { 1537 WREG32(CP_RB0_WPTR, ring->wptr); 1538 (void)RREG32(CP_RB0_WPTR); 1539 } else if (ring->idx == CAYMAN_RING_TYPE_CP1_INDEX) { 1540 WREG32(CP_RB1_WPTR, ring->wptr); 1541 (void)RREG32(CP_RB1_WPTR); 1542 } else { 1543 WREG32(CP_RB2_WPTR, ring->wptr); 1544 (void)RREG32(CP_RB2_WPTR); 1545 } 1546 } 1547 1548 static int cayman_cp_load_microcode(struct radeon_device *rdev) 1549 { 1550 const __be32 *fw_data; 1551 int i; 1552 1553 if (!rdev->me_fw || !rdev->pfp_fw) 1554 return -EINVAL; 1555 1556 cayman_cp_enable(rdev, false); 1557 1558 fw_data = (const __be32 *)rdev->pfp_fw->data; 1559 WREG32(CP_PFP_UCODE_ADDR, 0); 1560 for (i = 0; i < CAYMAN_PFP_UCODE_SIZE; i++) 1561 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++)); 1562 WREG32(CP_PFP_UCODE_ADDR, 0); 1563 1564 fw_data = (const __be32 *)rdev->me_fw->data; 1565 WREG32(CP_ME_RAM_WADDR, 0); 1566 for (i = 0; i < CAYMAN_PM4_UCODE_SIZE; i++) 1567 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++)); 1568 1569 WREG32(CP_PFP_UCODE_ADDR, 0); 1570 WREG32(CP_ME_RAM_WADDR, 0); 1571 WREG32(CP_ME_RAM_RADDR, 0); 1572 return 0; 1573 } 1574 1575 static int cayman_cp_start(struct radeon_device *rdev) 1576 { 1577 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 1578 int r, i; 1579 1580 r = radeon_ring_lock(rdev, ring, 7); 1581 if (r) { 1582 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); 1583 return r; 1584 } 1585 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); 1586 radeon_ring_write(ring, 0x1); 1587 radeon_ring_write(ring, 0x0); 1588 radeon_ring_write(ring, rdev->config.cayman.max_hw_contexts - 1); 1589 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); 1590 radeon_ring_write(ring, 0); 1591 radeon_ring_write(ring, 0); 1592 radeon_ring_unlock_commit(rdev, ring, false); 1593 1594 cayman_cp_enable(rdev, true); 1595 1596 r = radeon_ring_lock(rdev, ring, cayman_default_size + 19); 1597 if (r) { 1598 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); 1599 return r; 1600 } 1601 1602 /* setup clear context state */ 1603 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 1604 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 1605 1606 for (i = 0; i < cayman_default_size; i++) 1607 radeon_ring_write(ring, cayman_default_state[i]); 1608 1609 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 1610 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 1611 1612 /* set clear context state */ 1613 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 1614 radeon_ring_write(ring, 0); 1615 1616 /* SQ_VTX_BASE_VTX_LOC */ 1617 radeon_ring_write(ring, 0xc0026f00); 1618 radeon_ring_write(ring, 0x00000000); 1619 radeon_ring_write(ring, 0x00000000); 1620 radeon_ring_write(ring, 0x00000000); 1621 1622 /* Clear consts */ 1623 radeon_ring_write(ring, 0xc0036f00); 1624 radeon_ring_write(ring, 0x00000bc4); 1625 radeon_ring_write(ring, 0xffffffff); 1626 radeon_ring_write(ring, 0xffffffff); 1627 radeon_ring_write(ring, 0xffffffff); 1628 1629 radeon_ring_write(ring, 0xc0026900); 1630 radeon_ring_write(ring, 0x00000316); 1631 radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */ 1632 radeon_ring_write(ring, 0x00000010); /* */ 1633 1634 radeon_ring_unlock_commit(rdev, ring, false); 1635 1636 /* XXX init other rings */ 1637 1638 return 0; 1639 } 1640 1641 static void cayman_cp_fini(struct radeon_device *rdev) 1642 { 1643 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 1644 cayman_cp_enable(rdev, false); 1645 radeon_ring_fini(rdev, ring); 1646 radeon_scratch_free(rdev, ring->rptr_save_reg); 1647 } 1648 1649 static int cayman_cp_resume(struct radeon_device *rdev) 1650 { 1651 static const int ridx[] = { 1652 RADEON_RING_TYPE_GFX_INDEX, 1653 CAYMAN_RING_TYPE_CP1_INDEX, 1654 CAYMAN_RING_TYPE_CP2_INDEX 1655 }; 1656 static const unsigned cp_rb_cntl[] = { 1657 CP_RB0_CNTL, 1658 CP_RB1_CNTL, 1659 CP_RB2_CNTL, 1660 }; 1661 static const unsigned cp_rb_rptr_addr[] = { 1662 CP_RB0_RPTR_ADDR, 1663 CP_RB1_RPTR_ADDR, 1664 CP_RB2_RPTR_ADDR 1665 }; 1666 static const unsigned cp_rb_rptr_addr_hi[] = { 1667 CP_RB0_RPTR_ADDR_HI, 1668 CP_RB1_RPTR_ADDR_HI, 1669 CP_RB2_RPTR_ADDR_HI 1670 }; 1671 static const unsigned cp_rb_base[] = { 1672 CP_RB0_BASE, 1673 CP_RB1_BASE, 1674 CP_RB2_BASE 1675 }; 1676 static const unsigned cp_rb_rptr[] = { 1677 CP_RB0_RPTR, 1678 CP_RB1_RPTR, 1679 CP_RB2_RPTR 1680 }; 1681 static const unsigned cp_rb_wptr[] = { 1682 CP_RB0_WPTR, 1683 CP_RB1_WPTR, 1684 CP_RB2_WPTR 1685 }; 1686 struct radeon_ring *ring; 1687 int i, r; 1688 1689 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */ 1690 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP | 1691 SOFT_RESET_PA | 1692 SOFT_RESET_SH | 1693 SOFT_RESET_VGT | 1694 SOFT_RESET_SPI | 1695 SOFT_RESET_SX)); 1696 RREG32(GRBM_SOFT_RESET); 1697 mdelay(15); 1698 WREG32(GRBM_SOFT_RESET, 0); 1699 RREG32(GRBM_SOFT_RESET); 1700 1701 WREG32(CP_SEM_WAIT_TIMER, 0x0); 1702 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0); 1703 1704 /* Set the write pointer delay */ 1705 WREG32(CP_RB_WPTR_DELAY, 0); 1706 1707 WREG32(CP_DEBUG, (1 << 27)); 1708 1709 /* set the wb address whether it's enabled or not */ 1710 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); 1711 WREG32(SCRATCH_UMSK, 0xff); 1712 1713 for (i = 0; i < 3; ++i) { 1714 uint32_t rb_cntl; 1715 uint64_t addr; 1716 1717 /* Set ring buffer size */ 1718 ring = &rdev->ring[ridx[i]]; 1719 rb_cntl = order_base_2(ring->ring_size / 8); 1720 rb_cntl |= order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8; 1721 #ifdef __BIG_ENDIAN 1722 rb_cntl |= BUF_SWAP_32BIT; 1723 #endif 1724 WREG32(cp_rb_cntl[i], rb_cntl); 1725 1726 /* set the wb address whether it's enabled or not */ 1727 addr = rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET; 1728 WREG32(cp_rb_rptr_addr[i], addr & 0xFFFFFFFC); 1729 WREG32(cp_rb_rptr_addr_hi[i], upper_32_bits(addr) & 0xFF); 1730 } 1731 1732 /* set the rb base addr, this causes an internal reset of ALL rings */ 1733 for (i = 0; i < 3; ++i) { 1734 ring = &rdev->ring[ridx[i]]; 1735 WREG32(cp_rb_base[i], ring->gpu_addr >> 8); 1736 } 1737 1738 for (i = 0; i < 3; ++i) { 1739 /* Initialize the ring buffer's read and write pointers */ 1740 ring = &rdev->ring[ridx[i]]; 1741 WREG32_P(cp_rb_cntl[i], RB_RPTR_WR_ENA, ~RB_RPTR_WR_ENA); 1742 1743 ring->wptr = 0; 1744 WREG32(cp_rb_rptr[i], 0); 1745 WREG32(cp_rb_wptr[i], ring->wptr); 1746 1747 mdelay(1); 1748 WREG32_P(cp_rb_cntl[i], 0, ~RB_RPTR_WR_ENA); 1749 } 1750 1751 /* start the rings */ 1752 cayman_cp_start(rdev); 1753 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true; 1754 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false; 1755 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false; 1756 /* this only test cp0 */ 1757 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); 1758 if (r) { 1759 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; 1760 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false; 1761 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false; 1762 return r; 1763 } 1764 1765 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX) 1766 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); 1767 1768 return 0; 1769 } 1770 1771 u32 cayman_gpu_check_soft_reset(struct radeon_device *rdev) 1772 { 1773 u32 reset_mask = 0; 1774 u32 tmp; 1775 1776 /* GRBM_STATUS */ 1777 tmp = RREG32(GRBM_STATUS); 1778 if (tmp & (PA_BUSY | SC_BUSY | 1779 SH_BUSY | SX_BUSY | 1780 TA_BUSY | VGT_BUSY | 1781 DB_BUSY | CB_BUSY | 1782 GDS_BUSY | SPI_BUSY | 1783 IA_BUSY | IA_BUSY_NO_DMA)) 1784 reset_mask |= RADEON_RESET_GFX; 1785 1786 if (tmp & (CF_RQ_PENDING | PF_RQ_PENDING | 1787 CP_BUSY | CP_COHERENCY_BUSY)) 1788 reset_mask |= RADEON_RESET_CP; 1789 1790 if (tmp & GRBM_EE_BUSY) 1791 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP; 1792 1793 /* DMA_STATUS_REG 0 */ 1794 tmp = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET); 1795 if (!(tmp & DMA_IDLE)) 1796 reset_mask |= RADEON_RESET_DMA; 1797 1798 /* DMA_STATUS_REG 1 */ 1799 tmp = RREG32(DMA_STATUS_REG + DMA1_REGISTER_OFFSET); 1800 if (!(tmp & DMA_IDLE)) 1801 reset_mask |= RADEON_RESET_DMA1; 1802 1803 /* SRBM_STATUS2 */ 1804 tmp = RREG32(SRBM_STATUS2); 1805 if (tmp & DMA_BUSY) 1806 reset_mask |= RADEON_RESET_DMA; 1807 1808 if (tmp & DMA1_BUSY) 1809 reset_mask |= RADEON_RESET_DMA1; 1810 1811 /* SRBM_STATUS */ 1812 tmp = RREG32(SRBM_STATUS); 1813 if (tmp & (RLC_RQ_PENDING | RLC_BUSY)) 1814 reset_mask |= RADEON_RESET_RLC; 1815 1816 if (tmp & IH_BUSY) 1817 reset_mask |= RADEON_RESET_IH; 1818 1819 if (tmp & SEM_BUSY) 1820 reset_mask |= RADEON_RESET_SEM; 1821 1822 if (tmp & GRBM_RQ_PENDING) 1823 reset_mask |= RADEON_RESET_GRBM; 1824 1825 if (tmp & VMC_BUSY) 1826 reset_mask |= RADEON_RESET_VMC; 1827 1828 if (tmp & (MCB_BUSY | MCB_NON_DISPLAY_BUSY | 1829 MCC_BUSY | MCD_BUSY)) 1830 reset_mask |= RADEON_RESET_MC; 1831 1832 if (evergreen_is_display_hung(rdev)) 1833 reset_mask |= RADEON_RESET_DISPLAY; 1834 1835 /* VM_L2_STATUS */ 1836 tmp = RREG32(VM_L2_STATUS); 1837 if (tmp & L2_BUSY) 1838 reset_mask |= RADEON_RESET_VMC; 1839 1840 /* Skip MC reset as it's mostly likely not hung, just busy */ 1841 if (reset_mask & RADEON_RESET_MC) { 1842 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask); 1843 reset_mask &= ~RADEON_RESET_MC; 1844 } 1845 1846 return reset_mask; 1847 } 1848 1849 static void cayman_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask) 1850 { 1851 struct evergreen_mc_save save; 1852 u32 grbm_soft_reset = 0, srbm_soft_reset = 0; 1853 u32 tmp; 1854 1855 if (reset_mask == 0) 1856 return; 1857 1858 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask); 1859 1860 evergreen_print_gpu_status_regs(rdev); 1861 dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_ADDR 0x%08X\n", 1862 RREG32(0x14F8)); 1863 dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_STATUS 0x%08X\n", 1864 RREG32(0x14D8)); 1865 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", 1866 RREG32(0x14FC)); 1867 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", 1868 RREG32(0x14DC)); 1869 1870 /* Disable CP parsing/prefetching */ 1871 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT); 1872 1873 if (reset_mask & RADEON_RESET_DMA) { 1874 /* dma0 */ 1875 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); 1876 tmp &= ~DMA_RB_ENABLE; 1877 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp); 1878 } 1879 1880 if (reset_mask & RADEON_RESET_DMA1) { 1881 /* dma1 */ 1882 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET); 1883 tmp &= ~DMA_RB_ENABLE; 1884 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp); 1885 } 1886 1887 udelay(50); 1888 1889 evergreen_mc_stop(rdev, &save); 1890 if (evergreen_mc_wait_for_idle(rdev)) { 1891 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1892 } 1893 1894 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) { 1895 grbm_soft_reset = SOFT_RESET_CB | 1896 SOFT_RESET_DB | 1897 SOFT_RESET_GDS | 1898 SOFT_RESET_PA | 1899 SOFT_RESET_SC | 1900 SOFT_RESET_SPI | 1901 SOFT_RESET_SH | 1902 SOFT_RESET_SX | 1903 SOFT_RESET_TC | 1904 SOFT_RESET_TA | 1905 SOFT_RESET_VGT | 1906 SOFT_RESET_IA; 1907 } 1908 1909 if (reset_mask & RADEON_RESET_CP) { 1910 grbm_soft_reset |= SOFT_RESET_CP | SOFT_RESET_VGT; 1911 1912 srbm_soft_reset |= SOFT_RESET_GRBM; 1913 } 1914 1915 if (reset_mask & RADEON_RESET_DMA) 1916 srbm_soft_reset |= SOFT_RESET_DMA; 1917 1918 if (reset_mask & RADEON_RESET_DMA1) 1919 srbm_soft_reset |= SOFT_RESET_DMA1; 1920 1921 if (reset_mask & RADEON_RESET_DISPLAY) 1922 srbm_soft_reset |= SOFT_RESET_DC; 1923 1924 if (reset_mask & RADEON_RESET_RLC) 1925 srbm_soft_reset |= SOFT_RESET_RLC; 1926 1927 if (reset_mask & RADEON_RESET_SEM) 1928 srbm_soft_reset |= SOFT_RESET_SEM; 1929 1930 if (reset_mask & RADEON_RESET_IH) 1931 srbm_soft_reset |= SOFT_RESET_IH; 1932 1933 if (reset_mask & RADEON_RESET_GRBM) 1934 srbm_soft_reset |= SOFT_RESET_GRBM; 1935 1936 if (reset_mask & RADEON_RESET_VMC) 1937 srbm_soft_reset |= SOFT_RESET_VMC; 1938 1939 if (!(rdev->flags & RADEON_IS_IGP)) { 1940 if (reset_mask & RADEON_RESET_MC) 1941 srbm_soft_reset |= SOFT_RESET_MC; 1942 } 1943 1944 if (grbm_soft_reset) { 1945 tmp = RREG32(GRBM_SOFT_RESET); 1946 tmp |= grbm_soft_reset; 1947 dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 1948 WREG32(GRBM_SOFT_RESET, tmp); 1949 tmp = RREG32(GRBM_SOFT_RESET); 1950 1951 udelay(50); 1952 1953 tmp &= ~grbm_soft_reset; 1954 WREG32(GRBM_SOFT_RESET, tmp); 1955 tmp = RREG32(GRBM_SOFT_RESET); 1956 } 1957 1958 if (srbm_soft_reset) { 1959 tmp = RREG32(SRBM_SOFT_RESET); 1960 tmp |= srbm_soft_reset; 1961 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1962 WREG32(SRBM_SOFT_RESET, tmp); 1963 tmp = RREG32(SRBM_SOFT_RESET); 1964 1965 udelay(50); 1966 1967 tmp &= ~srbm_soft_reset; 1968 WREG32(SRBM_SOFT_RESET, tmp); 1969 tmp = RREG32(SRBM_SOFT_RESET); 1970 } 1971 1972 /* Wait a little for things to settle down */ 1973 udelay(50); 1974 1975 evergreen_mc_resume(rdev, &save); 1976 udelay(50); 1977 1978 evergreen_print_gpu_status_regs(rdev); 1979 } 1980 1981 int cayman_asic_reset(struct radeon_device *rdev) 1982 { 1983 u32 reset_mask; 1984 1985 reset_mask = cayman_gpu_check_soft_reset(rdev); 1986 1987 if (reset_mask) 1988 r600_set_bios_scratch_engine_hung(rdev, true); 1989 1990 cayman_gpu_soft_reset(rdev, reset_mask); 1991 1992 reset_mask = cayman_gpu_check_soft_reset(rdev); 1993 1994 if (reset_mask) 1995 evergreen_gpu_pci_config_reset(rdev); 1996 1997 r600_set_bios_scratch_engine_hung(rdev, false); 1998 1999 return 0; 2000 } 2001 2002 /** 2003 * cayman_gfx_is_lockup - Check if the GFX engine is locked up 2004 * 2005 * @rdev: radeon_device pointer 2006 * @ring: radeon_ring structure holding ring information 2007 * 2008 * Check if the GFX engine is locked up. 2009 * Returns true if the engine appears to be locked up, false if not. 2010 */ 2011 bool cayman_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) 2012 { 2013 u32 reset_mask = cayman_gpu_check_soft_reset(rdev); 2014 2015 if (!(reset_mask & (RADEON_RESET_GFX | 2016 RADEON_RESET_COMPUTE | 2017 RADEON_RESET_CP))) { 2018 radeon_ring_lockup_update(rdev, ring); 2019 return false; 2020 } 2021 return radeon_ring_test_lockup(rdev, ring); 2022 } 2023 2024 static int cayman_startup(struct radeon_device *rdev) 2025 { 2026 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2027 int r; 2028 2029 /* enable pcie gen2 link */ 2030 evergreen_pcie_gen2_enable(rdev); 2031 /* enable aspm */ 2032 evergreen_program_aspm(rdev); 2033 2034 /* scratch needs to be initialized before MC */ 2035 r = r600_vram_scratch_init(rdev); 2036 if (r) 2037 return r; 2038 2039 evergreen_mc_program(rdev); 2040 2041 if (!(rdev->flags & RADEON_IS_IGP) && !rdev->pm.dpm_enabled) { 2042 r = ni_mc_load_microcode(rdev); 2043 if (r) { 2044 DRM_ERROR("Failed to load MC firmware!\n"); 2045 return r; 2046 } 2047 } 2048 2049 r = cayman_pcie_gart_enable(rdev); 2050 if (r) 2051 return r; 2052 cayman_gpu_init(rdev); 2053 2054 /* allocate rlc buffers */ 2055 if (rdev->flags & RADEON_IS_IGP) { 2056 rdev->rlc.reg_list = tn_rlc_save_restore_register_list; 2057 rdev->rlc.reg_list_size = 2058 (u32)ARRAY_SIZE(tn_rlc_save_restore_register_list); 2059 rdev->rlc.cs_data = cayman_cs_data; 2060 r = sumo_rlc_init(rdev); 2061 if (r) { 2062 DRM_ERROR("Failed to init rlc BOs!\n"); 2063 return r; 2064 } 2065 } 2066 2067 /* allocate wb buffer */ 2068 r = radeon_wb_init(rdev); 2069 if (r) 2070 return r; 2071 2072 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 2073 if (r) { 2074 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 2075 return r; 2076 } 2077 2078 r = uvd_v2_2_resume(rdev); 2079 if (!r) { 2080 r = radeon_fence_driver_start_ring(rdev, 2081 R600_RING_TYPE_UVD_INDEX); 2082 if (r) 2083 dev_err(rdev->dev, "UVD fences init error (%d).\n", r); 2084 } 2085 if (r) 2086 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0; 2087 2088 if (rdev->family == CHIP_ARUBA) { 2089 r = radeon_vce_resume(rdev); 2090 if (!r) 2091 r = vce_v1_0_resume(rdev); 2092 2093 if (!r) 2094 r = radeon_fence_driver_start_ring(rdev, 2095 TN_RING_TYPE_VCE1_INDEX); 2096 if (!r) 2097 r = radeon_fence_driver_start_ring(rdev, 2098 TN_RING_TYPE_VCE2_INDEX); 2099 2100 if (r) { 2101 dev_err(rdev->dev, "VCE init error (%d).\n", r); 2102 rdev->ring[TN_RING_TYPE_VCE1_INDEX].ring_size = 0; 2103 rdev->ring[TN_RING_TYPE_VCE2_INDEX].ring_size = 0; 2104 } 2105 } 2106 2107 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP1_INDEX); 2108 if (r) { 2109 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 2110 return r; 2111 } 2112 2113 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP2_INDEX); 2114 if (r) { 2115 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 2116 return r; 2117 } 2118 2119 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX); 2120 if (r) { 2121 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r); 2122 return r; 2123 } 2124 2125 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_DMA1_INDEX); 2126 if (r) { 2127 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r); 2128 return r; 2129 } 2130 2131 /* Enable IRQ */ 2132 if (!rdev->irq.installed) { 2133 r = radeon_irq_kms_init(rdev); 2134 if (r) 2135 return r; 2136 } 2137 2138 r = r600_irq_init(rdev); 2139 if (r) { 2140 DRM_ERROR("radeon: IH init failed (%d).\n", r); 2141 radeon_irq_kms_fini(rdev); 2142 return r; 2143 } 2144 evergreen_irq_set(rdev); 2145 2146 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, 2147 RADEON_CP_PACKET2); 2148 if (r) 2149 return r; 2150 2151 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; 2152 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET, 2153 DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0)); 2154 if (r) 2155 return r; 2156 2157 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]; 2158 r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET, 2159 DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0)); 2160 if (r) 2161 return r; 2162 2163 r = cayman_cp_load_microcode(rdev); 2164 if (r) 2165 return r; 2166 r = cayman_cp_resume(rdev); 2167 if (r) 2168 return r; 2169 2170 r = cayman_dma_resume(rdev); 2171 if (r) 2172 return r; 2173 2174 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; 2175 if (ring->ring_size) { 2176 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, 2177 RADEON_CP_PACKET2); 2178 if (!r) 2179 r = uvd_v1_0_init(rdev); 2180 if (r) 2181 DRM_ERROR("radeon: failed initializing UVD (%d).\n", r); 2182 } 2183 2184 if (rdev->family == CHIP_ARUBA) { 2185 ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX]; 2186 if (ring->ring_size) 2187 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, 0x0); 2188 2189 ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX]; 2190 if (ring->ring_size) 2191 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, 0x0); 2192 2193 if (!r) 2194 r = vce_v1_0_init(rdev); 2195 if (r) 2196 DRM_ERROR("radeon: failed initializing VCE (%d).\n", r); 2197 } 2198 2199 r = radeon_ib_pool_init(rdev); 2200 if (r) { 2201 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 2202 return r; 2203 } 2204 2205 r = radeon_vm_manager_init(rdev); 2206 if (r) { 2207 dev_err(rdev->dev, "vm manager initialization failed (%d).\n", r); 2208 return r; 2209 } 2210 2211 r = radeon_audio_init(rdev); 2212 if (r) 2213 return r; 2214 2215 return 0; 2216 } 2217 2218 int cayman_resume(struct radeon_device *rdev) 2219 { 2220 int r; 2221 2222 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw, 2223 * posting will perform necessary task to bring back GPU into good 2224 * shape. 2225 */ 2226 /* post card */ 2227 atom_asic_init(rdev->mode_info.atom_context); 2228 2229 /* init golden registers */ 2230 ni_init_golden_registers(rdev); 2231 2232 if (rdev->pm.pm_method == PM_METHOD_DPM) 2233 radeon_pm_resume(rdev); 2234 2235 rdev->accel_working = true; 2236 r = cayman_startup(rdev); 2237 if (r) { 2238 DRM_ERROR("cayman startup failed on resume\n"); 2239 rdev->accel_working = false; 2240 return r; 2241 } 2242 return r; 2243 } 2244 2245 int cayman_suspend(struct radeon_device *rdev) 2246 { 2247 radeon_pm_suspend(rdev); 2248 radeon_audio_fini(rdev); 2249 radeon_vm_manager_fini(rdev); 2250 cayman_cp_enable(rdev, false); 2251 cayman_dma_stop(rdev); 2252 uvd_v1_0_fini(rdev); 2253 radeon_uvd_suspend(rdev); 2254 evergreen_irq_suspend(rdev); 2255 radeon_wb_disable(rdev); 2256 cayman_pcie_gart_disable(rdev); 2257 return 0; 2258 } 2259 2260 /* Plan is to move initialization in that function and use 2261 * helper function so that radeon_device_init pretty much 2262 * do nothing more than calling asic specific function. This 2263 * should also allow to remove a bunch of callback function 2264 * like vram_info. 2265 */ 2266 int cayman_init(struct radeon_device *rdev) 2267 { 2268 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2269 int r; 2270 2271 /* Read BIOS */ 2272 if (!radeon_get_bios(rdev)) { 2273 if (ASIC_IS_AVIVO(rdev)) 2274 return -EINVAL; 2275 } 2276 /* Must be an ATOMBIOS */ 2277 if (!rdev->is_atom_bios) { 2278 dev_err(rdev->dev, "Expecting atombios for cayman GPU\n"); 2279 return -EINVAL; 2280 } 2281 r = radeon_atombios_init(rdev); 2282 if (r) 2283 return r; 2284 2285 /* Post card if necessary */ 2286 if (!radeon_card_posted(rdev)) { 2287 if (!rdev->bios) { 2288 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); 2289 return -EINVAL; 2290 } 2291 DRM_INFO("GPU not posted. posting now...\n"); 2292 atom_asic_init(rdev->mode_info.atom_context); 2293 } 2294 /* init golden registers */ 2295 ni_init_golden_registers(rdev); 2296 /* Initialize scratch registers */ 2297 r600_scratch_init(rdev); 2298 /* Initialize surface registers */ 2299 radeon_surface_init(rdev); 2300 /* Initialize clocks */ 2301 radeon_get_clock_info(rdev->ddev); 2302 /* Fence driver */ 2303 r = radeon_fence_driver_init(rdev); 2304 if (r) 2305 return r; 2306 /* initialize memory controller */ 2307 r = evergreen_mc_init(rdev); 2308 if (r) 2309 return r; 2310 /* Memory manager */ 2311 r = radeon_bo_init(rdev); 2312 if (r) 2313 return r; 2314 2315 if (rdev->flags & RADEON_IS_IGP) { 2316 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { 2317 r = ni_init_microcode(rdev); 2318 if (r) { 2319 DRM_ERROR("Failed to load firmware!\n"); 2320 return r; 2321 } 2322 } 2323 } else { 2324 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) { 2325 r = ni_init_microcode(rdev); 2326 if (r) { 2327 DRM_ERROR("Failed to load firmware!\n"); 2328 return r; 2329 } 2330 } 2331 } 2332 2333 /* Initialize power management */ 2334 radeon_pm_init(rdev); 2335 2336 ring->ring_obj = NULL; 2337 r600_ring_init(rdev, ring, 1024 * 1024); 2338 2339 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; 2340 ring->ring_obj = NULL; 2341 r600_ring_init(rdev, ring, 64 * 1024); 2342 2343 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]; 2344 ring->ring_obj = NULL; 2345 r600_ring_init(rdev, ring, 64 * 1024); 2346 2347 r = radeon_uvd_init(rdev); 2348 if (!r) { 2349 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; 2350 ring->ring_obj = NULL; 2351 r600_ring_init(rdev, ring, 4096); 2352 } 2353 2354 if (rdev->family == CHIP_ARUBA) { 2355 r = radeon_vce_init(rdev); 2356 if (!r) { 2357 ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX]; 2358 ring->ring_obj = NULL; 2359 r600_ring_init(rdev, ring, 4096); 2360 2361 ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX]; 2362 ring->ring_obj = NULL; 2363 r600_ring_init(rdev, ring, 4096); 2364 } 2365 } 2366 2367 rdev->ih.ring_obj = NULL; 2368 r600_ih_ring_init(rdev, 64 * 1024); 2369 2370 r = r600_pcie_gart_init(rdev); 2371 if (r) 2372 return r; 2373 2374 rdev->accel_working = true; 2375 r = cayman_startup(rdev); 2376 if (r) { 2377 dev_err(rdev->dev, "disabling GPU acceleration\n"); 2378 cayman_cp_fini(rdev); 2379 cayman_dma_fini(rdev); 2380 r600_irq_fini(rdev); 2381 if (rdev->flags & RADEON_IS_IGP) 2382 sumo_rlc_fini(rdev); 2383 radeon_wb_fini(rdev); 2384 radeon_ib_pool_fini(rdev); 2385 radeon_vm_manager_fini(rdev); 2386 radeon_irq_kms_fini(rdev); 2387 cayman_pcie_gart_fini(rdev); 2388 rdev->accel_working = false; 2389 } 2390 2391 /* Don't start up if the MC ucode is missing. 2392 * The default clocks and voltages before the MC ucode 2393 * is loaded are not suffient for advanced operations. 2394 * 2395 * We can skip this check for TN, because there is no MC 2396 * ucode. 2397 */ 2398 if (!rdev->mc_fw && !(rdev->flags & RADEON_IS_IGP)) { 2399 DRM_ERROR("radeon: MC ucode required for NI+.\n"); 2400 return -EINVAL; 2401 } 2402 2403 return 0; 2404 } 2405 2406 void cayman_fini(struct radeon_device *rdev) 2407 { 2408 radeon_pm_fini(rdev); 2409 cayman_cp_fini(rdev); 2410 cayman_dma_fini(rdev); 2411 r600_irq_fini(rdev); 2412 if (rdev->flags & RADEON_IS_IGP) 2413 sumo_rlc_fini(rdev); 2414 radeon_wb_fini(rdev); 2415 radeon_vm_manager_fini(rdev); 2416 radeon_ib_pool_fini(rdev); 2417 radeon_irq_kms_fini(rdev); 2418 uvd_v1_0_fini(rdev); 2419 radeon_uvd_fini(rdev); 2420 if (rdev->family == CHIP_ARUBA) 2421 radeon_vce_fini(rdev); 2422 cayman_pcie_gart_fini(rdev); 2423 r600_vram_scratch_fini(rdev); 2424 radeon_gem_fini(rdev); 2425 radeon_fence_driver_fini(rdev); 2426 radeon_bo_fini(rdev); 2427 radeon_atombios_fini(rdev); 2428 kfree(rdev->bios); 2429 rdev->bios = NULL; 2430 } 2431 2432 /* 2433 * vm 2434 */ 2435 int cayman_vm_init(struct radeon_device *rdev) 2436 { 2437 /* number of VMs */ 2438 rdev->vm_manager.nvm = 8; 2439 /* base offset of vram pages */ 2440 if (rdev->flags & RADEON_IS_IGP) { 2441 u64 tmp = RREG32(FUS_MC_VM_FB_OFFSET); 2442 tmp <<= 22; 2443 rdev->vm_manager.vram_base_offset = tmp; 2444 } else 2445 rdev->vm_manager.vram_base_offset = 0; 2446 return 0; 2447 } 2448 2449 void cayman_vm_fini(struct radeon_device *rdev) 2450 { 2451 } 2452 2453 /** 2454 * cayman_vm_decode_fault - print human readable fault info 2455 * 2456 * @rdev: radeon_device pointer 2457 * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value 2458 * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value 2459 * 2460 * Print human readable fault information (cayman/TN). 2461 */ 2462 void cayman_vm_decode_fault(struct radeon_device *rdev, 2463 u32 status, u32 addr) 2464 { 2465 u32 mc_id = (status & MEMORY_CLIENT_ID_MASK) >> MEMORY_CLIENT_ID_SHIFT; 2466 u32 vmid = (status & FAULT_VMID_MASK) >> FAULT_VMID_SHIFT; 2467 u32 protections = (status & PROTECTIONS_MASK) >> PROTECTIONS_SHIFT; 2468 const char *block; 2469 2470 switch (mc_id) { 2471 case 32: 2472 case 16: 2473 case 96: 2474 case 80: 2475 case 160: 2476 case 144: 2477 case 224: 2478 case 208: 2479 block = "CB"; 2480 break; 2481 case 33: 2482 case 17: 2483 case 97: 2484 case 81: 2485 case 161: 2486 case 145: 2487 case 225: 2488 case 209: 2489 block = "CB_FMASK"; 2490 break; 2491 case 34: 2492 case 18: 2493 case 98: 2494 case 82: 2495 case 162: 2496 case 146: 2497 case 226: 2498 case 210: 2499 block = "CB_CMASK"; 2500 break; 2501 case 35: 2502 case 19: 2503 case 99: 2504 case 83: 2505 case 163: 2506 case 147: 2507 case 227: 2508 case 211: 2509 block = "CB_IMMED"; 2510 break; 2511 case 36: 2512 case 20: 2513 case 100: 2514 case 84: 2515 case 164: 2516 case 148: 2517 case 228: 2518 case 212: 2519 block = "DB"; 2520 break; 2521 case 37: 2522 case 21: 2523 case 101: 2524 case 85: 2525 case 165: 2526 case 149: 2527 case 229: 2528 case 213: 2529 block = "DB_HTILE"; 2530 break; 2531 case 38: 2532 case 22: 2533 case 102: 2534 case 86: 2535 case 166: 2536 case 150: 2537 case 230: 2538 case 214: 2539 block = "SX"; 2540 break; 2541 case 39: 2542 case 23: 2543 case 103: 2544 case 87: 2545 case 167: 2546 case 151: 2547 case 231: 2548 case 215: 2549 block = "DB_STEN"; 2550 break; 2551 case 40: 2552 case 24: 2553 case 104: 2554 case 88: 2555 case 232: 2556 case 216: 2557 case 168: 2558 case 152: 2559 block = "TC_TFETCH"; 2560 break; 2561 case 41: 2562 case 25: 2563 case 105: 2564 case 89: 2565 case 233: 2566 case 217: 2567 case 169: 2568 case 153: 2569 block = "TC_VFETCH"; 2570 break; 2571 case 42: 2572 case 26: 2573 case 106: 2574 case 90: 2575 case 234: 2576 case 218: 2577 case 170: 2578 case 154: 2579 block = "VC"; 2580 break; 2581 case 112: 2582 block = "CP"; 2583 break; 2584 case 113: 2585 case 114: 2586 block = "SH"; 2587 break; 2588 case 115: 2589 block = "VGT"; 2590 break; 2591 case 178: 2592 block = "IH"; 2593 break; 2594 case 51: 2595 block = "RLC"; 2596 break; 2597 case 55: 2598 block = "DMA"; 2599 break; 2600 case 56: 2601 block = "HDP"; 2602 break; 2603 default: 2604 block = "unknown"; 2605 break; 2606 } 2607 2608 printk("VM fault (0x%02x, vmid %d) at page %u, %s from %s (%d)\n", 2609 protections, vmid, addr, 2610 (status & MEMORY_CLIENT_RW_MASK) ? "write" : "read", 2611 block, mc_id); 2612 } 2613 2614 /** 2615 * cayman_vm_flush - vm flush using the CP 2616 * 2617 * @rdev: radeon_device pointer 2618 * 2619 * Update the page table base and flush the VM TLB 2620 * using the CP (cayman-si). 2621 */ 2622 void cayman_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring, 2623 unsigned vm_id, uint64_t pd_addr) 2624 { 2625 radeon_ring_write(ring, PACKET0(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm_id << 2), 0)); 2626 radeon_ring_write(ring, pd_addr >> 12); 2627 2628 /* flush hdp cache */ 2629 radeon_ring_write(ring, PACKET0(HDP_MEM_COHERENCY_FLUSH_CNTL, 0)); 2630 radeon_ring_write(ring, 0x1); 2631 2632 /* bits 0-7 are the VM contexts0-7 */ 2633 radeon_ring_write(ring, PACKET0(VM_INVALIDATE_REQUEST, 0)); 2634 radeon_ring_write(ring, 1 << vm_id); 2635 2636 /* wait for the invalidate to complete */ 2637 radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 2638 radeon_ring_write(ring, (WAIT_REG_MEM_FUNCTION(0) | /* always */ 2639 WAIT_REG_MEM_ENGINE(0))); /* me */ 2640 radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2); 2641 radeon_ring_write(ring, 0); 2642 radeon_ring_write(ring, 0); /* ref */ 2643 radeon_ring_write(ring, 0); /* mask */ 2644 radeon_ring_write(ring, 0x20); /* poll interval */ 2645 2646 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 2647 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 2648 radeon_ring_write(ring, 0x0); 2649 } 2650 2651 int tn_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk) 2652 { 2653 struct atom_clock_dividers dividers; 2654 int r, i; 2655 2656 r = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 2657 ecclk, false, ÷rs); 2658 if (r) 2659 return r; 2660 2661 for (i = 0; i < 100; i++) { 2662 if (RREG32(CG_ECLK_STATUS) & ECLK_STATUS) 2663 break; 2664 mdelay(10); 2665 } 2666 if (i == 100) 2667 return -ETIMEDOUT; 2668 2669 WREG32_P(CG_ECLK_CNTL, dividers.post_div, ~(ECLK_DIR_CNTL_EN|ECLK_DIVIDER_MASK)); 2670 2671 for (i = 0; i < 100; i++) { 2672 if (RREG32(CG_ECLK_STATUS) & ECLK_STATUS) 2673 break; 2674 mdelay(10); 2675 } 2676 if (i == 100) 2677 return -ETIMEDOUT; 2678 2679 return 0; 2680 } 2681
Indexes created Wed Oct 22 00:09:40 GMT 2025