radeon_ni_dpm.c revision 1.1.2.2
1 /* $NetBSD: radeon_ni_dpm.c,v 1.1.2.2 2018/09/06 06:56:32 pgoyette Exp $ */ 2 3 /* 4 * Copyright 2012 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 26 #include <sys/cdefs.h> 27 __KERNEL_RCSID(0, "$NetBSD: radeon_ni_dpm.c,v 1.1.2.2 2018/09/06 06:56:32 pgoyette Exp $"); 28 29 #include "drmP.h" 30 #include "radeon.h" 31 #include "radeon_asic.h" 32 #include "nid.h" 33 #include "r600_dpm.h" 34 #include "ni_dpm.h" 35 #include "atom.h" 36 #include <linux/math64.h> 37 #include <linux/seq_file.h> 38 39 #define MC_CG_ARB_FREQ_F0 0x0a 40 #define MC_CG_ARB_FREQ_F1 0x0b 41 #define MC_CG_ARB_FREQ_F2 0x0c 42 #define MC_CG_ARB_FREQ_F3 0x0d 43 44 #define SMC_RAM_END 0xC000 45 46 static const struct ni_cac_weights cac_weights_cayman_xt = 47 { 48 0x15, 49 0x2, 50 0x19, 51 0x2, 52 0x8, 53 0x14, 54 0x2, 55 0x16, 56 0xE, 57 0x17, 58 0x13, 59 0x2B, 60 0x10, 61 0x7, 62 0x5, 63 0x5, 64 0x5, 65 0x2, 66 0x3, 67 0x9, 68 0x10, 69 0x10, 70 0x2B, 71 0xA, 72 0x9, 73 0x4, 74 0xD, 75 0xD, 76 0x3E, 77 0x18, 78 0x14, 79 0, 80 0x3, 81 0x3, 82 0x5, 83 0, 84 0x2, 85 0, 86 0, 87 0, 88 0, 89 0, 90 0, 91 0, 92 0, 93 0, 94 0x1CC, 95 0, 96 0x164, 97 1, 98 1, 99 1, 100 1, 101 12, 102 12, 103 12, 104 0x12, 105 0x1F, 106 132, 107 5, 108 7, 109 0, 110 { 0, 0, 0, 0, 0, 0, 0, 0 }, 111 { 0, 0, 0, 0 }, 112 true 113 }; 114 115 static const struct ni_cac_weights cac_weights_cayman_pro = 116 { 117 0x16, 118 0x4, 119 0x10, 120 0x2, 121 0xA, 122 0x16, 123 0x2, 124 0x18, 125 0x10, 126 0x1A, 127 0x16, 128 0x2D, 129 0x12, 130 0xA, 131 0x6, 132 0x6, 133 0x6, 134 0x2, 135 0x4, 136 0xB, 137 0x11, 138 0x11, 139 0x2D, 140 0xC, 141 0xC, 142 0x7, 143 0x10, 144 0x10, 145 0x3F, 146 0x1A, 147 0x16, 148 0, 149 0x7, 150 0x4, 151 0x6, 152 1, 153 0x2, 154 0x1, 155 0, 156 0, 157 0, 158 0, 159 0, 160 0, 161 0x30, 162 0, 163 0x1CF, 164 0, 165 0x166, 166 1, 167 1, 168 1, 169 1, 170 12, 171 12, 172 12, 173 0x15, 174 0x1F, 175 132, 176 6, 177 6, 178 0, 179 { 0, 0, 0, 0, 0, 0, 0, 0 }, 180 { 0, 0, 0, 0 }, 181 true 182 }; 183 184 static const struct ni_cac_weights cac_weights_cayman_le = 185 { 186 0x7, 187 0xE, 188 0x1, 189 0xA, 190 0x1, 191 0x3F, 192 0x2, 193 0x18, 194 0x10, 195 0x1A, 196 0x1, 197 0x3F, 198 0x1, 199 0xE, 200 0x6, 201 0x6, 202 0x6, 203 0x2, 204 0x4, 205 0x9, 206 0x1A, 207 0x1A, 208 0x2C, 209 0xA, 210 0x11, 211 0x8, 212 0x19, 213 0x19, 214 0x1, 215 0x1, 216 0x1A, 217 0, 218 0x8, 219 0x5, 220 0x8, 221 0x1, 222 0x3, 223 0x1, 224 0, 225 0, 226 0, 227 0, 228 0, 229 0, 230 0x38, 231 0x38, 232 0x239, 233 0x3, 234 0x18A, 235 1, 236 1, 237 1, 238 1, 239 12, 240 12, 241 12, 242 0x15, 243 0x22, 244 132, 245 6, 246 6, 247 0, 248 { 0, 0, 0, 0, 0, 0, 0, 0 }, 249 { 0, 0, 0, 0 }, 250 true 251 }; 252 253 #define NISLANDS_MGCG_SEQUENCE 300 254 255 static const u32 cayman_cgcg_cgls_default[] = 256 { 257 0x000008f8, 0x00000010, 0xffffffff, 258 0x000008fc, 0x00000000, 0xffffffff, 259 0x000008f8, 0x00000011, 0xffffffff, 260 0x000008fc, 0x00000000, 0xffffffff, 261 0x000008f8, 0x00000012, 0xffffffff, 262 0x000008fc, 0x00000000, 0xffffffff, 263 0x000008f8, 0x00000013, 0xffffffff, 264 0x000008fc, 0x00000000, 0xffffffff, 265 0x000008f8, 0x00000014, 0xffffffff, 266 0x000008fc, 0x00000000, 0xffffffff, 267 0x000008f8, 0x00000015, 0xffffffff, 268 0x000008fc, 0x00000000, 0xffffffff, 269 0x000008f8, 0x00000016, 0xffffffff, 270 0x000008fc, 0x00000000, 0xffffffff, 271 0x000008f8, 0x00000017, 0xffffffff, 272 0x000008fc, 0x00000000, 0xffffffff, 273 0x000008f8, 0x00000018, 0xffffffff, 274 0x000008fc, 0x00000000, 0xffffffff, 275 0x000008f8, 0x00000019, 0xffffffff, 276 0x000008fc, 0x00000000, 0xffffffff, 277 0x000008f8, 0x0000001a, 0xffffffff, 278 0x000008fc, 0x00000000, 0xffffffff, 279 0x000008f8, 0x0000001b, 0xffffffff, 280 0x000008fc, 0x00000000, 0xffffffff, 281 0x000008f8, 0x00000020, 0xffffffff, 282 0x000008fc, 0x00000000, 0xffffffff, 283 0x000008f8, 0x00000021, 0xffffffff, 284 0x000008fc, 0x00000000, 0xffffffff, 285 0x000008f8, 0x00000022, 0xffffffff, 286 0x000008fc, 0x00000000, 0xffffffff, 287 0x000008f8, 0x00000023, 0xffffffff, 288 0x000008fc, 0x00000000, 0xffffffff, 289 0x000008f8, 0x00000024, 0xffffffff, 290 0x000008fc, 0x00000000, 0xffffffff, 291 0x000008f8, 0x00000025, 0xffffffff, 292 0x000008fc, 0x00000000, 0xffffffff, 293 0x000008f8, 0x00000026, 0xffffffff, 294 0x000008fc, 0x00000000, 0xffffffff, 295 0x000008f8, 0x00000027, 0xffffffff, 296 0x000008fc, 0x00000000, 0xffffffff, 297 0x000008f8, 0x00000028, 0xffffffff, 298 0x000008fc, 0x00000000, 0xffffffff, 299 0x000008f8, 0x00000029, 0xffffffff, 300 0x000008fc, 0x00000000, 0xffffffff, 301 0x000008f8, 0x0000002a, 0xffffffff, 302 0x000008fc, 0x00000000, 0xffffffff, 303 0x000008f8, 0x0000002b, 0xffffffff, 304 0x000008fc, 0x00000000, 0xffffffff 305 }; 306 #define CAYMAN_CGCG_CGLS_DEFAULT_LENGTH sizeof(cayman_cgcg_cgls_default) / (3 * sizeof(u32)) 307 308 static const u32 cayman_cgcg_cgls_disable[] = 309 { 310 0x000008f8, 0x00000010, 0xffffffff, 311 0x000008fc, 0xffffffff, 0xffffffff, 312 0x000008f8, 0x00000011, 0xffffffff, 313 0x000008fc, 0xffffffff, 0xffffffff, 314 0x000008f8, 0x00000012, 0xffffffff, 315 0x000008fc, 0xffffffff, 0xffffffff, 316 0x000008f8, 0x00000013, 0xffffffff, 317 0x000008fc, 0xffffffff, 0xffffffff, 318 0x000008f8, 0x00000014, 0xffffffff, 319 0x000008fc, 0xffffffff, 0xffffffff, 320 0x000008f8, 0x00000015, 0xffffffff, 321 0x000008fc, 0xffffffff, 0xffffffff, 322 0x000008f8, 0x00000016, 0xffffffff, 323 0x000008fc, 0xffffffff, 0xffffffff, 324 0x000008f8, 0x00000017, 0xffffffff, 325 0x000008fc, 0xffffffff, 0xffffffff, 326 0x000008f8, 0x00000018, 0xffffffff, 327 0x000008fc, 0xffffffff, 0xffffffff, 328 0x000008f8, 0x00000019, 0xffffffff, 329 0x000008fc, 0xffffffff, 0xffffffff, 330 0x000008f8, 0x0000001a, 0xffffffff, 331 0x000008fc, 0xffffffff, 0xffffffff, 332 0x000008f8, 0x0000001b, 0xffffffff, 333 0x000008fc, 0xffffffff, 0xffffffff, 334 0x000008f8, 0x00000020, 0xffffffff, 335 0x000008fc, 0x00000000, 0xffffffff, 336 0x000008f8, 0x00000021, 0xffffffff, 337 0x000008fc, 0x00000000, 0xffffffff, 338 0x000008f8, 0x00000022, 0xffffffff, 339 0x000008fc, 0x00000000, 0xffffffff, 340 0x000008f8, 0x00000023, 0xffffffff, 341 0x000008fc, 0x00000000, 0xffffffff, 342 0x000008f8, 0x00000024, 0xffffffff, 343 0x000008fc, 0x00000000, 0xffffffff, 344 0x000008f8, 0x00000025, 0xffffffff, 345 0x000008fc, 0x00000000, 0xffffffff, 346 0x000008f8, 0x00000026, 0xffffffff, 347 0x000008fc, 0x00000000, 0xffffffff, 348 0x000008f8, 0x00000027, 0xffffffff, 349 0x000008fc, 0x00000000, 0xffffffff, 350 0x000008f8, 0x00000028, 0xffffffff, 351 0x000008fc, 0x00000000, 0xffffffff, 352 0x000008f8, 0x00000029, 0xffffffff, 353 0x000008fc, 0x00000000, 0xffffffff, 354 0x000008f8, 0x0000002a, 0xffffffff, 355 0x000008fc, 0x00000000, 0xffffffff, 356 0x000008f8, 0x0000002b, 0xffffffff, 357 0x000008fc, 0x00000000, 0xffffffff, 358 0x00000644, 0x000f7902, 0x001f4180, 359 0x00000644, 0x000f3802, 0x001f4180 360 }; 361 #define CAYMAN_CGCG_CGLS_DISABLE_LENGTH sizeof(cayman_cgcg_cgls_disable) / (3 * sizeof(u32)) 362 363 static const u32 cayman_cgcg_cgls_enable[] = 364 { 365 0x00000644, 0x000f7882, 0x001f4080, 366 0x000008f8, 0x00000010, 0xffffffff, 367 0x000008fc, 0x00000000, 0xffffffff, 368 0x000008f8, 0x00000011, 0xffffffff, 369 0x000008fc, 0x00000000, 0xffffffff, 370 0x000008f8, 0x00000012, 0xffffffff, 371 0x000008fc, 0x00000000, 0xffffffff, 372 0x000008f8, 0x00000013, 0xffffffff, 373 0x000008fc, 0x00000000, 0xffffffff, 374 0x000008f8, 0x00000014, 0xffffffff, 375 0x000008fc, 0x00000000, 0xffffffff, 376 0x000008f8, 0x00000015, 0xffffffff, 377 0x000008fc, 0x00000000, 0xffffffff, 378 0x000008f8, 0x00000016, 0xffffffff, 379 0x000008fc, 0x00000000, 0xffffffff, 380 0x000008f8, 0x00000017, 0xffffffff, 381 0x000008fc, 0x00000000, 0xffffffff, 382 0x000008f8, 0x00000018, 0xffffffff, 383 0x000008fc, 0x00000000, 0xffffffff, 384 0x000008f8, 0x00000019, 0xffffffff, 385 0x000008fc, 0x00000000, 0xffffffff, 386 0x000008f8, 0x0000001a, 0xffffffff, 387 0x000008fc, 0x00000000, 0xffffffff, 388 0x000008f8, 0x0000001b, 0xffffffff, 389 0x000008fc, 0x00000000, 0xffffffff, 390 0x000008f8, 0x00000020, 0xffffffff, 391 0x000008fc, 0xffffffff, 0xffffffff, 392 0x000008f8, 0x00000021, 0xffffffff, 393 0x000008fc, 0xffffffff, 0xffffffff, 394 0x000008f8, 0x00000022, 0xffffffff, 395 0x000008fc, 0xffffffff, 0xffffffff, 396 0x000008f8, 0x00000023, 0xffffffff, 397 0x000008fc, 0xffffffff, 0xffffffff, 398 0x000008f8, 0x00000024, 0xffffffff, 399 0x000008fc, 0xffffffff, 0xffffffff, 400 0x000008f8, 0x00000025, 0xffffffff, 401 0x000008fc, 0xffffffff, 0xffffffff, 402 0x000008f8, 0x00000026, 0xffffffff, 403 0x000008fc, 0xffffffff, 0xffffffff, 404 0x000008f8, 0x00000027, 0xffffffff, 405 0x000008fc, 0xffffffff, 0xffffffff, 406 0x000008f8, 0x00000028, 0xffffffff, 407 0x000008fc, 0xffffffff, 0xffffffff, 408 0x000008f8, 0x00000029, 0xffffffff, 409 0x000008fc, 0xffffffff, 0xffffffff, 410 0x000008f8, 0x0000002a, 0xffffffff, 411 0x000008fc, 0xffffffff, 0xffffffff, 412 0x000008f8, 0x0000002b, 0xffffffff, 413 0x000008fc, 0xffffffff, 0xffffffff 414 }; 415 #define CAYMAN_CGCG_CGLS_ENABLE_LENGTH sizeof(cayman_cgcg_cgls_enable) / (3 * sizeof(u32)) 416 417 static const u32 cayman_mgcg_default[] = 418 { 419 0x0000802c, 0xc0000000, 0xffffffff, 420 0x00003fc4, 0xc0000000, 0xffffffff, 421 0x00005448, 0x00000100, 0xffffffff, 422 0x000055e4, 0x00000100, 0xffffffff, 423 0x0000160c, 0x00000100, 0xffffffff, 424 0x00008984, 0x06000100, 0xffffffff, 425 0x0000c164, 0x00000100, 0xffffffff, 426 0x00008a18, 0x00000100, 0xffffffff, 427 0x0000897c, 0x06000100, 0xffffffff, 428 0x00008b28, 0x00000100, 0xffffffff, 429 0x00009144, 0x00800200, 0xffffffff, 430 0x00009a60, 0x00000100, 0xffffffff, 431 0x00009868, 0x00000100, 0xffffffff, 432 0x00008d58, 0x00000100, 0xffffffff, 433 0x00009510, 0x00000100, 0xffffffff, 434 0x0000949c, 0x00000100, 0xffffffff, 435 0x00009654, 0x00000100, 0xffffffff, 436 0x00009030, 0x00000100, 0xffffffff, 437 0x00009034, 0x00000100, 0xffffffff, 438 0x00009038, 0x00000100, 0xffffffff, 439 0x0000903c, 0x00000100, 0xffffffff, 440 0x00009040, 0x00000100, 0xffffffff, 441 0x0000a200, 0x00000100, 0xffffffff, 442 0x0000a204, 0x00000100, 0xffffffff, 443 0x0000a208, 0x00000100, 0xffffffff, 444 0x0000a20c, 0x00000100, 0xffffffff, 445 0x00009744, 0x00000100, 0xffffffff, 446 0x00003f80, 0x00000100, 0xffffffff, 447 0x0000a210, 0x00000100, 0xffffffff, 448 0x0000a214, 0x00000100, 0xffffffff, 449 0x000004d8, 0x00000100, 0xffffffff, 450 0x00009664, 0x00000100, 0xffffffff, 451 0x00009698, 0x00000100, 0xffffffff, 452 0x000004d4, 0x00000200, 0xffffffff, 453 0x000004d0, 0x00000000, 0xffffffff, 454 0x000030cc, 0x00000104, 0xffffffff, 455 0x0000d0c0, 0x00000100, 0xffffffff, 456 0x0000d8c0, 0x00000100, 0xffffffff, 457 0x0000802c, 0x40000000, 0xffffffff, 458 0x00003fc4, 0x40000000, 0xffffffff, 459 0x0000915c, 0x00010000, 0xffffffff, 460 0x00009160, 0x00030002, 0xffffffff, 461 0x00009164, 0x00050004, 0xffffffff, 462 0x00009168, 0x00070006, 0xffffffff, 463 0x00009178, 0x00070000, 0xffffffff, 464 0x0000917c, 0x00030002, 0xffffffff, 465 0x00009180, 0x00050004, 0xffffffff, 466 0x0000918c, 0x00010006, 0xffffffff, 467 0x00009190, 0x00090008, 0xffffffff, 468 0x00009194, 0x00070000, 0xffffffff, 469 0x00009198, 0x00030002, 0xffffffff, 470 0x0000919c, 0x00050004, 0xffffffff, 471 0x000091a8, 0x00010006, 0xffffffff, 472 0x000091ac, 0x00090008, 0xffffffff, 473 0x000091b0, 0x00070000, 0xffffffff, 474 0x000091b4, 0x00030002, 0xffffffff, 475 0x000091b8, 0x00050004, 0xffffffff, 476 0x000091c4, 0x00010006, 0xffffffff, 477 0x000091c8, 0x00090008, 0xffffffff, 478 0x000091cc, 0x00070000, 0xffffffff, 479 0x000091d0, 0x00030002, 0xffffffff, 480 0x000091d4, 0x00050004, 0xffffffff, 481 0x000091e0, 0x00010006, 0xffffffff, 482 0x000091e4, 0x00090008, 0xffffffff, 483 0x000091e8, 0x00000000, 0xffffffff, 484 0x000091ec, 0x00070000, 0xffffffff, 485 0x000091f0, 0x00030002, 0xffffffff, 486 0x000091f4, 0x00050004, 0xffffffff, 487 0x00009200, 0x00010006, 0xffffffff, 488 0x00009204, 0x00090008, 0xffffffff, 489 0x00009208, 0x00070000, 0xffffffff, 490 0x0000920c, 0x00030002, 0xffffffff, 491 0x00009210, 0x00050004, 0xffffffff, 492 0x0000921c, 0x00010006, 0xffffffff, 493 0x00009220, 0x00090008, 0xffffffff, 494 0x00009224, 0x00070000, 0xffffffff, 495 0x00009228, 0x00030002, 0xffffffff, 496 0x0000922c, 0x00050004, 0xffffffff, 497 0x00009238, 0x00010006, 0xffffffff, 498 0x0000923c, 0x00090008, 0xffffffff, 499 0x00009240, 0x00070000, 0xffffffff, 500 0x00009244, 0x00030002, 0xffffffff, 501 0x00009248, 0x00050004, 0xffffffff, 502 0x00009254, 0x00010006, 0xffffffff, 503 0x00009258, 0x00090008, 0xffffffff, 504 0x0000925c, 0x00070000, 0xffffffff, 505 0x00009260, 0x00030002, 0xffffffff, 506 0x00009264, 0x00050004, 0xffffffff, 507 0x00009270, 0x00010006, 0xffffffff, 508 0x00009274, 0x00090008, 0xffffffff, 509 0x00009278, 0x00070000, 0xffffffff, 510 0x0000927c, 0x00030002, 0xffffffff, 511 0x00009280, 0x00050004, 0xffffffff, 512 0x0000928c, 0x00010006, 0xffffffff, 513 0x00009290, 0x00090008, 0xffffffff, 514 0x000092a8, 0x00070000, 0xffffffff, 515 0x000092ac, 0x00030002, 0xffffffff, 516 0x000092b0, 0x00050004, 0xffffffff, 517 0x000092bc, 0x00010006, 0xffffffff, 518 0x000092c0, 0x00090008, 0xffffffff, 519 0x000092c4, 0x00070000, 0xffffffff, 520 0x000092c8, 0x00030002, 0xffffffff, 521 0x000092cc, 0x00050004, 0xffffffff, 522 0x000092d8, 0x00010006, 0xffffffff, 523 0x000092dc, 0x00090008, 0xffffffff, 524 0x00009294, 0x00000000, 0xffffffff, 525 0x0000802c, 0x40010000, 0xffffffff, 526 0x00003fc4, 0x40010000, 0xffffffff, 527 0x0000915c, 0x00010000, 0xffffffff, 528 0x00009160, 0x00030002, 0xffffffff, 529 0x00009164, 0x00050004, 0xffffffff, 530 0x00009168, 0x00070006, 0xffffffff, 531 0x00009178, 0x00070000, 0xffffffff, 532 0x0000917c, 0x00030002, 0xffffffff, 533 0x00009180, 0x00050004, 0xffffffff, 534 0x0000918c, 0x00010006, 0xffffffff, 535 0x00009190, 0x00090008, 0xffffffff, 536 0x00009194, 0x00070000, 0xffffffff, 537 0x00009198, 0x00030002, 0xffffffff, 538 0x0000919c, 0x00050004, 0xffffffff, 539 0x000091a8, 0x00010006, 0xffffffff, 540 0x000091ac, 0x00090008, 0xffffffff, 541 0x000091b0, 0x00070000, 0xffffffff, 542 0x000091b4, 0x00030002, 0xffffffff, 543 0x000091b8, 0x00050004, 0xffffffff, 544 0x000091c4, 0x00010006, 0xffffffff, 545 0x000091c8, 0x00090008, 0xffffffff, 546 0x000091cc, 0x00070000, 0xffffffff, 547 0x000091d0, 0x00030002, 0xffffffff, 548 0x000091d4, 0x00050004, 0xffffffff, 549 0x000091e0, 0x00010006, 0xffffffff, 550 0x000091e4, 0x00090008, 0xffffffff, 551 0x000091e8, 0x00000000, 0xffffffff, 552 0x000091ec, 0x00070000, 0xffffffff, 553 0x000091f0, 0x00030002, 0xffffffff, 554 0x000091f4, 0x00050004, 0xffffffff, 555 0x00009200, 0x00010006, 0xffffffff, 556 0x00009204, 0x00090008, 0xffffffff, 557 0x00009208, 0x00070000, 0xffffffff, 558 0x0000920c, 0x00030002, 0xffffffff, 559 0x00009210, 0x00050004, 0xffffffff, 560 0x0000921c, 0x00010006, 0xffffffff, 561 0x00009220, 0x00090008, 0xffffffff, 562 0x00009224, 0x00070000, 0xffffffff, 563 0x00009228, 0x00030002, 0xffffffff, 564 0x0000922c, 0x00050004, 0xffffffff, 565 0x00009238, 0x00010006, 0xffffffff, 566 0x0000923c, 0x00090008, 0xffffffff, 567 0x00009240, 0x00070000, 0xffffffff, 568 0x00009244, 0x00030002, 0xffffffff, 569 0x00009248, 0x00050004, 0xffffffff, 570 0x00009254, 0x00010006, 0xffffffff, 571 0x00009258, 0x00090008, 0xffffffff, 572 0x0000925c, 0x00070000, 0xffffffff, 573 0x00009260, 0x00030002, 0xffffffff, 574 0x00009264, 0x00050004, 0xffffffff, 575 0x00009270, 0x00010006, 0xffffffff, 576 0x00009274, 0x00090008, 0xffffffff, 577 0x00009278, 0x00070000, 0xffffffff, 578 0x0000927c, 0x00030002, 0xffffffff, 579 0x00009280, 0x00050004, 0xffffffff, 580 0x0000928c, 0x00010006, 0xffffffff, 581 0x00009290, 0x00090008, 0xffffffff, 582 0x000092a8, 0x00070000, 0xffffffff, 583 0x000092ac, 0x00030002, 0xffffffff, 584 0x000092b0, 0x00050004, 0xffffffff, 585 0x000092bc, 0x00010006, 0xffffffff, 586 0x000092c0, 0x00090008, 0xffffffff, 587 0x000092c4, 0x00070000, 0xffffffff, 588 0x000092c8, 0x00030002, 0xffffffff, 589 0x000092cc, 0x00050004, 0xffffffff, 590 0x000092d8, 0x00010006, 0xffffffff, 591 0x000092dc, 0x00090008, 0xffffffff, 592 0x00009294, 0x00000000, 0xffffffff, 593 0x0000802c, 0xc0000000, 0xffffffff, 594 0x00003fc4, 0xc0000000, 0xffffffff, 595 0x000008f8, 0x00000010, 0xffffffff, 596 0x000008fc, 0x00000000, 0xffffffff, 597 0x000008f8, 0x00000011, 0xffffffff, 598 0x000008fc, 0x00000000, 0xffffffff, 599 0x000008f8, 0x00000012, 0xffffffff, 600 0x000008fc, 0x00000000, 0xffffffff, 601 0x000008f8, 0x00000013, 0xffffffff, 602 0x000008fc, 0x00000000, 0xffffffff, 603 0x000008f8, 0x00000014, 0xffffffff, 604 0x000008fc, 0x00000000, 0xffffffff, 605 0x000008f8, 0x00000015, 0xffffffff, 606 0x000008fc, 0x00000000, 0xffffffff, 607 0x000008f8, 0x00000016, 0xffffffff, 608 0x000008fc, 0x00000000, 0xffffffff, 609 0x000008f8, 0x00000017, 0xffffffff, 610 0x000008fc, 0x00000000, 0xffffffff, 611 0x000008f8, 0x00000018, 0xffffffff, 612 0x000008fc, 0x00000000, 0xffffffff, 613 0x000008f8, 0x00000019, 0xffffffff, 614 0x000008fc, 0x00000000, 0xffffffff, 615 0x000008f8, 0x0000001a, 0xffffffff, 616 0x000008fc, 0x00000000, 0xffffffff, 617 0x000008f8, 0x0000001b, 0xffffffff, 618 0x000008fc, 0x00000000, 0xffffffff 619 }; 620 #define CAYMAN_MGCG_DEFAULT_LENGTH sizeof(cayman_mgcg_default) / (3 * sizeof(u32)) 621 622 static const u32 cayman_mgcg_disable[] = 623 { 624 0x0000802c, 0xc0000000, 0xffffffff, 625 0x000008f8, 0x00000000, 0xffffffff, 626 0x000008fc, 0xffffffff, 0xffffffff, 627 0x000008f8, 0x00000001, 0xffffffff, 628 0x000008fc, 0xffffffff, 0xffffffff, 629 0x000008f8, 0x00000002, 0xffffffff, 630 0x000008fc, 0xffffffff, 0xffffffff, 631 0x000008f8, 0x00000003, 0xffffffff, 632 0x000008fc, 0xffffffff, 0xffffffff, 633 0x00009150, 0x00600000, 0xffffffff 634 }; 635 #define CAYMAN_MGCG_DISABLE_LENGTH sizeof(cayman_mgcg_disable) / (3 * sizeof(u32)) 636 637 static const u32 cayman_mgcg_enable[] = 638 { 639 0x0000802c, 0xc0000000, 0xffffffff, 640 0x000008f8, 0x00000000, 0xffffffff, 641 0x000008fc, 0x00000000, 0xffffffff, 642 0x000008f8, 0x00000001, 0xffffffff, 643 0x000008fc, 0x00000000, 0xffffffff, 644 0x000008f8, 0x00000002, 0xffffffff, 645 0x000008fc, 0x00600000, 0xffffffff, 646 0x000008f8, 0x00000003, 0xffffffff, 647 0x000008fc, 0x00000000, 0xffffffff, 648 0x00009150, 0x96944200, 0xffffffff 649 }; 650 651 #define CAYMAN_MGCG_ENABLE_LENGTH sizeof(cayman_mgcg_enable) / (3 * sizeof(u32)) 652 653 #define NISLANDS_SYSLS_SEQUENCE 100 654 655 static const u32 cayman_sysls_default[] = 656 { 657 /* Register, Value, Mask bits */ 658 0x000055e8, 0x00000000, 0xffffffff, 659 0x0000d0bc, 0x00000000, 0xffffffff, 660 0x0000d8bc, 0x00000000, 0xffffffff, 661 0x000015c0, 0x000c1401, 0xffffffff, 662 0x0000264c, 0x000c0400, 0xffffffff, 663 0x00002648, 0x000c0400, 0xffffffff, 664 0x00002650, 0x000c0400, 0xffffffff, 665 0x000020b8, 0x000c0400, 0xffffffff, 666 0x000020bc, 0x000c0400, 0xffffffff, 667 0x000020c0, 0x000c0c80, 0xffffffff, 668 0x0000f4a0, 0x000000c0, 0xffffffff, 669 0x0000f4a4, 0x00680fff, 0xffffffff, 670 0x00002f50, 0x00000404, 0xffffffff, 671 0x000004c8, 0x00000001, 0xffffffff, 672 0x000064ec, 0x00000000, 0xffffffff, 673 0x00000c7c, 0x00000000, 0xffffffff, 674 0x00008dfc, 0x00000000, 0xffffffff 675 }; 676 #define CAYMAN_SYSLS_DEFAULT_LENGTH sizeof(cayman_sysls_default) / (3 * sizeof(u32)) 677 678 static const u32 cayman_sysls_disable[] = 679 { 680 /* Register, Value, Mask bits */ 681 0x0000d0c0, 0x00000000, 0xffffffff, 682 0x0000d8c0, 0x00000000, 0xffffffff, 683 0x000055e8, 0x00000000, 0xffffffff, 684 0x0000d0bc, 0x00000000, 0xffffffff, 685 0x0000d8bc, 0x00000000, 0xffffffff, 686 0x000015c0, 0x00041401, 0xffffffff, 687 0x0000264c, 0x00040400, 0xffffffff, 688 0x00002648, 0x00040400, 0xffffffff, 689 0x00002650, 0x00040400, 0xffffffff, 690 0x000020b8, 0x00040400, 0xffffffff, 691 0x000020bc, 0x00040400, 0xffffffff, 692 0x000020c0, 0x00040c80, 0xffffffff, 693 0x0000f4a0, 0x000000c0, 0xffffffff, 694 0x0000f4a4, 0x00680000, 0xffffffff, 695 0x00002f50, 0x00000404, 0xffffffff, 696 0x000004c8, 0x00000001, 0xffffffff, 697 0x000064ec, 0x00007ffd, 0xffffffff, 698 0x00000c7c, 0x0000ff00, 0xffffffff, 699 0x00008dfc, 0x0000007f, 0xffffffff 700 }; 701 #define CAYMAN_SYSLS_DISABLE_LENGTH sizeof(cayman_sysls_disable) / (3 * sizeof(u32)) 702 703 static const u32 cayman_sysls_enable[] = 704 { 705 /* Register, Value, Mask bits */ 706 0x000055e8, 0x00000001, 0xffffffff, 707 0x0000d0bc, 0x00000100, 0xffffffff, 708 0x0000d8bc, 0x00000100, 0xffffffff, 709 0x000015c0, 0x000c1401, 0xffffffff, 710 0x0000264c, 0x000c0400, 0xffffffff, 711 0x00002648, 0x000c0400, 0xffffffff, 712 0x00002650, 0x000c0400, 0xffffffff, 713 0x000020b8, 0x000c0400, 0xffffffff, 714 0x000020bc, 0x000c0400, 0xffffffff, 715 0x000020c0, 0x000c0c80, 0xffffffff, 716 0x0000f4a0, 0x000000c0, 0xffffffff, 717 0x0000f4a4, 0x00680fff, 0xffffffff, 718 0x00002f50, 0x00000903, 0xffffffff, 719 0x000004c8, 0x00000000, 0xffffffff, 720 0x000064ec, 0x00000000, 0xffffffff, 721 0x00000c7c, 0x00000000, 0xffffffff, 722 0x00008dfc, 0x00000000, 0xffffffff 723 }; 724 #define CAYMAN_SYSLS_ENABLE_LENGTH sizeof(cayman_sysls_enable) / (3 * sizeof(u32)) 725 726 struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev); 727 struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev); 728 729 extern int ni_mc_load_microcode(struct radeon_device *rdev); 730 731 struct ni_power_info *ni_get_pi(struct radeon_device *rdev) 732 { 733 struct ni_power_info *pi = rdev->pm.dpm.priv; 734 735 return pi; 736 } 737 738 struct ni_ps *ni_get_ps(struct radeon_ps *rps) 739 { 740 struct ni_ps *ps = rps->ps_priv; 741 742 return ps; 743 } 744 745 static void ni_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff, 746 u16 v, s32 t, 747 u32 ileakage, 748 u32 *leakage) 749 { 750 s64 kt, kv, leakage_w, i_leakage, vddc, temperature; 751 752 i_leakage = div64_s64(drm_int2fixp(ileakage), 1000); 753 vddc = div64_s64(drm_int2fixp(v), 1000); 754 temperature = div64_s64(drm_int2fixp(t), 1000); 755 756 kt = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->at), 1000), 757 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bt), 1000), temperature))); 758 kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 1000), 759 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 1000), vddc))); 760 761 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); 762 763 *leakage = drm_fixp2int(leakage_w * 1000); 764 } 765 766 static void ni_calculate_leakage_for_v_and_t(struct radeon_device *rdev, 767 const struct ni_leakage_coeffients *coeff, 768 u16 v, 769 s32 t, 770 u32 i_leakage, 771 u32 *leakage) 772 { 773 ni_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage); 774 } 775 776 bool ni_dpm_vblank_too_short(struct radeon_device *rdev) 777 { 778 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 779 u32 vblank_time = r600_dpm_get_vblank_time(rdev); 780 /* we never hit the non-gddr5 limit so disable it */ 781 u32 switch_limit = pi->mem_gddr5 ? 450 : 0; 782 783 if (vblank_time < switch_limit) 784 return true; 785 else 786 return false; 787 788 } 789 790 static void ni_apply_state_adjust_rules(struct radeon_device *rdev, 791 struct radeon_ps *rps) 792 { 793 struct ni_ps *ps = ni_get_ps(rps); 794 struct radeon_clock_and_voltage_limits *max_limits; 795 bool disable_mclk_switching; 796 u32 mclk; 797 u16 vddci; 798 int i; 799 800 if ((rdev->pm.dpm.new_active_crtc_count > 1) || 801 ni_dpm_vblank_too_short(rdev)) 802 disable_mclk_switching = true; 803 else 804 disable_mclk_switching = false; 805 806 if (rdev->pm.dpm.ac_power) 807 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 808 else 809 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; 810 811 if (rdev->pm.dpm.ac_power == false) { 812 for (i = 0; i < ps->performance_level_count; i++) { 813 if (ps->performance_levels[i].mclk > max_limits->mclk) 814 ps->performance_levels[i].mclk = max_limits->mclk; 815 if (ps->performance_levels[i].sclk > max_limits->sclk) 816 ps->performance_levels[i].sclk = max_limits->sclk; 817 if (ps->performance_levels[i].vddc > max_limits->vddc) 818 ps->performance_levels[i].vddc = max_limits->vddc; 819 if (ps->performance_levels[i].vddci > max_limits->vddci) 820 ps->performance_levels[i].vddci = max_limits->vddci; 821 } 822 } 823 824 /* XXX validate the min clocks required for display */ 825 826 /* adjust low state */ 827 if (disable_mclk_switching) { 828 ps->performance_levels[0].mclk = 829 ps->performance_levels[ps->performance_level_count - 1].mclk; 830 ps->performance_levels[0].vddci = 831 ps->performance_levels[ps->performance_level_count - 1].vddci; 832 } 833 834 btc_skip_blacklist_clocks(rdev, max_limits->sclk, max_limits->mclk, 835 &ps->performance_levels[0].sclk, 836 &ps->performance_levels[0].mclk); 837 838 for (i = 1; i < ps->performance_level_count; i++) { 839 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk) 840 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk; 841 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc) 842 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc; 843 } 844 845 /* adjust remaining states */ 846 if (disable_mclk_switching) { 847 mclk = ps->performance_levels[0].mclk; 848 vddci = ps->performance_levels[0].vddci; 849 for (i = 1; i < ps->performance_level_count; i++) { 850 if (mclk < ps->performance_levels[i].mclk) 851 mclk = ps->performance_levels[i].mclk; 852 if (vddci < ps->performance_levels[i].vddci) 853 vddci = ps->performance_levels[i].vddci; 854 } 855 for (i = 0; i < ps->performance_level_count; i++) { 856 ps->performance_levels[i].mclk = mclk; 857 ps->performance_levels[i].vddci = vddci; 858 } 859 } else { 860 for (i = 1; i < ps->performance_level_count; i++) { 861 if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk) 862 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk; 863 if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci) 864 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci; 865 } 866 } 867 868 for (i = 1; i < ps->performance_level_count; i++) 869 btc_skip_blacklist_clocks(rdev, max_limits->sclk, max_limits->mclk, 870 &ps->performance_levels[i].sclk, 871 &ps->performance_levels[i].mclk); 872 873 for (i = 0; i < ps->performance_level_count; i++) 874 btc_adjust_clock_combinations(rdev, max_limits, 875 &ps->performance_levels[i]); 876 877 for (i = 0; i < ps->performance_level_count; i++) { 878 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, 879 ps->performance_levels[i].sclk, 880 max_limits->vddc, &ps->performance_levels[i].vddc); 881 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 882 ps->performance_levels[i].mclk, 883 max_limits->vddci, &ps->performance_levels[i].vddci); 884 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 885 ps->performance_levels[i].mclk, 886 max_limits->vddc, &ps->performance_levels[i].vddc); 887 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk, 888 rdev->clock.current_dispclk, 889 max_limits->vddc, &ps->performance_levels[i].vddc); 890 } 891 892 for (i = 0; i < ps->performance_level_count; i++) { 893 btc_apply_voltage_delta_rules(rdev, 894 max_limits->vddc, max_limits->vddci, 895 &ps->performance_levels[i].vddc, 896 &ps->performance_levels[i].vddci); 897 } 898 899 ps->dc_compatible = true; 900 for (i = 0; i < ps->performance_level_count; i++) { 901 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) 902 ps->dc_compatible = false; 903 904 if (ps->performance_levels[i].vddc < rdev->pm.dpm.dyn_state.min_vddc_for_pcie_gen2) 905 ps->performance_levels[i].flags &= ~ATOM_PPLIB_R600_FLAGS_PCIEGEN2; 906 } 907 } 908 909 static void ni_cg_clockgating_default(struct radeon_device *rdev) 910 { 911 u32 count; 912 const u32 *ps = NULL; 913 914 ps = (const u32 *)&cayman_cgcg_cgls_default; 915 count = CAYMAN_CGCG_CGLS_DEFAULT_LENGTH; 916 917 btc_program_mgcg_hw_sequence(rdev, ps, count); 918 } 919 920 static void ni_gfx_clockgating_enable(struct radeon_device *rdev, 921 bool enable) 922 { 923 u32 count; 924 const u32 *ps = NULL; 925 926 if (enable) { 927 ps = (const u32 *)&cayman_cgcg_cgls_enable; 928 count = CAYMAN_CGCG_CGLS_ENABLE_LENGTH; 929 } else { 930 ps = (const u32 *)&cayman_cgcg_cgls_disable; 931 count = CAYMAN_CGCG_CGLS_DISABLE_LENGTH; 932 } 933 934 btc_program_mgcg_hw_sequence(rdev, ps, count); 935 } 936 937 static void ni_mg_clockgating_default(struct radeon_device *rdev) 938 { 939 u32 count; 940 const u32 *ps = NULL; 941 942 ps = (const u32 *)&cayman_mgcg_default; 943 count = CAYMAN_MGCG_DEFAULT_LENGTH; 944 945 btc_program_mgcg_hw_sequence(rdev, ps, count); 946 } 947 948 static void ni_mg_clockgating_enable(struct radeon_device *rdev, 949 bool enable) 950 { 951 u32 count; 952 const u32 *ps = NULL; 953 954 if (enable) { 955 ps = (const u32 *)&cayman_mgcg_enable; 956 count = CAYMAN_MGCG_ENABLE_LENGTH; 957 } else { 958 ps = (const u32 *)&cayman_mgcg_disable; 959 count = CAYMAN_MGCG_DISABLE_LENGTH; 960 } 961 962 btc_program_mgcg_hw_sequence(rdev, ps, count); 963 } 964 965 static void ni_ls_clockgating_default(struct radeon_device *rdev) 966 { 967 u32 count; 968 const u32 *ps = NULL; 969 970 ps = (const u32 *)&cayman_sysls_default; 971 count = CAYMAN_SYSLS_DEFAULT_LENGTH; 972 973 btc_program_mgcg_hw_sequence(rdev, ps, count); 974 } 975 976 static void ni_ls_clockgating_enable(struct radeon_device *rdev, 977 bool enable) 978 { 979 u32 count; 980 const u32 *ps = NULL; 981 982 if (enable) { 983 ps = (const u32 *)&cayman_sysls_enable; 984 count = CAYMAN_SYSLS_ENABLE_LENGTH; 985 } else { 986 ps = (const u32 *)&cayman_sysls_disable; 987 count = CAYMAN_SYSLS_DISABLE_LENGTH; 988 } 989 990 btc_program_mgcg_hw_sequence(rdev, ps, count); 991 992 } 993 994 static int ni_patch_single_dependency_table_based_on_leakage(struct radeon_device *rdev, 995 struct radeon_clock_voltage_dependency_table *table) 996 { 997 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 998 u32 i; 999 1000 if (table) { 1001 for (i = 0; i < table->count; i++) { 1002 if (0xff01 == table->entries[i].v) { 1003 if (pi->max_vddc == 0) 1004 return -EINVAL; 1005 table->entries[i].v = pi->max_vddc; 1006 } 1007 } 1008 } 1009 return 0; 1010 } 1011 1012 static int ni_patch_dependency_tables_based_on_leakage(struct radeon_device *rdev) 1013 { 1014 int ret = 0; 1015 1016 ret = ni_patch_single_dependency_table_based_on_leakage(rdev, 1017 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk); 1018 1019 ret = ni_patch_single_dependency_table_based_on_leakage(rdev, 1020 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk); 1021 return ret; 1022 } 1023 1024 static void ni_stop_dpm(struct radeon_device *rdev) 1025 { 1026 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN); 1027 } 1028 1029 #if 0 1030 static int ni_notify_hw_of_power_source(struct radeon_device *rdev, 1031 bool ac_power) 1032 { 1033 if (ac_power) 1034 return (rv770_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ? 1035 0 : -EINVAL; 1036 1037 return 0; 1038 } 1039 #endif 1040 1041 static PPSMC_Result ni_send_msg_to_smc_with_parameter(struct radeon_device *rdev, 1042 PPSMC_Msg msg, u32 parameter) 1043 { 1044 WREG32(SMC_SCRATCH0, parameter); 1045 return rv770_send_msg_to_smc(rdev, msg); 1046 } 1047 1048 static int ni_restrict_performance_levels_before_switch(struct radeon_device *rdev) 1049 { 1050 if (rv770_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK) 1051 return -EINVAL; 1052 1053 return (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ? 1054 0 : -EINVAL; 1055 } 1056 1057 int ni_dpm_force_performance_level(struct radeon_device *rdev, 1058 enum radeon_dpm_forced_level level) 1059 { 1060 if (level == RADEON_DPM_FORCED_LEVEL_HIGH) { 1061 if (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 0) != PPSMC_Result_OK) 1062 return -EINVAL; 1063 1064 if (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK) 1065 return -EINVAL; 1066 } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) { 1067 if (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) 1068 return -EINVAL; 1069 1070 if (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK) 1071 return -EINVAL; 1072 } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) { 1073 if (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) 1074 return -EINVAL; 1075 1076 if (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 0) != PPSMC_Result_OK) 1077 return -EINVAL; 1078 } 1079 1080 rdev->pm.dpm.forced_level = level; 1081 1082 return 0; 1083 } 1084 1085 static void ni_stop_smc(struct radeon_device *rdev) 1086 { 1087 u32 tmp; 1088 int i; 1089 1090 for (i = 0; i < rdev->usec_timeout; i++) { 1091 tmp = RREG32(LB_SYNC_RESET_SEL) & LB_SYNC_RESET_SEL_MASK; 1092 if (tmp != 1) 1093 break; 1094 udelay(1); 1095 } 1096 1097 udelay(100); 1098 1099 r7xx_stop_smc(rdev); 1100 } 1101 1102 static int ni_process_firmware_header(struct radeon_device *rdev) 1103 { 1104 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 1105 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 1106 struct ni_power_info *ni_pi = ni_get_pi(rdev); 1107 u32 tmp; 1108 int ret; 1109 1110 ret = rv770_read_smc_sram_dword(rdev, 1111 NISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 1112 NISLANDS_SMC_FIRMWARE_HEADER_stateTable, 1113 &tmp, pi->sram_end); 1114 1115 if (ret) 1116 return ret; 1117 1118 pi->state_table_start = (u16)tmp; 1119 1120 ret = rv770_read_smc_sram_dword(rdev, 1121 NISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 1122 NISLANDS_SMC_FIRMWARE_HEADER_softRegisters, 1123 &tmp, pi->sram_end); 1124 1125 if (ret) 1126 return ret; 1127 1128 pi->soft_regs_start = (u16)tmp; 1129 1130 ret = rv770_read_smc_sram_dword(rdev, 1131 NISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 1132 NISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable, 1133 &tmp, pi->sram_end); 1134 1135 if (ret) 1136 return ret; 1137 1138 eg_pi->mc_reg_table_start = (u16)tmp; 1139 1140 ret = rv770_read_smc_sram_dword(rdev, 1141 NISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 1142 NISLANDS_SMC_FIRMWARE_HEADER_fanTable, 1143 &tmp, pi->sram_end); 1144 1145 if (ret) 1146 return ret; 1147 1148 ni_pi->fan_table_start = (u16)tmp; 1149 1150 ret = rv770_read_smc_sram_dword(rdev, 1151 NISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 1152 NISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable, 1153 &tmp, pi->sram_end); 1154 1155 if (ret) 1156 return ret; 1157 1158 ni_pi->arb_table_start = (u16)tmp; 1159 1160 ret = rv770_read_smc_sram_dword(rdev, 1161 NISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 1162 NISLANDS_SMC_FIRMWARE_HEADER_cacTable, 1163 &tmp, pi->sram_end); 1164 1165 if (ret) 1166 return ret; 1167 1168 ni_pi->cac_table_start = (u16)tmp; 1169 1170 ret = rv770_read_smc_sram_dword(rdev, 1171 NISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 1172 NISLANDS_SMC_FIRMWARE_HEADER_spllTable, 1173 &tmp, pi->sram_end); 1174 1175 if (ret) 1176 return ret; 1177 1178 ni_pi->spll_table_start = (u16)tmp; 1179 1180 1181 return ret; 1182 } 1183 1184 static void ni_read_clock_registers(struct radeon_device *rdev) 1185 { 1186 struct ni_power_info *ni_pi = ni_get_pi(rdev); 1187 1188 ni_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL); 1189 ni_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2); 1190 ni_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3); 1191 ni_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4); 1192 ni_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM); 1193 ni_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2); 1194 ni_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL); 1195 ni_pi->clock_registers.mpll_ad_func_cntl_2 = RREG32(MPLL_AD_FUNC_CNTL_2); 1196 ni_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL); 1197 ni_pi->clock_registers.mpll_dq_func_cntl_2 = RREG32(MPLL_DQ_FUNC_CNTL_2); 1198 ni_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL); 1199 ni_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL); 1200 ni_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1); 1201 ni_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2); 1202 } 1203 1204 #if 0 1205 static int ni_enter_ulp_state(struct radeon_device *rdev) 1206 { 1207 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 1208 1209 if (pi->gfx_clock_gating) { 1210 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN); 1211 WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON); 1212 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON); 1213 RREG32(GB_ADDR_CONFIG); 1214 } 1215 1216 WREG32_P(SMC_MSG, HOST_SMC_MSG(PPSMC_MSG_SwitchToMinimumPower), 1217 ~HOST_SMC_MSG_MASK); 1218 1219 udelay(25000); 1220 1221 return 0; 1222 } 1223 #endif 1224 1225 static void ni_program_response_times(struct radeon_device *rdev) 1226 { 1227 u32 voltage_response_time, backbias_response_time, acpi_delay_time, vbi_time_out; 1228 u32 vddc_dly, bb_dly, acpi_dly, vbi_dly, mclk_switch_limit; 1229 u32 reference_clock; 1230 1231 rv770_write_smc_soft_register(rdev, NI_SMC_SOFT_REGISTER_mvdd_chg_time, 1); 1232 1233 voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time; 1234 backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time; 1235 1236 if (voltage_response_time == 0) 1237 voltage_response_time = 1000; 1238 1239 if (backbias_response_time == 0) 1240 backbias_response_time = 1000; 1241 1242 acpi_delay_time = 15000; 1243 vbi_time_out = 100000; 1244 1245 reference_clock = radeon_get_xclk(rdev); 1246 1247 vddc_dly = (voltage_response_time * reference_clock) / 1600; 1248 bb_dly = (backbias_response_time * reference_clock) / 1600; 1249 acpi_dly = (acpi_delay_time * reference_clock) / 1600; 1250 vbi_dly = (vbi_time_out * reference_clock) / 1600; 1251 1252 mclk_switch_limit = (460 * reference_clock) / 100; 1253 1254 rv770_write_smc_soft_register(rdev, NI_SMC_SOFT_REGISTER_delay_vreg, vddc_dly); 1255 rv770_write_smc_soft_register(rdev, NI_SMC_SOFT_REGISTER_delay_bbias, bb_dly); 1256 rv770_write_smc_soft_register(rdev, NI_SMC_SOFT_REGISTER_delay_acpi, acpi_dly); 1257 rv770_write_smc_soft_register(rdev, NI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly); 1258 rv770_write_smc_soft_register(rdev, NI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA); 1259 rv770_write_smc_soft_register(rdev, NI_SMC_SOFT_REGISTER_mclk_switch_lim, mclk_switch_limit); 1260 } 1261 1262 static void ni_populate_smc_voltage_table(struct radeon_device *rdev, 1263 struct atom_voltage_table *voltage_table, 1264 NISLANDS_SMC_STATETABLE *table) 1265 { 1266 unsigned int i; 1267 1268 for (i = 0; i < voltage_table->count; i++) { 1269 table->highSMIO[i] = 0; 1270 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low); 1271 } 1272 } 1273 1274 static void ni_populate_smc_voltage_tables(struct radeon_device *rdev, 1275 NISLANDS_SMC_STATETABLE *table) 1276 { 1277 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 1278 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 1279 unsigned char i; 1280 1281 if (eg_pi->vddc_voltage_table.count) { 1282 ni_populate_smc_voltage_table(rdev, &eg_pi->vddc_voltage_table, table); 1283 table->voltageMaskTable.highMask[NISLANDS_SMC_VOLTAGEMASK_VDDC] = 0; 1284 table->voltageMaskTable.lowMask[NISLANDS_SMC_VOLTAGEMASK_VDDC] = 1285 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low); 1286 1287 for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) { 1288 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) { 1289 table->maxVDDCIndexInPPTable = i; 1290 break; 1291 } 1292 } 1293 } 1294 1295 if (eg_pi->vddci_voltage_table.count) { 1296 ni_populate_smc_voltage_table(rdev, &eg_pi->vddci_voltage_table, table); 1297 1298 table->voltageMaskTable.highMask[NISLANDS_SMC_VOLTAGEMASK_VDDCI] = 0; 1299 table->voltageMaskTable.lowMask[NISLANDS_SMC_VOLTAGEMASK_VDDCI] = 1300 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low); 1301 } 1302 } 1303 1304 static int ni_populate_voltage_value(struct radeon_device *rdev, 1305 struct atom_voltage_table *table, 1306 u16 value, 1307 NISLANDS_SMC_VOLTAGE_VALUE *voltage) 1308 { 1309 unsigned int i; 1310 1311 for (i = 0; i < table->count; i++) { 1312 if (value <= table->entries[i].value) { 1313 voltage->index = (u8)i; 1314 voltage->value = cpu_to_be16(table->entries[i].value); 1315 break; 1316 } 1317 } 1318 1319 if (i >= table->count) 1320 return -EINVAL; 1321 1322 return 0; 1323 } 1324 1325 static void ni_populate_mvdd_value(struct radeon_device *rdev, 1326 u32 mclk, 1327 NISLANDS_SMC_VOLTAGE_VALUE *voltage) 1328 { 1329 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 1330 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 1331 1332 if (!pi->mvdd_control) { 1333 voltage->index = eg_pi->mvdd_high_index; 1334 voltage->value = cpu_to_be16(MVDD_HIGH_VALUE); 1335 return; 1336 } 1337 1338 if (mclk <= pi->mvdd_split_frequency) { 1339 voltage->index = eg_pi->mvdd_low_index; 1340 voltage->value = cpu_to_be16(MVDD_LOW_VALUE); 1341 } else { 1342 voltage->index = eg_pi->mvdd_high_index; 1343 voltage->value = cpu_to_be16(MVDD_HIGH_VALUE); 1344 } 1345 } 1346 1347 static int ni_get_std_voltage_value(struct radeon_device *rdev, 1348 NISLANDS_SMC_VOLTAGE_VALUE *voltage, 1349 u16 *std_voltage) 1350 { 1351 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries && 1352 ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)) 1353 *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc; 1354 else 1355 *std_voltage = be16_to_cpu(voltage->value); 1356 1357 return 0; 1358 } 1359 1360 static void ni_populate_std_voltage_value(struct radeon_device *rdev, 1361 u16 value, u8 index, 1362 NISLANDS_SMC_VOLTAGE_VALUE *voltage) 1363 { 1364 voltage->index = index; 1365 voltage->value = cpu_to_be16(value); 1366 } 1367 1368 static u32 ni_get_smc_power_scaling_factor(struct radeon_device *rdev) 1369 { 1370 u32 xclk_period; 1371 u32 xclk = radeon_get_xclk(rdev); 1372 u32 tmp = RREG32(CG_CAC_CTRL) & TID_CNT_MASK; 1373 1374 xclk_period = (1000000000UL / xclk); 1375 xclk_period /= 10000UL; 1376 1377 return tmp * xclk_period; 1378 } 1379 1380 static u32 ni_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor) 1381 { 1382 return (power_in_watts * scaling_factor) << 2; 1383 } 1384 1385 static u32 ni_calculate_power_boost_limit(struct radeon_device *rdev, 1386 struct radeon_ps *radeon_state, 1387 u32 near_tdp_limit) 1388 { 1389 struct ni_ps *state = ni_get_ps(radeon_state); 1390 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 1391 struct ni_power_info *ni_pi = ni_get_pi(rdev); 1392 u32 power_boost_limit = 0; 1393 int ret; 1394 1395 if (ni_pi->enable_power_containment && 1396 ni_pi->use_power_boost_limit) { 1397 NISLANDS_SMC_VOLTAGE_VALUE vddc; 1398 u16 std_vddc_med; 1399 u16 std_vddc_high; 1400 u64 tmp, n, d; 1401 1402 if (state->performance_level_count < 3) 1403 return 0; 1404 1405 ret = ni_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 1406 state->performance_levels[state->performance_level_count - 2].vddc, 1407 &vddc); 1408 if (ret) 1409 return 0; 1410 1411 ret = ni_get_std_voltage_value(rdev, &vddc, &std_vddc_med); 1412 if (ret) 1413 return 0; 1414 1415 ret = ni_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 1416 state->performance_levels[state->performance_level_count - 1].vddc, 1417 &vddc); 1418 if (ret) 1419 return 0; 1420 1421 ret = ni_get_std_voltage_value(rdev, &vddc, &std_vddc_high); 1422 if (ret) 1423 return 0; 1424 1425 n = ((u64)near_tdp_limit * ((u64)std_vddc_med * (u64)std_vddc_med) * 90); 1426 d = ((u64)std_vddc_high * (u64)std_vddc_high * 100); 1427 tmp = div64_u64(n, d); 1428 1429 if (tmp >> 32) 1430 return 0; 1431 power_boost_limit = (u32)tmp; 1432 } 1433 1434 return power_boost_limit; 1435 } 1436 1437 static int ni_calculate_adjusted_tdp_limits(struct radeon_device *rdev, 1438 bool adjust_polarity, 1439 u32 tdp_adjustment, 1440 u32 *tdp_limit, 1441 u32 *near_tdp_limit) 1442 { 1443 if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit) 1444 return -EINVAL; 1445 1446 if (adjust_polarity) { 1447 *tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; 1448 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit + (*tdp_limit - rdev->pm.dpm.tdp_limit); 1449 } else { 1450 *tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; 1451 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit - (rdev->pm.dpm.tdp_limit - *tdp_limit); 1452 } 1453 1454 return 0; 1455 } 1456 1457 static int ni_populate_smc_tdp_limits(struct radeon_device *rdev, 1458 struct radeon_ps *radeon_state) 1459 { 1460 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 1461 struct ni_power_info *ni_pi = ni_get_pi(rdev); 1462 1463 if (ni_pi->enable_power_containment) { 1464 NISLANDS_SMC_STATETABLE *smc_table = &ni_pi->smc_statetable; 1465 u32 scaling_factor = ni_get_smc_power_scaling_factor(rdev); 1466 u32 tdp_limit; 1467 u32 near_tdp_limit; 1468 u32 power_boost_limit; 1469 int ret; 1470 1471 if (scaling_factor == 0) 1472 return -EINVAL; 1473 1474 memset(smc_table, 0, sizeof(NISLANDS_SMC_STATETABLE)); 1475 1476 ret = ni_calculate_adjusted_tdp_limits(rdev, 1477 false, /* ??? */ 1478 rdev->pm.dpm.tdp_adjustment, 1479 &tdp_limit, 1480 &near_tdp_limit); 1481 if (ret) 1482 return ret; 1483 1484 power_boost_limit = ni_calculate_power_boost_limit(rdev, radeon_state, 1485 near_tdp_limit); 1486 1487 smc_table->dpm2Params.TDPLimit = 1488 cpu_to_be32(ni_scale_power_for_smc(tdp_limit, scaling_factor)); 1489 smc_table->dpm2Params.NearTDPLimit = 1490 cpu_to_be32(ni_scale_power_for_smc(near_tdp_limit, scaling_factor)); 1491 smc_table->dpm2Params.SafePowerLimit = 1492 cpu_to_be32(ni_scale_power_for_smc((near_tdp_limit * NISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, 1493 scaling_factor)); 1494 smc_table->dpm2Params.PowerBoostLimit = 1495 cpu_to_be32(ni_scale_power_for_smc(power_boost_limit, scaling_factor)); 1496 1497 ret = rv770_copy_bytes_to_smc(rdev, 1498 (u16)(pi->state_table_start + offsetof(NISLANDS_SMC_STATETABLE, dpm2Params) + 1499 offsetof(PP_NIslands_DPM2Parameters, TDPLimit)), 1500 (u8 *)(&smc_table->dpm2Params.TDPLimit), 1501 sizeof(u32) * 4, pi->sram_end); 1502 if (ret) 1503 return ret; 1504 } 1505 1506 return 0; 1507 } 1508 1509 int ni_copy_and_switch_arb_sets(struct radeon_device *rdev, 1510 u32 arb_freq_src, u32 arb_freq_dest) 1511 { 1512 u32 mc_arb_dram_timing; 1513 u32 mc_arb_dram_timing2; 1514 u32 burst_time; 1515 u32 mc_cg_config; 1516 1517 switch (arb_freq_src) { 1518 case MC_CG_ARB_FREQ_F0: 1519 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING); 1520 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); 1521 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE0_MASK) >> STATE0_SHIFT; 1522 break; 1523 case MC_CG_ARB_FREQ_F1: 1524 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_1); 1525 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_1); 1526 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE1_MASK) >> STATE1_SHIFT; 1527 break; 1528 case MC_CG_ARB_FREQ_F2: 1529 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_2); 1530 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_2); 1531 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE2_MASK) >> STATE2_SHIFT; 1532 break; 1533 case MC_CG_ARB_FREQ_F3: 1534 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_3); 1535 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_3); 1536 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE3_MASK) >> STATE3_SHIFT; 1537 break; 1538 default: 1539 return -EINVAL; 1540 } 1541 1542 switch (arb_freq_dest) { 1543 case MC_CG_ARB_FREQ_F0: 1544 WREG32(MC_ARB_DRAM_TIMING, mc_arb_dram_timing); 1545 WREG32(MC_ARB_DRAM_TIMING2, mc_arb_dram_timing2); 1546 WREG32_P(MC_ARB_BURST_TIME, STATE0(burst_time), ~STATE0_MASK); 1547 break; 1548 case MC_CG_ARB_FREQ_F1: 1549 WREG32(MC_ARB_DRAM_TIMING_1, mc_arb_dram_timing); 1550 WREG32(MC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2); 1551 WREG32_P(MC_ARB_BURST_TIME, STATE1(burst_time), ~STATE1_MASK); 1552 break; 1553 case MC_CG_ARB_FREQ_F2: 1554 WREG32(MC_ARB_DRAM_TIMING_2, mc_arb_dram_timing); 1555 WREG32(MC_ARB_DRAM_TIMING2_2, mc_arb_dram_timing2); 1556 WREG32_P(MC_ARB_BURST_TIME, STATE2(burst_time), ~STATE2_MASK); 1557 break; 1558 case MC_CG_ARB_FREQ_F3: 1559 WREG32(MC_ARB_DRAM_TIMING_3, mc_arb_dram_timing); 1560 WREG32(MC_ARB_DRAM_TIMING2_3, mc_arb_dram_timing2); 1561 WREG32_P(MC_ARB_BURST_TIME, STATE3(burst_time), ~STATE3_MASK); 1562 break; 1563 default: 1564 return -EINVAL; 1565 } 1566 1567 mc_cg_config = RREG32(MC_CG_CONFIG) | 0x0000000F; 1568 WREG32(MC_CG_CONFIG, mc_cg_config); 1569 WREG32_P(MC_ARB_CG, CG_ARB_REQ(arb_freq_dest), ~CG_ARB_REQ_MASK); 1570 1571 return 0; 1572 } 1573 1574 static int ni_init_arb_table_index(struct radeon_device *rdev) 1575 { 1576 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 1577 struct ni_power_info *ni_pi = ni_get_pi(rdev); 1578 u32 tmp; 1579 int ret; 1580 1581 ret = rv770_read_smc_sram_dword(rdev, ni_pi->arb_table_start, 1582 &tmp, pi->sram_end); 1583 if (ret) 1584 return ret; 1585 1586 tmp &= 0x00FFFFFF; 1587 tmp |= ((u32)MC_CG_ARB_FREQ_F1) << 24; 1588 1589 return rv770_write_smc_sram_dword(rdev, ni_pi->arb_table_start, 1590 tmp, pi->sram_end); 1591 } 1592 1593 static int ni_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev) 1594 { 1595 return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1); 1596 } 1597 1598 static int ni_force_switch_to_arb_f0(struct radeon_device *rdev) 1599 { 1600 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 1601 struct ni_power_info *ni_pi = ni_get_pi(rdev); 1602 u32 tmp; 1603 int ret; 1604 1605 ret = rv770_read_smc_sram_dword(rdev, ni_pi->arb_table_start, 1606 &tmp, pi->sram_end); 1607 if (ret) 1608 return ret; 1609 1610 tmp = (tmp >> 24) & 0xff; 1611 1612 if (tmp == MC_CG_ARB_FREQ_F0) 1613 return 0; 1614 1615 return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0); 1616 } 1617 1618 static int ni_populate_memory_timing_parameters(struct radeon_device *rdev, 1619 struct rv7xx_pl *pl, 1620 SMC_NIslands_MCArbDramTimingRegisterSet *arb_regs) 1621 { 1622 u32 dram_timing; 1623 u32 dram_timing2; 1624 1625 arb_regs->mc_arb_rfsh_rate = 1626 (u8)rv770_calculate_memory_refresh_rate(rdev, pl->sclk); 1627 1628 1629 radeon_atom_set_engine_dram_timings(rdev, 1630 pl->sclk, 1631 pl->mclk); 1632 1633 dram_timing = RREG32(MC_ARB_DRAM_TIMING); 1634 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); 1635 1636 arb_regs->mc_arb_dram_timing = cpu_to_be32(dram_timing); 1637 arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2); 1638 1639 return 0; 1640 } 1641 1642 static int ni_do_program_memory_timing_parameters(struct radeon_device *rdev, 1643 struct radeon_ps *radeon_state, 1644 unsigned int first_arb_set) 1645 { 1646 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 1647 struct ni_power_info *ni_pi = ni_get_pi(rdev); 1648 struct ni_ps *state = ni_get_ps(radeon_state); 1649 SMC_NIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; 1650 int i, ret = 0; 1651 1652 for (i = 0; i < state->performance_level_count; i++) { 1653 ret = ni_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs); 1654 if (ret) 1655 break; 1656 1657 ret = rv770_copy_bytes_to_smc(rdev, 1658 (u16)(ni_pi->arb_table_start + 1659 offsetof(SMC_NIslands_MCArbDramTimingRegisters, data) + 1660 sizeof(SMC_NIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i)), 1661 (u8 *)&arb_regs, 1662 (u16)sizeof(SMC_NIslands_MCArbDramTimingRegisterSet), 1663 pi->sram_end); 1664 if (ret) 1665 break; 1666 } 1667 return ret; 1668 } 1669 1670 static int ni_program_memory_timing_parameters(struct radeon_device *rdev, 1671 struct radeon_ps *radeon_new_state) 1672 { 1673 return ni_do_program_memory_timing_parameters(rdev, radeon_new_state, 1674 NISLANDS_DRIVER_STATE_ARB_INDEX); 1675 } 1676 1677 static void ni_populate_initial_mvdd_value(struct radeon_device *rdev, 1678 struct NISLANDS_SMC_VOLTAGE_VALUE *voltage) 1679 { 1680 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 1681 1682 voltage->index = eg_pi->mvdd_high_index; 1683 voltage->value = cpu_to_be16(MVDD_HIGH_VALUE); 1684 } 1685 1686 static int ni_populate_smc_initial_state(struct radeon_device *rdev, 1687 struct radeon_ps *radeon_initial_state, 1688 NISLANDS_SMC_STATETABLE *table) 1689 { 1690 struct ni_ps *initial_state = ni_get_ps(radeon_initial_state); 1691 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 1692 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 1693 struct ni_power_info *ni_pi = ni_get_pi(rdev); 1694 u32 reg; 1695 int ret; 1696 1697 table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = 1698 cpu_to_be32(ni_pi->clock_registers.mpll_ad_func_cntl); 1699 table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL_2 = 1700 cpu_to_be32(ni_pi->clock_registers.mpll_ad_func_cntl_2); 1701 table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL = 1702 cpu_to_be32(ni_pi->clock_registers.mpll_dq_func_cntl); 1703 table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL_2 = 1704 cpu_to_be32(ni_pi->clock_registers.mpll_dq_func_cntl_2); 1705 table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL = 1706 cpu_to_be32(ni_pi->clock_registers.mclk_pwrmgt_cntl); 1707 table->initialState.levels[0].mclk.vDLL_CNTL = 1708 cpu_to_be32(ni_pi->clock_registers.dll_cntl); 1709 table->initialState.levels[0].mclk.vMPLL_SS = 1710 cpu_to_be32(ni_pi->clock_registers.mpll_ss1); 1711 table->initialState.levels[0].mclk.vMPLL_SS2 = 1712 cpu_to_be32(ni_pi->clock_registers.mpll_ss2); 1713 table->initialState.levels[0].mclk.mclk_value = 1714 cpu_to_be32(initial_state->performance_levels[0].mclk); 1715 1716 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = 1717 cpu_to_be32(ni_pi->clock_registers.cg_spll_func_cntl); 1718 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = 1719 cpu_to_be32(ni_pi->clock_registers.cg_spll_func_cntl_2); 1720 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = 1721 cpu_to_be32(ni_pi->clock_registers.cg_spll_func_cntl_3); 1722 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 = 1723 cpu_to_be32(ni_pi->clock_registers.cg_spll_func_cntl_4); 1724 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM = 1725 cpu_to_be32(ni_pi->clock_registers.cg_spll_spread_spectrum); 1726 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 = 1727 cpu_to_be32(ni_pi->clock_registers.cg_spll_spread_spectrum_2); 1728 table->initialState.levels[0].sclk.sclk_value = 1729 cpu_to_be32(initial_state->performance_levels[0].sclk); 1730 table->initialState.levels[0].arbRefreshState = 1731 NISLANDS_INITIAL_STATE_ARB_INDEX; 1732 1733 table->initialState.levels[0].ACIndex = 0; 1734 1735 ret = ni_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 1736 initial_state->performance_levels[0].vddc, 1737 &table->initialState.levels[0].vddc); 1738 if (!ret) { 1739 u16 std_vddc; 1740 1741 ret = ni_get_std_voltage_value(rdev, 1742 &table->initialState.levels[0].vddc, 1743 &std_vddc); 1744 if (!ret) 1745 ni_populate_std_voltage_value(rdev, std_vddc, 1746 table->initialState.levels[0].vddc.index, 1747 &table->initialState.levels[0].std_vddc); 1748 } 1749 1750 if (eg_pi->vddci_control) 1751 ni_populate_voltage_value(rdev, 1752 &eg_pi->vddci_voltage_table, 1753 initial_state->performance_levels[0].vddci, 1754 &table->initialState.levels[0].vddci); 1755 1756 ni_populate_initial_mvdd_value(rdev, &table->initialState.levels[0].mvdd); 1757 1758 reg = CG_R(0xffff) | CG_L(0); 1759 table->initialState.levels[0].aT = cpu_to_be32(reg); 1760 1761 table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp); 1762 1763 if (pi->boot_in_gen2) 1764 table->initialState.levels[0].gen2PCIE = 1; 1765 else 1766 table->initialState.levels[0].gen2PCIE = 0; 1767 1768 if (pi->mem_gddr5) { 1769 table->initialState.levels[0].strobeMode = 1770 cypress_get_strobe_mode_settings(rdev, 1771 initial_state->performance_levels[0].mclk); 1772 1773 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold) 1774 table->initialState.levels[0].mcFlags = NISLANDS_SMC_MC_EDC_RD_FLAG | NISLANDS_SMC_MC_EDC_WR_FLAG; 1775 else 1776 table->initialState.levels[0].mcFlags = 0; 1777 } 1778 1779 table->initialState.levelCount = 1; 1780 1781 table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC; 1782 1783 table->initialState.levels[0].dpm2.MaxPS = 0; 1784 table->initialState.levels[0].dpm2.NearTDPDec = 0; 1785 table->initialState.levels[0].dpm2.AboveSafeInc = 0; 1786 table->initialState.levels[0].dpm2.BelowSafeInc = 0; 1787 1788 reg = MIN_POWER_MASK | MAX_POWER_MASK; 1789 table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg); 1790 1791 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 1792 table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg); 1793 1794 return 0; 1795 } 1796 1797 static int ni_populate_smc_acpi_state(struct radeon_device *rdev, 1798 NISLANDS_SMC_STATETABLE *table) 1799 { 1800 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 1801 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 1802 struct ni_power_info *ni_pi = ni_get_pi(rdev); 1803 u32 mpll_ad_func_cntl = ni_pi->clock_registers.mpll_ad_func_cntl; 1804 u32 mpll_ad_func_cntl_2 = ni_pi->clock_registers.mpll_ad_func_cntl_2; 1805 u32 mpll_dq_func_cntl = ni_pi->clock_registers.mpll_dq_func_cntl; 1806 u32 mpll_dq_func_cntl_2 = ni_pi->clock_registers.mpll_dq_func_cntl_2; 1807 u32 spll_func_cntl = ni_pi->clock_registers.cg_spll_func_cntl; 1808 u32 spll_func_cntl_2 = ni_pi->clock_registers.cg_spll_func_cntl_2; 1809 u32 spll_func_cntl_3 = ni_pi->clock_registers.cg_spll_func_cntl_3; 1810 u32 spll_func_cntl_4 = ni_pi->clock_registers.cg_spll_func_cntl_4; 1811 u32 mclk_pwrmgt_cntl = ni_pi->clock_registers.mclk_pwrmgt_cntl; 1812 u32 dll_cntl = ni_pi->clock_registers.dll_cntl; 1813 u32 reg; 1814 int ret; 1815 1816 table->ACPIState = table->initialState; 1817 1818 table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC; 1819 1820 if (pi->acpi_vddc) { 1821 ret = ni_populate_voltage_value(rdev, 1822 &eg_pi->vddc_voltage_table, 1823 pi->acpi_vddc, &table->ACPIState.levels[0].vddc); 1824 if (!ret) { 1825 u16 std_vddc; 1826 1827 ret = ni_get_std_voltage_value(rdev, 1828 &table->ACPIState.levels[0].vddc, &std_vddc); 1829 if (!ret) 1830 ni_populate_std_voltage_value(rdev, std_vddc, 1831 table->ACPIState.levels[0].vddc.index, 1832 &table->ACPIState.levels[0].std_vddc); 1833 } 1834 1835 if (pi->pcie_gen2) { 1836 if (pi->acpi_pcie_gen2) 1837 table->ACPIState.levels[0].gen2PCIE = 1; 1838 else 1839 table->ACPIState.levels[0].gen2PCIE = 0; 1840 } else { 1841 table->ACPIState.levels[0].gen2PCIE = 0; 1842 } 1843 } else { 1844 ret = ni_populate_voltage_value(rdev, 1845 &eg_pi->vddc_voltage_table, 1846 pi->min_vddc_in_table, 1847 &table->ACPIState.levels[0].vddc); 1848 if (!ret) { 1849 u16 std_vddc; 1850 1851 ret = ni_get_std_voltage_value(rdev, 1852 &table->ACPIState.levels[0].vddc, 1853 &std_vddc); 1854 if (!ret) 1855 ni_populate_std_voltage_value(rdev, std_vddc, 1856 table->ACPIState.levels[0].vddc.index, 1857 &table->ACPIState.levels[0].std_vddc); 1858 } 1859 table->ACPIState.levels[0].gen2PCIE = 0; 1860 } 1861 1862 if (eg_pi->acpi_vddci) { 1863 if (eg_pi->vddci_control) 1864 ni_populate_voltage_value(rdev, 1865 &eg_pi->vddci_voltage_table, 1866 eg_pi->acpi_vddci, 1867 &table->ACPIState.levels[0].vddci); 1868 } 1869 1870 1871 mpll_ad_func_cntl &= ~PDNB; 1872 1873 mpll_ad_func_cntl_2 |= BIAS_GEN_PDNB | RESET_EN; 1874 1875 if (pi->mem_gddr5) 1876 mpll_dq_func_cntl &= ~PDNB; 1877 mpll_dq_func_cntl_2 |= BIAS_GEN_PDNB | RESET_EN | BYPASS; 1878 1879 1880 mclk_pwrmgt_cntl |= (MRDCKA0_RESET | 1881 MRDCKA1_RESET | 1882 MRDCKB0_RESET | 1883 MRDCKB1_RESET | 1884 MRDCKC0_RESET | 1885 MRDCKC1_RESET | 1886 MRDCKD0_RESET | 1887 MRDCKD1_RESET); 1888 1889 mclk_pwrmgt_cntl &= ~(MRDCKA0_PDNB | 1890 MRDCKA1_PDNB | 1891 MRDCKB0_PDNB | 1892 MRDCKB1_PDNB | 1893 MRDCKC0_PDNB | 1894 MRDCKC1_PDNB | 1895 MRDCKD0_PDNB | 1896 MRDCKD1_PDNB); 1897 1898 dll_cntl |= (MRDCKA0_BYPASS | 1899 MRDCKA1_BYPASS | 1900 MRDCKB0_BYPASS | 1901 MRDCKB1_BYPASS | 1902 MRDCKC0_BYPASS | 1903 MRDCKC1_BYPASS | 1904 MRDCKD0_BYPASS | 1905 MRDCKD1_BYPASS); 1906 1907 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; 1908 spll_func_cntl_2 |= SCLK_MUX_SEL(4); 1909 1910 table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl); 1911 table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL_2 = cpu_to_be32(mpll_ad_func_cntl_2); 1912 table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl); 1913 table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL_2 = cpu_to_be32(mpll_dq_func_cntl_2); 1914 table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); 1915 table->ACPIState.levels[0].mclk.vDLL_CNTL = cpu_to_be32(dll_cntl); 1916 1917 table->ACPIState.levels[0].mclk.mclk_value = 0; 1918 1919 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl); 1920 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2); 1921 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3); 1922 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(spll_func_cntl_4); 1923 1924 table->ACPIState.levels[0].sclk.sclk_value = 0; 1925 1926 ni_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd); 1927 1928 if (eg_pi->dynamic_ac_timing) 1929 table->ACPIState.levels[0].ACIndex = 1; 1930 1931 table->ACPIState.levels[0].dpm2.MaxPS = 0; 1932 table->ACPIState.levels[0].dpm2.NearTDPDec = 0; 1933 table->ACPIState.levels[0].dpm2.AboveSafeInc = 0; 1934 table->ACPIState.levels[0].dpm2.BelowSafeInc = 0; 1935 1936 reg = MIN_POWER_MASK | MAX_POWER_MASK; 1937 table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg); 1938 1939 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 1940 table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg); 1941 1942 return 0; 1943 } 1944 1945 static int ni_init_smc_table(struct radeon_device *rdev) 1946 { 1947 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 1948 struct ni_power_info *ni_pi = ni_get_pi(rdev); 1949 int ret; 1950 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps; 1951 NISLANDS_SMC_STATETABLE *table = &ni_pi->smc_statetable; 1952 1953 memset(table, 0, sizeof(NISLANDS_SMC_STATETABLE)); 1954 1955 ni_populate_smc_voltage_tables(rdev, table); 1956 1957 switch (rdev->pm.int_thermal_type) { 1958 case THERMAL_TYPE_NI: 1959 case THERMAL_TYPE_EMC2103_WITH_INTERNAL: 1960 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL; 1961 break; 1962 case THERMAL_TYPE_NONE: 1963 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE; 1964 break; 1965 default: 1966 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL; 1967 break; 1968 } 1969 1970 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC) 1971 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC; 1972 1973 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) 1974 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT; 1975 1976 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) 1977 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC; 1978 1979 if (pi->mem_gddr5) 1980 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5; 1981 1982 ret = ni_populate_smc_initial_state(rdev, radeon_boot_state, table); 1983 if (ret) 1984 return ret; 1985 1986 ret = ni_populate_smc_acpi_state(rdev, table); 1987 if (ret) 1988 return ret; 1989 1990 table->driverState = table->initialState; 1991 1992 table->ULVState = table->initialState; 1993 1994 ret = ni_do_program_memory_timing_parameters(rdev, radeon_boot_state, 1995 NISLANDS_INITIAL_STATE_ARB_INDEX); 1996 if (ret) 1997 return ret; 1998 1999 return rv770_copy_bytes_to_smc(rdev, pi->state_table_start, (u8 *)table, 2000 sizeof(NISLANDS_SMC_STATETABLE), pi->sram_end); 2001 } 2002 2003 static int ni_calculate_sclk_params(struct radeon_device *rdev, 2004 u32 engine_clock, 2005 NISLANDS_SMC_SCLK_VALUE *sclk) 2006 { 2007 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 2008 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2009 struct atom_clock_dividers dividers; 2010 u32 spll_func_cntl = ni_pi->clock_registers.cg_spll_func_cntl; 2011 u32 spll_func_cntl_2 = ni_pi->clock_registers.cg_spll_func_cntl_2; 2012 u32 spll_func_cntl_3 = ni_pi->clock_registers.cg_spll_func_cntl_3; 2013 u32 spll_func_cntl_4 = ni_pi->clock_registers.cg_spll_func_cntl_4; 2014 u32 cg_spll_spread_spectrum = ni_pi->clock_registers.cg_spll_spread_spectrum; 2015 u32 cg_spll_spread_spectrum_2 = ni_pi->clock_registers.cg_spll_spread_spectrum_2; 2016 u64 tmp; 2017 u32 reference_clock = rdev->clock.spll.reference_freq; 2018 u32 reference_divider; 2019 u32 fbdiv; 2020 int ret; 2021 2022 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 2023 engine_clock, false, ÷rs); 2024 if (ret) 2025 return ret; 2026 2027 reference_divider = 1 + dividers.ref_div; 2028 2029 2030 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16834; 2031 do_div(tmp, reference_clock); 2032 fbdiv = (u32) tmp; 2033 2034 spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK); 2035 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); 2036 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div); 2037 2038 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; 2039 spll_func_cntl_2 |= SCLK_MUX_SEL(2); 2040 2041 spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK; 2042 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv); 2043 spll_func_cntl_3 |= SPLL_DITHEN; 2044 2045 if (pi->sclk_ss) { 2046 struct radeon_atom_ss ss; 2047 u32 vco_freq = engine_clock * dividers.post_div; 2048 2049 if (radeon_atombios_get_asic_ss_info(rdev, &ss, 2050 ASIC_INTERNAL_ENGINE_SS, vco_freq)) { 2051 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); 2052 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000); 2053 2054 cg_spll_spread_spectrum &= ~CLK_S_MASK; 2055 cg_spll_spread_spectrum |= CLK_S(clk_s); 2056 cg_spll_spread_spectrum |= SSEN; 2057 2058 cg_spll_spread_spectrum_2 &= ~CLK_V_MASK; 2059 cg_spll_spread_spectrum_2 |= CLK_V(clk_v); 2060 } 2061 } 2062 2063 sclk->sclk_value = engine_clock; 2064 sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl; 2065 sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2; 2066 sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3; 2067 sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4; 2068 sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum; 2069 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2; 2070 2071 return 0; 2072 } 2073 2074 static int ni_populate_sclk_value(struct radeon_device *rdev, 2075 u32 engine_clock, 2076 NISLANDS_SMC_SCLK_VALUE *sclk) 2077 { 2078 NISLANDS_SMC_SCLK_VALUE sclk_tmp; 2079 int ret; 2080 2081 ret = ni_calculate_sclk_params(rdev, engine_clock, &sclk_tmp); 2082 if (!ret) { 2083 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value); 2084 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL); 2085 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2); 2086 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3); 2087 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4); 2088 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM); 2089 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2); 2090 } 2091 2092 return ret; 2093 } 2094 2095 static int ni_init_smc_spll_table(struct radeon_device *rdev) 2096 { 2097 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 2098 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2099 SMC_NISLANDS_SPLL_DIV_TABLE *spll_table; 2100 NISLANDS_SMC_SCLK_VALUE sclk_params; 2101 u32 fb_div; 2102 u32 p_div; 2103 u32 clk_s; 2104 u32 clk_v; 2105 u32 sclk = 0; 2106 int i, ret; 2107 u32 tmp; 2108 2109 if (ni_pi->spll_table_start == 0) 2110 return -EINVAL; 2111 2112 spll_table = kzalloc(sizeof(SMC_NISLANDS_SPLL_DIV_TABLE), GFP_KERNEL); 2113 if (spll_table == NULL) 2114 return -ENOMEM; 2115 2116 for (i = 0; i < 256; i++) { 2117 ret = ni_calculate_sclk_params(rdev, sclk, &sclk_params); 2118 if (ret) 2119 break; 2120 2121 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT; 2122 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT; 2123 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT; 2124 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT; 2125 2126 fb_div &= ~0x00001FFF; 2127 fb_div >>= 1; 2128 clk_v >>= 6; 2129 2130 if (p_div & ~(SMC_NISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_NISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT)) 2131 ret = -EINVAL; 2132 2133 if (clk_s & ~(SMC_NISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_NISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT)) 2134 ret = -EINVAL; 2135 2136 if (clk_s & ~(SMC_NISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_NISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT)) 2137 ret = -EINVAL; 2138 2139 if (clk_v & ~(SMC_NISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_NISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT)) 2140 ret = -EINVAL; 2141 2142 if (ret) 2143 break; 2144 2145 tmp = ((fb_div << SMC_NISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_NISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) | 2146 ((p_div << SMC_NISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_NISLANDS_SPLL_DIV_TABLE_PDIV_MASK); 2147 spll_table->freq[i] = cpu_to_be32(tmp); 2148 2149 tmp = ((clk_v << SMC_NISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_NISLANDS_SPLL_DIV_TABLE_CLKV_MASK) | 2150 ((clk_s << SMC_NISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_NISLANDS_SPLL_DIV_TABLE_CLKS_MASK); 2151 spll_table->ss[i] = cpu_to_be32(tmp); 2152 2153 sclk += 512; 2154 } 2155 2156 if (!ret) 2157 ret = rv770_copy_bytes_to_smc(rdev, ni_pi->spll_table_start, (u8 *)spll_table, 2158 sizeof(SMC_NISLANDS_SPLL_DIV_TABLE), pi->sram_end); 2159 2160 kfree(spll_table); 2161 2162 return ret; 2163 } 2164 2165 static int ni_populate_mclk_value(struct radeon_device *rdev, 2166 u32 engine_clock, 2167 u32 memory_clock, 2168 NISLANDS_SMC_MCLK_VALUE *mclk, 2169 bool strobe_mode, 2170 bool dll_state_on) 2171 { 2172 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 2173 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2174 u32 mpll_ad_func_cntl = ni_pi->clock_registers.mpll_ad_func_cntl; 2175 u32 mpll_ad_func_cntl_2 = ni_pi->clock_registers.mpll_ad_func_cntl_2; 2176 u32 mpll_dq_func_cntl = ni_pi->clock_registers.mpll_dq_func_cntl; 2177 u32 mpll_dq_func_cntl_2 = ni_pi->clock_registers.mpll_dq_func_cntl_2; 2178 u32 mclk_pwrmgt_cntl = ni_pi->clock_registers.mclk_pwrmgt_cntl; 2179 u32 dll_cntl = ni_pi->clock_registers.dll_cntl; 2180 u32 mpll_ss1 = ni_pi->clock_registers.mpll_ss1; 2181 u32 mpll_ss2 = ni_pi->clock_registers.mpll_ss2; 2182 struct atom_clock_dividers dividers; 2183 u32 ibias; 2184 u32 dll_speed; 2185 int ret; 2186 u32 mc_seq_misc7; 2187 2188 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_MEMORY_PLL_PARAM, 2189 memory_clock, strobe_mode, ÷rs); 2190 if (ret) 2191 return ret; 2192 2193 if (!strobe_mode) { 2194 mc_seq_misc7 = RREG32(MC_SEQ_MISC7); 2195 2196 if (mc_seq_misc7 & 0x8000000) 2197 dividers.post_div = 1; 2198 } 2199 2200 ibias = cypress_map_clkf_to_ibias(rdev, dividers.whole_fb_div); 2201 2202 mpll_ad_func_cntl &= ~(CLKR_MASK | 2203 YCLK_POST_DIV_MASK | 2204 CLKF_MASK | 2205 CLKFRAC_MASK | 2206 IBIAS_MASK); 2207 mpll_ad_func_cntl |= CLKR(dividers.ref_div); 2208 mpll_ad_func_cntl |= YCLK_POST_DIV(dividers.post_div); 2209 mpll_ad_func_cntl |= CLKF(dividers.whole_fb_div); 2210 mpll_ad_func_cntl |= CLKFRAC(dividers.frac_fb_div); 2211 mpll_ad_func_cntl |= IBIAS(ibias); 2212 2213 if (dividers.vco_mode) 2214 mpll_ad_func_cntl_2 |= VCO_MODE; 2215 else 2216 mpll_ad_func_cntl_2 &= ~VCO_MODE; 2217 2218 if (pi->mem_gddr5) { 2219 mpll_dq_func_cntl &= ~(CLKR_MASK | 2220 YCLK_POST_DIV_MASK | 2221 CLKF_MASK | 2222 CLKFRAC_MASK | 2223 IBIAS_MASK); 2224 mpll_dq_func_cntl |= CLKR(dividers.ref_div); 2225 mpll_dq_func_cntl |= YCLK_POST_DIV(dividers.post_div); 2226 mpll_dq_func_cntl |= CLKF(dividers.whole_fb_div); 2227 mpll_dq_func_cntl |= CLKFRAC(dividers.frac_fb_div); 2228 mpll_dq_func_cntl |= IBIAS(ibias); 2229 2230 if (strobe_mode) 2231 mpll_dq_func_cntl &= ~PDNB; 2232 else 2233 mpll_dq_func_cntl |= PDNB; 2234 2235 if (dividers.vco_mode) 2236 mpll_dq_func_cntl_2 |= VCO_MODE; 2237 else 2238 mpll_dq_func_cntl_2 &= ~VCO_MODE; 2239 } 2240 2241 if (pi->mclk_ss) { 2242 struct radeon_atom_ss ss; 2243 u32 vco_freq = memory_clock * dividers.post_div; 2244 2245 if (radeon_atombios_get_asic_ss_info(rdev, &ss, 2246 ASIC_INTERNAL_MEMORY_SS, vco_freq)) { 2247 u32 reference_clock = rdev->clock.mpll.reference_freq; 2248 u32 decoded_ref = rv740_get_decoded_reference_divider(dividers.ref_div); 2249 u32 clk_s = reference_clock * 5 / (decoded_ref * ss.rate); 2250 u32 clk_v = ss.percentage * 2251 (0x4000 * dividers.whole_fb_div + 0x800 * dividers.frac_fb_div) / (clk_s * 625); 2252 2253 mpll_ss1 &= ~CLKV_MASK; 2254 mpll_ss1 |= CLKV(clk_v); 2255 2256 mpll_ss2 &= ~CLKS_MASK; 2257 mpll_ss2 |= CLKS(clk_s); 2258 } 2259 } 2260 2261 dll_speed = rv740_get_dll_speed(pi->mem_gddr5, 2262 memory_clock); 2263 2264 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK; 2265 mclk_pwrmgt_cntl |= DLL_SPEED(dll_speed); 2266 if (dll_state_on) 2267 mclk_pwrmgt_cntl |= (MRDCKA0_PDNB | 2268 MRDCKA1_PDNB | 2269 MRDCKB0_PDNB | 2270 MRDCKB1_PDNB | 2271 MRDCKC0_PDNB | 2272 MRDCKC1_PDNB | 2273 MRDCKD0_PDNB | 2274 MRDCKD1_PDNB); 2275 else 2276 mclk_pwrmgt_cntl &= ~(MRDCKA0_PDNB | 2277 MRDCKA1_PDNB | 2278 MRDCKB0_PDNB | 2279 MRDCKB1_PDNB | 2280 MRDCKC0_PDNB | 2281 MRDCKC1_PDNB | 2282 MRDCKD0_PDNB | 2283 MRDCKD1_PDNB); 2284 2285 2286 mclk->mclk_value = cpu_to_be32(memory_clock); 2287 mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl); 2288 mclk->vMPLL_AD_FUNC_CNTL_2 = cpu_to_be32(mpll_ad_func_cntl_2); 2289 mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl); 2290 mclk->vMPLL_DQ_FUNC_CNTL_2 = cpu_to_be32(mpll_dq_func_cntl_2); 2291 mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); 2292 mclk->vDLL_CNTL = cpu_to_be32(dll_cntl); 2293 mclk->vMPLL_SS = cpu_to_be32(mpll_ss1); 2294 mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2); 2295 2296 return 0; 2297 } 2298 2299 static void ni_populate_smc_sp(struct radeon_device *rdev, 2300 struct radeon_ps *radeon_state, 2301 NISLANDS_SMC_SWSTATE *smc_state) 2302 { 2303 struct ni_ps *ps = ni_get_ps(radeon_state); 2304 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 2305 int i; 2306 2307 for (i = 0; i < ps->performance_level_count - 1; i++) 2308 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp); 2309 2310 smc_state->levels[ps->performance_level_count - 1].bSP = 2311 cpu_to_be32(pi->psp); 2312 } 2313 2314 static int ni_convert_power_level_to_smc(struct radeon_device *rdev, 2315 struct rv7xx_pl *pl, 2316 NISLANDS_SMC_HW_PERFORMANCE_LEVEL *level) 2317 { 2318 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 2319 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 2320 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2321 int ret; 2322 bool dll_state_on; 2323 u16 std_vddc; 2324 u32 tmp = RREG32(DC_STUTTER_CNTL); 2325 2326 level->gen2PCIE = pi->pcie_gen2 ? 2327 ((pl->flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) ? 1 : 0) : 0; 2328 2329 ret = ni_populate_sclk_value(rdev, pl->sclk, &level->sclk); 2330 if (ret) 2331 return ret; 2332 2333 level->mcFlags = 0; 2334 if (pi->mclk_stutter_mode_threshold && 2335 (pl->mclk <= pi->mclk_stutter_mode_threshold) && 2336 !eg_pi->uvd_enabled && 2337 (tmp & DC_STUTTER_ENABLE_A) && 2338 (tmp & DC_STUTTER_ENABLE_B)) 2339 level->mcFlags |= NISLANDS_SMC_MC_STUTTER_EN; 2340 2341 if (pi->mem_gddr5) { 2342 if (pl->mclk > pi->mclk_edc_enable_threshold) 2343 level->mcFlags |= NISLANDS_SMC_MC_EDC_RD_FLAG; 2344 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold) 2345 level->mcFlags |= NISLANDS_SMC_MC_EDC_WR_FLAG; 2346 2347 level->strobeMode = cypress_get_strobe_mode_settings(rdev, pl->mclk); 2348 2349 if (level->strobeMode & NISLANDS_SMC_STROBE_ENABLE) { 2350 if (cypress_get_mclk_frequency_ratio(rdev, pl->mclk, true) >= 2351 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf)) 2352 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; 2353 else 2354 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false; 2355 } else { 2356 dll_state_on = false; 2357 if (pl->mclk > ni_pi->mclk_rtt_mode_threshold) 2358 level->mcFlags |= NISLANDS_SMC_MC_RTT_ENABLE; 2359 } 2360 2361 ret = ni_populate_mclk_value(rdev, pl->sclk, pl->mclk, 2362 &level->mclk, 2363 (level->strobeMode & NISLANDS_SMC_STROBE_ENABLE) != 0, 2364 dll_state_on); 2365 } else 2366 ret = ni_populate_mclk_value(rdev, pl->sclk, pl->mclk, &level->mclk, 1, 1); 2367 2368 if (ret) 2369 return ret; 2370 2371 ret = ni_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 2372 pl->vddc, &level->vddc); 2373 if (ret) 2374 return ret; 2375 2376 ret = ni_get_std_voltage_value(rdev, &level->vddc, &std_vddc); 2377 if (ret) 2378 return ret; 2379 2380 ni_populate_std_voltage_value(rdev, std_vddc, 2381 level->vddc.index, &level->std_vddc); 2382 2383 if (eg_pi->vddci_control) { 2384 ret = ni_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table, 2385 pl->vddci, &level->vddci); 2386 if (ret) 2387 return ret; 2388 } 2389 2390 ni_populate_mvdd_value(rdev, pl->mclk, &level->mvdd); 2391 2392 return ret; 2393 } 2394 2395 static int ni_populate_smc_t(struct radeon_device *rdev, 2396 struct radeon_ps *radeon_state, 2397 NISLANDS_SMC_SWSTATE *smc_state) 2398 { 2399 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 2400 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 2401 struct ni_ps *state = ni_get_ps(radeon_state); 2402 u32 a_t; 2403 u32 t_l, t_h; 2404 u32 high_bsp; 2405 int i, ret; 2406 2407 if (state->performance_level_count >= 9) 2408 return -EINVAL; 2409 2410 if (state->performance_level_count < 2) { 2411 a_t = CG_R(0xffff) | CG_L(0); 2412 smc_state->levels[0].aT = cpu_to_be32(a_t); 2413 return 0; 2414 } 2415 2416 smc_state->levels[0].aT = cpu_to_be32(0); 2417 2418 for (i = 0; i <= state->performance_level_count - 2; i++) { 2419 if (eg_pi->uvd_enabled) 2420 ret = r600_calculate_at( 2421 1000 * (i * (eg_pi->smu_uvd_hs ? 2 : 8) + 2), 2422 100 * R600_AH_DFLT, 2423 state->performance_levels[i + 1].sclk, 2424 state->performance_levels[i].sclk, 2425 &t_l, 2426 &t_h); 2427 else 2428 ret = r600_calculate_at( 2429 1000 * (i + 1), 2430 100 * R600_AH_DFLT, 2431 state->performance_levels[i + 1].sclk, 2432 state->performance_levels[i].sclk, 2433 &t_l, 2434 &t_h); 2435 2436 if (ret) { 2437 t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT; 2438 t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT; 2439 } 2440 2441 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK; 2442 a_t |= CG_R(t_l * pi->bsp / 20000); 2443 smc_state->levels[i].aT = cpu_to_be32(a_t); 2444 2445 high_bsp = (i == state->performance_level_count - 2) ? 2446 pi->pbsp : pi->bsp; 2447 2448 a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000); 2449 smc_state->levels[i + 1].aT = cpu_to_be32(a_t); 2450 } 2451 2452 return 0; 2453 } 2454 2455 static int ni_populate_power_containment_values(struct radeon_device *rdev, 2456 struct radeon_ps *radeon_state, 2457 NISLANDS_SMC_SWSTATE *smc_state) 2458 { 2459 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 2460 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 2461 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2462 struct ni_ps *state = ni_get_ps(radeon_state); 2463 u32 prev_sclk; 2464 u32 max_sclk; 2465 u32 min_sclk; 2466 int i, ret; 2467 u32 tdp_limit; 2468 u32 near_tdp_limit; 2469 u32 power_boost_limit; 2470 u8 max_ps_percent; 2471 2472 if (ni_pi->enable_power_containment == false) 2473 return 0; 2474 2475 if (state->performance_level_count == 0) 2476 return -EINVAL; 2477 2478 if (smc_state->levelCount != state->performance_level_count) 2479 return -EINVAL; 2480 2481 ret = ni_calculate_adjusted_tdp_limits(rdev, 2482 false, /* ??? */ 2483 rdev->pm.dpm.tdp_adjustment, 2484 &tdp_limit, 2485 &near_tdp_limit); 2486 if (ret) 2487 return ret; 2488 2489 power_boost_limit = ni_calculate_power_boost_limit(rdev, radeon_state, near_tdp_limit); 2490 2491 ret = rv770_write_smc_sram_dword(rdev, 2492 pi->state_table_start + 2493 offsetof(NISLANDS_SMC_STATETABLE, dpm2Params) + 2494 offsetof(PP_NIslands_DPM2Parameters, PowerBoostLimit), 2495 ni_scale_power_for_smc(power_boost_limit, ni_get_smc_power_scaling_factor(rdev)), 2496 pi->sram_end); 2497 if (ret) 2498 power_boost_limit = 0; 2499 2500 smc_state->levels[0].dpm2.MaxPS = 0; 2501 smc_state->levels[0].dpm2.NearTDPDec = 0; 2502 smc_state->levels[0].dpm2.AboveSafeInc = 0; 2503 smc_state->levels[0].dpm2.BelowSafeInc = 0; 2504 smc_state->levels[0].stateFlags |= power_boost_limit ? PPSMC_STATEFLAG_POWERBOOST : 0; 2505 2506 for (i = 1; i < state->performance_level_count; i++) { 2507 prev_sclk = state->performance_levels[i-1].sclk; 2508 max_sclk = state->performance_levels[i].sclk; 2509 max_ps_percent = (i != (state->performance_level_count - 1)) ? 2510 NISLANDS_DPM2_MAXPS_PERCENT_M : NISLANDS_DPM2_MAXPS_PERCENT_H; 2511 2512 if (max_sclk < prev_sclk) 2513 return -EINVAL; 2514 2515 if ((max_ps_percent == 0) || (prev_sclk == max_sclk) || eg_pi->uvd_enabled) 2516 min_sclk = max_sclk; 2517 else if (1 == i) 2518 min_sclk = prev_sclk; 2519 else 2520 min_sclk = (prev_sclk * (u32)max_ps_percent) / 100; 2521 2522 if (min_sclk < state->performance_levels[0].sclk) 2523 min_sclk = state->performance_levels[0].sclk; 2524 2525 if (min_sclk == 0) 2526 return -EINVAL; 2527 2528 smc_state->levels[i].dpm2.MaxPS = 2529 (u8)((NISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk); 2530 smc_state->levels[i].dpm2.NearTDPDec = NISLANDS_DPM2_NEAR_TDP_DEC; 2531 smc_state->levels[i].dpm2.AboveSafeInc = NISLANDS_DPM2_ABOVE_SAFE_INC; 2532 smc_state->levels[i].dpm2.BelowSafeInc = NISLANDS_DPM2_BELOW_SAFE_INC; 2533 smc_state->levels[i].stateFlags |= 2534 ((i != (state->performance_level_count - 1)) && power_boost_limit) ? 2535 PPSMC_STATEFLAG_POWERBOOST : 0; 2536 } 2537 2538 return 0; 2539 } 2540 2541 static int ni_populate_sq_ramping_values(struct radeon_device *rdev, 2542 struct radeon_ps *radeon_state, 2543 NISLANDS_SMC_SWSTATE *smc_state) 2544 { 2545 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2546 struct ni_ps *state = ni_get_ps(radeon_state); 2547 u32 sq_power_throttle; 2548 u32 sq_power_throttle2; 2549 bool enable_sq_ramping = ni_pi->enable_sq_ramping; 2550 int i; 2551 2552 if (state->performance_level_count == 0) 2553 return -EINVAL; 2554 2555 if (smc_state->levelCount != state->performance_level_count) 2556 return -EINVAL; 2557 2558 if (rdev->pm.dpm.sq_ramping_threshold == 0) 2559 return -EINVAL; 2560 2561 if (NISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT)) 2562 enable_sq_ramping = false; 2563 2564 if (NISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT)) 2565 enable_sq_ramping = false; 2566 2567 if (NISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT)) 2568 enable_sq_ramping = false; 2569 2570 if (NISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT)) 2571 enable_sq_ramping = false; 2572 2573 if (NISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (LTI_RATIO_MASK >> LTI_RATIO_SHIFT)) 2574 enable_sq_ramping = false; 2575 2576 for (i = 0; i < state->performance_level_count; i++) { 2577 sq_power_throttle = 0; 2578 sq_power_throttle2 = 0; 2579 2580 if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) && 2581 enable_sq_ramping) { 2582 sq_power_throttle |= MAX_POWER(NISLANDS_DPM2_SQ_RAMP_MAX_POWER); 2583 sq_power_throttle |= MIN_POWER(NISLANDS_DPM2_SQ_RAMP_MIN_POWER); 2584 sq_power_throttle2 |= MAX_POWER_DELTA(NISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA); 2585 sq_power_throttle2 |= STI_SIZE(NISLANDS_DPM2_SQ_RAMP_STI_SIZE); 2586 sq_power_throttle2 |= LTI_RATIO(NISLANDS_DPM2_SQ_RAMP_LTI_RATIO); 2587 } else { 2588 sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK; 2589 sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 2590 } 2591 2592 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle); 2593 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2); 2594 } 2595 2596 return 0; 2597 } 2598 2599 static int ni_enable_power_containment(struct radeon_device *rdev, 2600 struct radeon_ps *radeon_new_state, 2601 bool enable) 2602 { 2603 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2604 PPSMC_Result smc_result; 2605 int ret = 0; 2606 2607 if (ni_pi->enable_power_containment) { 2608 if (enable) { 2609 if (!r600_is_uvd_state(radeon_new_state->class, radeon_new_state->class2)) { 2610 smc_result = rv770_send_msg_to_smc(rdev, PPSMC_TDPClampingActive); 2611 if (smc_result != PPSMC_Result_OK) { 2612 ret = -EINVAL; 2613 ni_pi->pc_enabled = false; 2614 } else { 2615 ni_pi->pc_enabled = true; 2616 } 2617 } 2618 } else { 2619 smc_result = rv770_send_msg_to_smc(rdev, PPSMC_TDPClampingInactive); 2620 if (smc_result != PPSMC_Result_OK) 2621 ret = -EINVAL; 2622 ni_pi->pc_enabled = false; 2623 } 2624 } 2625 2626 return ret; 2627 } 2628 2629 static int ni_convert_power_state_to_smc(struct radeon_device *rdev, 2630 struct radeon_ps *radeon_state, 2631 NISLANDS_SMC_SWSTATE *smc_state) 2632 { 2633 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 2634 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2635 struct ni_ps *state = ni_get_ps(radeon_state); 2636 int i, ret; 2637 u32 threshold = state->performance_levels[state->performance_level_count - 1].sclk * 100 / 100; 2638 2639 if (!(radeon_state->caps & ATOM_PPLIB_DISALLOW_ON_DC)) 2640 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC; 2641 2642 smc_state->levelCount = 0; 2643 2644 if (state->performance_level_count > NISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE) 2645 return -EINVAL; 2646 2647 for (i = 0; i < state->performance_level_count; i++) { 2648 ret = ni_convert_power_level_to_smc(rdev, &state->performance_levels[i], 2649 &smc_state->levels[i]); 2650 smc_state->levels[i].arbRefreshState = 2651 (u8)(NISLANDS_DRIVER_STATE_ARB_INDEX + i); 2652 2653 if (ret) 2654 return ret; 2655 2656 if (ni_pi->enable_power_containment) 2657 smc_state->levels[i].displayWatermark = 2658 (state->performance_levels[i].sclk < threshold) ? 2659 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH; 2660 else 2661 smc_state->levels[i].displayWatermark = (i < 2) ? 2662 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH; 2663 2664 if (eg_pi->dynamic_ac_timing) 2665 smc_state->levels[i].ACIndex = NISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i; 2666 else 2667 smc_state->levels[i].ACIndex = 0; 2668 2669 smc_state->levelCount++; 2670 } 2671 2672 rv770_write_smc_soft_register(rdev, NI_SMC_SOFT_REGISTER_watermark_threshold, 2673 cpu_to_be32(threshold / 512)); 2674 2675 ni_populate_smc_sp(rdev, radeon_state, smc_state); 2676 2677 ret = ni_populate_power_containment_values(rdev, radeon_state, smc_state); 2678 if (ret) 2679 ni_pi->enable_power_containment = false; 2680 2681 ret = ni_populate_sq_ramping_values(rdev, radeon_state, smc_state); 2682 if (ret) 2683 ni_pi->enable_sq_ramping = false; 2684 2685 return ni_populate_smc_t(rdev, radeon_state, smc_state); 2686 } 2687 2688 static int ni_upload_sw_state(struct radeon_device *rdev, 2689 struct radeon_ps *radeon_new_state) 2690 { 2691 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 2692 u16 address = pi->state_table_start + 2693 offsetof(NISLANDS_SMC_STATETABLE, driverState); 2694 u16 state_size = sizeof(NISLANDS_SMC_SWSTATE) + 2695 ((NISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE - 1) * sizeof(NISLANDS_SMC_HW_PERFORMANCE_LEVEL)); 2696 int ret; 2697 NISLANDS_SMC_SWSTATE *smc_state = kzalloc(state_size, GFP_KERNEL); 2698 2699 if (smc_state == NULL) 2700 return -ENOMEM; 2701 2702 ret = ni_convert_power_state_to_smc(rdev, radeon_new_state, smc_state); 2703 if (ret) 2704 goto done; 2705 2706 ret = rv770_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, state_size, pi->sram_end); 2707 2708 done: 2709 kfree(smc_state); 2710 2711 return ret; 2712 } 2713 2714 static int ni_set_mc_special_registers(struct radeon_device *rdev, 2715 struct ni_mc_reg_table *table) 2716 { 2717 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 2718 u8 i, j, k; 2719 u32 temp_reg; 2720 2721 for (i = 0, j = table->last; i < table->last; i++) { 2722 switch (table->mc_reg_address[i].s1) { 2723 case MC_SEQ_MISC1 >> 2: 2724 if (j >= SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE) 2725 return -EINVAL; 2726 temp_reg = RREG32(MC_PMG_CMD_EMRS); 2727 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2; 2728 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2; 2729 for (k = 0; k < table->num_entries; k++) 2730 table->mc_reg_table_entry[k].mc_data[j] = 2731 ((temp_reg & 0xffff0000)) | 2732 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); 2733 j++; 2734 if (j >= SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE) 2735 return -EINVAL; 2736 2737 temp_reg = RREG32(MC_PMG_CMD_MRS); 2738 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2; 2739 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2; 2740 for(k = 0; k < table->num_entries; k++) { 2741 table->mc_reg_table_entry[k].mc_data[j] = 2742 (temp_reg & 0xffff0000) | 2743 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 2744 if (!pi->mem_gddr5) 2745 table->mc_reg_table_entry[k].mc_data[j] |= 0x100; 2746 } 2747 j++; 2748 if (j > SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE) 2749 return -EINVAL; 2750 break; 2751 case MC_SEQ_RESERVE_M >> 2: 2752 temp_reg = RREG32(MC_PMG_CMD_MRS1); 2753 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2; 2754 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2; 2755 for (k = 0; k < table->num_entries; k++) 2756 table->mc_reg_table_entry[k].mc_data[j] = 2757 (temp_reg & 0xffff0000) | 2758 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 2759 j++; 2760 if (j > SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE) 2761 return -EINVAL; 2762 break; 2763 default: 2764 break; 2765 } 2766 } 2767 2768 table->last = j; 2769 2770 return 0; 2771 } 2772 2773 static bool ni_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg) 2774 { 2775 bool result = true; 2776 2777 switch (in_reg) { 2778 case MC_SEQ_RAS_TIMING >> 2: 2779 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2; 2780 break; 2781 case MC_SEQ_CAS_TIMING >> 2: 2782 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2; 2783 break; 2784 case MC_SEQ_MISC_TIMING >> 2: 2785 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2; 2786 break; 2787 case MC_SEQ_MISC_TIMING2 >> 2: 2788 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2; 2789 break; 2790 case MC_SEQ_RD_CTL_D0 >> 2: 2791 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2; 2792 break; 2793 case MC_SEQ_RD_CTL_D1 >> 2: 2794 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2; 2795 break; 2796 case MC_SEQ_WR_CTL_D0 >> 2: 2797 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2; 2798 break; 2799 case MC_SEQ_WR_CTL_D1 >> 2: 2800 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2; 2801 break; 2802 case MC_PMG_CMD_EMRS >> 2: 2803 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2; 2804 break; 2805 case MC_PMG_CMD_MRS >> 2: 2806 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2; 2807 break; 2808 case MC_PMG_CMD_MRS1 >> 2: 2809 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2; 2810 break; 2811 case MC_SEQ_PMG_TIMING >> 2: 2812 *out_reg = MC_SEQ_PMG_TIMING_LP >> 2; 2813 break; 2814 case MC_PMG_CMD_MRS2 >> 2: 2815 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2; 2816 break; 2817 default: 2818 result = false; 2819 break; 2820 } 2821 2822 return result; 2823 } 2824 2825 static void ni_set_valid_flag(struct ni_mc_reg_table *table) 2826 { 2827 u8 i, j; 2828 2829 for (i = 0; i < table->last; i++) { 2830 for (j = 1; j < table->num_entries; j++) { 2831 if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) { 2832 table->valid_flag |= 1 << i; 2833 break; 2834 } 2835 } 2836 } 2837 } 2838 2839 static void ni_set_s0_mc_reg_index(struct ni_mc_reg_table *table) 2840 { 2841 u32 i; 2842 u16 address; 2843 2844 for (i = 0; i < table->last; i++) 2845 table->mc_reg_address[i].s0 = 2846 ni_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ? 2847 address : table->mc_reg_address[i].s1; 2848 } 2849 2850 static int ni_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table, 2851 struct ni_mc_reg_table *ni_table) 2852 { 2853 u8 i, j; 2854 2855 if (table->last > SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE) 2856 return -EINVAL; 2857 if (table->num_entries > MAX_AC_TIMING_ENTRIES) 2858 return -EINVAL; 2859 2860 for (i = 0; i < table->last; i++) 2861 ni_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1; 2862 ni_table->last = table->last; 2863 2864 for (i = 0; i < table->num_entries; i++) { 2865 ni_table->mc_reg_table_entry[i].mclk_max = 2866 table->mc_reg_table_entry[i].mclk_max; 2867 for (j = 0; j < table->last; j++) 2868 ni_table->mc_reg_table_entry[i].mc_data[j] = 2869 table->mc_reg_table_entry[i].mc_data[j]; 2870 } 2871 ni_table->num_entries = table->num_entries; 2872 2873 return 0; 2874 } 2875 2876 static int ni_initialize_mc_reg_table(struct radeon_device *rdev) 2877 { 2878 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2879 int ret; 2880 struct atom_mc_reg_table *table; 2881 struct ni_mc_reg_table *ni_table = &ni_pi->mc_reg_table; 2882 u8 module_index = rv770_get_memory_module_index(rdev); 2883 2884 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL); 2885 if (!table) 2886 return -ENOMEM; 2887 2888 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING)); 2889 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING)); 2890 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING)); 2891 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2)); 2892 WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS)); 2893 WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS)); 2894 WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1)); 2895 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0)); 2896 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1)); 2897 WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0)); 2898 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1)); 2899 WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING)); 2900 WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2)); 2901 2902 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table); 2903 2904 if (ret) 2905 goto init_mc_done; 2906 2907 ret = ni_copy_vbios_mc_reg_table(table, ni_table); 2908 2909 if (ret) 2910 goto init_mc_done; 2911 2912 ni_set_s0_mc_reg_index(ni_table); 2913 2914 ret = ni_set_mc_special_registers(rdev, ni_table); 2915 2916 if (ret) 2917 goto init_mc_done; 2918 2919 ni_set_valid_flag(ni_table); 2920 2921 init_mc_done: 2922 kfree(table); 2923 2924 return ret; 2925 } 2926 2927 static void ni_populate_mc_reg_addresses(struct radeon_device *rdev, 2928 SMC_NIslands_MCRegisters *mc_reg_table) 2929 { 2930 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2931 u32 i, j; 2932 2933 for (i = 0, j = 0; j < ni_pi->mc_reg_table.last; j++) { 2934 if (ni_pi->mc_reg_table.valid_flag & (1 << j)) { 2935 if (i >= SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE) 2936 break; 2937 mc_reg_table->address[i].s0 = 2938 cpu_to_be16(ni_pi->mc_reg_table.mc_reg_address[j].s0); 2939 mc_reg_table->address[i].s1 = 2940 cpu_to_be16(ni_pi->mc_reg_table.mc_reg_address[j].s1); 2941 i++; 2942 } 2943 } 2944 mc_reg_table->last = (u8)i; 2945 } 2946 2947 2948 static void ni_convert_mc_registers(struct ni_mc_reg_entry *entry, 2949 SMC_NIslands_MCRegisterSet *data, 2950 u32 num_entries, u32 valid_flag) 2951 { 2952 u32 i, j; 2953 2954 for (i = 0, j = 0; j < num_entries; j++) { 2955 if (valid_flag & (1 << j)) { 2956 data->value[i] = cpu_to_be32(entry->mc_data[j]); 2957 i++; 2958 } 2959 } 2960 } 2961 2962 static void ni_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev, 2963 struct rv7xx_pl *pl, 2964 SMC_NIslands_MCRegisterSet *mc_reg_table_data) 2965 { 2966 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2967 u32 i = 0; 2968 2969 for (i = 0; i < ni_pi->mc_reg_table.num_entries; i++) { 2970 if (pl->mclk <= ni_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max) 2971 break; 2972 } 2973 2974 if ((i == ni_pi->mc_reg_table.num_entries) && (i > 0)) 2975 --i; 2976 2977 ni_convert_mc_registers(&ni_pi->mc_reg_table.mc_reg_table_entry[i], 2978 mc_reg_table_data, 2979 ni_pi->mc_reg_table.last, 2980 ni_pi->mc_reg_table.valid_flag); 2981 } 2982 2983 static void ni_convert_mc_reg_table_to_smc(struct radeon_device *rdev, 2984 struct radeon_ps *radeon_state, 2985 SMC_NIslands_MCRegisters *mc_reg_table) 2986 { 2987 struct ni_ps *state = ni_get_ps(radeon_state); 2988 int i; 2989 2990 for (i = 0; i < state->performance_level_count; i++) { 2991 ni_convert_mc_reg_table_entry_to_smc(rdev, 2992 &state->performance_levels[i], 2993 &mc_reg_table->data[NISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]); 2994 } 2995 } 2996 2997 static int ni_populate_mc_reg_table(struct radeon_device *rdev, 2998 struct radeon_ps *radeon_boot_state) 2999 { 3000 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3001 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3002 struct ni_power_info *ni_pi = ni_get_pi(rdev); 3003 struct ni_ps *boot_state = ni_get_ps(radeon_boot_state); 3004 SMC_NIslands_MCRegisters *mc_reg_table = &ni_pi->smc_mc_reg_table; 3005 3006 memset(mc_reg_table, 0, sizeof(SMC_NIslands_MCRegisters)); 3007 3008 rv770_write_smc_soft_register(rdev, NI_SMC_SOFT_REGISTER_seq_index, 1); 3009 3010 ni_populate_mc_reg_addresses(rdev, mc_reg_table); 3011 3012 ni_convert_mc_reg_table_entry_to_smc(rdev, &boot_state->performance_levels[0], 3013 &mc_reg_table->data[0]); 3014 3015 ni_convert_mc_registers(&ni_pi->mc_reg_table.mc_reg_table_entry[0], 3016 &mc_reg_table->data[1], 3017 ni_pi->mc_reg_table.last, 3018 ni_pi->mc_reg_table.valid_flag); 3019 3020 ni_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, mc_reg_table); 3021 3022 return rv770_copy_bytes_to_smc(rdev, eg_pi->mc_reg_table_start, 3023 (u8 *)mc_reg_table, 3024 sizeof(SMC_NIslands_MCRegisters), 3025 pi->sram_end); 3026 } 3027 3028 static int ni_upload_mc_reg_table(struct radeon_device *rdev, 3029 struct radeon_ps *radeon_new_state) 3030 { 3031 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3032 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3033 struct ni_power_info *ni_pi = ni_get_pi(rdev); 3034 struct ni_ps *ni_new_state = ni_get_ps(radeon_new_state); 3035 SMC_NIslands_MCRegisters *mc_reg_table = &ni_pi->smc_mc_reg_table; 3036 u16 address; 3037 3038 memset(mc_reg_table, 0, sizeof(SMC_NIslands_MCRegisters)); 3039 3040 ni_convert_mc_reg_table_to_smc(rdev, radeon_new_state, mc_reg_table); 3041 3042 address = eg_pi->mc_reg_table_start + 3043 (u16)offsetof(SMC_NIslands_MCRegisters, data[NISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]); 3044 3045 return rv770_copy_bytes_to_smc(rdev, address, 3046 (u8 *)&mc_reg_table->data[NISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT], 3047 sizeof(SMC_NIslands_MCRegisterSet) * ni_new_state->performance_level_count, 3048 pi->sram_end); 3049 } 3050 3051 static int ni_init_driver_calculated_leakage_table(struct radeon_device *rdev, 3052 PP_NIslands_CACTABLES *cac_tables) 3053 { 3054 struct ni_power_info *ni_pi = ni_get_pi(rdev); 3055 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3056 u32 leakage = 0; 3057 unsigned int i, j, table_size; 3058 s32 t; 3059 u32 smc_leakage, max_leakage = 0; 3060 u32 scaling_factor; 3061 3062 table_size = eg_pi->vddc_voltage_table.count; 3063 3064 if (SMC_NISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES < table_size) 3065 table_size = SMC_NISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; 3066 3067 scaling_factor = ni_get_smc_power_scaling_factor(rdev); 3068 3069 for (i = 0; i < SMC_NISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES; i++) { 3070 for (j = 0; j < table_size; j++) { 3071 t = (1000 * ((i + 1) * 8)); 3072 3073 if (t < ni_pi->cac_data.leakage_minimum_temperature) 3074 t = ni_pi->cac_data.leakage_minimum_temperature; 3075 3076 ni_calculate_leakage_for_v_and_t(rdev, 3077 &ni_pi->cac_data.leakage_coefficients, 3078 eg_pi->vddc_voltage_table.entries[j].value, 3079 t, 3080 ni_pi->cac_data.i_leakage, 3081 &leakage); 3082 3083 smc_leakage = ni_scale_power_for_smc(leakage, scaling_factor) / 1000; 3084 if (smc_leakage > max_leakage) 3085 max_leakage = smc_leakage; 3086 3087 cac_tables->cac_lkge_lut[i][j] = cpu_to_be32(smc_leakage); 3088 } 3089 } 3090 3091 for (j = table_size; j < SMC_NISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) { 3092 for (i = 0; i < SMC_NISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES; i++) 3093 cac_tables->cac_lkge_lut[i][j] = cpu_to_be32(max_leakage); 3094 } 3095 return 0; 3096 } 3097 3098 static int ni_init_simplified_leakage_table(struct radeon_device *rdev, 3099 PP_NIslands_CACTABLES *cac_tables) 3100 { 3101 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3102 struct radeon_cac_leakage_table *leakage_table = 3103 &rdev->pm.dpm.dyn_state.cac_leakage_table; 3104 u32 i, j, table_size; 3105 u32 smc_leakage, max_leakage = 0; 3106 u32 scaling_factor; 3107 3108 if (!leakage_table) 3109 return -EINVAL; 3110 3111 table_size = leakage_table->count; 3112 3113 if (eg_pi->vddc_voltage_table.count != table_size) 3114 table_size = (eg_pi->vddc_voltage_table.count < leakage_table->count) ? 3115 eg_pi->vddc_voltage_table.count : leakage_table->count; 3116 3117 if (SMC_NISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES < table_size) 3118 table_size = SMC_NISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; 3119 3120 if (table_size == 0) 3121 return -EINVAL; 3122 3123 scaling_factor = ni_get_smc_power_scaling_factor(rdev); 3124 3125 for (j = 0; j < table_size; j++) { 3126 smc_leakage = leakage_table->entries[j].leakage; 3127 3128 if (smc_leakage > max_leakage) 3129 max_leakage = smc_leakage; 3130 3131 for (i = 0; i < SMC_NISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES; i++) 3132 cac_tables->cac_lkge_lut[i][j] = 3133 cpu_to_be32(ni_scale_power_for_smc(smc_leakage, scaling_factor)); 3134 } 3135 3136 for (j = table_size; j < SMC_NISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) { 3137 for (i = 0; i < SMC_NISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES; i++) 3138 cac_tables->cac_lkge_lut[i][j] = 3139 cpu_to_be32(ni_scale_power_for_smc(max_leakage, scaling_factor)); 3140 } 3141 return 0; 3142 } 3143 3144 static int ni_initialize_smc_cac_tables(struct radeon_device *rdev) 3145 { 3146 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3147 struct ni_power_info *ni_pi = ni_get_pi(rdev); 3148 PP_NIslands_CACTABLES *cac_tables = NULL; 3149 int i, ret; 3150 u32 reg; 3151 3152 if (ni_pi->enable_cac == false) 3153 return 0; 3154 3155 cac_tables = kzalloc(sizeof(PP_NIslands_CACTABLES), GFP_KERNEL); 3156 if (!cac_tables) 3157 return -ENOMEM; 3158 3159 reg = RREG32(CG_CAC_CTRL) & ~(TID_CNT_MASK | TID_UNIT_MASK); 3160 reg |= (TID_CNT(ni_pi->cac_weights->tid_cnt) | 3161 TID_UNIT(ni_pi->cac_weights->tid_unit)); 3162 WREG32(CG_CAC_CTRL, reg); 3163 3164 for (i = 0; i < NISLANDS_DCCAC_MAX_LEVELS; i++) 3165 ni_pi->dc_cac_table[i] = ni_pi->cac_weights->dc_cac[i]; 3166 3167 for (i = 0; i < SMC_NISLANDS_BIF_LUT_NUM_OF_ENTRIES; i++) 3168 cac_tables->cac_bif_lut[i] = ni_pi->cac_weights->pcie_cac[i]; 3169 3170 ni_pi->cac_data.i_leakage = rdev->pm.dpm.cac_leakage; 3171 ni_pi->cac_data.pwr_const = 0; 3172 ni_pi->cac_data.dc_cac_value = ni_pi->dc_cac_table[NISLANDS_DCCAC_LEVEL_0]; 3173 ni_pi->cac_data.bif_cac_value = 0; 3174 ni_pi->cac_data.mc_wr_weight = ni_pi->cac_weights->mc_write_weight; 3175 ni_pi->cac_data.mc_rd_weight = ni_pi->cac_weights->mc_read_weight; 3176 ni_pi->cac_data.allow_ovrflw = 0; 3177 ni_pi->cac_data.l2num_win_tdp = ni_pi->lta_window_size; 3178 ni_pi->cac_data.num_win_tdp = 0; 3179 ni_pi->cac_data.lts_truncate_n = ni_pi->lts_truncate; 3180 3181 if (ni_pi->driver_calculate_cac_leakage) 3182 ret = ni_init_driver_calculated_leakage_table(rdev, cac_tables); 3183 else 3184 ret = ni_init_simplified_leakage_table(rdev, cac_tables); 3185 3186 if (ret) 3187 goto done_free; 3188 3189 cac_tables->pwr_const = cpu_to_be32(ni_pi->cac_data.pwr_const); 3190 cac_tables->dc_cacValue = cpu_to_be32(ni_pi->cac_data.dc_cac_value); 3191 cac_tables->bif_cacValue = cpu_to_be32(ni_pi->cac_data.bif_cac_value); 3192 cac_tables->AllowOvrflw = ni_pi->cac_data.allow_ovrflw; 3193 cac_tables->MCWrWeight = ni_pi->cac_data.mc_wr_weight; 3194 cac_tables->MCRdWeight = ni_pi->cac_data.mc_rd_weight; 3195 cac_tables->numWin_TDP = ni_pi->cac_data.num_win_tdp; 3196 cac_tables->l2numWin_TDP = ni_pi->cac_data.l2num_win_tdp; 3197 cac_tables->lts_truncate_n = ni_pi->cac_data.lts_truncate_n; 3198 3199 ret = rv770_copy_bytes_to_smc(rdev, ni_pi->cac_table_start, (u8 *)cac_tables, 3200 sizeof(PP_NIslands_CACTABLES), pi->sram_end); 3201 3202 done_free: 3203 if (ret) { 3204 ni_pi->enable_cac = false; 3205 ni_pi->enable_power_containment = false; 3206 } 3207 3208 kfree(cac_tables); 3209 3210 return 0; 3211 } 3212 3213 static int ni_initialize_hardware_cac_manager(struct radeon_device *rdev) 3214 { 3215 struct ni_power_info *ni_pi = ni_get_pi(rdev); 3216 u32 reg; 3217 3218 if (!ni_pi->enable_cac || 3219 !ni_pi->cac_configuration_required) 3220 return 0; 3221 3222 if (ni_pi->cac_weights == NULL) 3223 return -EINVAL; 3224 3225 reg = RREG32_CG(CG_CAC_REGION_1_WEIGHT_0) & ~(WEIGHT_TCP_SIG0_MASK | 3226 WEIGHT_TCP_SIG1_MASK | 3227 WEIGHT_TA_SIG_MASK); 3228 reg |= (WEIGHT_TCP_SIG0(ni_pi->cac_weights->weight_tcp_sig0) | 3229 WEIGHT_TCP_SIG1(ni_pi->cac_weights->weight_tcp_sig1) | 3230 WEIGHT_TA_SIG(ni_pi->cac_weights->weight_ta_sig)); 3231 WREG32_CG(CG_CAC_REGION_1_WEIGHT_0, reg); 3232 3233 reg = RREG32_CG(CG_CAC_REGION_1_WEIGHT_1) & ~(WEIGHT_TCC_EN0_MASK | 3234 WEIGHT_TCC_EN1_MASK | 3235 WEIGHT_TCC_EN2_MASK); 3236 reg |= (WEIGHT_TCC_EN0(ni_pi->cac_weights->weight_tcc_en0) | 3237 WEIGHT_TCC_EN1(ni_pi->cac_weights->weight_tcc_en1) | 3238 WEIGHT_TCC_EN2(ni_pi->cac_weights->weight_tcc_en2)); 3239 WREG32_CG(CG_CAC_REGION_1_WEIGHT_1, reg); 3240 3241 reg = RREG32_CG(CG_CAC_REGION_2_WEIGHT_0) & ~(WEIGHT_CB_EN0_MASK | 3242 WEIGHT_CB_EN1_MASK | 3243 WEIGHT_CB_EN2_MASK | 3244 WEIGHT_CB_EN3_MASK); 3245 reg |= (WEIGHT_CB_EN0(ni_pi->cac_weights->weight_cb_en0) | 3246 WEIGHT_CB_EN1(ni_pi->cac_weights->weight_cb_en1) | 3247 WEIGHT_CB_EN2(ni_pi->cac_weights->weight_cb_en2) | 3248 WEIGHT_CB_EN3(ni_pi->cac_weights->weight_cb_en3)); 3249 WREG32_CG(CG_CAC_REGION_2_WEIGHT_0, reg); 3250 3251 reg = RREG32_CG(CG_CAC_REGION_2_WEIGHT_1) & ~(WEIGHT_DB_SIG0_MASK | 3252 WEIGHT_DB_SIG1_MASK | 3253 WEIGHT_DB_SIG2_MASK | 3254 WEIGHT_DB_SIG3_MASK); 3255 reg |= (WEIGHT_DB_SIG0(ni_pi->cac_weights->weight_db_sig0) | 3256 WEIGHT_DB_SIG1(ni_pi->cac_weights->weight_db_sig1) | 3257 WEIGHT_DB_SIG2(ni_pi->cac_weights->weight_db_sig2) | 3258 WEIGHT_DB_SIG3(ni_pi->cac_weights->weight_db_sig3)); 3259 WREG32_CG(CG_CAC_REGION_2_WEIGHT_1, reg); 3260 3261 reg = RREG32_CG(CG_CAC_REGION_2_WEIGHT_2) & ~(WEIGHT_SXM_SIG0_MASK | 3262 WEIGHT_SXM_SIG1_MASK | 3263 WEIGHT_SXM_SIG2_MASK | 3264 WEIGHT_SXS_SIG0_MASK | 3265 WEIGHT_SXS_SIG1_MASK); 3266 reg |= (WEIGHT_SXM_SIG0(ni_pi->cac_weights->weight_sxm_sig0) | 3267 WEIGHT_SXM_SIG1(ni_pi->cac_weights->weight_sxm_sig1) | 3268 WEIGHT_SXM_SIG2(ni_pi->cac_weights->weight_sxm_sig2) | 3269 WEIGHT_SXS_SIG0(ni_pi->cac_weights->weight_sxs_sig0) | 3270 WEIGHT_SXS_SIG1(ni_pi->cac_weights->weight_sxs_sig1)); 3271 WREG32_CG(CG_CAC_REGION_2_WEIGHT_2, reg); 3272 3273 reg = RREG32_CG(CG_CAC_REGION_3_WEIGHT_0) & ~(WEIGHT_XBR_0_MASK | 3274 WEIGHT_XBR_1_MASK | 3275 WEIGHT_XBR_2_MASK | 3276 WEIGHT_SPI_SIG0_MASK); 3277 reg |= (WEIGHT_XBR_0(ni_pi->cac_weights->weight_xbr_0) | 3278 WEIGHT_XBR_1(ni_pi->cac_weights->weight_xbr_1) | 3279 WEIGHT_XBR_2(ni_pi->cac_weights->weight_xbr_2) | 3280 WEIGHT_SPI_SIG0(ni_pi->cac_weights->weight_spi_sig0)); 3281 WREG32_CG(CG_CAC_REGION_3_WEIGHT_0, reg); 3282 3283 reg = RREG32_CG(CG_CAC_REGION_3_WEIGHT_1) & ~(WEIGHT_SPI_SIG1_MASK | 3284 WEIGHT_SPI_SIG2_MASK | 3285 WEIGHT_SPI_SIG3_MASK | 3286 WEIGHT_SPI_SIG4_MASK | 3287 WEIGHT_SPI_SIG5_MASK); 3288 reg |= (WEIGHT_SPI_SIG1(ni_pi->cac_weights->weight_spi_sig1) | 3289 WEIGHT_SPI_SIG2(ni_pi->cac_weights->weight_spi_sig2) | 3290 WEIGHT_SPI_SIG3(ni_pi->cac_weights->weight_spi_sig3) | 3291 WEIGHT_SPI_SIG4(ni_pi->cac_weights->weight_spi_sig4) | 3292 WEIGHT_SPI_SIG5(ni_pi->cac_weights->weight_spi_sig5)); 3293 WREG32_CG(CG_CAC_REGION_3_WEIGHT_1, reg); 3294 3295 reg = RREG32_CG(CG_CAC_REGION_4_WEIGHT_0) & ~(WEIGHT_LDS_SIG0_MASK | 3296 WEIGHT_LDS_SIG1_MASK | 3297 WEIGHT_SC_MASK); 3298 reg |= (WEIGHT_LDS_SIG0(ni_pi->cac_weights->weight_lds_sig0) | 3299 WEIGHT_LDS_SIG1(ni_pi->cac_weights->weight_lds_sig1) | 3300 WEIGHT_SC(ni_pi->cac_weights->weight_sc)); 3301 WREG32_CG(CG_CAC_REGION_4_WEIGHT_0, reg); 3302 3303 reg = RREG32_CG(CG_CAC_REGION_4_WEIGHT_1) & ~(WEIGHT_BIF_MASK | 3304 WEIGHT_CP_MASK | 3305 WEIGHT_PA_SIG0_MASK | 3306 WEIGHT_PA_SIG1_MASK | 3307 WEIGHT_VGT_SIG0_MASK); 3308 reg |= (WEIGHT_BIF(ni_pi->cac_weights->weight_bif) | 3309 WEIGHT_CP(ni_pi->cac_weights->weight_cp) | 3310 WEIGHT_PA_SIG0(ni_pi->cac_weights->weight_pa_sig0) | 3311 WEIGHT_PA_SIG1(ni_pi->cac_weights->weight_pa_sig1) | 3312 WEIGHT_VGT_SIG0(ni_pi->cac_weights->weight_vgt_sig0)); 3313 WREG32_CG(CG_CAC_REGION_4_WEIGHT_1, reg); 3314 3315 reg = RREG32_CG(CG_CAC_REGION_4_WEIGHT_2) & ~(WEIGHT_VGT_SIG1_MASK | 3316 WEIGHT_VGT_SIG2_MASK | 3317 WEIGHT_DC_SIG0_MASK | 3318 WEIGHT_DC_SIG1_MASK | 3319 WEIGHT_DC_SIG2_MASK); 3320 reg |= (WEIGHT_VGT_SIG1(ni_pi->cac_weights->weight_vgt_sig1) | 3321 WEIGHT_VGT_SIG2(ni_pi->cac_weights->weight_vgt_sig2) | 3322 WEIGHT_DC_SIG0(ni_pi->cac_weights->weight_dc_sig0) | 3323 WEIGHT_DC_SIG1(ni_pi->cac_weights->weight_dc_sig1) | 3324 WEIGHT_DC_SIG2(ni_pi->cac_weights->weight_dc_sig2)); 3325 WREG32_CG(CG_CAC_REGION_4_WEIGHT_2, reg); 3326 3327 reg = RREG32_CG(CG_CAC_REGION_4_WEIGHT_3) & ~(WEIGHT_DC_SIG3_MASK | 3328 WEIGHT_UVD_SIG0_MASK | 3329 WEIGHT_UVD_SIG1_MASK | 3330 WEIGHT_SPARE0_MASK | 3331 WEIGHT_SPARE1_MASK); 3332 reg |= (WEIGHT_DC_SIG3(ni_pi->cac_weights->weight_dc_sig3) | 3333 WEIGHT_UVD_SIG0(ni_pi->cac_weights->weight_uvd_sig0) | 3334 WEIGHT_UVD_SIG1(ni_pi->cac_weights->weight_uvd_sig1) | 3335 WEIGHT_SPARE0(ni_pi->cac_weights->weight_spare0) | 3336 WEIGHT_SPARE1(ni_pi->cac_weights->weight_spare1)); 3337 WREG32_CG(CG_CAC_REGION_4_WEIGHT_3, reg); 3338 3339 reg = RREG32_CG(CG_CAC_REGION_5_WEIGHT_0) & ~(WEIGHT_SQ_VSP_MASK | 3340 WEIGHT_SQ_VSP0_MASK); 3341 reg |= (WEIGHT_SQ_VSP(ni_pi->cac_weights->weight_sq_vsp) | 3342 WEIGHT_SQ_VSP0(ni_pi->cac_weights->weight_sq_vsp0)); 3343 WREG32_CG(CG_CAC_REGION_5_WEIGHT_0, reg); 3344 3345 reg = RREG32_CG(CG_CAC_REGION_5_WEIGHT_1) & ~(WEIGHT_SQ_GPR_MASK); 3346 reg |= WEIGHT_SQ_GPR(ni_pi->cac_weights->weight_sq_gpr); 3347 WREG32_CG(CG_CAC_REGION_5_WEIGHT_1, reg); 3348 3349 reg = RREG32_CG(CG_CAC_REGION_4_OVERRIDE_4) & ~(OVR_MODE_SPARE_0_MASK | 3350 OVR_VAL_SPARE_0_MASK | 3351 OVR_MODE_SPARE_1_MASK | 3352 OVR_VAL_SPARE_1_MASK); 3353 reg |= (OVR_MODE_SPARE_0(ni_pi->cac_weights->ovr_mode_spare_0) | 3354 OVR_VAL_SPARE_0(ni_pi->cac_weights->ovr_val_spare_0) | 3355 OVR_MODE_SPARE_1(ni_pi->cac_weights->ovr_mode_spare_1) | 3356 OVR_VAL_SPARE_1(ni_pi->cac_weights->ovr_val_spare_1)); 3357 WREG32_CG(CG_CAC_REGION_4_OVERRIDE_4, reg); 3358 3359 reg = RREG32(SQ_CAC_THRESHOLD) & ~(VSP_MASK | 3360 VSP0_MASK | 3361 GPR_MASK); 3362 reg |= (VSP(ni_pi->cac_weights->vsp) | 3363 VSP0(ni_pi->cac_weights->vsp0) | 3364 GPR(ni_pi->cac_weights->gpr)); 3365 WREG32(SQ_CAC_THRESHOLD, reg); 3366 3367 reg = (MCDW_WR_ENABLE | 3368 MCDX_WR_ENABLE | 3369 MCDY_WR_ENABLE | 3370 MCDZ_WR_ENABLE | 3371 INDEX(0x09D4)); 3372 WREG32(MC_CG_CONFIG, reg); 3373 3374 reg = (READ_WEIGHT(ni_pi->cac_weights->mc_read_weight) | 3375 WRITE_WEIGHT(ni_pi->cac_weights->mc_write_weight) | 3376 ALLOW_OVERFLOW); 3377 WREG32(MC_CG_DATAPORT, reg); 3378 3379 return 0; 3380 } 3381 3382 static int ni_enable_smc_cac(struct radeon_device *rdev, 3383 struct radeon_ps *radeon_new_state, 3384 bool enable) 3385 { 3386 struct ni_power_info *ni_pi = ni_get_pi(rdev); 3387 int ret = 0; 3388 PPSMC_Result smc_result; 3389 3390 if (ni_pi->enable_cac) { 3391 if (enable) { 3392 if (!r600_is_uvd_state(radeon_new_state->class, radeon_new_state->class2)) { 3393 smc_result = rv770_send_msg_to_smc(rdev, PPSMC_MSG_CollectCAC_PowerCorreln); 3394 3395 if (ni_pi->support_cac_long_term_average) { 3396 smc_result = rv770_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgEnable); 3397 if (PPSMC_Result_OK != smc_result) 3398 ni_pi->support_cac_long_term_average = false; 3399 } 3400 3401 smc_result = rv770_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac); 3402 if (PPSMC_Result_OK != smc_result) 3403 ret = -EINVAL; 3404 3405 ni_pi->cac_enabled = (PPSMC_Result_OK == smc_result) ? true : false; 3406 } 3407 } else if (ni_pi->cac_enabled) { 3408 smc_result = rv770_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac); 3409 3410 ni_pi->cac_enabled = false; 3411 3412 if (ni_pi->support_cac_long_term_average) { 3413 smc_result = rv770_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgDisable); 3414 if (PPSMC_Result_OK != smc_result) 3415 ni_pi->support_cac_long_term_average = false; 3416 } 3417 } 3418 } 3419 3420 return ret; 3421 } 3422 3423 static int ni_pcie_performance_request(struct radeon_device *rdev, 3424 u8 perf_req, bool advertise) 3425 { 3426 #if defined(CONFIG_ACPI) 3427 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3428 3429 if ((perf_req == PCIE_PERF_REQ_PECI_GEN1) || 3430 (perf_req == PCIE_PERF_REQ_PECI_GEN2)) { 3431 if (eg_pi->pcie_performance_request_registered == false) 3432 radeon_acpi_pcie_notify_device_ready(rdev); 3433 eg_pi->pcie_performance_request_registered = true; 3434 return radeon_acpi_pcie_performance_request(rdev, perf_req, advertise); 3435 } else if ((perf_req == PCIE_PERF_REQ_REMOVE_REGISTRY) && 3436 eg_pi->pcie_performance_request_registered) { 3437 eg_pi->pcie_performance_request_registered = false; 3438 return radeon_acpi_pcie_performance_request(rdev, perf_req, advertise); 3439 } 3440 #endif 3441 return 0; 3442 } 3443 3444 static int ni_advertise_gen2_capability(struct radeon_device *rdev) 3445 { 3446 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3447 u32 tmp; 3448 3449 tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 3450 3451 if ((tmp & LC_OTHER_SIDE_EVER_SENT_GEN2) && 3452 (tmp & LC_OTHER_SIDE_SUPPORTS_GEN2)) 3453 pi->pcie_gen2 = true; 3454 else 3455 pi->pcie_gen2 = false; 3456 3457 if (!pi->pcie_gen2) 3458 ni_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, true); 3459 3460 return 0; 3461 } 3462 3463 static void ni_enable_bif_dynamic_pcie_gen2(struct radeon_device *rdev, 3464 bool enable) 3465 { 3466 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3467 u32 tmp, bif; 3468 3469 tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 3470 3471 if ((tmp & LC_OTHER_SIDE_EVER_SENT_GEN2) && 3472 (tmp & LC_OTHER_SIDE_SUPPORTS_GEN2)) { 3473 if (enable) { 3474 if (!pi->boot_in_gen2) { 3475 bif = RREG32(CG_BIF_REQ_AND_RSP) & ~CG_CLIENT_REQ_MASK; 3476 bif |= CG_CLIENT_REQ(0xd); 3477 WREG32(CG_BIF_REQ_AND_RSP, bif); 3478 } 3479 tmp &= ~LC_HW_VOLTAGE_IF_CONTROL_MASK; 3480 tmp |= LC_HW_VOLTAGE_IF_CONTROL(1); 3481 tmp |= LC_GEN2_EN_STRAP; 3482 3483 tmp |= LC_CLR_FAILED_SPD_CHANGE_CNT; 3484 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp); 3485 udelay(10); 3486 tmp &= ~LC_CLR_FAILED_SPD_CHANGE_CNT; 3487 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp); 3488 } else { 3489 if (!pi->boot_in_gen2) { 3490 bif = RREG32(CG_BIF_REQ_AND_RSP) & ~CG_CLIENT_REQ_MASK; 3491 bif |= CG_CLIENT_REQ(0xd); 3492 WREG32(CG_BIF_REQ_AND_RSP, bif); 3493 3494 tmp &= ~LC_HW_VOLTAGE_IF_CONTROL_MASK; 3495 tmp &= ~LC_GEN2_EN_STRAP; 3496 } 3497 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp); 3498 } 3499 } 3500 } 3501 3502 static void ni_enable_dynamic_pcie_gen2(struct radeon_device *rdev, 3503 bool enable) 3504 { 3505 ni_enable_bif_dynamic_pcie_gen2(rdev, enable); 3506 3507 if (enable) 3508 WREG32_P(GENERAL_PWRMGT, ENABLE_GEN2PCIE, ~ENABLE_GEN2PCIE); 3509 else 3510 WREG32_P(GENERAL_PWRMGT, 0, ~ENABLE_GEN2PCIE); 3511 } 3512 3513 void ni_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev, 3514 struct radeon_ps *new_ps, 3515 struct radeon_ps *old_ps) 3516 { 3517 struct ni_ps *new_state = ni_get_ps(new_ps); 3518 struct ni_ps *current_state = ni_get_ps(old_ps); 3519 3520 if ((new_ps->vclk == old_ps->vclk) && 3521 (new_ps->dclk == old_ps->dclk)) 3522 return; 3523 3524 if (new_state->performance_levels[new_state->performance_level_count - 1].sclk >= 3525 current_state->performance_levels[current_state->performance_level_count - 1].sclk) 3526 return; 3527 3528 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); 3529 } 3530 3531 void ni_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev, 3532 struct radeon_ps *new_ps, 3533 struct radeon_ps *old_ps) 3534 { 3535 struct ni_ps *new_state = ni_get_ps(new_ps); 3536 struct ni_ps *current_state = ni_get_ps(old_ps); 3537 3538 if ((new_ps->vclk == old_ps->vclk) && 3539 (new_ps->dclk == old_ps->dclk)) 3540 return; 3541 3542 if (new_state->performance_levels[new_state->performance_level_count - 1].sclk < 3543 current_state->performance_levels[current_state->performance_level_count - 1].sclk) 3544 return; 3545 3546 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); 3547 } 3548 3549 void ni_dpm_setup_asic(struct radeon_device *rdev) 3550 { 3551 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3552 int r; 3553 3554 r = ni_mc_load_microcode(rdev); 3555 if (r) 3556 DRM_ERROR("Failed to load MC firmware!\n"); 3557 ni_read_clock_registers(rdev); 3558 btc_read_arb_registers(rdev); 3559 rv770_get_memory_type(rdev); 3560 if (eg_pi->pcie_performance_request) 3561 ni_advertise_gen2_capability(rdev); 3562 rv770_get_pcie_gen2_status(rdev); 3563 rv770_enable_acpi_pm(rdev); 3564 } 3565 3566 void ni_update_current_ps(struct radeon_device *rdev, 3567 struct radeon_ps *rps) 3568 { 3569 struct ni_ps *new_ps = ni_get_ps(rps); 3570 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3571 struct ni_power_info *ni_pi = ni_get_pi(rdev); 3572 3573 eg_pi->current_rps = *rps; 3574 ni_pi->current_ps = *new_ps; 3575 eg_pi->current_rps.ps_priv = &ni_pi->current_ps; 3576 } 3577 3578 void ni_update_requested_ps(struct radeon_device *rdev, 3579 struct radeon_ps *rps) 3580 { 3581 struct ni_ps *new_ps = ni_get_ps(rps); 3582 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3583 struct ni_power_info *ni_pi = ni_get_pi(rdev); 3584 3585 eg_pi->requested_rps = *rps; 3586 ni_pi->requested_ps = *new_ps; 3587 eg_pi->requested_rps.ps_priv = &ni_pi->requested_ps; 3588 } 3589 3590 int ni_dpm_enable(struct radeon_device *rdev) 3591 { 3592 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3593 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3594 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; 3595 int ret; 3596 3597 if (pi->gfx_clock_gating) 3598 ni_cg_clockgating_default(rdev); 3599 if (btc_dpm_enabled(rdev)) 3600 return -EINVAL; 3601 if (pi->mg_clock_gating) 3602 ni_mg_clockgating_default(rdev); 3603 if (eg_pi->ls_clock_gating) 3604 ni_ls_clockgating_default(rdev); 3605 if (pi->voltage_control) { 3606 rv770_enable_voltage_control(rdev, true); 3607 ret = cypress_construct_voltage_tables(rdev); 3608 if (ret) { 3609 DRM_ERROR("cypress_construct_voltage_tables failed\n"); 3610 return ret; 3611 } 3612 } 3613 if (eg_pi->dynamic_ac_timing) { 3614 ret = ni_initialize_mc_reg_table(rdev); 3615 if (ret) 3616 eg_pi->dynamic_ac_timing = false; 3617 } 3618 if (pi->dynamic_ss) 3619 cypress_enable_spread_spectrum(rdev, true); 3620 if (pi->thermal_protection) 3621 rv770_enable_thermal_protection(rdev, true); 3622 rv770_setup_bsp(rdev); 3623 rv770_program_git(rdev); 3624 rv770_program_tp(rdev); 3625 rv770_program_tpp(rdev); 3626 rv770_program_sstp(rdev); 3627 cypress_enable_display_gap(rdev); 3628 rv770_program_vc(rdev); 3629 if (pi->dynamic_pcie_gen2) 3630 ni_enable_dynamic_pcie_gen2(rdev, true); 3631 ret = rv770_upload_firmware(rdev); 3632 if (ret) { 3633 DRM_ERROR("rv770_upload_firmware failed\n"); 3634 return ret; 3635 } 3636 ret = ni_process_firmware_header(rdev); 3637 if (ret) { 3638 DRM_ERROR("ni_process_firmware_header failed\n"); 3639 return ret; 3640 } 3641 ret = ni_initial_switch_from_arb_f0_to_f1(rdev); 3642 if (ret) { 3643 DRM_ERROR("ni_initial_switch_from_arb_f0_to_f1 failed\n"); 3644 return ret; 3645 } 3646 ret = ni_init_smc_table(rdev); 3647 if (ret) { 3648 DRM_ERROR("ni_init_smc_table failed\n"); 3649 return ret; 3650 } 3651 ret = ni_init_smc_spll_table(rdev); 3652 if (ret) { 3653 DRM_ERROR("ni_init_smc_spll_table failed\n"); 3654 return ret; 3655 } 3656 ret = ni_init_arb_table_index(rdev); 3657 if (ret) { 3658 DRM_ERROR("ni_init_arb_table_index failed\n"); 3659 return ret; 3660 } 3661 if (eg_pi->dynamic_ac_timing) { 3662 ret = ni_populate_mc_reg_table(rdev, boot_ps); 3663 if (ret) { 3664 DRM_ERROR("ni_populate_mc_reg_table failed\n"); 3665 return ret; 3666 } 3667 } 3668 ret = ni_initialize_smc_cac_tables(rdev); 3669 if (ret) { 3670 DRM_ERROR("ni_initialize_smc_cac_tables failed\n"); 3671 return ret; 3672 } 3673 ret = ni_initialize_hardware_cac_manager(rdev); 3674 if (ret) { 3675 DRM_ERROR("ni_initialize_hardware_cac_manager failed\n"); 3676 return ret; 3677 } 3678 ret = ni_populate_smc_tdp_limits(rdev, boot_ps); 3679 if (ret) { 3680 DRM_ERROR("ni_populate_smc_tdp_limits failed\n"); 3681 return ret; 3682 } 3683 ni_program_response_times(rdev); 3684 r7xx_start_smc(rdev); 3685 ret = cypress_notify_smc_display_change(rdev, false); 3686 if (ret) { 3687 DRM_ERROR("cypress_notify_smc_display_change failed\n"); 3688 return ret; 3689 } 3690 cypress_enable_sclk_control(rdev, true); 3691 if (eg_pi->memory_transition) 3692 cypress_enable_mclk_control(rdev, true); 3693 cypress_start_dpm(rdev); 3694 if (pi->gfx_clock_gating) 3695 ni_gfx_clockgating_enable(rdev, true); 3696 if (pi->mg_clock_gating) 3697 ni_mg_clockgating_enable(rdev, true); 3698 if (eg_pi->ls_clock_gating) 3699 ni_ls_clockgating_enable(rdev, true); 3700 3701 rv770_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true); 3702 3703 ni_update_current_ps(rdev, boot_ps); 3704 3705 return 0; 3706 } 3707 3708 void ni_dpm_disable(struct radeon_device *rdev) 3709 { 3710 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3711 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3712 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; 3713 3714 if (!btc_dpm_enabled(rdev)) 3715 return; 3716 rv770_clear_vc(rdev); 3717 if (pi->thermal_protection) 3718 rv770_enable_thermal_protection(rdev, false); 3719 ni_enable_power_containment(rdev, boot_ps, false); 3720 ni_enable_smc_cac(rdev, boot_ps, false); 3721 cypress_enable_spread_spectrum(rdev, false); 3722 rv770_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false); 3723 if (pi->dynamic_pcie_gen2) 3724 ni_enable_dynamic_pcie_gen2(rdev, false); 3725 3726 if (rdev->irq.installed && 3727 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) { 3728 rdev->irq.dpm_thermal = false; 3729 radeon_irq_set(rdev); 3730 } 3731 3732 if (pi->gfx_clock_gating) 3733 ni_gfx_clockgating_enable(rdev, false); 3734 if (pi->mg_clock_gating) 3735 ni_mg_clockgating_enable(rdev, false); 3736 if (eg_pi->ls_clock_gating) 3737 ni_ls_clockgating_enable(rdev, false); 3738 ni_stop_dpm(rdev); 3739 btc_reset_to_default(rdev); 3740 ni_stop_smc(rdev); 3741 ni_force_switch_to_arb_f0(rdev); 3742 3743 ni_update_current_ps(rdev, boot_ps); 3744 } 3745 3746 static int ni_power_control_set_level(struct radeon_device *rdev) 3747 { 3748 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps; 3749 int ret; 3750 3751 ret = ni_restrict_performance_levels_before_switch(rdev); 3752 if (ret) 3753 return ret; 3754 ret = rv770_halt_smc(rdev); 3755 if (ret) 3756 return ret; 3757 ret = ni_populate_smc_tdp_limits(rdev, new_ps); 3758 if (ret) 3759 return ret; 3760 ret = rv770_resume_smc(rdev); 3761 if (ret) 3762 return ret; 3763 ret = rv770_set_sw_state(rdev); 3764 if (ret) 3765 return ret; 3766 3767 return 0; 3768 } 3769 3770 int ni_dpm_pre_set_power_state(struct radeon_device *rdev) 3771 { 3772 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3773 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps; 3774 struct radeon_ps *new_ps = &requested_ps; 3775 3776 ni_update_requested_ps(rdev, new_ps); 3777 3778 ni_apply_state_adjust_rules(rdev, &eg_pi->requested_rps); 3779 3780 return 0; 3781 } 3782 3783 int ni_dpm_set_power_state(struct radeon_device *rdev) 3784 { 3785 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3786 struct radeon_ps *new_ps = &eg_pi->requested_rps; 3787 struct radeon_ps *old_ps = &eg_pi->current_rps; 3788 int ret; 3789 3790 ret = ni_restrict_performance_levels_before_switch(rdev); 3791 if (ret) { 3792 DRM_ERROR("ni_restrict_performance_levels_before_switch failed\n"); 3793 return ret; 3794 } 3795 ni_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps); 3796 ret = ni_enable_power_containment(rdev, new_ps, false); 3797 if (ret) { 3798 DRM_ERROR("ni_enable_power_containment failed\n"); 3799 return ret; 3800 } 3801 ret = ni_enable_smc_cac(rdev, new_ps, false); 3802 if (ret) { 3803 DRM_ERROR("ni_enable_smc_cac failed\n"); 3804 return ret; 3805 } 3806 ret = rv770_halt_smc(rdev); 3807 if (ret) { 3808 DRM_ERROR("rv770_halt_smc failed\n"); 3809 return ret; 3810 } 3811 if (eg_pi->smu_uvd_hs) 3812 btc_notify_uvd_to_smc(rdev, new_ps); 3813 ret = ni_upload_sw_state(rdev, new_ps); 3814 if (ret) { 3815 DRM_ERROR("ni_upload_sw_state failed\n"); 3816 return ret; 3817 } 3818 if (eg_pi->dynamic_ac_timing) { 3819 ret = ni_upload_mc_reg_table(rdev, new_ps); 3820 if (ret) { 3821 DRM_ERROR("ni_upload_mc_reg_table failed\n"); 3822 return ret; 3823 } 3824 } 3825 ret = ni_program_memory_timing_parameters(rdev, new_ps); 3826 if (ret) { 3827 DRM_ERROR("ni_program_memory_timing_parameters failed\n"); 3828 return ret; 3829 } 3830 ret = rv770_resume_smc(rdev); 3831 if (ret) { 3832 DRM_ERROR("rv770_resume_smc failed\n"); 3833 return ret; 3834 } 3835 ret = rv770_set_sw_state(rdev); 3836 if (ret) { 3837 DRM_ERROR("rv770_set_sw_state failed\n"); 3838 return ret; 3839 } 3840 ni_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps); 3841 ret = ni_enable_smc_cac(rdev, new_ps, true); 3842 if (ret) { 3843 DRM_ERROR("ni_enable_smc_cac failed\n"); 3844 return ret; 3845 } 3846 ret = ni_enable_power_containment(rdev, new_ps, true); 3847 if (ret) { 3848 DRM_ERROR("ni_enable_power_containment failed\n"); 3849 return ret; 3850 } 3851 3852 /* update tdp */ 3853 ret = ni_power_control_set_level(rdev); 3854 if (ret) { 3855 DRM_ERROR("ni_power_control_set_level failed\n"); 3856 return ret; 3857 } 3858 3859 return 0; 3860 } 3861 3862 void ni_dpm_post_set_power_state(struct radeon_device *rdev) 3863 { 3864 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3865 struct radeon_ps *new_ps = &eg_pi->requested_rps; 3866 3867 ni_update_current_ps(rdev, new_ps); 3868 } 3869 3870 #if 0 3871 void ni_dpm_reset_asic(struct radeon_device *rdev) 3872 { 3873 ni_restrict_performance_levels_before_switch(rdev); 3874 rv770_set_boot_state(rdev); 3875 } 3876 #endif 3877 3878 union power_info { 3879 struct _ATOM_POWERPLAY_INFO info; 3880 struct _ATOM_POWERPLAY_INFO_V2 info_2; 3881 struct _ATOM_POWERPLAY_INFO_V3 info_3; 3882 struct _ATOM_PPLIB_POWERPLAYTABLE pplib; 3883 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2; 3884 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3; 3885 }; 3886 3887 union pplib_clock_info { 3888 struct _ATOM_PPLIB_R600_CLOCK_INFO r600; 3889 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780; 3890 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; 3891 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo; 3892 }; 3893 3894 union pplib_power_state { 3895 struct _ATOM_PPLIB_STATE v1; 3896 struct _ATOM_PPLIB_STATE_V2 v2; 3897 }; 3898 3899 static void ni_parse_pplib_non_clock_info(struct radeon_device *rdev, 3900 struct radeon_ps *rps, 3901 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info, 3902 u8 table_rev) 3903 { 3904 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); 3905 rps->class = le16_to_cpu(non_clock_info->usClassification); 3906 rps->class2 = le16_to_cpu(non_clock_info->usClassification2); 3907 3908 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) { 3909 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); 3910 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); 3911 } else if (r600_is_uvd_state(rps->class, rps->class2)) { 3912 rps->vclk = RV770_DEFAULT_VCLK_FREQ; 3913 rps->dclk = RV770_DEFAULT_DCLK_FREQ; 3914 } else { 3915 rps->vclk = 0; 3916 rps->dclk = 0; 3917 } 3918 3919 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) 3920 rdev->pm.dpm.boot_ps = rps; 3921 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) 3922 rdev->pm.dpm.uvd_ps = rps; 3923 } 3924 3925 static void ni_parse_pplib_clock_info(struct radeon_device *rdev, 3926 struct radeon_ps *rps, int index, 3927 union pplib_clock_info *clock_info) 3928 { 3929 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3930 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3931 struct ni_ps *ps = ni_get_ps(rps); 3932 struct rv7xx_pl *pl = &ps->performance_levels[index]; 3933 3934 ps->performance_level_count = index + 1; 3935 3936 pl->sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow); 3937 pl->sclk |= clock_info->evergreen.ucEngineClockHigh << 16; 3938 pl->mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow); 3939 pl->mclk |= clock_info->evergreen.ucMemoryClockHigh << 16; 3940 3941 pl->vddc = le16_to_cpu(clock_info->evergreen.usVDDC); 3942 pl->vddci = le16_to_cpu(clock_info->evergreen.usVDDCI); 3943 pl->flags = le32_to_cpu(clock_info->evergreen.ulFlags); 3944 3945 /* patch up vddc if necessary */ 3946 if (pl->vddc == 0xff01) { 3947 if (pi->max_vddc) 3948 pl->vddc = pi->max_vddc; 3949 } 3950 3951 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) { 3952 pi->acpi_vddc = pl->vddc; 3953 eg_pi->acpi_vddci = pl->vddci; 3954 if (ps->performance_levels[0].flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) 3955 pi->acpi_pcie_gen2 = true; 3956 else 3957 pi->acpi_pcie_gen2 = false; 3958 } 3959 3960 if (rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) { 3961 eg_pi->ulv.supported = true; 3962 eg_pi->ulv.pl = pl; 3963 } 3964 3965 if (pi->min_vddc_in_table > pl->vddc) 3966 pi->min_vddc_in_table = pl->vddc; 3967 3968 if (pi->max_vddc_in_table < pl->vddc) 3969 pi->max_vddc_in_table = pl->vddc; 3970 3971 /* patch up boot state */ 3972 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) { 3973 u16 vddc, vddci, mvdd; 3974 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd); 3975 pl->mclk = rdev->clock.default_mclk; 3976 pl->sclk = rdev->clock.default_sclk; 3977 pl->vddc = vddc; 3978 pl->vddci = vddci; 3979 } 3980 3981 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == 3982 ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) { 3983 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk; 3984 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk; 3985 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc; 3986 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci; 3987 } 3988 } 3989 3990 static int ni_parse_power_table(struct radeon_device *rdev) 3991 { 3992 struct radeon_mode_info *mode_info = &rdev->mode_info; 3993 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; 3994 union pplib_power_state *power_state; 3995 int i, j; 3996 union pplib_clock_info *clock_info; 3997 union power_info *power_info; 3998 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 3999 u16 data_offset; 4000 u8 frev, crev; 4001 struct ni_ps *ps; 4002 4003 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, 4004 &frev, &crev, &data_offset)) 4005 return -EINVAL; 4006 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 4007 4008 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) * 4009 power_info->pplib.ucNumStates, GFP_KERNEL); 4010 if (!rdev->pm.dpm.ps) 4011 return -ENOMEM; 4012 4013 for (i = 0; i < power_info->pplib.ucNumStates; i++) { 4014 power_state = (union pplib_power_state *) 4015 (mode_info->atom_context->bios + data_offset + 4016 le16_to_cpu(power_info->pplib.usStateArrayOffset) + 4017 i * power_info->pplib.ucStateEntrySize); 4018 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) 4019 (mode_info->atom_context->bios + data_offset + 4020 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) + 4021 (power_state->v1.ucNonClockStateIndex * 4022 power_info->pplib.ucNonClockSize)); 4023 if (power_info->pplib.ucStateEntrySize - 1) { 4024 u8 *idx; 4025 ps = kzalloc(sizeof(struct ni_ps), GFP_KERNEL); 4026 if (ps == NULL) { 4027 kfree(rdev->pm.dpm.ps); 4028 return -ENOMEM; 4029 } 4030 rdev->pm.dpm.ps[i].ps_priv = ps; 4031 ni_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i], 4032 non_clock_info, 4033 power_info->pplib.ucNonClockSize); 4034 idx = (u8 *)&power_state->v1.ucClockStateIndices[0]; 4035 for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) { 4036 clock_info = (union pplib_clock_info *) 4037 (mode_info->atom_context->bios + data_offset + 4038 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) + 4039 (idx[j] * power_info->pplib.ucClockInfoSize)); 4040 ni_parse_pplib_clock_info(rdev, 4041 &rdev->pm.dpm.ps[i], j, 4042 clock_info); 4043 } 4044 } 4045 } 4046 rdev->pm.dpm.num_ps = power_info->pplib.ucNumStates; 4047 return 0; 4048 } 4049 4050 int ni_dpm_init(struct radeon_device *rdev) 4051 { 4052 struct rv7xx_power_info *pi; 4053 struct evergreen_power_info *eg_pi; 4054 struct ni_power_info *ni_pi; 4055 struct atom_clock_dividers dividers; 4056 int ret; 4057 4058 ni_pi = kzalloc(sizeof(struct ni_power_info), GFP_KERNEL); 4059 if (ni_pi == NULL) 4060 return -ENOMEM; 4061 rdev->pm.dpm.priv = ni_pi; 4062 eg_pi = &ni_pi->eg; 4063 pi = &eg_pi->rv7xx; 4064 4065 rv770_get_max_vddc(rdev); 4066 4067 eg_pi->ulv.supported = false; 4068 pi->acpi_vddc = 0; 4069 eg_pi->acpi_vddci = 0; 4070 pi->min_vddc_in_table = 0; 4071 pi->max_vddc_in_table = 0; 4072 4073 ret = r600_get_platform_caps(rdev); 4074 if (ret) 4075 return ret; 4076 4077 ret = ni_parse_power_table(rdev); 4078 if (ret) 4079 return ret; 4080 ret = r600_parse_extended_power_table(rdev); 4081 if (ret) 4082 return ret; 4083 4084 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries = 4085 kzalloc(4 * sizeof(struct radeon_clock_voltage_dependency_entry), GFP_KERNEL); 4086 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) { 4087 r600_free_extended_power_table(rdev); 4088 return -ENOMEM; 4089 } 4090 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4; 4091 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0; 4092 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0; 4093 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000; 4094 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720; 4095 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000; 4096 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810; 4097 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000; 4098 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900; 4099 4100 ni_patch_dependency_tables_based_on_leakage(rdev); 4101 4102 if (rdev->pm.dpm.voltage_response_time == 0) 4103 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT; 4104 if (rdev->pm.dpm.backbias_response_time == 0) 4105 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT; 4106 4107 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 4108 0, false, ÷rs); 4109 if (ret) 4110 pi->ref_div = dividers.ref_div + 1; 4111 else 4112 pi->ref_div = R600_REFERENCEDIVIDER_DFLT; 4113 4114 pi->rlp = RV770_RLP_DFLT; 4115 pi->rmp = RV770_RMP_DFLT; 4116 pi->lhp = RV770_LHP_DFLT; 4117 pi->lmp = RV770_LMP_DFLT; 4118 4119 eg_pi->ats[0].rlp = RV770_RLP_DFLT; 4120 eg_pi->ats[0].rmp = RV770_RMP_DFLT; 4121 eg_pi->ats[0].lhp = RV770_LHP_DFLT; 4122 eg_pi->ats[0].lmp = RV770_LMP_DFLT; 4123 4124 eg_pi->ats[1].rlp = BTC_RLP_UVD_DFLT; 4125 eg_pi->ats[1].rmp = BTC_RMP_UVD_DFLT; 4126 eg_pi->ats[1].lhp = BTC_LHP_UVD_DFLT; 4127 eg_pi->ats[1].lmp = BTC_LMP_UVD_DFLT; 4128 4129 eg_pi->smu_uvd_hs = true; 4130 4131 if (rdev->pdev->device == 0x6707) { 4132 pi->mclk_strobe_mode_threshold = 55000; 4133 pi->mclk_edc_enable_threshold = 55000; 4134 eg_pi->mclk_edc_wr_enable_threshold = 55000; 4135 } else { 4136 pi->mclk_strobe_mode_threshold = 40000; 4137 pi->mclk_edc_enable_threshold = 40000; 4138 eg_pi->mclk_edc_wr_enable_threshold = 40000; 4139 } 4140 ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold; 4141 4142 pi->voltage_control = 4143 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 0); 4144 4145 pi->mvdd_control = 4146 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC, 0); 4147 4148 eg_pi->vddci_control = 4149 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 0); 4150 4151 rv770_get_engine_memory_ss(rdev); 4152 4153 pi->asi = RV770_ASI_DFLT; 4154 pi->pasi = CYPRESS_HASI_DFLT; 4155 pi->vrc = CYPRESS_VRC_DFLT; 4156 4157 pi->power_gating = false; 4158 4159 pi->gfx_clock_gating = true; 4160 4161 pi->mg_clock_gating = true; 4162 pi->mgcgtssm = true; 4163 eg_pi->ls_clock_gating = false; 4164 eg_pi->sclk_deep_sleep = false; 4165 4166 pi->dynamic_pcie_gen2 = true; 4167 4168 if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE) 4169 pi->thermal_protection = true; 4170 else 4171 pi->thermal_protection = false; 4172 4173 pi->display_gap = true; 4174 4175 pi->dcodt = true; 4176 4177 pi->ulps = true; 4178 4179 eg_pi->dynamic_ac_timing = true; 4180 eg_pi->abm = true; 4181 eg_pi->mcls = true; 4182 eg_pi->light_sleep = true; 4183 eg_pi->memory_transition = true; 4184 #if defined(CONFIG_ACPI) 4185 eg_pi->pcie_performance_request = 4186 radeon_acpi_is_pcie_performance_request_supported(rdev); 4187 #else 4188 eg_pi->pcie_performance_request = false; 4189 #endif 4190 4191 eg_pi->dll_default_on = false; 4192 4193 eg_pi->sclk_deep_sleep = false; 4194 4195 pi->mclk_stutter_mode_threshold = 0; 4196 4197 pi->sram_end = SMC_RAM_END; 4198 4199 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 3; 4200 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200; 4201 rdev->pm.dpm.dyn_state.min_vddc_for_pcie_gen2 = 900; 4202 rdev->pm.dpm.dyn_state.valid_sclk_values.count = ARRAY_SIZE(btc_valid_sclk); 4203 rdev->pm.dpm.dyn_state.valid_sclk_values.values = btc_valid_sclk; 4204 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0; 4205 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL; 4206 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 12500; 4207 4208 ni_pi->cac_data.leakage_coefficients.at = 516; 4209 ni_pi->cac_data.leakage_coefficients.bt = 18; 4210 ni_pi->cac_data.leakage_coefficients.av = 51; 4211 ni_pi->cac_data.leakage_coefficients.bv = 2957; 4212 4213 switch (rdev->pdev->device) { 4214 case 0x6700: 4215 case 0x6701: 4216 case 0x6702: 4217 case 0x6703: 4218 case 0x6718: 4219 ni_pi->cac_weights = &cac_weights_cayman_xt; 4220 break; 4221 case 0x6705: 4222 case 0x6719: 4223 case 0x671D: 4224 case 0x671C: 4225 default: 4226 ni_pi->cac_weights = &cac_weights_cayman_pro; 4227 break; 4228 case 0x6704: 4229 case 0x6706: 4230 case 0x6707: 4231 case 0x6708: 4232 case 0x6709: 4233 ni_pi->cac_weights = &cac_weights_cayman_le; 4234 break; 4235 } 4236 4237 if (ni_pi->cac_weights->enable_power_containment_by_default) { 4238 ni_pi->enable_power_containment = true; 4239 ni_pi->enable_cac = true; 4240 ni_pi->enable_sq_ramping = true; 4241 } else { 4242 ni_pi->enable_power_containment = false; 4243 ni_pi->enable_cac = false; 4244 ni_pi->enable_sq_ramping = false; 4245 } 4246 4247 ni_pi->driver_calculate_cac_leakage = false; 4248 ni_pi->cac_configuration_required = true; 4249 4250 if (ni_pi->cac_configuration_required) { 4251 ni_pi->support_cac_long_term_average = true; 4252 ni_pi->lta_window_size = ni_pi->cac_weights->l2_lta_window_size; 4253 ni_pi->lts_truncate = ni_pi->cac_weights->lts_truncate; 4254 } else { 4255 ni_pi->support_cac_long_term_average = false; 4256 ni_pi->lta_window_size = 0; 4257 ni_pi->lts_truncate = 0; 4258 } 4259 4260 ni_pi->use_power_boost_limit = true; 4261 4262 /* make sure dc limits are valid */ 4263 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) || 4264 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0)) 4265 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc = 4266 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 4267 4268 return 0; 4269 } 4270 4271 void ni_dpm_fini(struct radeon_device *rdev) 4272 { 4273 int i; 4274 4275 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { 4276 kfree(rdev->pm.dpm.ps[i].ps_priv); 4277 } 4278 kfree(rdev->pm.dpm.ps); 4279 kfree(rdev->pm.dpm.priv); 4280 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries); 4281 r600_free_extended_power_table(rdev); 4282 } 4283 4284 void ni_dpm_print_power_state(struct radeon_device *rdev, 4285 struct radeon_ps *rps) 4286 { 4287 struct ni_ps *ps = ni_get_ps(rps); 4288 struct rv7xx_pl *pl; 4289 int i; 4290 4291 r600_dpm_print_class_info(rps->class, rps->class2); 4292 r600_dpm_print_cap_info(rps->caps); 4293 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); 4294 for (i = 0; i < ps->performance_level_count; i++) { 4295 pl = &ps->performance_levels[i]; 4296 if (rdev->family >= CHIP_TAHITI) 4297 printk("\t\tpower level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n", 4298 i, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1); 4299 else 4300 printk("\t\tpower level %d sclk: %u mclk: %u vddc: %u vddci: %u\n", 4301 i, pl->sclk, pl->mclk, pl->vddc, pl->vddci); 4302 } 4303 r600_dpm_print_ps_status(rdev, rps); 4304 } 4305 4306 #ifdef CONFIG_DEBUG_FS 4307 void ni_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 4308 struct seq_file *m) 4309 { 4310 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4311 struct radeon_ps *rps = &eg_pi->current_rps; 4312 struct ni_ps *ps = ni_get_ps(rps); 4313 struct rv7xx_pl *pl; 4314 u32 current_index = 4315 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> 4316 CURRENT_STATE_INDEX_SHIFT; 4317 4318 if (current_index >= ps->performance_level_count) { 4319 seq_printf(m, "invalid dpm profile %d\n", current_index); 4320 } else { 4321 pl = &ps->performance_levels[current_index]; 4322 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); 4323 seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u\n", 4324 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci); 4325 } 4326 } 4327 #endif /* CONFIG_DEBUG_FS */ 4328 4329 u32 ni_dpm_get_current_sclk(struct radeon_device *rdev) 4330 { 4331 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4332 struct radeon_ps *rps = &eg_pi->current_rps; 4333 struct ni_ps *ps = ni_get_ps(rps); 4334 struct rv7xx_pl *pl; 4335 u32 current_index = 4336 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> 4337 CURRENT_STATE_INDEX_SHIFT; 4338 4339 if (current_index >= ps->performance_level_count) { 4340 return 0; 4341 } else { 4342 pl = &ps->performance_levels[current_index]; 4343 return pl->sclk; 4344 } 4345 } 4346 4347 u32 ni_dpm_get_current_mclk(struct radeon_device *rdev) 4348 { 4349 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4350 struct radeon_ps *rps = &eg_pi->current_rps; 4351 struct ni_ps *ps = ni_get_ps(rps); 4352 struct rv7xx_pl *pl; 4353 u32 current_index = 4354 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> 4355 CURRENT_STATE_INDEX_SHIFT; 4356 4357 if (current_index >= ps->performance_level_count) { 4358 return 0; 4359 } else { 4360 pl = &ps->performance_levels[current_index]; 4361 return pl->mclk; 4362 } 4363 } 4364 4365 u32 ni_dpm_get_sclk(struct radeon_device *rdev, bool low) 4366 { 4367 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4368 struct ni_ps *requested_state = ni_get_ps(&eg_pi->requested_rps); 4369 4370 if (low) 4371 return requested_state->performance_levels[0].sclk; 4372 else 4373 return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk; 4374 } 4375 4376 u32 ni_dpm_get_mclk(struct radeon_device *rdev, bool low) 4377 { 4378 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4379 struct ni_ps *requested_state = ni_get_ps(&eg_pi->requested_rps); 4380 4381 if (low) 4382 return requested_state->performance_levels[0].mclk; 4383 else 4384 return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk; 4385 } 4386 4387
Indexes created Tue Oct 28 12:10:06 GMT 2025