radeon_pm.c revision 1.1.1.2
1 /* $NetBSD: radeon_pm.c,v 1.1.1.2 2018/08/27 01:34:59 riastradh Exp $ */ 2 3 /* 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Rafa Miecki <zajec5 (at) gmail.com> 23 * Alex Deucher <alexdeucher (at) gmail.com> 24 */ 25 #include <sys/cdefs.h> 26 __KERNEL_RCSID(0, "$NetBSD: radeon_pm.c,v 1.1.1.2 2018/08/27 01:34:59 riastradh Exp $"); 27 28 #include <drm/drmP.h> 29 #include "radeon.h" 30 #include "avivod.h" 31 #include "atom.h" 32 #include "r600_dpm.h" 33 #include <linux/power_supply.h> 34 #include <linux/hwmon.h> 35 #include <linux/hwmon-sysfs.h> 36 37 #define RADEON_IDLE_LOOP_MS 100 38 #define RADEON_RECLOCK_DELAY_MS 200 39 #define RADEON_WAIT_VBLANK_TIMEOUT 200 40 41 static const char *radeon_pm_state_type_name[5] = { 42 "", 43 "Powersave", 44 "Battery", 45 "Balanced", 46 "Performance", 47 }; 48 49 static void radeon_dynpm_idle_work_handler(struct work_struct *work); 50 static int radeon_debugfs_pm_init(struct radeon_device *rdev); 51 static bool radeon_pm_in_vbl(struct radeon_device *rdev); 52 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish); 53 static void radeon_pm_update_profile(struct radeon_device *rdev); 54 static void radeon_pm_set_clocks(struct radeon_device *rdev); 55 56 int radeon_pm_get_type_index(struct radeon_device *rdev, 57 enum radeon_pm_state_type ps_type, 58 int instance) 59 { 60 int i; 61 int found_instance = -1; 62 63 for (i = 0; i < rdev->pm.num_power_states; i++) { 64 if (rdev->pm.power_state[i].type == ps_type) { 65 found_instance++; 66 if (found_instance == instance) 67 return i; 68 } 69 } 70 /* return default if no match */ 71 return rdev->pm.default_power_state_index; 72 } 73 74 void radeon_pm_acpi_event_handler(struct radeon_device *rdev) 75 { 76 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { 77 mutex_lock(&rdev->pm.mutex); 78 if (power_supply_is_system_supplied() > 0) 79 rdev->pm.dpm.ac_power = true; 80 else 81 rdev->pm.dpm.ac_power = false; 82 if (rdev->family == CHIP_ARUBA) { 83 if (rdev->asic->dpm.enable_bapm) 84 radeon_dpm_enable_bapm(rdev, rdev->pm.dpm.ac_power); 85 } 86 mutex_unlock(&rdev->pm.mutex); 87 } else if (rdev->pm.pm_method == PM_METHOD_PROFILE) { 88 if (rdev->pm.profile == PM_PROFILE_AUTO) { 89 mutex_lock(&rdev->pm.mutex); 90 radeon_pm_update_profile(rdev); 91 radeon_pm_set_clocks(rdev); 92 mutex_unlock(&rdev->pm.mutex); 93 } 94 } 95 } 96 97 static void radeon_pm_update_profile(struct radeon_device *rdev) 98 { 99 switch (rdev->pm.profile) { 100 case PM_PROFILE_DEFAULT: 101 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX; 102 break; 103 case PM_PROFILE_AUTO: 104 if (power_supply_is_system_supplied() > 0) { 105 if (rdev->pm.active_crtc_count > 1) 106 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX; 107 else 108 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX; 109 } else { 110 if (rdev->pm.active_crtc_count > 1) 111 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX; 112 else 113 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX; 114 } 115 break; 116 case PM_PROFILE_LOW: 117 if (rdev->pm.active_crtc_count > 1) 118 rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX; 119 else 120 rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX; 121 break; 122 case PM_PROFILE_MID: 123 if (rdev->pm.active_crtc_count > 1) 124 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX; 125 else 126 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX; 127 break; 128 case PM_PROFILE_HIGH: 129 if (rdev->pm.active_crtc_count > 1) 130 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX; 131 else 132 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX; 133 break; 134 } 135 136 if (rdev->pm.active_crtc_count == 0) { 137 rdev->pm.requested_power_state_index = 138 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx; 139 rdev->pm.requested_clock_mode_index = 140 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx; 141 } else { 142 rdev->pm.requested_power_state_index = 143 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx; 144 rdev->pm.requested_clock_mode_index = 145 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx; 146 } 147 } 148 149 static void radeon_unmap_vram_bos(struct radeon_device *rdev) 150 { 151 struct radeon_bo *bo, *n; 152 153 if (list_empty(&rdev->gem.objects)) 154 return; 155 156 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) { 157 if (bo->tbo.mem.mem_type == TTM_PL_VRAM) 158 ttm_bo_unmap_virtual(&bo->tbo); 159 } 160 } 161 162 static void radeon_sync_with_vblank(struct radeon_device *rdev) 163 { 164 if (rdev->pm.active_crtcs) { 165 rdev->pm.vblank_sync = false; 166 wait_event_timeout( 167 rdev->irq.vblank_queue, rdev->pm.vblank_sync, 168 msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT)); 169 } 170 } 171 172 static void radeon_set_power_state(struct radeon_device *rdev) 173 { 174 u32 sclk, mclk; 175 bool misc_after = false; 176 177 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) && 178 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index)) 179 return; 180 181 if (radeon_gui_idle(rdev)) { 182 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index]. 183 clock_info[rdev->pm.requested_clock_mode_index].sclk; 184 if (sclk > rdev->pm.default_sclk) 185 sclk = rdev->pm.default_sclk; 186 187 /* starting with BTC, there is one state that is used for both 188 * MH and SH. Difference is that we always use the high clock index for 189 * mclk and vddci. 190 */ 191 if ((rdev->pm.pm_method == PM_METHOD_PROFILE) && 192 (rdev->family >= CHIP_BARTS) && 193 rdev->pm.active_crtc_count && 194 ((rdev->pm.profile_index == PM_PROFILE_MID_MH_IDX) || 195 (rdev->pm.profile_index == PM_PROFILE_LOW_MH_IDX))) 196 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index]. 197 clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].mclk; 198 else 199 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index]. 200 clock_info[rdev->pm.requested_clock_mode_index].mclk; 201 202 if (mclk > rdev->pm.default_mclk) 203 mclk = rdev->pm.default_mclk; 204 205 /* upvolt before raising clocks, downvolt after lowering clocks */ 206 if (sclk < rdev->pm.current_sclk) 207 misc_after = true; 208 209 radeon_sync_with_vblank(rdev); 210 211 if (rdev->pm.pm_method == PM_METHOD_DYNPM) { 212 if (!radeon_pm_in_vbl(rdev)) 213 return; 214 } 215 216 radeon_pm_prepare(rdev); 217 218 if (!misc_after) 219 /* voltage, pcie lanes, etc.*/ 220 radeon_pm_misc(rdev); 221 222 /* set engine clock */ 223 if (sclk != rdev->pm.current_sclk) { 224 radeon_pm_debug_check_in_vbl(rdev, false); 225 radeon_set_engine_clock(rdev, sclk); 226 radeon_pm_debug_check_in_vbl(rdev, true); 227 rdev->pm.current_sclk = sclk; 228 DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk); 229 } 230 231 /* set memory clock */ 232 if (rdev->asic->pm.set_memory_clock && (mclk != rdev->pm.current_mclk)) { 233 radeon_pm_debug_check_in_vbl(rdev, false); 234 radeon_set_memory_clock(rdev, mclk); 235 radeon_pm_debug_check_in_vbl(rdev, true); 236 rdev->pm.current_mclk = mclk; 237 DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk); 238 } 239 240 if (misc_after) 241 /* voltage, pcie lanes, etc.*/ 242 radeon_pm_misc(rdev); 243 244 radeon_pm_finish(rdev); 245 246 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index; 247 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index; 248 } else 249 DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n"); 250 } 251 252 static void radeon_pm_set_clocks(struct radeon_device *rdev) 253 { 254 int i, r; 255 256 /* no need to take locks, etc. if nothing's going to change */ 257 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) && 258 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index)) 259 return; 260 261 down_write(&rdev->pm.mclk_lock); 262 mutex_lock(&rdev->ring_lock); 263 264 /* wait for the rings to drain */ 265 for (i = 0; i < RADEON_NUM_RINGS; i++) { 266 struct radeon_ring *ring = &rdev->ring[i]; 267 if (!ring->ready) { 268 continue; 269 } 270 r = radeon_fence_wait_empty(rdev, i); 271 if (r) { 272 /* needs a GPU reset dont reset here */ 273 mutex_unlock(&rdev->ring_lock); 274 up_write(&rdev->pm.mclk_lock); 275 return; 276 } 277 } 278 279 radeon_unmap_vram_bos(rdev); 280 281 if (rdev->irq.installed) { 282 for (i = 0; i < rdev->num_crtc; i++) { 283 if (rdev->pm.active_crtcs & (1 << i)) { 284 rdev->pm.req_vblank |= (1 << i); 285 drm_vblank_get(rdev->ddev, i); 286 } 287 } 288 } 289 290 radeon_set_power_state(rdev); 291 292 if (rdev->irq.installed) { 293 for (i = 0; i < rdev->num_crtc; i++) { 294 if (rdev->pm.req_vblank & (1 << i)) { 295 rdev->pm.req_vblank &= ~(1 << i); 296 drm_vblank_put(rdev->ddev, i); 297 } 298 } 299 } 300 301 /* update display watermarks based on new power state */ 302 radeon_update_bandwidth_info(rdev); 303 if (rdev->pm.active_crtc_count) 304 radeon_bandwidth_update(rdev); 305 306 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; 307 308 mutex_unlock(&rdev->ring_lock); 309 up_write(&rdev->pm.mclk_lock); 310 } 311 312 static void radeon_pm_print_states(struct radeon_device *rdev) 313 { 314 int i, j; 315 struct radeon_power_state *power_state; 316 struct radeon_pm_clock_info *clock_info; 317 318 DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states); 319 for (i = 0; i < rdev->pm.num_power_states; i++) { 320 power_state = &rdev->pm.power_state[i]; 321 DRM_DEBUG_DRIVER("State %d: %s\n", i, 322 radeon_pm_state_type_name[power_state->type]); 323 if (i == rdev->pm.default_power_state_index) 324 DRM_DEBUG_DRIVER("\tDefault"); 325 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP)) 326 DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes); 327 if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 328 DRM_DEBUG_DRIVER("\tSingle display only\n"); 329 DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state->num_clock_modes); 330 for (j = 0; j < power_state->num_clock_modes; j++) { 331 clock_info = &(power_state->clock_info[j]); 332 if (rdev->flags & RADEON_IS_IGP) 333 DRM_DEBUG_DRIVER("\t\t%d e: %d\n", 334 j, 335 clock_info->sclk * 10); 336 else 337 DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d\n", 338 j, 339 clock_info->sclk * 10, 340 clock_info->mclk * 10, 341 clock_info->voltage.voltage); 342 } 343 } 344 } 345 346 static ssize_t radeon_get_pm_profile(struct device *dev, 347 struct device_attribute *attr, 348 char *buf) 349 { 350 struct drm_device *ddev = dev_get_drvdata(dev); 351 struct radeon_device *rdev = ddev->dev_private; 352 int cp = rdev->pm.profile; 353 354 return snprintf(buf, PAGE_SIZE, "%s\n", 355 (cp == PM_PROFILE_AUTO) ? "auto" : 356 (cp == PM_PROFILE_LOW) ? "low" : 357 (cp == PM_PROFILE_MID) ? "mid" : 358 (cp == PM_PROFILE_HIGH) ? "high" : "default"); 359 } 360 361 static ssize_t radeon_set_pm_profile(struct device *dev, 362 struct device_attribute *attr, 363 const char *buf, 364 size_t count) 365 { 366 struct drm_device *ddev = dev_get_drvdata(dev); 367 struct radeon_device *rdev = ddev->dev_private; 368 369 /* Can't set profile when the card is off */ 370 if ((rdev->flags & RADEON_IS_PX) && 371 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) 372 return -EINVAL; 373 374 mutex_lock(&rdev->pm.mutex); 375 if (rdev->pm.pm_method == PM_METHOD_PROFILE) { 376 if (strncmp("default", buf, strlen("default")) == 0) 377 rdev->pm.profile = PM_PROFILE_DEFAULT; 378 else if (strncmp("auto", buf, strlen("auto")) == 0) 379 rdev->pm.profile = PM_PROFILE_AUTO; 380 else if (strncmp("low", buf, strlen("low")) == 0) 381 rdev->pm.profile = PM_PROFILE_LOW; 382 else if (strncmp("mid", buf, strlen("mid")) == 0) 383 rdev->pm.profile = PM_PROFILE_MID; 384 else if (strncmp("high", buf, strlen("high")) == 0) 385 rdev->pm.profile = PM_PROFILE_HIGH; 386 else { 387 count = -EINVAL; 388 goto fail; 389 } 390 radeon_pm_update_profile(rdev); 391 radeon_pm_set_clocks(rdev); 392 } else 393 count = -EINVAL; 394 395 fail: 396 mutex_unlock(&rdev->pm.mutex); 397 398 return count; 399 } 400 401 static ssize_t radeon_get_pm_method(struct device *dev, 402 struct device_attribute *attr, 403 char *buf) 404 { 405 struct drm_device *ddev = dev_get_drvdata(dev); 406 struct radeon_device *rdev = ddev->dev_private; 407 int pm = rdev->pm.pm_method; 408 409 return snprintf(buf, PAGE_SIZE, "%s\n", 410 (pm == PM_METHOD_DYNPM) ? "dynpm" : 411 (pm == PM_METHOD_PROFILE) ? "profile" : "dpm"); 412 } 413 414 static ssize_t radeon_set_pm_method(struct device *dev, 415 struct device_attribute *attr, 416 const char *buf, 417 size_t count) 418 { 419 struct drm_device *ddev = dev_get_drvdata(dev); 420 struct radeon_device *rdev = ddev->dev_private; 421 422 /* Can't set method when the card is off */ 423 if ((rdev->flags & RADEON_IS_PX) && 424 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) { 425 count = -EINVAL; 426 goto fail; 427 } 428 429 /* we don't support the legacy modes with dpm */ 430 if (rdev->pm.pm_method == PM_METHOD_DPM) { 431 count = -EINVAL; 432 goto fail; 433 } 434 435 if (strncmp("dynpm", buf, strlen("dynpm")) == 0) { 436 mutex_lock(&rdev->pm.mutex); 437 rdev->pm.pm_method = PM_METHOD_DYNPM; 438 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED; 439 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT; 440 mutex_unlock(&rdev->pm.mutex); 441 } else if (strncmp("profile", buf, strlen("profile")) == 0) { 442 mutex_lock(&rdev->pm.mutex); 443 /* disable dynpm */ 444 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED; 445 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; 446 rdev->pm.pm_method = PM_METHOD_PROFILE; 447 mutex_unlock(&rdev->pm.mutex); 448 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work); 449 } else { 450 count = -EINVAL; 451 goto fail; 452 } 453 radeon_pm_compute_clocks(rdev); 454 fail: 455 return count; 456 } 457 458 static ssize_t radeon_get_dpm_state(struct device *dev, 459 struct device_attribute *attr, 460 char *buf) 461 { 462 struct drm_device *ddev = dev_get_drvdata(dev); 463 struct radeon_device *rdev = ddev->dev_private; 464 enum radeon_pm_state_type pm = rdev->pm.dpm.user_state; 465 466 return snprintf(buf, PAGE_SIZE, "%s\n", 467 (pm == POWER_STATE_TYPE_BATTERY) ? "battery" : 468 (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance"); 469 } 470 471 static ssize_t radeon_set_dpm_state(struct device *dev, 472 struct device_attribute *attr, 473 const char *buf, 474 size_t count) 475 { 476 struct drm_device *ddev = dev_get_drvdata(dev); 477 struct radeon_device *rdev = ddev->dev_private; 478 479 mutex_lock(&rdev->pm.mutex); 480 if (strncmp("battery", buf, strlen("battery")) == 0) 481 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BATTERY; 482 else if (strncmp("balanced", buf, strlen("balanced")) == 0) 483 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED; 484 else if (strncmp("performance", buf, strlen("performance")) == 0) 485 rdev->pm.dpm.user_state = POWER_STATE_TYPE_PERFORMANCE; 486 else { 487 mutex_unlock(&rdev->pm.mutex); 488 count = -EINVAL; 489 goto fail; 490 } 491 mutex_unlock(&rdev->pm.mutex); 492 493 /* Can't set dpm state when the card is off */ 494 if (!(rdev->flags & RADEON_IS_PX) || 495 (ddev->switch_power_state == DRM_SWITCH_POWER_ON)) 496 radeon_pm_compute_clocks(rdev); 497 498 fail: 499 return count; 500 } 501 502 static ssize_t radeon_get_dpm_forced_performance_level(struct device *dev, 503 struct device_attribute *attr, 504 char *buf) 505 { 506 struct drm_device *ddev = dev_get_drvdata(dev); 507 struct radeon_device *rdev = ddev->dev_private; 508 enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level; 509 510 if ((rdev->flags & RADEON_IS_PX) && 511 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) 512 return snprintf(buf, PAGE_SIZE, "off\n"); 513 514 return snprintf(buf, PAGE_SIZE, "%s\n", 515 (level == RADEON_DPM_FORCED_LEVEL_AUTO) ? "auto" : 516 (level == RADEON_DPM_FORCED_LEVEL_LOW) ? "low" : "high"); 517 } 518 519 static ssize_t radeon_set_dpm_forced_performance_level(struct device *dev, 520 struct device_attribute *attr, 521 const char *buf, 522 size_t count) 523 { 524 struct drm_device *ddev = dev_get_drvdata(dev); 525 struct radeon_device *rdev = ddev->dev_private; 526 enum radeon_dpm_forced_level level; 527 int ret = 0; 528 529 /* Can't force performance level when the card is off */ 530 if ((rdev->flags & RADEON_IS_PX) && 531 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) 532 return -EINVAL; 533 534 mutex_lock(&rdev->pm.mutex); 535 if (strncmp("low", buf, strlen("low")) == 0) { 536 level = RADEON_DPM_FORCED_LEVEL_LOW; 537 } else if (strncmp("high", buf, strlen("high")) == 0) { 538 level = RADEON_DPM_FORCED_LEVEL_HIGH; 539 } else if (strncmp("auto", buf, strlen("auto")) == 0) { 540 level = RADEON_DPM_FORCED_LEVEL_AUTO; 541 } else { 542 count = -EINVAL; 543 goto fail; 544 } 545 if (rdev->asic->dpm.force_performance_level) { 546 if (rdev->pm.dpm.thermal_active) { 547 count = -EINVAL; 548 goto fail; 549 } 550 ret = radeon_dpm_force_performance_level(rdev, level); 551 if (ret) 552 count = -EINVAL; 553 } 554 fail: 555 mutex_unlock(&rdev->pm.mutex); 556 557 return count; 558 } 559 560 static ssize_t radeon_hwmon_get_pwm1_enable(struct device *dev, 561 struct device_attribute *attr, 562 char *buf) 563 { 564 struct radeon_device *rdev = dev_get_drvdata(dev); 565 u32 pwm_mode = 0; 566 567 if (rdev->asic->dpm.fan_ctrl_get_mode) 568 pwm_mode = rdev->asic->dpm.fan_ctrl_get_mode(rdev); 569 570 /* never 0 (full-speed), fuse or smc-controlled always */ 571 return sprintf(buf, "%i\n", pwm_mode == FDO_PWM_MODE_STATIC ? 1 : 2); 572 } 573 574 static ssize_t radeon_hwmon_set_pwm1_enable(struct device *dev, 575 struct device_attribute *attr, 576 const char *buf, 577 size_t count) 578 { 579 struct radeon_device *rdev = dev_get_drvdata(dev); 580 int err; 581 int value; 582 583 if(!rdev->asic->dpm.fan_ctrl_set_mode) 584 return -EINVAL; 585 586 err = kstrtoint(buf, 10, &value); 587 if (err) 588 return err; 589 590 switch (value) { 591 case 1: /* manual, percent-based */ 592 rdev->asic->dpm.fan_ctrl_set_mode(rdev, FDO_PWM_MODE_STATIC); 593 break; 594 default: /* disable */ 595 rdev->asic->dpm.fan_ctrl_set_mode(rdev, 0); 596 break; 597 } 598 599 return count; 600 } 601 602 static ssize_t radeon_hwmon_get_pwm1_min(struct device *dev, 603 struct device_attribute *attr, 604 char *buf) 605 { 606 return sprintf(buf, "%i\n", 0); 607 } 608 609 static ssize_t radeon_hwmon_get_pwm1_max(struct device *dev, 610 struct device_attribute *attr, 611 char *buf) 612 { 613 return sprintf(buf, "%i\n", 255); 614 } 615 616 static ssize_t radeon_hwmon_set_pwm1(struct device *dev, 617 struct device_attribute *attr, 618 const char *buf, size_t count) 619 { 620 struct radeon_device *rdev = dev_get_drvdata(dev); 621 int err; 622 u32 value; 623 624 err = kstrtou32(buf, 10, &value); 625 if (err) 626 return err; 627 628 value = (value * 100) / 255; 629 630 err = rdev->asic->dpm.set_fan_speed_percent(rdev, value); 631 if (err) 632 return err; 633 634 return count; 635 } 636 637 static ssize_t radeon_hwmon_get_pwm1(struct device *dev, 638 struct device_attribute *attr, 639 char *buf) 640 { 641 struct radeon_device *rdev = dev_get_drvdata(dev); 642 int err; 643 u32 speed; 644 645 err = rdev->asic->dpm.get_fan_speed_percent(rdev, &speed); 646 if (err) 647 return err; 648 649 speed = (speed * 255) / 100; 650 651 return sprintf(buf, "%i\n", speed); 652 } 653 654 static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile); 655 static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method); 656 static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, radeon_get_dpm_state, radeon_set_dpm_state); 657 static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR, 658 radeon_get_dpm_forced_performance_level, 659 radeon_set_dpm_forced_performance_level); 660 661 static ssize_t radeon_hwmon_show_temp(struct device *dev, 662 struct device_attribute *attr, 663 char *buf) 664 { 665 struct radeon_device *rdev = dev_get_drvdata(dev); 666 struct drm_device *ddev = rdev->ddev; 667 int temp; 668 669 /* Can't get temperature when the card is off */ 670 if ((rdev->flags & RADEON_IS_PX) && 671 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) 672 return -EINVAL; 673 674 if (rdev->asic->pm.get_temperature) 675 temp = radeon_get_temperature(rdev); 676 else 677 temp = 0; 678 679 return snprintf(buf, PAGE_SIZE, "%d\n", temp); 680 } 681 682 static ssize_t radeon_hwmon_show_temp_thresh(struct device *dev, 683 struct device_attribute *attr, 684 char *buf) 685 { 686 struct radeon_device *rdev = dev_get_drvdata(dev); 687 int hyst = to_sensor_dev_attr(attr)->index; 688 int temp; 689 690 if (hyst) 691 temp = rdev->pm.dpm.thermal.min_temp; 692 else 693 temp = rdev->pm.dpm.thermal.max_temp; 694 695 return snprintf(buf, PAGE_SIZE, "%d\n", temp); 696 } 697 698 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, radeon_hwmon_show_temp, NULL, 0); 699 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, radeon_hwmon_show_temp_thresh, NULL, 0); 700 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, radeon_hwmon_show_temp_thresh, NULL, 1); 701 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, radeon_hwmon_get_pwm1, radeon_hwmon_set_pwm1, 0); 702 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, radeon_hwmon_get_pwm1_enable, radeon_hwmon_set_pwm1_enable, 0); 703 static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, radeon_hwmon_get_pwm1_min, NULL, 0); 704 static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, radeon_hwmon_get_pwm1_max, NULL, 0); 705 706 707 static struct attribute *hwmon_attributes[] = { 708 &sensor_dev_attr_temp1_input.dev_attr.attr, 709 &sensor_dev_attr_temp1_crit.dev_attr.attr, 710 &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr, 711 &sensor_dev_attr_pwm1.dev_attr.attr, 712 &sensor_dev_attr_pwm1_enable.dev_attr.attr, 713 &sensor_dev_attr_pwm1_min.dev_attr.attr, 714 &sensor_dev_attr_pwm1_max.dev_attr.attr, 715 NULL 716 }; 717 718 static umode_t hwmon_attributes_visible(struct kobject *kobj, 719 struct attribute *attr, int index) 720 { 721 struct device *dev = container_of(kobj, struct device, kobj); 722 struct radeon_device *rdev = dev_get_drvdata(dev); 723 umode_t effective_mode = attr->mode; 724 725 /* Skip attributes if DPM is not enabled */ 726 if (rdev->pm.pm_method != PM_METHOD_DPM && 727 (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr || 728 attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr || 729 attr == &sensor_dev_attr_pwm1.dev_attr.attr || 730 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr || 731 attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || 732 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr)) 733 return 0; 734 735 /* Skip fan attributes if fan is not present */ 736 if (rdev->pm.no_fan && 737 (attr == &sensor_dev_attr_pwm1.dev_attr.attr || 738 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr || 739 attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || 740 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr)) 741 return 0; 742 743 /* mask fan attributes if we have no bindings for this asic to expose */ 744 if ((!rdev->asic->dpm.get_fan_speed_percent && 745 attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */ 746 (!rdev->asic->dpm.fan_ctrl_get_mode && 747 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */ 748 effective_mode &= ~S_IRUGO; 749 750 if ((!rdev->asic->dpm.set_fan_speed_percent && 751 attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */ 752 (!rdev->asic->dpm.fan_ctrl_set_mode && 753 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */ 754 effective_mode &= ~S_IWUSR; 755 756 /* hide max/min values if we can't both query and manage the fan */ 757 if ((!rdev->asic->dpm.set_fan_speed_percent && 758 !rdev->asic->dpm.get_fan_speed_percent) && 759 (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || 760 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr)) 761 return 0; 762 763 return effective_mode; 764 } 765 766 static const struct attribute_group hwmon_attrgroup = { 767 .attrs = hwmon_attributes, 768 .is_visible = hwmon_attributes_visible, 769 }; 770 771 static const struct attribute_group *hwmon_groups[] = { 772 &hwmon_attrgroup, 773 NULL 774 }; 775 776 static int radeon_hwmon_init(struct radeon_device *rdev) 777 { 778 int err = 0; 779 780 switch (rdev->pm.int_thermal_type) { 781 case THERMAL_TYPE_RV6XX: 782 case THERMAL_TYPE_RV770: 783 case THERMAL_TYPE_EVERGREEN: 784 case THERMAL_TYPE_NI: 785 case THERMAL_TYPE_SUMO: 786 case THERMAL_TYPE_SI: 787 case THERMAL_TYPE_CI: 788 case THERMAL_TYPE_KV: 789 if (rdev->asic->pm.get_temperature == NULL) 790 return err; 791 rdev->pm.int_hwmon_dev = hwmon_device_register_with_groups(rdev->dev, 792 "radeon", rdev, 793 hwmon_groups); 794 if (IS_ERR(rdev->pm.int_hwmon_dev)) { 795 err = PTR_ERR(rdev->pm.int_hwmon_dev); 796 dev_err(rdev->dev, 797 "Unable to register hwmon device: %d\n", err); 798 } 799 break; 800 default: 801 break; 802 } 803 804 return err; 805 } 806 807 static void radeon_hwmon_fini(struct radeon_device *rdev) 808 { 809 if (rdev->pm.int_hwmon_dev) 810 hwmon_device_unregister(rdev->pm.int_hwmon_dev); 811 } 812 813 static void radeon_dpm_thermal_work_handler(struct work_struct *work) 814 { 815 struct radeon_device *rdev = 816 container_of(work, struct radeon_device, 817 pm.dpm.thermal.work); 818 /* switch to the thermal state */ 819 enum radeon_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL; 820 821 if (!rdev->pm.dpm_enabled) 822 return; 823 824 if (rdev->asic->pm.get_temperature) { 825 int temp = radeon_get_temperature(rdev); 826 827 if (temp < rdev->pm.dpm.thermal.min_temp) 828 /* switch back the user state */ 829 dpm_state = rdev->pm.dpm.user_state; 830 } else { 831 if (rdev->pm.dpm.thermal.high_to_low) 832 /* switch back the user state */ 833 dpm_state = rdev->pm.dpm.user_state; 834 } 835 mutex_lock(&rdev->pm.mutex); 836 if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL) 837 rdev->pm.dpm.thermal_active = true; 838 else 839 rdev->pm.dpm.thermal_active = false; 840 rdev->pm.dpm.state = dpm_state; 841 mutex_unlock(&rdev->pm.mutex); 842 843 radeon_pm_compute_clocks(rdev); 844 } 845 846 static bool radeon_dpm_single_display(struct radeon_device *rdev) 847 { 848 bool single_display = (rdev->pm.dpm.new_active_crtc_count < 2) ? 849 true : false; 850 851 /* check if the vblank period is too short to adjust the mclk */ 852 if (single_display && rdev->asic->dpm.vblank_too_short) { 853 if (radeon_dpm_vblank_too_short(rdev)) 854 single_display = false; 855 } 856 857 /* 120hz tends to be problematic even if they are under the 858 * vblank limit. 859 */ 860 if (single_display && (r600_dpm_get_vrefresh(rdev) >= 120)) 861 single_display = false; 862 863 return single_display; 864 } 865 866 static struct radeon_ps *radeon_dpm_pick_power_state(struct radeon_device *rdev, 867 enum radeon_pm_state_type dpm_state) 868 { 869 int i; 870 struct radeon_ps *ps; 871 u32 ui_class; 872 bool single_display = radeon_dpm_single_display(rdev); 873 874 /* certain older asics have a separare 3D performance state, 875 * so try that first if the user selected performance 876 */ 877 if (dpm_state == POWER_STATE_TYPE_PERFORMANCE) 878 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF; 879 /* balanced states don't exist at the moment */ 880 if (dpm_state == POWER_STATE_TYPE_BALANCED) 881 dpm_state = POWER_STATE_TYPE_PERFORMANCE; 882 883 restart_search: 884 /* Pick the best power state based on current conditions */ 885 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { 886 ps = &rdev->pm.dpm.ps[i]; 887 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK; 888 switch (dpm_state) { 889 /* user states */ 890 case POWER_STATE_TYPE_BATTERY: 891 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) { 892 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) { 893 if (single_display) 894 return ps; 895 } else 896 return ps; 897 } 898 break; 899 case POWER_STATE_TYPE_BALANCED: 900 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) { 901 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) { 902 if (single_display) 903 return ps; 904 } else 905 return ps; 906 } 907 break; 908 case POWER_STATE_TYPE_PERFORMANCE: 909 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) { 910 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) { 911 if (single_display) 912 return ps; 913 } else 914 return ps; 915 } 916 break; 917 /* internal states */ 918 case POWER_STATE_TYPE_INTERNAL_UVD: 919 if (rdev->pm.dpm.uvd_ps) 920 return rdev->pm.dpm.uvd_ps; 921 else 922 break; 923 case POWER_STATE_TYPE_INTERNAL_UVD_SD: 924 if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE) 925 return ps; 926 break; 927 case POWER_STATE_TYPE_INTERNAL_UVD_HD: 928 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE) 929 return ps; 930 break; 931 case POWER_STATE_TYPE_INTERNAL_UVD_HD2: 932 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE) 933 return ps; 934 break; 935 case POWER_STATE_TYPE_INTERNAL_UVD_MVC: 936 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC) 937 return ps; 938 break; 939 case POWER_STATE_TYPE_INTERNAL_BOOT: 940 return rdev->pm.dpm.boot_ps; 941 case POWER_STATE_TYPE_INTERNAL_THERMAL: 942 if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL) 943 return ps; 944 break; 945 case POWER_STATE_TYPE_INTERNAL_ACPI: 946 if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) 947 return ps; 948 break; 949 case POWER_STATE_TYPE_INTERNAL_ULV: 950 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) 951 return ps; 952 break; 953 case POWER_STATE_TYPE_INTERNAL_3DPERF: 954 if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE) 955 return ps; 956 break; 957 default: 958 break; 959 } 960 } 961 /* use a fallback state if we didn't match */ 962 switch (dpm_state) { 963 case POWER_STATE_TYPE_INTERNAL_UVD_SD: 964 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD; 965 goto restart_search; 966 case POWER_STATE_TYPE_INTERNAL_UVD_HD: 967 case POWER_STATE_TYPE_INTERNAL_UVD_HD2: 968 case POWER_STATE_TYPE_INTERNAL_UVD_MVC: 969 if (rdev->pm.dpm.uvd_ps) { 970 return rdev->pm.dpm.uvd_ps; 971 } else { 972 dpm_state = POWER_STATE_TYPE_PERFORMANCE; 973 goto restart_search; 974 } 975 case POWER_STATE_TYPE_INTERNAL_THERMAL: 976 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI; 977 goto restart_search; 978 case POWER_STATE_TYPE_INTERNAL_ACPI: 979 dpm_state = POWER_STATE_TYPE_BATTERY; 980 goto restart_search; 981 case POWER_STATE_TYPE_BATTERY: 982 case POWER_STATE_TYPE_BALANCED: 983 case POWER_STATE_TYPE_INTERNAL_3DPERF: 984 dpm_state = POWER_STATE_TYPE_PERFORMANCE; 985 goto restart_search; 986 default: 987 break; 988 } 989 990 return NULL; 991 } 992 993 static void radeon_dpm_change_power_state_locked(struct radeon_device *rdev) 994 { 995 int i; 996 struct radeon_ps *ps; 997 enum radeon_pm_state_type dpm_state; 998 int ret; 999 bool single_display = radeon_dpm_single_display(rdev); 1000 1001 /* if dpm init failed */ 1002 if (!rdev->pm.dpm_enabled) 1003 return; 1004 1005 if (rdev->pm.dpm.user_state != rdev->pm.dpm.state) { 1006 /* add other state override checks here */ 1007 if ((!rdev->pm.dpm.thermal_active) && 1008 (!rdev->pm.dpm.uvd_active)) 1009 rdev->pm.dpm.state = rdev->pm.dpm.user_state; 1010 } 1011 dpm_state = rdev->pm.dpm.state; 1012 1013 ps = radeon_dpm_pick_power_state(rdev, dpm_state); 1014 if (ps) 1015 rdev->pm.dpm.requested_ps = ps; 1016 else 1017 return; 1018 1019 /* no need to reprogram if nothing changed unless we are on BTC+ */ 1020 if (rdev->pm.dpm.current_ps == rdev->pm.dpm.requested_ps) { 1021 /* vce just modifies an existing state so force a change */ 1022 if (ps->vce_active != rdev->pm.dpm.vce_active) 1023 goto force; 1024 /* user has made a display change (such as timing) */ 1025 if (rdev->pm.dpm.single_display != single_display) 1026 goto force; 1027 if ((rdev->family < CHIP_BARTS) || (rdev->flags & RADEON_IS_IGP)) { 1028 /* for pre-BTC and APUs if the num crtcs changed but state is the same, 1029 * all we need to do is update the display configuration. 1030 */ 1031 if (rdev->pm.dpm.new_active_crtcs != rdev->pm.dpm.current_active_crtcs) { 1032 /* update display watermarks based on new power state */ 1033 radeon_bandwidth_update(rdev); 1034 /* update displays */ 1035 radeon_dpm_display_configuration_changed(rdev); 1036 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs; 1037 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count; 1038 } 1039 return; 1040 } else { 1041 /* for BTC+ if the num crtcs hasn't changed and state is the same, 1042 * nothing to do, if the num crtcs is > 1 and state is the same, 1043 * update display configuration. 1044 */ 1045 if (rdev->pm.dpm.new_active_crtcs == 1046 rdev->pm.dpm.current_active_crtcs) { 1047 return; 1048 } else { 1049 if ((rdev->pm.dpm.current_active_crtc_count > 1) && 1050 (rdev->pm.dpm.new_active_crtc_count > 1)) { 1051 /* update display watermarks based on new power state */ 1052 radeon_bandwidth_update(rdev); 1053 /* update displays */ 1054 radeon_dpm_display_configuration_changed(rdev); 1055 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs; 1056 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count; 1057 return; 1058 } 1059 } 1060 } 1061 } 1062 1063 force: 1064 if (radeon_dpm == 1) { 1065 printk("switching from power state:\n"); 1066 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.current_ps); 1067 printk("switching to power state:\n"); 1068 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.requested_ps); 1069 } 1070 1071 down_write(&rdev->pm.mclk_lock); 1072 mutex_lock(&rdev->ring_lock); 1073 1074 /* update whether vce is active */ 1075 ps->vce_active = rdev->pm.dpm.vce_active; 1076 1077 ret = radeon_dpm_pre_set_power_state(rdev); 1078 if (ret) 1079 goto done; 1080 1081 /* update display watermarks based on new power state */ 1082 radeon_bandwidth_update(rdev); 1083 /* update displays */ 1084 radeon_dpm_display_configuration_changed(rdev); 1085 1086 /* wait for the rings to drain */ 1087 for (i = 0; i < RADEON_NUM_RINGS; i++) { 1088 struct radeon_ring *ring = &rdev->ring[i]; 1089 if (ring->ready) 1090 radeon_fence_wait_empty(rdev, i); 1091 } 1092 1093 /* program the new power state */ 1094 radeon_dpm_set_power_state(rdev); 1095 1096 /* update current power state */ 1097 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps; 1098 1099 radeon_dpm_post_set_power_state(rdev); 1100 1101 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs; 1102 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count; 1103 rdev->pm.dpm.single_display = single_display; 1104 1105 if (rdev->asic->dpm.force_performance_level) { 1106 if (rdev->pm.dpm.thermal_active) { 1107 enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level; 1108 /* force low perf level for thermal */ 1109 radeon_dpm_force_performance_level(rdev, RADEON_DPM_FORCED_LEVEL_LOW); 1110 /* save the user's level */ 1111 rdev->pm.dpm.forced_level = level; 1112 } else { 1113 /* otherwise, user selected level */ 1114 radeon_dpm_force_performance_level(rdev, rdev->pm.dpm.forced_level); 1115 } 1116 } 1117 1118 done: 1119 mutex_unlock(&rdev->ring_lock); 1120 up_write(&rdev->pm.mclk_lock); 1121 } 1122 1123 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable) 1124 { 1125 enum radeon_pm_state_type dpm_state; 1126 1127 if (rdev->asic->dpm.powergate_uvd) { 1128 mutex_lock(&rdev->pm.mutex); 1129 /* don't powergate anything if we 1130 have active but pause streams */ 1131 enable |= rdev->pm.dpm.sd > 0; 1132 enable |= rdev->pm.dpm.hd > 0; 1133 /* enable/disable UVD */ 1134 radeon_dpm_powergate_uvd(rdev, !enable); 1135 mutex_unlock(&rdev->pm.mutex); 1136 } else { 1137 if (enable) { 1138 mutex_lock(&rdev->pm.mutex); 1139 rdev->pm.dpm.uvd_active = true; 1140 /* disable this for now */ 1141 #if 0 1142 if ((rdev->pm.dpm.sd == 1) && (rdev->pm.dpm.hd == 0)) 1143 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_SD; 1144 else if ((rdev->pm.dpm.sd == 2) && (rdev->pm.dpm.hd == 0)) 1145 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD; 1146 else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 1)) 1147 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD; 1148 else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 2)) 1149 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD2; 1150 else 1151 #endif 1152 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD; 1153 rdev->pm.dpm.state = dpm_state; 1154 mutex_unlock(&rdev->pm.mutex); 1155 } else { 1156 mutex_lock(&rdev->pm.mutex); 1157 rdev->pm.dpm.uvd_active = false; 1158 mutex_unlock(&rdev->pm.mutex); 1159 } 1160 1161 radeon_pm_compute_clocks(rdev); 1162 } 1163 } 1164 1165 void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable) 1166 { 1167 if (enable) { 1168 mutex_lock(&rdev->pm.mutex); 1169 rdev->pm.dpm.vce_active = true; 1170 /* XXX select vce level based on ring/task */ 1171 rdev->pm.dpm.vce_level = RADEON_VCE_LEVEL_AC_ALL; 1172 mutex_unlock(&rdev->pm.mutex); 1173 } else { 1174 mutex_lock(&rdev->pm.mutex); 1175 rdev->pm.dpm.vce_active = false; 1176 mutex_unlock(&rdev->pm.mutex); 1177 } 1178 1179 radeon_pm_compute_clocks(rdev); 1180 } 1181 1182 static void radeon_pm_suspend_old(struct radeon_device *rdev) 1183 { 1184 mutex_lock(&rdev->pm.mutex); 1185 if (rdev->pm.pm_method == PM_METHOD_DYNPM) { 1186 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) 1187 rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED; 1188 } 1189 mutex_unlock(&rdev->pm.mutex); 1190 1191 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work); 1192 } 1193 1194 static void radeon_pm_suspend_dpm(struct radeon_device *rdev) 1195 { 1196 mutex_lock(&rdev->pm.mutex); 1197 /* disable dpm */ 1198 radeon_dpm_disable(rdev); 1199 /* reset the power state */ 1200 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps; 1201 rdev->pm.dpm_enabled = false; 1202 mutex_unlock(&rdev->pm.mutex); 1203 } 1204 1205 void radeon_pm_suspend(struct radeon_device *rdev) 1206 { 1207 if (rdev->pm.pm_method == PM_METHOD_DPM) 1208 radeon_pm_suspend_dpm(rdev); 1209 else 1210 radeon_pm_suspend_old(rdev); 1211 } 1212 1213 static void radeon_pm_resume_old(struct radeon_device *rdev) 1214 { 1215 /* set up the default clocks if the MC ucode is loaded */ 1216 if ((rdev->family >= CHIP_BARTS) && 1217 (rdev->family <= CHIP_CAYMAN) && 1218 rdev->mc_fw) { 1219 if (rdev->pm.default_vddc) 1220 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc, 1221 SET_VOLTAGE_TYPE_ASIC_VDDC); 1222 if (rdev->pm.default_vddci) 1223 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci, 1224 SET_VOLTAGE_TYPE_ASIC_VDDCI); 1225 if (rdev->pm.default_sclk) 1226 radeon_set_engine_clock(rdev, rdev->pm.default_sclk); 1227 if (rdev->pm.default_mclk) 1228 radeon_set_memory_clock(rdev, rdev->pm.default_mclk); 1229 } 1230 /* asic init will reset the default power state */ 1231 mutex_lock(&rdev->pm.mutex); 1232 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index; 1233 rdev->pm.current_clock_mode_index = 0; 1234 rdev->pm.current_sclk = rdev->pm.default_sclk; 1235 rdev->pm.current_mclk = rdev->pm.default_mclk; 1236 if (rdev->pm.power_state) { 1237 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage; 1238 rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci; 1239 } 1240 if (rdev->pm.pm_method == PM_METHOD_DYNPM 1241 && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) { 1242 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE; 1243 schedule_delayed_work(&rdev->pm.dynpm_idle_work, 1244 msecs_to_jiffies(RADEON_IDLE_LOOP_MS)); 1245 } 1246 mutex_unlock(&rdev->pm.mutex); 1247 radeon_pm_compute_clocks(rdev); 1248 } 1249 1250 static void radeon_pm_resume_dpm(struct radeon_device *rdev) 1251 { 1252 int ret; 1253 1254 /* asic init will reset to the boot state */ 1255 mutex_lock(&rdev->pm.mutex); 1256 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps; 1257 radeon_dpm_setup_asic(rdev); 1258 ret = radeon_dpm_enable(rdev); 1259 mutex_unlock(&rdev->pm.mutex); 1260 if (ret) 1261 goto dpm_resume_fail; 1262 rdev->pm.dpm_enabled = true; 1263 return; 1264 1265 dpm_resume_fail: 1266 DRM_ERROR("radeon: dpm resume failed\n"); 1267 if ((rdev->family >= CHIP_BARTS) && 1268 (rdev->family <= CHIP_CAYMAN) && 1269 rdev->mc_fw) { 1270 if (rdev->pm.default_vddc) 1271 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc, 1272 SET_VOLTAGE_TYPE_ASIC_VDDC); 1273 if (rdev->pm.default_vddci) 1274 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci, 1275 SET_VOLTAGE_TYPE_ASIC_VDDCI); 1276 if (rdev->pm.default_sclk) 1277 radeon_set_engine_clock(rdev, rdev->pm.default_sclk); 1278 if (rdev->pm.default_mclk) 1279 radeon_set_memory_clock(rdev, rdev->pm.default_mclk); 1280 } 1281 } 1282 1283 void radeon_pm_resume(struct radeon_device *rdev) 1284 { 1285 if (rdev->pm.pm_method == PM_METHOD_DPM) 1286 radeon_pm_resume_dpm(rdev); 1287 else 1288 radeon_pm_resume_old(rdev); 1289 } 1290 1291 static int radeon_pm_init_old(struct radeon_device *rdev) 1292 { 1293 int ret; 1294 1295 rdev->pm.profile = PM_PROFILE_DEFAULT; 1296 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED; 1297 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; 1298 rdev->pm.dynpm_can_upclock = true; 1299 rdev->pm.dynpm_can_downclock = true; 1300 rdev->pm.default_sclk = rdev->clock.default_sclk; 1301 rdev->pm.default_mclk = rdev->clock.default_mclk; 1302 rdev->pm.current_sclk = rdev->clock.default_sclk; 1303 rdev->pm.current_mclk = rdev->clock.default_mclk; 1304 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE; 1305 1306 if (rdev->bios) { 1307 if (rdev->is_atom_bios) 1308 radeon_atombios_get_power_modes(rdev); 1309 else 1310 radeon_combios_get_power_modes(rdev); 1311 radeon_pm_print_states(rdev); 1312 radeon_pm_init_profile(rdev); 1313 /* set up the default clocks if the MC ucode is loaded */ 1314 if ((rdev->family >= CHIP_BARTS) && 1315 (rdev->family <= CHIP_CAYMAN) && 1316 rdev->mc_fw) { 1317 if (rdev->pm.default_vddc) 1318 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc, 1319 SET_VOLTAGE_TYPE_ASIC_VDDC); 1320 if (rdev->pm.default_vddci) 1321 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci, 1322 SET_VOLTAGE_TYPE_ASIC_VDDCI); 1323 if (rdev->pm.default_sclk) 1324 radeon_set_engine_clock(rdev, rdev->pm.default_sclk); 1325 if (rdev->pm.default_mclk) 1326 radeon_set_memory_clock(rdev, rdev->pm.default_mclk); 1327 } 1328 } 1329 1330 /* set up the internal thermal sensor if applicable */ 1331 ret = radeon_hwmon_init(rdev); 1332 if (ret) 1333 return ret; 1334 1335 INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler); 1336 1337 if (rdev->pm.num_power_states > 1) { 1338 if (radeon_debugfs_pm_init(rdev)) { 1339 DRM_ERROR("Failed to register debugfs file for PM!\n"); 1340 } 1341 1342 DRM_INFO("radeon: power management initialized\n"); 1343 } 1344 1345 return 0; 1346 } 1347 1348 static void radeon_dpm_print_power_states(struct radeon_device *rdev) 1349 { 1350 int i; 1351 1352 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { 1353 printk("== power state %d ==\n", i); 1354 radeon_dpm_print_power_state(rdev, &rdev->pm.dpm.ps[i]); 1355 } 1356 } 1357 1358 static int radeon_pm_init_dpm(struct radeon_device *rdev) 1359 { 1360 int ret; 1361 1362 /* default to balanced state */ 1363 rdev->pm.dpm.state = POWER_STATE_TYPE_BALANCED; 1364 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED; 1365 rdev->pm.dpm.forced_level = RADEON_DPM_FORCED_LEVEL_AUTO; 1366 rdev->pm.default_sclk = rdev->clock.default_sclk; 1367 rdev->pm.default_mclk = rdev->clock.default_mclk; 1368 rdev->pm.current_sclk = rdev->clock.default_sclk; 1369 rdev->pm.current_mclk = rdev->clock.default_mclk; 1370 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE; 1371 1372 if (rdev->bios && rdev->is_atom_bios) 1373 radeon_atombios_get_power_modes(rdev); 1374 else 1375 return -EINVAL; 1376 1377 /* set up the internal thermal sensor if applicable */ 1378 ret = radeon_hwmon_init(rdev); 1379 if (ret) 1380 return ret; 1381 1382 INIT_WORK(&rdev->pm.dpm.thermal.work, radeon_dpm_thermal_work_handler); 1383 mutex_lock(&rdev->pm.mutex); 1384 radeon_dpm_init(rdev); 1385 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps; 1386 if (radeon_dpm == 1) 1387 radeon_dpm_print_power_states(rdev); 1388 radeon_dpm_setup_asic(rdev); 1389 ret = radeon_dpm_enable(rdev); 1390 mutex_unlock(&rdev->pm.mutex); 1391 if (ret) 1392 goto dpm_failed; 1393 rdev->pm.dpm_enabled = true; 1394 1395 if (radeon_debugfs_pm_init(rdev)) { 1396 DRM_ERROR("Failed to register debugfs file for dpm!\n"); 1397 } 1398 1399 DRM_INFO("radeon: dpm initialized\n"); 1400 1401 return 0; 1402 1403 dpm_failed: 1404 rdev->pm.dpm_enabled = false; 1405 if ((rdev->family >= CHIP_BARTS) && 1406 (rdev->family <= CHIP_CAYMAN) && 1407 rdev->mc_fw) { 1408 if (rdev->pm.default_vddc) 1409 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc, 1410 SET_VOLTAGE_TYPE_ASIC_VDDC); 1411 if (rdev->pm.default_vddci) 1412 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci, 1413 SET_VOLTAGE_TYPE_ASIC_VDDCI); 1414 if (rdev->pm.default_sclk) 1415 radeon_set_engine_clock(rdev, rdev->pm.default_sclk); 1416 if (rdev->pm.default_mclk) 1417 radeon_set_memory_clock(rdev, rdev->pm.default_mclk); 1418 } 1419 DRM_ERROR("radeon: dpm initialization failed\n"); 1420 return ret; 1421 } 1422 1423 struct radeon_dpm_quirk { 1424 u32 chip_vendor; 1425 u32 chip_device; 1426 u32 subsys_vendor; 1427 u32 subsys_device; 1428 }; 1429 1430 /* cards with dpm stability problems */ 1431 static struct radeon_dpm_quirk radeon_dpm_quirk_list[] = { 1432 /* TURKS - https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1386534 */ 1433 { PCI_VENDOR_ID_ATI, 0x6759, 0x1682, 0x3195 }, 1434 /* TURKS - https://bugzilla.kernel.org/show_bug.cgi?id=83731 */ 1435 { PCI_VENDOR_ID_ATI, 0x6840, 0x1179, 0xfb81 }, 1436 { 0, 0, 0, 0 }, 1437 }; 1438 1439 int radeon_pm_init(struct radeon_device *rdev) 1440 { 1441 struct radeon_dpm_quirk *p = radeon_dpm_quirk_list; 1442 bool disable_dpm = false; 1443 1444 /* Apply dpm quirks */ 1445 while (p && p->chip_device != 0) { 1446 if (rdev->pdev->vendor == p->chip_vendor && 1447 rdev->pdev->device == p->chip_device && 1448 rdev->pdev->subsystem_vendor == p->subsys_vendor && 1449 rdev->pdev->subsystem_device == p->subsys_device) { 1450 disable_dpm = true; 1451 break; 1452 } 1453 ++p; 1454 } 1455 1456 /* enable dpm on rv6xx+ */ 1457 switch (rdev->family) { 1458 case CHIP_RV610: 1459 case CHIP_RV630: 1460 case CHIP_RV620: 1461 case CHIP_RV635: 1462 case CHIP_RV670: 1463 case CHIP_RS780: 1464 case CHIP_RS880: 1465 case CHIP_RV770: 1466 /* DPM requires the RLC, RV770+ dGPU requires SMC */ 1467 if (!rdev->rlc_fw) 1468 rdev->pm.pm_method = PM_METHOD_PROFILE; 1469 else if ((rdev->family >= CHIP_RV770) && 1470 (!(rdev->flags & RADEON_IS_IGP)) && 1471 (!rdev->smc_fw)) 1472 rdev->pm.pm_method = PM_METHOD_PROFILE; 1473 else if (radeon_dpm == 1) 1474 rdev->pm.pm_method = PM_METHOD_DPM; 1475 else 1476 rdev->pm.pm_method = PM_METHOD_PROFILE; 1477 break; 1478 case CHIP_RV730: 1479 case CHIP_RV710: 1480 case CHIP_RV740: 1481 case CHIP_CEDAR: 1482 case CHIP_REDWOOD: 1483 case CHIP_JUNIPER: 1484 case CHIP_CYPRESS: 1485 case CHIP_HEMLOCK: 1486 case CHIP_PALM: 1487 case CHIP_SUMO: 1488 case CHIP_SUMO2: 1489 case CHIP_BARTS: 1490 case CHIP_TURKS: 1491 case CHIP_CAICOS: 1492 case CHIP_CAYMAN: 1493 case CHIP_ARUBA: 1494 case CHIP_TAHITI: 1495 case CHIP_PITCAIRN: 1496 case CHIP_VERDE: 1497 case CHIP_OLAND: 1498 case CHIP_HAINAN: 1499 case CHIP_BONAIRE: 1500 case CHIP_KABINI: 1501 case CHIP_KAVERI: 1502 case CHIP_HAWAII: 1503 case CHIP_MULLINS: 1504 /* DPM requires the RLC, RV770+ dGPU requires SMC */ 1505 if (!rdev->rlc_fw) 1506 rdev->pm.pm_method = PM_METHOD_PROFILE; 1507 else if ((rdev->family >= CHIP_RV770) && 1508 (!(rdev->flags & RADEON_IS_IGP)) && 1509 (!rdev->smc_fw)) 1510 rdev->pm.pm_method = PM_METHOD_PROFILE; 1511 else if (disable_dpm && (radeon_dpm == -1)) 1512 rdev->pm.pm_method = PM_METHOD_PROFILE; 1513 else if (radeon_dpm == 0) 1514 rdev->pm.pm_method = PM_METHOD_PROFILE; 1515 else 1516 rdev->pm.pm_method = PM_METHOD_DPM; 1517 break; 1518 default: 1519 /* default to profile method */ 1520 rdev->pm.pm_method = PM_METHOD_PROFILE; 1521 break; 1522 } 1523 1524 if (rdev->pm.pm_method == PM_METHOD_DPM) 1525 return radeon_pm_init_dpm(rdev); 1526 else 1527 return radeon_pm_init_old(rdev); 1528 } 1529 1530 int radeon_pm_late_init(struct radeon_device *rdev) 1531 { 1532 int ret = 0; 1533 1534 if (rdev->pm.pm_method == PM_METHOD_DPM) { 1535 if (rdev->pm.dpm_enabled) { 1536 if (!rdev->pm.sysfs_initialized) { 1537 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_state); 1538 if (ret) 1539 DRM_ERROR("failed to create device file for dpm state\n"); 1540 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_force_performance_level); 1541 if (ret) 1542 DRM_ERROR("failed to create device file for dpm state\n"); 1543 /* XXX: these are noops for dpm but are here for backwards compat */ 1544 ret = device_create_file(rdev->dev, &dev_attr_power_profile); 1545 if (ret) 1546 DRM_ERROR("failed to create device file for power profile\n"); 1547 ret = device_create_file(rdev->dev, &dev_attr_power_method); 1548 if (ret) 1549 DRM_ERROR("failed to create device file for power method\n"); 1550 rdev->pm.sysfs_initialized = true; 1551 } 1552 1553 mutex_lock(&rdev->pm.mutex); 1554 ret = radeon_dpm_late_enable(rdev); 1555 mutex_unlock(&rdev->pm.mutex); 1556 if (ret) { 1557 rdev->pm.dpm_enabled = false; 1558 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n"); 1559 } else { 1560 /* set the dpm state for PX since there won't be 1561 * a modeset to call this. 1562 */ 1563 radeon_pm_compute_clocks(rdev); 1564 } 1565 } 1566 } else { 1567 if ((rdev->pm.num_power_states > 1) && 1568 (!rdev->pm.sysfs_initialized)) { 1569 /* where's the best place to put these? */ 1570 ret = device_create_file(rdev->dev, &dev_attr_power_profile); 1571 if (ret) 1572 DRM_ERROR("failed to create device file for power profile\n"); 1573 ret = device_create_file(rdev->dev, &dev_attr_power_method); 1574 if (ret) 1575 DRM_ERROR("failed to create device file for power method\n"); 1576 if (!ret) 1577 rdev->pm.sysfs_initialized = true; 1578 } 1579 } 1580 return ret; 1581 } 1582 1583 static void radeon_pm_fini_old(struct radeon_device *rdev) 1584 { 1585 if (rdev->pm.num_power_states > 1) { 1586 mutex_lock(&rdev->pm.mutex); 1587 if (rdev->pm.pm_method == PM_METHOD_PROFILE) { 1588 rdev->pm.profile = PM_PROFILE_DEFAULT; 1589 radeon_pm_update_profile(rdev); 1590 radeon_pm_set_clocks(rdev); 1591 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) { 1592 /* reset default clocks */ 1593 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED; 1594 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT; 1595 radeon_pm_set_clocks(rdev); 1596 } 1597 mutex_unlock(&rdev->pm.mutex); 1598 1599 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work); 1600 1601 device_remove_file(rdev->dev, &dev_attr_power_profile); 1602 device_remove_file(rdev->dev, &dev_attr_power_method); 1603 } 1604 1605 radeon_hwmon_fini(rdev); 1606 kfree(rdev->pm.power_state); 1607 } 1608 1609 static void radeon_pm_fini_dpm(struct radeon_device *rdev) 1610 { 1611 if (rdev->pm.num_power_states > 1) { 1612 mutex_lock(&rdev->pm.mutex); 1613 radeon_dpm_disable(rdev); 1614 mutex_unlock(&rdev->pm.mutex); 1615 1616 device_remove_file(rdev->dev, &dev_attr_power_dpm_state); 1617 device_remove_file(rdev->dev, &dev_attr_power_dpm_force_performance_level); 1618 /* XXX backwards compat */ 1619 device_remove_file(rdev->dev, &dev_attr_power_profile); 1620 device_remove_file(rdev->dev, &dev_attr_power_method); 1621 } 1622 radeon_dpm_fini(rdev); 1623 1624 radeon_hwmon_fini(rdev); 1625 kfree(rdev->pm.power_state); 1626 } 1627 1628 void radeon_pm_fini(struct radeon_device *rdev) 1629 { 1630 if (rdev->pm.pm_method == PM_METHOD_DPM) 1631 radeon_pm_fini_dpm(rdev); 1632 else 1633 radeon_pm_fini_old(rdev); 1634 } 1635 1636 static void radeon_pm_compute_clocks_old(struct radeon_device *rdev) 1637 { 1638 struct drm_device *ddev = rdev->ddev; 1639 struct drm_crtc *crtc; 1640 struct radeon_crtc *radeon_crtc; 1641 1642 if (rdev->pm.num_power_states < 2) 1643 return; 1644 1645 mutex_lock(&rdev->pm.mutex); 1646 1647 rdev->pm.active_crtcs = 0; 1648 rdev->pm.active_crtc_count = 0; 1649 if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) { 1650 list_for_each_entry(crtc, 1651 &ddev->mode_config.crtc_list, head) { 1652 radeon_crtc = to_radeon_crtc(crtc); 1653 if (radeon_crtc->enabled) { 1654 rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id); 1655 rdev->pm.active_crtc_count++; 1656 } 1657 } 1658 } 1659 1660 if (rdev->pm.pm_method == PM_METHOD_PROFILE) { 1661 radeon_pm_update_profile(rdev); 1662 radeon_pm_set_clocks(rdev); 1663 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) { 1664 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) { 1665 if (rdev->pm.active_crtc_count > 1) { 1666 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) { 1667 cancel_delayed_work(&rdev->pm.dynpm_idle_work); 1668 1669 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED; 1670 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT; 1671 radeon_pm_get_dynpm_state(rdev); 1672 radeon_pm_set_clocks(rdev); 1673 1674 DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n"); 1675 } 1676 } else if (rdev->pm.active_crtc_count == 1) { 1677 /* TODO: Increase clocks if needed for current mode */ 1678 1679 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) { 1680 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE; 1681 rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK; 1682 radeon_pm_get_dynpm_state(rdev); 1683 radeon_pm_set_clocks(rdev); 1684 1685 schedule_delayed_work(&rdev->pm.dynpm_idle_work, 1686 msecs_to_jiffies(RADEON_IDLE_LOOP_MS)); 1687 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) { 1688 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE; 1689 schedule_delayed_work(&rdev->pm.dynpm_idle_work, 1690 msecs_to_jiffies(RADEON_IDLE_LOOP_MS)); 1691 DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n"); 1692 } 1693 } else { /* count == 0 */ 1694 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) { 1695 cancel_delayed_work(&rdev->pm.dynpm_idle_work); 1696 1697 rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM; 1698 rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM; 1699 radeon_pm_get_dynpm_state(rdev); 1700 radeon_pm_set_clocks(rdev); 1701 } 1702 } 1703 } 1704 } 1705 1706 mutex_unlock(&rdev->pm.mutex); 1707 } 1708 1709 static void radeon_pm_compute_clocks_dpm(struct radeon_device *rdev) 1710 { 1711 struct drm_device *ddev = rdev->ddev; 1712 struct drm_crtc *crtc; 1713 struct radeon_crtc *radeon_crtc; 1714 1715 if (!rdev->pm.dpm_enabled) 1716 return; 1717 1718 mutex_lock(&rdev->pm.mutex); 1719 1720 /* update active crtc counts */ 1721 rdev->pm.dpm.new_active_crtcs = 0; 1722 rdev->pm.dpm.new_active_crtc_count = 0; 1723 if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) { 1724 list_for_each_entry(crtc, 1725 &ddev->mode_config.crtc_list, head) { 1726 radeon_crtc = to_radeon_crtc(crtc); 1727 if (crtc->enabled) { 1728 rdev->pm.dpm.new_active_crtcs |= (1 << radeon_crtc->crtc_id); 1729 rdev->pm.dpm.new_active_crtc_count++; 1730 } 1731 } 1732 } 1733 1734 /* update battery/ac status */ 1735 if (power_supply_is_system_supplied() > 0) 1736 rdev->pm.dpm.ac_power = true; 1737 else 1738 rdev->pm.dpm.ac_power = false; 1739 1740 radeon_dpm_change_power_state_locked(rdev); 1741 1742 mutex_unlock(&rdev->pm.mutex); 1743 1744 } 1745 1746 void radeon_pm_compute_clocks(struct radeon_device *rdev) 1747 { 1748 if (rdev->pm.pm_method == PM_METHOD_DPM) 1749 radeon_pm_compute_clocks_dpm(rdev); 1750 else 1751 radeon_pm_compute_clocks_old(rdev); 1752 } 1753 1754 static bool radeon_pm_in_vbl(struct radeon_device *rdev) 1755 { 1756 int crtc, vpos, hpos, vbl_status; 1757 bool in_vbl = true; 1758 1759 /* Iterate over all active crtc's. All crtc's must be in vblank, 1760 * otherwise return in_vbl == false. 1761 */ 1762 for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) { 1763 if (rdev->pm.active_crtcs & (1 << crtc)) { 1764 vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev, 1765 crtc, 1766 USE_REAL_VBLANKSTART, 1767 &vpos, &hpos, NULL, NULL, 1768 &rdev->mode_info.crtcs[crtc]->base.hwmode); 1769 if ((vbl_status & DRM_SCANOUTPOS_VALID) && 1770 !(vbl_status & DRM_SCANOUTPOS_IN_VBLANK)) 1771 in_vbl = false; 1772 } 1773 } 1774 1775 return in_vbl; 1776 } 1777 1778 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish) 1779 { 1780 u32 stat_crtc = 0; 1781 bool in_vbl = radeon_pm_in_vbl(rdev); 1782 1783 if (in_vbl == false) 1784 DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc, 1785 finish ? "exit" : "entry"); 1786 return in_vbl; 1787 } 1788 1789 static void radeon_dynpm_idle_work_handler(struct work_struct *work) 1790 { 1791 struct radeon_device *rdev; 1792 int resched; 1793 rdev = container_of(work, struct radeon_device, 1794 pm.dynpm_idle_work.work); 1795 1796 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev); 1797 mutex_lock(&rdev->pm.mutex); 1798 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) { 1799 int not_processed = 0; 1800 int i; 1801 1802 for (i = 0; i < RADEON_NUM_RINGS; ++i) { 1803 struct radeon_ring *ring = &rdev->ring[i]; 1804 1805 if (ring->ready) { 1806 not_processed += radeon_fence_count_emitted(rdev, i); 1807 if (not_processed >= 3) 1808 break; 1809 } 1810 } 1811 1812 if (not_processed >= 3) { /* should upclock */ 1813 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) { 1814 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; 1815 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE && 1816 rdev->pm.dynpm_can_upclock) { 1817 rdev->pm.dynpm_planned_action = 1818 DYNPM_ACTION_UPCLOCK; 1819 rdev->pm.dynpm_action_timeout = jiffies + 1820 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS); 1821 } 1822 } else if (not_processed == 0) { /* should downclock */ 1823 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) { 1824 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; 1825 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE && 1826 rdev->pm.dynpm_can_downclock) { 1827 rdev->pm.dynpm_planned_action = 1828 DYNPM_ACTION_DOWNCLOCK; 1829 rdev->pm.dynpm_action_timeout = jiffies + 1830 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS); 1831 } 1832 } 1833 1834 /* Note, radeon_pm_set_clocks is called with static_switch set 1835 * to false since we want to wait for vbl to avoid flicker. 1836 */ 1837 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE && 1838 jiffies > rdev->pm.dynpm_action_timeout) { 1839 radeon_pm_get_dynpm_state(rdev); 1840 radeon_pm_set_clocks(rdev); 1841 } 1842 1843 schedule_delayed_work(&rdev->pm.dynpm_idle_work, 1844 msecs_to_jiffies(RADEON_IDLE_LOOP_MS)); 1845 } 1846 mutex_unlock(&rdev->pm.mutex); 1847 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched); 1848 } 1849 1850 /* 1851 * Debugfs info 1852 */ 1853 #if defined(CONFIG_DEBUG_FS) 1854 1855 static int radeon_debugfs_pm_info(struct seq_file *m, void *data) 1856 { 1857 struct drm_info_node *node = (struct drm_info_node *) m->private; 1858 struct drm_device *dev = node->minor->dev; 1859 struct radeon_device *rdev = dev->dev_private; 1860 struct drm_device *ddev = rdev->ddev; 1861 1862 if ((rdev->flags & RADEON_IS_PX) && 1863 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) { 1864 seq_printf(m, "PX asic powered off\n"); 1865 } else if (rdev->pm.dpm_enabled) { 1866 mutex_lock(&rdev->pm.mutex); 1867 if (rdev->asic->dpm.debugfs_print_current_performance_level) 1868 radeon_dpm_debugfs_print_current_performance_level(rdev, m); 1869 else 1870 seq_printf(m, "Debugfs support not implemented for this asic\n"); 1871 mutex_unlock(&rdev->pm.mutex); 1872 } else { 1873 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk); 1874 /* radeon_get_engine_clock is not reliable on APUs so just print the current clock */ 1875 if ((rdev->family >= CHIP_PALM) && (rdev->flags & RADEON_IS_IGP)) 1876 seq_printf(m, "current engine clock: %u0 kHz\n", rdev->pm.current_sclk); 1877 else 1878 seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev)); 1879 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk); 1880 if (rdev->asic->pm.get_memory_clock) 1881 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev)); 1882 if (rdev->pm.current_vddc) 1883 seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc); 1884 if (rdev->asic->pm.get_pcie_lanes) 1885 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev)); 1886 } 1887 1888 return 0; 1889 } 1890 1891 static struct drm_info_list radeon_pm_info_list[] = { 1892 {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL}, 1893 }; 1894 #endif 1895 1896 static int radeon_debugfs_pm_init(struct radeon_device *rdev) 1897 { 1898 #if defined(CONFIG_DEBUG_FS) 1899 return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list)); 1900 #else 1901 return 0; 1902 #endif 1903 } 1904
Indexes created Sat Oct 25 01:09:55 GMT 2025