radeon_r100.c revision 1.1.1.1
1 /* $NetBSD: radeon_r100.c,v 1.1.1.1 2021/12/18 20:15:49 riastradh Exp $ */ 2 3 /* 4 * Copyright 2008 Advanced Micro Devices, Inc. 5 * Copyright 2008 Red Hat Inc. 6 * Copyright 2009 Jerome Glisse. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: Dave Airlie 27 * Alex Deucher 28 * Jerome Glisse 29 */ 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: radeon_r100.c,v 1.1.1.1 2021/12/18 20:15:49 riastradh Exp $"); 33 34 #include <linux/firmware.h> 35 #include <linux/module.h> 36 #include <linux/pci.h> 37 #include <linux/seq_file.h> 38 #include <linux/slab.h> 39 40 #include <drm/drm_debugfs.h> 41 #include <drm/drm_device.h> 42 #include <drm/drm_file.h> 43 #include <drm/drm_fourcc.h> 44 #include <drm/drm_vblank.h> 45 #include <drm/radeon_drm.h> 46 47 #include "atom.h" 48 #include "r100_reg_safe.h" 49 #include "r100d.h" 50 #include "radeon.h" 51 #include "radeon_asic.h" 52 #include "radeon_reg.h" 53 #include "rn50_reg_safe.h" 54 #include "rs100d.h" 55 #include "rv200d.h" 56 #include "rv250d.h" 57 58 /* Firmware Names */ 59 #define FIRMWARE_R100 "radeon/R100_cp.bin" 60 #define FIRMWARE_R200 "radeon/R200_cp.bin" 61 #define FIRMWARE_R300 "radeon/R300_cp.bin" 62 #define FIRMWARE_R420 "radeon/R420_cp.bin" 63 #define FIRMWARE_RS690 "radeon/RS690_cp.bin" 64 #define FIRMWARE_RS600 "radeon/RS600_cp.bin" 65 #define FIRMWARE_R520 "radeon/R520_cp.bin" 66 67 MODULE_FIRMWARE(FIRMWARE_R100); 68 MODULE_FIRMWARE(FIRMWARE_R200); 69 MODULE_FIRMWARE(FIRMWARE_R300); 70 MODULE_FIRMWARE(FIRMWARE_R420); 71 MODULE_FIRMWARE(FIRMWARE_RS690); 72 MODULE_FIRMWARE(FIRMWARE_RS600); 73 MODULE_FIRMWARE(FIRMWARE_R520); 74 75 #include "r100_track.h" 76 77 /* This files gather functions specifics to: 78 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 79 * and others in some cases. 80 */ 81 82 static bool r100_is_in_vblank(struct radeon_device *rdev, int crtc) 83 { 84 if (crtc == 0) { 85 if (RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR) 86 return true; 87 else 88 return false; 89 } else { 90 if (RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR) 91 return true; 92 else 93 return false; 94 } 95 } 96 97 static bool r100_is_counter_moving(struct radeon_device *rdev, int crtc) 98 { 99 u32 vline1, vline2; 100 101 if (crtc == 0) { 102 vline1 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; 103 vline2 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; 104 } else { 105 vline1 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; 106 vline2 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; 107 } 108 if (vline1 != vline2) 109 return true; 110 else 111 return false; 112 } 113 114 /** 115 * r100_wait_for_vblank - vblank wait asic callback. 116 * 117 * @rdev: radeon_device pointer 118 * @crtc: crtc to wait for vblank on 119 * 120 * Wait for vblank on the requested crtc (r1xx-r4xx). 121 */ 122 void r100_wait_for_vblank(struct radeon_device *rdev, int crtc) 123 { 124 unsigned i = 0; 125 126 if (crtc >= rdev->num_crtc) 127 return; 128 129 if (crtc == 0) { 130 if (!(RREG32(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EN)) 131 return; 132 } else { 133 if (!(RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN)) 134 return; 135 } 136 137 /* depending on when we hit vblank, we may be close to active; if so, 138 * wait for another frame. 139 */ 140 while (r100_is_in_vblank(rdev, crtc)) { 141 if (i++ % 100 == 0) { 142 if (!r100_is_counter_moving(rdev, crtc)) 143 break; 144 } 145 } 146 147 while (!r100_is_in_vblank(rdev, crtc)) { 148 if (i++ % 100 == 0) { 149 if (!r100_is_counter_moving(rdev, crtc)) 150 break; 151 } 152 } 153 } 154 155 /** 156 * r100_page_flip - pageflip callback. 157 * 158 * @rdev: radeon_device pointer 159 * @crtc_id: crtc to cleanup pageflip on 160 * @crtc_base: new address of the crtc (GPU MC address) 161 * 162 * Does the actual pageflip (r1xx-r4xx). 163 * During vblank we take the crtc lock and wait for the update_pending 164 * bit to go high, when it does, we release the lock, and allow the 165 * double buffered update to take place. 166 */ 167 void r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base, bool async) 168 { 169 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 170 u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK; 171 int i; 172 173 /* Lock the graphics update lock */ 174 /* update the scanout addresses */ 175 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp); 176 177 /* Wait for update_pending to go high. */ 178 for (i = 0; i < rdev->usec_timeout; i++) { 179 if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET) 180 break; 181 udelay(1); 182 } 183 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n"); 184 185 /* Unlock the lock, so double-buffering can take place inside vblank */ 186 tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK; 187 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp); 188 189 } 190 191 /** 192 * r100_page_flip_pending - check if page flip is still pending 193 * 194 * @rdev: radeon_device pointer 195 * @crtc_id: crtc to check 196 * 197 * Check if the last pagefilp is still pending (r1xx-r4xx). 198 * Returns the current update pending status. 199 */ 200 bool r100_page_flip_pending(struct radeon_device *rdev, int crtc_id) 201 { 202 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 203 204 /* Return current update_pending status: */ 205 return !!(RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & 206 RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET); 207 } 208 209 /** 210 * r100_pm_get_dynpm_state - look up dynpm power state callback. 211 * 212 * @rdev: radeon_device pointer 213 * 214 * Look up the optimal power state based on the 215 * current state of the GPU (r1xx-r5xx). 216 * Used for dynpm only. 217 */ 218 void r100_pm_get_dynpm_state(struct radeon_device *rdev) 219 { 220 int i; 221 rdev->pm.dynpm_can_upclock = true; 222 rdev->pm.dynpm_can_downclock = true; 223 224 switch (rdev->pm.dynpm_planned_action) { 225 case DYNPM_ACTION_MINIMUM: 226 rdev->pm.requested_power_state_index = 0; 227 rdev->pm.dynpm_can_downclock = false; 228 break; 229 case DYNPM_ACTION_DOWNCLOCK: 230 if (rdev->pm.current_power_state_index == 0) { 231 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 232 rdev->pm.dynpm_can_downclock = false; 233 } else { 234 if (rdev->pm.active_crtc_count > 1) { 235 for (i = 0; i < rdev->pm.num_power_states; i++) { 236 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 237 continue; 238 else if (i >= rdev->pm.current_power_state_index) { 239 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 240 break; 241 } else { 242 rdev->pm.requested_power_state_index = i; 243 break; 244 } 245 } 246 } else 247 rdev->pm.requested_power_state_index = 248 rdev->pm.current_power_state_index - 1; 249 } 250 /* don't use the power state if crtcs are active and no display flag is set */ 251 if ((rdev->pm.active_crtc_count > 0) && 252 (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags & 253 RADEON_PM_MODE_NO_DISPLAY)) { 254 rdev->pm.requested_power_state_index++; 255 } 256 break; 257 case DYNPM_ACTION_UPCLOCK: 258 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) { 259 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 260 rdev->pm.dynpm_can_upclock = false; 261 } else { 262 if (rdev->pm.active_crtc_count > 1) { 263 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) { 264 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 265 continue; 266 else if (i <= rdev->pm.current_power_state_index) { 267 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 268 break; 269 } else { 270 rdev->pm.requested_power_state_index = i; 271 break; 272 } 273 } 274 } else 275 rdev->pm.requested_power_state_index = 276 rdev->pm.current_power_state_index + 1; 277 } 278 break; 279 case DYNPM_ACTION_DEFAULT: 280 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; 281 rdev->pm.dynpm_can_upclock = false; 282 break; 283 case DYNPM_ACTION_NONE: 284 default: 285 DRM_ERROR("Requested mode for not defined action\n"); 286 return; 287 } 288 /* only one clock mode per power state */ 289 rdev->pm.requested_clock_mode_index = 0; 290 291 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n", 292 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 293 clock_info[rdev->pm.requested_clock_mode_index].sclk, 294 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 295 clock_info[rdev->pm.requested_clock_mode_index].mclk, 296 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 297 pcie_lanes); 298 } 299 300 /** 301 * r100_pm_init_profile - Initialize power profiles callback. 302 * 303 * @rdev: radeon_device pointer 304 * 305 * Initialize the power states used in profile mode 306 * (r1xx-r3xx). 307 * Used for profile mode only. 308 */ 309 void r100_pm_init_profile(struct radeon_device *rdev) 310 { 311 /* default */ 312 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 313 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 314 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 315 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 316 /* low sh */ 317 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0; 318 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0; 319 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 320 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 321 /* mid sh */ 322 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0; 323 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0; 324 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 325 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 326 /* high sh */ 327 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0; 328 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 329 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 330 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 331 /* low mh */ 332 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0; 333 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 334 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 335 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 336 /* mid mh */ 337 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0; 338 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 339 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 340 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 341 /* high mh */ 342 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0; 343 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 344 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 345 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 346 } 347 348 /** 349 * r100_pm_misc - set additional pm hw parameters callback. 350 * 351 * @rdev: radeon_device pointer 352 * 353 * Set non-clock parameters associated with a power state 354 * (voltage, pcie lanes, etc.) (r1xx-r4xx). 355 */ 356 void r100_pm_misc(struct radeon_device *rdev) 357 { 358 int requested_index = rdev->pm.requested_power_state_index; 359 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index]; 360 struct radeon_voltage *voltage = &ps->clock_info[0].voltage; 361 u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl; 362 363 if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) { 364 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) { 365 tmp = RREG32(voltage->gpio.reg); 366 if (voltage->active_high) 367 tmp |= voltage->gpio.mask; 368 else 369 tmp &= ~(voltage->gpio.mask); 370 WREG32(voltage->gpio.reg, tmp); 371 if (voltage->delay) 372 udelay(voltage->delay); 373 } else { 374 tmp = RREG32(voltage->gpio.reg); 375 if (voltage->active_high) 376 tmp &= ~voltage->gpio.mask; 377 else 378 tmp |= voltage->gpio.mask; 379 WREG32(voltage->gpio.reg, tmp); 380 if (voltage->delay) 381 udelay(voltage->delay); 382 } 383 } 384 385 sclk_cntl = RREG32_PLL(SCLK_CNTL); 386 sclk_cntl2 = RREG32_PLL(SCLK_CNTL2); 387 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3); 388 sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL); 389 sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3); 390 if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) { 391 sclk_more_cntl |= REDUCED_SPEED_SCLK_EN; 392 if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE) 393 sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE; 394 else 395 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE; 396 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2) 397 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0); 398 else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4) 399 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2); 400 } else 401 sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN; 402 403 if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) { 404 sclk_more_cntl |= IO_CG_VOLTAGE_DROP; 405 if (voltage->delay) { 406 sclk_more_cntl |= VOLTAGE_DROP_SYNC; 407 switch (voltage->delay) { 408 case 33: 409 sclk_more_cntl |= VOLTAGE_DELAY_SEL(0); 410 break; 411 case 66: 412 sclk_more_cntl |= VOLTAGE_DELAY_SEL(1); 413 break; 414 case 99: 415 sclk_more_cntl |= VOLTAGE_DELAY_SEL(2); 416 break; 417 case 132: 418 sclk_more_cntl |= VOLTAGE_DELAY_SEL(3); 419 break; 420 } 421 } else 422 sclk_more_cntl &= ~VOLTAGE_DROP_SYNC; 423 } else 424 sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP; 425 426 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN) 427 sclk_cntl &= ~FORCE_HDP; 428 else 429 sclk_cntl |= FORCE_HDP; 430 431 WREG32_PLL(SCLK_CNTL, sclk_cntl); 432 WREG32_PLL(SCLK_CNTL2, sclk_cntl2); 433 WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl); 434 435 /* set pcie lanes */ 436 if ((rdev->flags & RADEON_IS_PCIE) && 437 !(rdev->flags & RADEON_IS_IGP) && 438 rdev->asic->pm.set_pcie_lanes && 439 (ps->pcie_lanes != 440 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) { 441 radeon_set_pcie_lanes(rdev, 442 ps->pcie_lanes); 443 DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes); 444 } 445 } 446 447 /** 448 * r100_pm_prepare - pre-power state change callback. 449 * 450 * @rdev: radeon_device pointer 451 * 452 * Prepare for a power state change (r1xx-r4xx). 453 */ 454 void r100_pm_prepare(struct radeon_device *rdev) 455 { 456 struct drm_device *ddev = rdev->ddev; 457 struct drm_crtc *crtc; 458 struct radeon_crtc *radeon_crtc; 459 u32 tmp; 460 461 /* disable any active CRTCs */ 462 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { 463 radeon_crtc = to_radeon_crtc(crtc); 464 if (radeon_crtc->enabled) { 465 if (radeon_crtc->crtc_id) { 466 tmp = RREG32(RADEON_CRTC2_GEN_CNTL); 467 tmp |= RADEON_CRTC2_DISP_REQ_EN_B; 468 WREG32(RADEON_CRTC2_GEN_CNTL, tmp); 469 } else { 470 tmp = RREG32(RADEON_CRTC_GEN_CNTL); 471 tmp |= RADEON_CRTC_DISP_REQ_EN_B; 472 WREG32(RADEON_CRTC_GEN_CNTL, tmp); 473 } 474 } 475 } 476 } 477 478 /** 479 * r100_pm_finish - post-power state change callback. 480 * 481 * @rdev: radeon_device pointer 482 * 483 * Clean up after a power state change (r1xx-r4xx). 484 */ 485 void r100_pm_finish(struct radeon_device *rdev) 486 { 487 struct drm_device *ddev = rdev->ddev; 488 struct drm_crtc *crtc; 489 struct radeon_crtc *radeon_crtc; 490 u32 tmp; 491 492 /* enable any active CRTCs */ 493 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { 494 radeon_crtc = to_radeon_crtc(crtc); 495 if (radeon_crtc->enabled) { 496 if (radeon_crtc->crtc_id) { 497 tmp = RREG32(RADEON_CRTC2_GEN_CNTL); 498 tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B; 499 WREG32(RADEON_CRTC2_GEN_CNTL, tmp); 500 } else { 501 tmp = RREG32(RADEON_CRTC_GEN_CNTL); 502 tmp &= ~RADEON_CRTC_DISP_REQ_EN_B; 503 WREG32(RADEON_CRTC_GEN_CNTL, tmp); 504 } 505 } 506 } 507 } 508 509 /** 510 * r100_gui_idle - gui idle callback. 511 * 512 * @rdev: radeon_device pointer 513 * 514 * Check of the GUI (2D/3D engines) are idle (r1xx-r5xx). 515 * Returns true if idle, false if not. 516 */ 517 bool r100_gui_idle(struct radeon_device *rdev) 518 { 519 if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE) 520 return false; 521 else 522 return true; 523 } 524 525 /* hpd for digital panel detect/disconnect */ 526 /** 527 * r100_hpd_sense - hpd sense callback. 528 * 529 * @rdev: radeon_device pointer 530 * @hpd: hpd (hotplug detect) pin 531 * 532 * Checks if a digital monitor is connected (r1xx-r4xx). 533 * Returns true if connected, false if not connected. 534 */ 535 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) 536 { 537 bool connected = false; 538 539 switch (hpd) { 540 case RADEON_HPD_1: 541 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE) 542 connected = true; 543 break; 544 case RADEON_HPD_2: 545 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE) 546 connected = true; 547 break; 548 default: 549 break; 550 } 551 return connected; 552 } 553 554 /** 555 * r100_hpd_set_polarity - hpd set polarity callback. 556 * 557 * @rdev: radeon_device pointer 558 * @hpd: hpd (hotplug detect) pin 559 * 560 * Set the polarity of the hpd pin (r1xx-r4xx). 561 */ 562 void r100_hpd_set_polarity(struct radeon_device *rdev, 563 enum radeon_hpd_id hpd) 564 { 565 u32 tmp; 566 bool connected = r100_hpd_sense(rdev, hpd); 567 568 switch (hpd) { 569 case RADEON_HPD_1: 570 tmp = RREG32(RADEON_FP_GEN_CNTL); 571 if (connected) 572 tmp &= ~RADEON_FP_DETECT_INT_POL; 573 else 574 tmp |= RADEON_FP_DETECT_INT_POL; 575 WREG32(RADEON_FP_GEN_CNTL, tmp); 576 break; 577 case RADEON_HPD_2: 578 tmp = RREG32(RADEON_FP2_GEN_CNTL); 579 if (connected) 580 tmp &= ~RADEON_FP2_DETECT_INT_POL; 581 else 582 tmp |= RADEON_FP2_DETECT_INT_POL; 583 WREG32(RADEON_FP2_GEN_CNTL, tmp); 584 break; 585 default: 586 break; 587 } 588 } 589 590 /** 591 * r100_hpd_init - hpd setup callback. 592 * 593 * @rdev: radeon_device pointer 594 * 595 * Setup the hpd pins used by the card (r1xx-r4xx). 596 * Set the polarity, and enable the hpd interrupts. 597 */ 598 void r100_hpd_init(struct radeon_device *rdev) 599 { 600 struct drm_device *dev = rdev->ddev; 601 struct drm_connector *connector; 602 unsigned enable = 0; 603 604 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 605 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 606 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) 607 enable |= 1 << radeon_connector->hpd.hpd; 608 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); 609 } 610 radeon_irq_kms_enable_hpd(rdev, enable); 611 } 612 613 /** 614 * r100_hpd_fini - hpd tear down callback. 615 * 616 * @rdev: radeon_device pointer 617 * 618 * Tear down the hpd pins used by the card (r1xx-r4xx). 619 * Disable the hpd interrupts. 620 */ 621 void r100_hpd_fini(struct radeon_device *rdev) 622 { 623 struct drm_device *dev = rdev->ddev; 624 struct drm_connector *connector; 625 unsigned disable = 0; 626 627 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 628 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 629 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) 630 disable |= 1 << radeon_connector->hpd.hpd; 631 } 632 radeon_irq_kms_disable_hpd(rdev, disable); 633 } 634 635 /* 636 * PCI GART 637 */ 638 void r100_pci_gart_tlb_flush(struct radeon_device *rdev) 639 { 640 /* TODO: can we do somethings here ? */ 641 /* It seems hw only cache one entry so we should discard this 642 * entry otherwise if first GPU GART read hit this entry it 643 * could end up in wrong address. */ 644 } 645 646 int r100_pci_gart_init(struct radeon_device *rdev) 647 { 648 int r; 649 650 if (rdev->gart.ptr) { 651 WARN(1, "R100 PCI GART already initialized\n"); 652 return 0; 653 } 654 /* Initialize common gart structure */ 655 r = radeon_gart_init(rdev); 656 if (r) 657 return r; 658 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; 659 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush; 660 rdev->asic->gart.get_page_entry = &r100_pci_gart_get_page_entry; 661 rdev->asic->gart.set_page = &r100_pci_gart_set_page; 662 return radeon_gart_table_ram_alloc(rdev); 663 } 664 665 int r100_pci_gart_enable(struct radeon_device *rdev) 666 { 667 uint32_t tmp; 668 669 /* discard memory request outside of configured range */ 670 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS; 671 WREG32(RADEON_AIC_CNTL, tmp); 672 /* set address range for PCI address translate */ 673 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start); 674 WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end); 675 /* set PCI GART page-table base address */ 676 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr); 677 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN; 678 WREG32(RADEON_AIC_CNTL, tmp); 679 r100_pci_gart_tlb_flush(rdev); 680 DRM_INFO("PCI GART of %uM enabled (table at 0x%016llX).\n", 681 (unsigned)(rdev->mc.gtt_size >> 20), 682 (unsigned long long)rdev->gart.table_addr); 683 rdev->gart.ready = true; 684 return 0; 685 } 686 687 void r100_pci_gart_disable(struct radeon_device *rdev) 688 { 689 uint32_t tmp; 690 691 /* discard memory request outside of configured range */ 692 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS; 693 WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN); 694 WREG32(RADEON_AIC_LO_ADDR, 0); 695 WREG32(RADEON_AIC_HI_ADDR, 0); 696 } 697 698 uint64_t r100_pci_gart_get_page_entry(uint64_t addr, uint32_t flags) 699 { 700 return addr; 701 } 702 703 void r100_pci_gart_set_page(struct radeon_device *rdev, unsigned i, 704 uint64_t entry) 705 { 706 u32 *gtt = rdev->gart.ptr; 707 gtt[i] = cpu_to_le32(lower_32_bits(entry)); 708 } 709 710 void r100_pci_gart_fini(struct radeon_device *rdev) 711 { 712 radeon_gart_fini(rdev); 713 r100_pci_gart_disable(rdev); 714 radeon_gart_table_ram_free(rdev); 715 } 716 717 int r100_irq_set(struct radeon_device *rdev) 718 { 719 uint32_t tmp = 0; 720 721 if (!rdev->irq.installed) { 722 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); 723 WREG32(R_000040_GEN_INT_CNTL, 0); 724 return -EINVAL; 725 } 726 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { 727 tmp |= RADEON_SW_INT_ENABLE; 728 } 729 if (rdev->irq.crtc_vblank_int[0] || 730 atomic_read(&rdev->irq.pflip[0])) { 731 tmp |= RADEON_CRTC_VBLANK_MASK; 732 } 733 if (rdev->irq.crtc_vblank_int[1] || 734 atomic_read(&rdev->irq.pflip[1])) { 735 tmp |= RADEON_CRTC2_VBLANK_MASK; 736 } 737 if (rdev->irq.hpd[0]) { 738 tmp |= RADEON_FP_DETECT_MASK; 739 } 740 if (rdev->irq.hpd[1]) { 741 tmp |= RADEON_FP2_DETECT_MASK; 742 } 743 WREG32(RADEON_GEN_INT_CNTL, tmp); 744 745 /* read back to post the write */ 746 RREG32(RADEON_GEN_INT_CNTL); 747 748 return 0; 749 } 750 751 void r100_irq_disable(struct radeon_device *rdev) 752 { 753 u32 tmp; 754 755 WREG32(R_000040_GEN_INT_CNTL, 0); 756 /* Wait and acknowledge irq */ 757 mdelay(1); 758 tmp = RREG32(R_000044_GEN_INT_STATUS); 759 WREG32(R_000044_GEN_INT_STATUS, tmp); 760 } 761 762 static uint32_t r100_irq_ack(struct radeon_device *rdev) 763 { 764 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS); 765 uint32_t irq_mask = RADEON_SW_INT_TEST | 766 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT | 767 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT; 768 769 if (irqs) { 770 WREG32(RADEON_GEN_INT_STATUS, irqs); 771 } 772 return irqs & irq_mask; 773 } 774 775 int r100_irq_process(struct radeon_device *rdev) 776 { 777 uint32_t status, msi_rearm; 778 bool queue_hotplug = false; 779 780 status = r100_irq_ack(rdev); 781 if (!status) { 782 return IRQ_NONE; 783 } 784 if (rdev->shutdown) { 785 return IRQ_NONE; 786 } 787 while (status) { 788 /* SW interrupt */ 789 if (status & RADEON_SW_INT_TEST) { 790 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); 791 } 792 /* Vertical blank interrupts */ 793 if (status & RADEON_CRTC_VBLANK_STAT) { 794 if (rdev->irq.crtc_vblank_int[0]) { 795 drm_handle_vblank(rdev->ddev, 0); 796 rdev->pm.vblank_sync = true; 797 wake_up(&rdev->irq.vblank_queue); 798 } 799 if (atomic_read(&rdev->irq.pflip[0])) 800 radeon_crtc_handle_vblank(rdev, 0); 801 } 802 if (status & RADEON_CRTC2_VBLANK_STAT) { 803 if (rdev->irq.crtc_vblank_int[1]) { 804 drm_handle_vblank(rdev->ddev, 1); 805 rdev->pm.vblank_sync = true; 806 wake_up(&rdev->irq.vblank_queue); 807 } 808 if (atomic_read(&rdev->irq.pflip[1])) 809 radeon_crtc_handle_vblank(rdev, 1); 810 } 811 if (status & RADEON_FP_DETECT_STAT) { 812 queue_hotplug = true; 813 DRM_DEBUG("HPD1\n"); 814 } 815 if (status & RADEON_FP2_DETECT_STAT) { 816 queue_hotplug = true; 817 DRM_DEBUG("HPD2\n"); 818 } 819 status = r100_irq_ack(rdev); 820 } 821 if (queue_hotplug) 822 schedule_delayed_work(&rdev->hotplug_work, 0); 823 if (rdev->msi_enabled) { 824 switch (rdev->family) { 825 case CHIP_RS400: 826 case CHIP_RS480: 827 msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM; 828 WREG32(RADEON_AIC_CNTL, msi_rearm); 829 WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM); 830 break; 831 default: 832 WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN); 833 break; 834 } 835 } 836 return IRQ_HANDLED; 837 } 838 839 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc) 840 { 841 if (crtc == 0) 842 return RREG32(RADEON_CRTC_CRNT_FRAME); 843 else 844 return RREG32(RADEON_CRTC2_CRNT_FRAME); 845 } 846 847 /** 848 * r100_ring_hdp_flush - flush Host Data Path via the ring buffer 849 * rdev: radeon device structure 850 * ring: ring buffer struct for emitting packets 851 */ 852 static void r100_ring_hdp_flush(struct radeon_device *rdev, struct radeon_ring *ring) 853 { 854 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); 855 radeon_ring_write(ring, rdev->config.r100.hdp_cntl | 856 RADEON_HDP_READ_BUFFER_INVALIDATE); 857 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); 858 radeon_ring_write(ring, rdev->config.r100.hdp_cntl); 859 } 860 861 /* Who ever call radeon_fence_emit should call ring_lock and ask 862 * for enough space (today caller are ib schedule and buffer move) */ 863 void r100_fence_ring_emit(struct radeon_device *rdev, 864 struct radeon_fence *fence) 865 { 866 struct radeon_ring *ring = &rdev->ring[fence->ring]; 867 868 /* We have to make sure that caches are flushed before 869 * CPU might read something from VRAM. */ 870 radeon_ring_write(ring, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); 871 radeon_ring_write(ring, RADEON_RB3D_DC_FLUSH_ALL); 872 radeon_ring_write(ring, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); 873 radeon_ring_write(ring, RADEON_RB3D_ZC_FLUSH_ALL); 874 /* Wait until IDLE & CLEAN */ 875 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); 876 radeon_ring_write(ring, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); 877 r100_ring_hdp_flush(rdev, ring); 878 /* Emit fence sequence & fire IRQ */ 879 radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0)); 880 radeon_ring_write(ring, fence->seq); 881 radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0)); 882 radeon_ring_write(ring, RADEON_SW_INT_FIRE); 883 } 884 885 bool r100_semaphore_ring_emit(struct radeon_device *rdev, 886 struct radeon_ring *ring, 887 struct radeon_semaphore *semaphore, 888 bool emit_wait) 889 { 890 /* Unused on older asics, since we don't have semaphores or multiple rings */ 891 BUG(); 892 return false; 893 } 894 895 struct radeon_fence *r100_copy_blit(struct radeon_device *rdev, 896 uint64_t src_offset, 897 uint64_t dst_offset, 898 unsigned num_gpu_pages, 899 struct dma_resv *resv) 900 { 901 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 902 struct radeon_fence *fence; 903 uint32_t cur_pages; 904 uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE; 905 uint32_t pitch; 906 uint32_t stride_pixels; 907 unsigned ndw; 908 int num_loops; 909 int r = 0; 910 911 /* radeon limited to 16k stride */ 912 stride_bytes &= 0x3fff; 913 /* radeon pitch is /64 */ 914 pitch = stride_bytes / 64; 915 stride_pixels = stride_bytes / 4; 916 num_loops = DIV_ROUND_UP(num_gpu_pages, 8191); 917 918 /* Ask for enough room for blit + flush + fence */ 919 ndw = 64 + (10 * num_loops); 920 r = radeon_ring_lock(rdev, ring, ndw); 921 if (r) { 922 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw); 923 return ERR_PTR(-EINVAL); 924 } 925 while (num_gpu_pages > 0) { 926 cur_pages = num_gpu_pages; 927 if (cur_pages > 8191) { 928 cur_pages = 8191; 929 } 930 num_gpu_pages -= cur_pages; 931 932 /* pages are in Y direction - height 933 page width in X direction - width */ 934 radeon_ring_write(ring, PACKET3(PACKET3_BITBLT_MULTI, 8)); 935 radeon_ring_write(ring, 936 RADEON_GMC_SRC_PITCH_OFFSET_CNTL | 937 RADEON_GMC_DST_PITCH_OFFSET_CNTL | 938 RADEON_GMC_SRC_CLIPPING | 939 RADEON_GMC_DST_CLIPPING | 940 RADEON_GMC_BRUSH_NONE | 941 (RADEON_COLOR_FORMAT_ARGB8888 << 8) | 942 RADEON_GMC_SRC_DATATYPE_COLOR | 943 RADEON_ROP3_S | 944 RADEON_DP_SRC_SOURCE_MEMORY | 945 RADEON_GMC_CLR_CMP_CNTL_DIS | 946 RADEON_GMC_WR_MSK_DIS); 947 radeon_ring_write(ring, (pitch << 22) | (src_offset >> 10)); 948 radeon_ring_write(ring, (pitch << 22) | (dst_offset >> 10)); 949 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16)); 950 radeon_ring_write(ring, 0); 951 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16)); 952 radeon_ring_write(ring, num_gpu_pages); 953 radeon_ring_write(ring, num_gpu_pages); 954 radeon_ring_write(ring, cur_pages | (stride_pixels << 16)); 955 } 956 radeon_ring_write(ring, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0)); 957 radeon_ring_write(ring, RADEON_RB2D_DC_FLUSH_ALL); 958 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); 959 radeon_ring_write(ring, 960 RADEON_WAIT_2D_IDLECLEAN | 961 RADEON_WAIT_HOST_IDLECLEAN | 962 RADEON_WAIT_DMA_GUI_IDLE); 963 r = radeon_fence_emit(rdev, &fence, RADEON_RING_TYPE_GFX_INDEX); 964 if (r) { 965 radeon_ring_unlock_undo(rdev, ring); 966 return ERR_PTR(r); 967 } 968 radeon_ring_unlock_commit(rdev, ring, false); 969 return fence; 970 } 971 972 static int r100_cp_wait_for_idle(struct radeon_device *rdev) 973 { 974 unsigned i; 975 u32 tmp; 976 977 for (i = 0; i < rdev->usec_timeout; i++) { 978 tmp = RREG32(R_000E40_RBBM_STATUS); 979 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) { 980 return 0; 981 } 982 udelay(1); 983 } 984 return -1; 985 } 986 987 void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring) 988 { 989 int r; 990 991 r = radeon_ring_lock(rdev, ring, 2); 992 if (r) { 993 return; 994 } 995 radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0)); 996 radeon_ring_write(ring, 997 RADEON_ISYNC_ANY2D_IDLE3D | 998 RADEON_ISYNC_ANY3D_IDLE2D | 999 RADEON_ISYNC_WAIT_IDLEGUI | 1000 RADEON_ISYNC_CPSCRATCH_IDLEGUI); 1001 radeon_ring_unlock_commit(rdev, ring, false); 1002 } 1003 1004 1005 /* Load the microcode for the CP */ 1006 static int r100_cp_init_microcode(struct radeon_device *rdev) 1007 { 1008 const char *fw_name = NULL; 1009 int err; 1010 1011 DRM_DEBUG_KMS("\n"); 1012 1013 if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) || 1014 (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) || 1015 (rdev->family == CHIP_RS200)) { 1016 DRM_INFO("Loading R100 Microcode\n"); 1017 fw_name = FIRMWARE_R100; 1018 } else if ((rdev->family == CHIP_R200) || 1019 (rdev->family == CHIP_RV250) || 1020 (rdev->family == CHIP_RV280) || 1021 (rdev->family == CHIP_RS300)) { 1022 DRM_INFO("Loading R200 Microcode\n"); 1023 fw_name = FIRMWARE_R200; 1024 } else if ((rdev->family == CHIP_R300) || 1025 (rdev->family == CHIP_R350) || 1026 (rdev->family == CHIP_RV350) || 1027 (rdev->family == CHIP_RV380) || 1028 (rdev->family == CHIP_RS400) || 1029 (rdev->family == CHIP_RS480)) { 1030 DRM_INFO("Loading R300 Microcode\n"); 1031 fw_name = FIRMWARE_R300; 1032 } else if ((rdev->family == CHIP_R420) || 1033 (rdev->family == CHIP_R423) || 1034 (rdev->family == CHIP_RV410)) { 1035 DRM_INFO("Loading R400 Microcode\n"); 1036 fw_name = FIRMWARE_R420; 1037 } else if ((rdev->family == CHIP_RS690) || 1038 (rdev->family == CHIP_RS740)) { 1039 DRM_INFO("Loading RS690/RS740 Microcode\n"); 1040 fw_name = FIRMWARE_RS690; 1041 } else if (rdev->family == CHIP_RS600) { 1042 DRM_INFO("Loading RS600 Microcode\n"); 1043 fw_name = FIRMWARE_RS600; 1044 } else if ((rdev->family == CHIP_RV515) || 1045 (rdev->family == CHIP_R520) || 1046 (rdev->family == CHIP_RV530) || 1047 (rdev->family == CHIP_R580) || 1048 (rdev->family == CHIP_RV560) || 1049 (rdev->family == CHIP_RV570)) { 1050 DRM_INFO("Loading R500 Microcode\n"); 1051 fw_name = FIRMWARE_R520; 1052 } 1053 1054 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev); 1055 if (err) { 1056 pr_err("radeon_cp: Failed to load firmware \"%s\"\n", fw_name); 1057 } else if (rdev->me_fw->size % 8) { 1058 pr_err("radeon_cp: Bogus length %zu in firmware \"%s\"\n", 1059 rdev->me_fw->size, fw_name); 1060 err = -EINVAL; 1061 release_firmware(rdev->me_fw); 1062 rdev->me_fw = NULL; 1063 } 1064 return err; 1065 } 1066 1067 u32 r100_gfx_get_rptr(struct radeon_device *rdev, 1068 struct radeon_ring *ring) 1069 { 1070 u32 rptr; 1071 1072 if (rdev->wb.enabled) 1073 rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]); 1074 else 1075 rptr = RREG32(RADEON_CP_RB_RPTR); 1076 1077 return rptr; 1078 } 1079 1080 u32 r100_gfx_get_wptr(struct radeon_device *rdev, 1081 struct radeon_ring *ring) 1082 { 1083 return RREG32(RADEON_CP_RB_WPTR); 1084 } 1085 1086 void r100_gfx_set_wptr(struct radeon_device *rdev, 1087 struct radeon_ring *ring) 1088 { 1089 WREG32(RADEON_CP_RB_WPTR, ring->wptr); 1090 (void)RREG32(RADEON_CP_RB_WPTR); 1091 } 1092 1093 static void r100_cp_load_microcode(struct radeon_device *rdev) 1094 { 1095 const __be32 *fw_data; 1096 int i, size; 1097 1098 if (r100_gui_wait_for_idle(rdev)) { 1099 pr_warn("Failed to wait GUI idle while programming pipes. Bad things might happen.\n"); 1100 } 1101 1102 if (rdev->me_fw) { 1103 size = rdev->me_fw->size / 4; 1104 fw_data = (const __be32 *)&rdev->me_fw->data[0]; 1105 WREG32(RADEON_CP_ME_RAM_ADDR, 0); 1106 for (i = 0; i < size; i += 2) { 1107 WREG32(RADEON_CP_ME_RAM_DATAH, 1108 be32_to_cpup(&fw_data[i])); 1109 WREG32(RADEON_CP_ME_RAM_DATAL, 1110 be32_to_cpup(&fw_data[i + 1])); 1111 } 1112 } 1113 } 1114 1115 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size) 1116 { 1117 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 1118 unsigned rb_bufsz; 1119 unsigned rb_blksz; 1120 unsigned max_fetch; 1121 unsigned pre_write_timer; 1122 unsigned pre_write_limit; 1123 unsigned indirect2_start; 1124 unsigned indirect1_start; 1125 uint32_t tmp; 1126 int r; 1127 1128 if (r100_debugfs_cp_init(rdev)) { 1129 DRM_ERROR("Failed to register debugfs file for CP !\n"); 1130 } 1131 if (!rdev->me_fw) { 1132 r = r100_cp_init_microcode(rdev); 1133 if (r) { 1134 DRM_ERROR("Failed to load firmware!\n"); 1135 return r; 1136 } 1137 } 1138 1139 /* Align ring size */ 1140 rb_bufsz = order_base_2(ring_size / 8); 1141 ring_size = (1 << (rb_bufsz + 1)) * 4; 1142 r100_cp_load_microcode(rdev); 1143 r = radeon_ring_init(rdev, ring, ring_size, RADEON_WB_CP_RPTR_OFFSET, 1144 RADEON_CP_PACKET2); 1145 if (r) { 1146 return r; 1147 } 1148 /* Each time the cp read 1024 bytes (16 dword/quadword) update 1149 * the rptr copy in system ram */ 1150 rb_blksz = 9; 1151 /* cp will read 128bytes at a time (4 dwords) */ 1152 max_fetch = 1; 1153 ring->align_mask = 16 - 1; 1154 /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */ 1155 pre_write_timer = 64; 1156 /* Force CP_RB_WPTR write if written more than one time before the 1157 * delay expire 1158 */ 1159 pre_write_limit = 0; 1160 /* Setup the cp cache like this (cache size is 96 dwords) : 1161 * RING 0 to 15 1162 * INDIRECT1 16 to 79 1163 * INDIRECT2 80 to 95 1164 * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords)) 1165 * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords)) 1166 * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords)) 1167 * Idea being that most of the gpu cmd will be through indirect1 buffer 1168 * so it gets the bigger cache. 1169 */ 1170 indirect2_start = 80; 1171 indirect1_start = 16; 1172 /* cp setup */ 1173 WREG32(0x718, pre_write_timer | (pre_write_limit << 28)); 1174 tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) | 1175 REG_SET(RADEON_RB_BLKSZ, rb_blksz) | 1176 REG_SET(RADEON_MAX_FETCH, max_fetch)); 1177 #ifdef __BIG_ENDIAN 1178 tmp |= RADEON_BUF_SWAP_32BIT; 1179 #endif 1180 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE); 1181 1182 /* Set ring address */ 1183 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)ring->gpu_addr); 1184 WREG32(RADEON_CP_RB_BASE, ring->gpu_addr); 1185 /* Force read & write ptr to 0 */ 1186 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE); 1187 WREG32(RADEON_CP_RB_RPTR_WR, 0); 1188 ring->wptr = 0; 1189 WREG32(RADEON_CP_RB_WPTR, ring->wptr); 1190 1191 /* set the wb address whether it's enabled or not */ 1192 WREG32(R_00070C_CP_RB_RPTR_ADDR, 1193 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2)); 1194 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET); 1195 1196 if (rdev->wb.enabled) 1197 WREG32(R_000770_SCRATCH_UMSK, 0xff); 1198 else { 1199 tmp |= RADEON_RB_NO_UPDATE; 1200 WREG32(R_000770_SCRATCH_UMSK, 0); 1201 } 1202 1203 WREG32(RADEON_CP_RB_CNTL, tmp); 1204 udelay(10); 1205 /* Set cp mode to bus mastering & enable cp*/ 1206 WREG32(RADEON_CP_CSQ_MODE, 1207 REG_SET(RADEON_INDIRECT2_START, indirect2_start) | 1208 REG_SET(RADEON_INDIRECT1_START, indirect1_start)); 1209 WREG32(RADEON_CP_RB_WPTR_DELAY, 0); 1210 WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D); 1211 WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM); 1212 1213 /* at this point everything should be setup correctly to enable master */ 1214 pci_set_master(rdev->pdev); 1215 1216 radeon_ring_start(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); 1217 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring); 1218 if (r) { 1219 DRM_ERROR("radeon: cp isn't working (%d).\n", r); 1220 return r; 1221 } 1222 ring->ready = true; 1223 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); 1224 1225 if (!ring->rptr_save_reg /* not resuming from suspend */ 1226 && radeon_ring_supports_scratch_reg(rdev, ring)) { 1227 r = radeon_scratch_get(rdev, &ring->rptr_save_reg); 1228 if (r) { 1229 DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r); 1230 ring->rptr_save_reg = 0; 1231 } 1232 } 1233 return 0; 1234 } 1235 1236 void r100_cp_fini(struct radeon_device *rdev) 1237 { 1238 if (r100_cp_wait_for_idle(rdev)) { 1239 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n"); 1240 } 1241 /* Disable ring */ 1242 r100_cp_disable(rdev); 1243 radeon_scratch_free(rdev, rdev->ring[RADEON_RING_TYPE_GFX_INDEX].rptr_save_reg); 1244 radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); 1245 DRM_INFO("radeon: cp finalized\n"); 1246 } 1247 1248 void r100_cp_disable(struct radeon_device *rdev) 1249 { 1250 /* Disable ring */ 1251 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 1252 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; 1253 WREG32(RADEON_CP_CSQ_MODE, 0); 1254 WREG32(RADEON_CP_CSQ_CNTL, 0); 1255 WREG32(R_000770_SCRATCH_UMSK, 0); 1256 if (r100_gui_wait_for_idle(rdev)) { 1257 pr_warn("Failed to wait GUI idle while programming pipes. Bad things might happen.\n"); 1258 } 1259 } 1260 1261 /* 1262 * CS functions 1263 */ 1264 int r100_reloc_pitch_offset(struct radeon_cs_parser *p, 1265 struct radeon_cs_packet *pkt, 1266 unsigned idx, 1267 unsigned reg) 1268 { 1269 int r; 1270 u32 tile_flags = 0; 1271 u32 tmp; 1272 struct radeon_bo_list *reloc; 1273 u32 value; 1274 1275 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1276 if (r) { 1277 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1278 idx, reg); 1279 radeon_cs_dump_packet(p, pkt); 1280 return r; 1281 } 1282 1283 value = radeon_get_ib_value(p, idx); 1284 tmp = value & 0x003fffff; 1285 tmp += (((u32)reloc->gpu_offset) >> 10); 1286 1287 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 1288 if (reloc->tiling_flags & RADEON_TILING_MACRO) 1289 tile_flags |= RADEON_DST_TILE_MACRO; 1290 if (reloc->tiling_flags & RADEON_TILING_MICRO) { 1291 if (reg == RADEON_SRC_PITCH_OFFSET) { 1292 DRM_ERROR("Cannot src blit from microtiled surface\n"); 1293 radeon_cs_dump_packet(p, pkt); 1294 return -EINVAL; 1295 } 1296 tile_flags |= RADEON_DST_TILE_MICRO; 1297 } 1298 1299 tmp |= tile_flags; 1300 p->ib.ptr[idx] = (value & 0x3fc00000) | tmp; 1301 } else 1302 p->ib.ptr[idx] = (value & 0xffc00000) | tmp; 1303 return 0; 1304 } 1305 1306 int r100_packet3_load_vbpntr(struct radeon_cs_parser *p, 1307 struct radeon_cs_packet *pkt, 1308 int idx) 1309 { 1310 unsigned c, i; 1311 struct radeon_bo_list *reloc; 1312 struct r100_cs_track *track; 1313 int r = 0; 1314 volatile uint32_t *ib; 1315 u32 idx_value; 1316 1317 ib = p->ib.ptr; 1318 track = (struct r100_cs_track *)p->track; 1319 c = radeon_get_ib_value(p, idx++) & 0x1F; 1320 if (c > 16) { 1321 DRM_ERROR("Only 16 vertex buffers are allowed %d\n", 1322 pkt->opcode); 1323 radeon_cs_dump_packet(p, pkt); 1324 return -EINVAL; 1325 } 1326 track->num_arrays = c; 1327 for (i = 0; i < (c - 1); i+=2, idx+=3) { 1328 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1329 if (r) { 1330 DRM_ERROR("No reloc for packet3 %d\n", 1331 pkt->opcode); 1332 radeon_cs_dump_packet(p, pkt); 1333 return r; 1334 } 1335 idx_value = radeon_get_ib_value(p, idx); 1336 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset); 1337 1338 track->arrays[i + 0].esize = idx_value >> 8; 1339 track->arrays[i + 0].robj = reloc->robj; 1340 track->arrays[i + 0].esize &= 0x7F; 1341 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1342 if (r) { 1343 DRM_ERROR("No reloc for packet3 %d\n", 1344 pkt->opcode); 1345 radeon_cs_dump_packet(p, pkt); 1346 return r; 1347 } 1348 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->gpu_offset); 1349 track->arrays[i + 1].robj = reloc->robj; 1350 track->arrays[i + 1].esize = idx_value >> 24; 1351 track->arrays[i + 1].esize &= 0x7F; 1352 } 1353 if (c & 1) { 1354 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1355 if (r) { 1356 DRM_ERROR("No reloc for packet3 %d\n", 1357 pkt->opcode); 1358 radeon_cs_dump_packet(p, pkt); 1359 return r; 1360 } 1361 idx_value = radeon_get_ib_value(p, idx); 1362 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset); 1363 track->arrays[i + 0].robj = reloc->robj; 1364 track->arrays[i + 0].esize = idx_value >> 8; 1365 track->arrays[i + 0].esize &= 0x7F; 1366 } 1367 return r; 1368 } 1369 1370 int r100_cs_parse_packet0(struct radeon_cs_parser *p, 1371 struct radeon_cs_packet *pkt, 1372 const unsigned *auth, unsigned n, 1373 radeon_packet0_check_t check) 1374 { 1375 unsigned reg; 1376 unsigned i, j, m; 1377 unsigned idx; 1378 int r; 1379 1380 idx = pkt->idx + 1; 1381 reg = pkt->reg; 1382 /* Check that register fall into register range 1383 * determined by the number of entry (n) in the 1384 * safe register bitmap. 1385 */ 1386 if (pkt->one_reg_wr) { 1387 if ((reg >> 7) > n) { 1388 return -EINVAL; 1389 } 1390 } else { 1391 if (((reg + (pkt->count << 2)) >> 7) > n) { 1392 return -EINVAL; 1393 } 1394 } 1395 for (i = 0; i <= pkt->count; i++, idx++) { 1396 j = (reg >> 7); 1397 m = 1 << ((reg >> 2) & 31); 1398 if (auth[j] & m) { 1399 r = check(p, pkt, idx, reg); 1400 if (r) { 1401 return r; 1402 } 1403 } 1404 if (pkt->one_reg_wr) { 1405 if (!(auth[j] & m)) { 1406 break; 1407 } 1408 } else { 1409 reg += 4; 1410 } 1411 } 1412 return 0; 1413 } 1414 1415 /** 1416 * r100_cs_packet_next_vline() - parse userspace VLINE packet 1417 * @parser: parser structure holding parsing context. 1418 * 1419 * Userspace sends a special sequence for VLINE waits. 1420 * PACKET0 - VLINE_START_END + value 1421 * PACKET0 - WAIT_UNTIL +_value 1422 * RELOC (P3) - crtc_id in reloc. 1423 * 1424 * This function parses this and relocates the VLINE START END 1425 * and WAIT UNTIL packets to the correct crtc. 1426 * It also detects a switched off crtc and nulls out the 1427 * wait in that case. 1428 */ 1429 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p) 1430 { 1431 struct drm_crtc *crtc; 1432 struct radeon_crtc *radeon_crtc; 1433 struct radeon_cs_packet p3reloc, waitreloc; 1434 int crtc_id; 1435 int r; 1436 uint32_t header, h_idx, reg; 1437 volatile uint32_t *ib; 1438 1439 ib = p->ib.ptr; 1440 1441 /* parse the wait until */ 1442 r = radeon_cs_packet_parse(p, &waitreloc, p->idx); 1443 if (r) 1444 return r; 1445 1446 /* check its a wait until and only 1 count */ 1447 if (waitreloc.reg != RADEON_WAIT_UNTIL || 1448 waitreloc.count != 0) { 1449 DRM_ERROR("vline wait had illegal wait until segment\n"); 1450 return -EINVAL; 1451 } 1452 1453 if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) { 1454 DRM_ERROR("vline wait had illegal wait until\n"); 1455 return -EINVAL; 1456 } 1457 1458 /* jump over the NOP */ 1459 r = radeon_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2); 1460 if (r) 1461 return r; 1462 1463 h_idx = p->idx - 2; 1464 p->idx += waitreloc.count + 2; 1465 p->idx += p3reloc.count + 2; 1466 1467 header = radeon_get_ib_value(p, h_idx); 1468 crtc_id = radeon_get_ib_value(p, h_idx + 5); 1469 reg = R100_CP_PACKET0_GET_REG(header); 1470 crtc = drm_crtc_find(p->rdev->ddev, p->filp, crtc_id); 1471 if (!crtc) { 1472 DRM_ERROR("cannot find crtc %d\n", crtc_id); 1473 return -ENOENT; 1474 } 1475 radeon_crtc = to_radeon_crtc(crtc); 1476 crtc_id = radeon_crtc->crtc_id; 1477 1478 if (!crtc->enabled) { 1479 /* if the CRTC isn't enabled - we need to nop out the wait until */ 1480 ib[h_idx + 2] = PACKET2(0); 1481 ib[h_idx + 3] = PACKET2(0); 1482 } else if (crtc_id == 1) { 1483 switch (reg) { 1484 case AVIVO_D1MODE_VLINE_START_END: 1485 header &= ~R300_CP_PACKET0_REG_MASK; 1486 header |= AVIVO_D2MODE_VLINE_START_END >> 2; 1487 break; 1488 case RADEON_CRTC_GUI_TRIG_VLINE: 1489 header &= ~R300_CP_PACKET0_REG_MASK; 1490 header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2; 1491 break; 1492 default: 1493 DRM_ERROR("unknown crtc reloc\n"); 1494 return -EINVAL; 1495 } 1496 ib[h_idx] = header; 1497 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1; 1498 } 1499 1500 return 0; 1501 } 1502 1503 static int r100_get_vtx_size(uint32_t vtx_fmt) 1504 { 1505 int vtx_size; 1506 vtx_size = 2; 1507 /* ordered according to bits in spec */ 1508 if (vtx_fmt & RADEON_SE_VTX_FMT_W0) 1509 vtx_size++; 1510 if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR) 1511 vtx_size += 3; 1512 if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA) 1513 vtx_size++; 1514 if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR) 1515 vtx_size++; 1516 if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC) 1517 vtx_size += 3; 1518 if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG) 1519 vtx_size++; 1520 if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC) 1521 vtx_size++; 1522 if (vtx_fmt & RADEON_SE_VTX_FMT_ST0) 1523 vtx_size += 2; 1524 if (vtx_fmt & RADEON_SE_VTX_FMT_ST1) 1525 vtx_size += 2; 1526 if (vtx_fmt & RADEON_SE_VTX_FMT_Q1) 1527 vtx_size++; 1528 if (vtx_fmt & RADEON_SE_VTX_FMT_ST2) 1529 vtx_size += 2; 1530 if (vtx_fmt & RADEON_SE_VTX_FMT_Q2) 1531 vtx_size++; 1532 if (vtx_fmt & RADEON_SE_VTX_FMT_ST3) 1533 vtx_size += 2; 1534 if (vtx_fmt & RADEON_SE_VTX_FMT_Q3) 1535 vtx_size++; 1536 if (vtx_fmt & RADEON_SE_VTX_FMT_Q0) 1537 vtx_size++; 1538 /* blend weight */ 1539 if (vtx_fmt & (0x7 << 15)) 1540 vtx_size += (vtx_fmt >> 15) & 0x7; 1541 if (vtx_fmt & RADEON_SE_VTX_FMT_N0) 1542 vtx_size += 3; 1543 if (vtx_fmt & RADEON_SE_VTX_FMT_XY1) 1544 vtx_size += 2; 1545 if (vtx_fmt & RADEON_SE_VTX_FMT_Z1) 1546 vtx_size++; 1547 if (vtx_fmt & RADEON_SE_VTX_FMT_W1) 1548 vtx_size++; 1549 if (vtx_fmt & RADEON_SE_VTX_FMT_N1) 1550 vtx_size++; 1551 if (vtx_fmt & RADEON_SE_VTX_FMT_Z) 1552 vtx_size++; 1553 return vtx_size; 1554 } 1555 1556 static int r100_packet0_check(struct radeon_cs_parser *p, 1557 struct radeon_cs_packet *pkt, 1558 unsigned idx, unsigned reg) 1559 { 1560 struct radeon_bo_list *reloc; 1561 struct r100_cs_track *track; 1562 volatile uint32_t *ib; 1563 uint32_t tmp; 1564 int r; 1565 int i, face; 1566 u32 tile_flags = 0; 1567 u32 idx_value; 1568 1569 ib = p->ib.ptr; 1570 track = (struct r100_cs_track *)p->track; 1571 1572 idx_value = radeon_get_ib_value(p, idx); 1573 1574 switch (reg) { 1575 case RADEON_CRTC_GUI_TRIG_VLINE: 1576 r = r100_cs_packet_parse_vline(p); 1577 if (r) { 1578 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1579 idx, reg); 1580 radeon_cs_dump_packet(p, pkt); 1581 return r; 1582 } 1583 break; 1584 /* FIXME: only allow PACKET3 blit? easier to check for out of 1585 * range access */ 1586 case RADEON_DST_PITCH_OFFSET: 1587 case RADEON_SRC_PITCH_OFFSET: 1588 r = r100_reloc_pitch_offset(p, pkt, idx, reg); 1589 if (r) 1590 return r; 1591 break; 1592 case RADEON_RB3D_DEPTHOFFSET: 1593 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1594 if (r) { 1595 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1596 idx, reg); 1597 radeon_cs_dump_packet(p, pkt); 1598 return r; 1599 } 1600 track->zb.robj = reloc->robj; 1601 track->zb.offset = idx_value; 1602 track->zb_dirty = true; 1603 ib[idx] = idx_value + ((u32)reloc->gpu_offset); 1604 break; 1605 case RADEON_RB3D_COLOROFFSET: 1606 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1607 if (r) { 1608 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1609 idx, reg); 1610 radeon_cs_dump_packet(p, pkt); 1611 return r; 1612 } 1613 track->cb[0].robj = reloc->robj; 1614 track->cb[0].offset = idx_value; 1615 track->cb_dirty = true; 1616 ib[idx] = idx_value + ((u32)reloc->gpu_offset); 1617 break; 1618 case RADEON_PP_TXOFFSET_0: 1619 case RADEON_PP_TXOFFSET_1: 1620 case RADEON_PP_TXOFFSET_2: 1621 i = (reg - RADEON_PP_TXOFFSET_0) / 24; 1622 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1623 if (r) { 1624 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1625 idx, reg); 1626 radeon_cs_dump_packet(p, pkt); 1627 return r; 1628 } 1629 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 1630 if (reloc->tiling_flags & RADEON_TILING_MACRO) 1631 tile_flags |= RADEON_TXO_MACRO_TILE; 1632 if (reloc->tiling_flags & RADEON_TILING_MICRO) 1633 tile_flags |= RADEON_TXO_MICRO_TILE_X2; 1634 1635 tmp = idx_value & ~(0x7 << 2); 1636 tmp |= tile_flags; 1637 ib[idx] = tmp + ((u32)reloc->gpu_offset); 1638 } else 1639 ib[idx] = idx_value + ((u32)reloc->gpu_offset); 1640 track->textures[i].robj = reloc->robj; 1641 track->tex_dirty = true; 1642 break; 1643 case RADEON_PP_CUBIC_OFFSET_T0_0: 1644 case RADEON_PP_CUBIC_OFFSET_T0_1: 1645 case RADEON_PP_CUBIC_OFFSET_T0_2: 1646 case RADEON_PP_CUBIC_OFFSET_T0_3: 1647 case RADEON_PP_CUBIC_OFFSET_T0_4: 1648 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4; 1649 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1650 if (r) { 1651 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1652 idx, reg); 1653 radeon_cs_dump_packet(p, pkt); 1654 return r; 1655 } 1656 track->textures[0].cube_info[i].offset = idx_value; 1657 ib[idx] = idx_value + ((u32)reloc->gpu_offset); 1658 track->textures[0].cube_info[i].robj = reloc->robj; 1659 track->tex_dirty = true; 1660 break; 1661 case RADEON_PP_CUBIC_OFFSET_T1_0: 1662 case RADEON_PP_CUBIC_OFFSET_T1_1: 1663 case RADEON_PP_CUBIC_OFFSET_T1_2: 1664 case RADEON_PP_CUBIC_OFFSET_T1_3: 1665 case RADEON_PP_CUBIC_OFFSET_T1_4: 1666 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4; 1667 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1668 if (r) { 1669 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1670 idx, reg); 1671 radeon_cs_dump_packet(p, pkt); 1672 return r; 1673 } 1674 track->textures[1].cube_info[i].offset = idx_value; 1675 ib[idx] = idx_value + ((u32)reloc->gpu_offset); 1676 track->textures[1].cube_info[i].robj = reloc->robj; 1677 track->tex_dirty = true; 1678 break; 1679 case RADEON_PP_CUBIC_OFFSET_T2_0: 1680 case RADEON_PP_CUBIC_OFFSET_T2_1: 1681 case RADEON_PP_CUBIC_OFFSET_T2_2: 1682 case RADEON_PP_CUBIC_OFFSET_T2_3: 1683 case RADEON_PP_CUBIC_OFFSET_T2_4: 1684 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4; 1685 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1686 if (r) { 1687 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1688 idx, reg); 1689 radeon_cs_dump_packet(p, pkt); 1690 return r; 1691 } 1692 track->textures[2].cube_info[i].offset = idx_value; 1693 ib[idx] = idx_value + ((u32)reloc->gpu_offset); 1694 track->textures[2].cube_info[i].robj = reloc->robj; 1695 track->tex_dirty = true; 1696 break; 1697 case RADEON_RE_WIDTH_HEIGHT: 1698 track->maxy = ((idx_value >> 16) & 0x7FF); 1699 track->cb_dirty = true; 1700 track->zb_dirty = true; 1701 break; 1702 case RADEON_RB3D_COLORPITCH: 1703 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1704 if (r) { 1705 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1706 idx, reg); 1707 radeon_cs_dump_packet(p, pkt); 1708 return r; 1709 } 1710 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 1711 if (reloc->tiling_flags & RADEON_TILING_MACRO) 1712 tile_flags |= RADEON_COLOR_TILE_ENABLE; 1713 if (reloc->tiling_flags & RADEON_TILING_MICRO) 1714 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE; 1715 1716 tmp = idx_value & ~(0x7 << 16); 1717 tmp |= tile_flags; 1718 ib[idx] = tmp; 1719 } else 1720 ib[idx] = idx_value; 1721 1722 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK; 1723 track->cb_dirty = true; 1724 break; 1725 case RADEON_RB3D_DEPTHPITCH: 1726 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK; 1727 track->zb_dirty = true; 1728 break; 1729 case RADEON_RB3D_CNTL: 1730 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) { 1731 case 7: 1732 case 8: 1733 case 9: 1734 case 11: 1735 case 12: 1736 track->cb[0].cpp = 1; 1737 break; 1738 case 3: 1739 case 4: 1740 case 15: 1741 track->cb[0].cpp = 2; 1742 break; 1743 case 6: 1744 track->cb[0].cpp = 4; 1745 break; 1746 default: 1747 DRM_ERROR("Invalid color buffer format (%d) !\n", 1748 ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f)); 1749 return -EINVAL; 1750 } 1751 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE); 1752 track->cb_dirty = true; 1753 track->zb_dirty = true; 1754 break; 1755 case RADEON_RB3D_ZSTENCILCNTL: 1756 switch (idx_value & 0xf) { 1757 case 0: 1758 track->zb.cpp = 2; 1759 break; 1760 case 2: 1761 case 3: 1762 case 4: 1763 case 5: 1764 case 9: 1765 case 11: 1766 track->zb.cpp = 4; 1767 break; 1768 default: 1769 break; 1770 } 1771 track->zb_dirty = true; 1772 break; 1773 case RADEON_RB3D_ZPASS_ADDR: 1774 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1775 if (r) { 1776 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1777 idx, reg); 1778 radeon_cs_dump_packet(p, pkt); 1779 return r; 1780 } 1781 ib[idx] = idx_value + ((u32)reloc->gpu_offset); 1782 break; 1783 case RADEON_PP_CNTL: 1784 { 1785 uint32_t temp = idx_value >> 4; 1786 for (i = 0; i < track->num_texture; i++) 1787 track->textures[i].enabled = !!(temp & (1 << i)); 1788 track->tex_dirty = true; 1789 } 1790 break; 1791 case RADEON_SE_VF_CNTL: 1792 track->vap_vf_cntl = idx_value; 1793 break; 1794 case RADEON_SE_VTX_FMT: 1795 track->vtx_size = r100_get_vtx_size(idx_value); 1796 break; 1797 case RADEON_PP_TEX_SIZE_0: 1798 case RADEON_PP_TEX_SIZE_1: 1799 case RADEON_PP_TEX_SIZE_2: 1800 i = (reg - RADEON_PP_TEX_SIZE_0) / 8; 1801 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1; 1802 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1; 1803 track->tex_dirty = true; 1804 break; 1805 case RADEON_PP_TEX_PITCH_0: 1806 case RADEON_PP_TEX_PITCH_1: 1807 case RADEON_PP_TEX_PITCH_2: 1808 i = (reg - RADEON_PP_TEX_PITCH_0) / 8; 1809 track->textures[i].pitch = idx_value + 32; 1810 track->tex_dirty = true; 1811 break; 1812 case RADEON_PP_TXFILTER_0: 1813 case RADEON_PP_TXFILTER_1: 1814 case RADEON_PP_TXFILTER_2: 1815 i = (reg - RADEON_PP_TXFILTER_0) / 24; 1816 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK) 1817 >> RADEON_MAX_MIP_LEVEL_SHIFT); 1818 tmp = (idx_value >> 23) & 0x7; 1819 if (tmp == 2 || tmp == 6) 1820 track->textures[i].roundup_w = false; 1821 tmp = (idx_value >> 27) & 0x7; 1822 if (tmp == 2 || tmp == 6) 1823 track->textures[i].roundup_h = false; 1824 track->tex_dirty = true; 1825 break; 1826 case RADEON_PP_TXFORMAT_0: 1827 case RADEON_PP_TXFORMAT_1: 1828 case RADEON_PP_TXFORMAT_2: 1829 i = (reg - RADEON_PP_TXFORMAT_0) / 24; 1830 if (idx_value & RADEON_TXFORMAT_NON_POWER2) { 1831 track->textures[i].use_pitch = true; 1832 } else { 1833 track->textures[i].use_pitch = false; 1834 track->textures[i].width = 1 << ((idx_value & RADEON_TXFORMAT_WIDTH_MASK) >> RADEON_TXFORMAT_WIDTH_SHIFT); 1835 track->textures[i].height = 1 << ((idx_value & RADEON_TXFORMAT_HEIGHT_MASK) >> RADEON_TXFORMAT_HEIGHT_SHIFT); 1836 } 1837 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE) 1838 track->textures[i].tex_coord_type = 2; 1839 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) { 1840 case RADEON_TXFORMAT_I8: 1841 case RADEON_TXFORMAT_RGB332: 1842 case RADEON_TXFORMAT_Y8: 1843 track->textures[i].cpp = 1; 1844 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 1845 break; 1846 case RADEON_TXFORMAT_AI88: 1847 case RADEON_TXFORMAT_ARGB1555: 1848 case RADEON_TXFORMAT_RGB565: 1849 case RADEON_TXFORMAT_ARGB4444: 1850 case RADEON_TXFORMAT_VYUY422: 1851 case RADEON_TXFORMAT_YVYU422: 1852 case RADEON_TXFORMAT_SHADOW16: 1853 case RADEON_TXFORMAT_LDUDV655: 1854 case RADEON_TXFORMAT_DUDV88: 1855 track->textures[i].cpp = 2; 1856 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 1857 break; 1858 case RADEON_TXFORMAT_ARGB8888: 1859 case RADEON_TXFORMAT_RGBA8888: 1860 case RADEON_TXFORMAT_SHADOW32: 1861 case RADEON_TXFORMAT_LDUDUV8888: 1862 track->textures[i].cpp = 4; 1863 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 1864 break; 1865 case RADEON_TXFORMAT_DXT1: 1866 track->textures[i].cpp = 1; 1867 track->textures[i].compress_format = R100_TRACK_COMP_DXT1; 1868 break; 1869 case RADEON_TXFORMAT_DXT23: 1870 case RADEON_TXFORMAT_DXT45: 1871 track->textures[i].cpp = 1; 1872 track->textures[i].compress_format = R100_TRACK_COMP_DXT35; 1873 break; 1874 } 1875 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf); 1876 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf); 1877 track->tex_dirty = true; 1878 break; 1879 case RADEON_PP_CUBIC_FACES_0: 1880 case RADEON_PP_CUBIC_FACES_1: 1881 case RADEON_PP_CUBIC_FACES_2: 1882 tmp = idx_value; 1883 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4; 1884 for (face = 0; face < 4; face++) { 1885 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf); 1886 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf); 1887 } 1888 track->tex_dirty = true; 1889 break; 1890 default: 1891 pr_err("Forbidden register 0x%04X in cs at %d\n", reg, idx); 1892 return -EINVAL; 1893 } 1894 return 0; 1895 } 1896 1897 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, 1898 struct radeon_cs_packet *pkt, 1899 struct radeon_bo *robj) 1900 { 1901 unsigned idx; 1902 u32 value; 1903 idx = pkt->idx + 1; 1904 value = radeon_get_ib_value(p, idx + 2); 1905 if ((value + 1) > radeon_bo_size(robj)) { 1906 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER " 1907 "(need %u have %lu) !\n", 1908 value + 1, 1909 radeon_bo_size(robj)); 1910 return -EINVAL; 1911 } 1912 return 0; 1913 } 1914 1915 static int r100_packet3_check(struct radeon_cs_parser *p, 1916 struct radeon_cs_packet *pkt) 1917 { 1918 struct radeon_bo_list *reloc; 1919 struct r100_cs_track *track; 1920 unsigned idx; 1921 volatile uint32_t *ib; 1922 int r; 1923 1924 ib = p->ib.ptr; 1925 idx = pkt->idx + 1; 1926 track = (struct r100_cs_track *)p->track; 1927 switch (pkt->opcode) { 1928 case PACKET3_3D_LOAD_VBPNTR: 1929 r = r100_packet3_load_vbpntr(p, pkt, idx); 1930 if (r) 1931 return r; 1932 break; 1933 case PACKET3_INDX_BUFFER: 1934 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1935 if (r) { 1936 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); 1937 radeon_cs_dump_packet(p, pkt); 1938 return r; 1939 } 1940 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->gpu_offset); 1941 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj); 1942 if (r) { 1943 return r; 1944 } 1945 break; 1946 case 0x23: 1947 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */ 1948 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1949 if (r) { 1950 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); 1951 radeon_cs_dump_packet(p, pkt); 1952 return r; 1953 } 1954 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->gpu_offset); 1955 track->num_arrays = 1; 1956 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2)); 1957 1958 track->arrays[0].robj = reloc->robj; 1959 track->arrays[0].esize = track->vtx_size; 1960 1961 track->max_indx = radeon_get_ib_value(p, idx+1); 1962 1963 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3); 1964 track->immd_dwords = pkt->count - 1; 1965 r = r100_cs_track_check(p->rdev, track); 1966 if (r) 1967 return r; 1968 break; 1969 case PACKET3_3D_DRAW_IMMD: 1970 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) { 1971 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); 1972 return -EINVAL; 1973 } 1974 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0)); 1975 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 1976 track->immd_dwords = pkt->count - 1; 1977 r = r100_cs_track_check(p->rdev, track); 1978 if (r) 1979 return r; 1980 break; 1981 /* triggers drawing using in-packet vertex data */ 1982 case PACKET3_3D_DRAW_IMMD_2: 1983 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) { 1984 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); 1985 return -EINVAL; 1986 } 1987 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 1988 track->immd_dwords = pkt->count; 1989 r = r100_cs_track_check(p->rdev, track); 1990 if (r) 1991 return r; 1992 break; 1993 /* triggers drawing using in-packet vertex data */ 1994 case PACKET3_3D_DRAW_VBUF_2: 1995 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 1996 r = r100_cs_track_check(p->rdev, track); 1997 if (r) 1998 return r; 1999 break; 2000 /* triggers drawing of vertex buffers setup elsewhere */ 2001 case PACKET3_3D_DRAW_INDX_2: 2002 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 2003 r = r100_cs_track_check(p->rdev, track); 2004 if (r) 2005 return r; 2006 break; 2007 /* triggers drawing using indices to vertex buffer */ 2008 case PACKET3_3D_DRAW_VBUF: 2009 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 2010 r = r100_cs_track_check(p->rdev, track); 2011 if (r) 2012 return r; 2013 break; 2014 /* triggers drawing of vertex buffers setup elsewhere */ 2015 case PACKET3_3D_DRAW_INDX: 2016 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 2017 r = r100_cs_track_check(p->rdev, track); 2018 if (r) 2019 return r; 2020 break; 2021 /* triggers drawing using indices to vertex buffer */ 2022 case PACKET3_3D_CLEAR_HIZ: 2023 case PACKET3_3D_CLEAR_ZMASK: 2024 if (p->rdev->hyperz_filp != p->filp) 2025 return -EINVAL; 2026 break; 2027 case PACKET3_NOP: 2028 break; 2029 default: 2030 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode); 2031 return -EINVAL; 2032 } 2033 return 0; 2034 } 2035 2036 int r100_cs_parse(struct radeon_cs_parser *p) 2037 { 2038 struct radeon_cs_packet pkt; 2039 struct r100_cs_track *track; 2040 int r; 2041 2042 track = kzalloc(sizeof(*track), GFP_KERNEL); 2043 if (!track) 2044 return -ENOMEM; 2045 r100_cs_track_clear(p->rdev, track); 2046 p->track = track; 2047 do { 2048 r = radeon_cs_packet_parse(p, &pkt, p->idx); 2049 if (r) { 2050 return r; 2051 } 2052 p->idx += pkt.count + 2; 2053 switch (pkt.type) { 2054 case RADEON_PACKET_TYPE0: 2055 if (p->rdev->family >= CHIP_R200) 2056 r = r100_cs_parse_packet0(p, &pkt, 2057 p->rdev->config.r100.reg_safe_bm, 2058 p->rdev->config.r100.reg_safe_bm_size, 2059 &r200_packet0_check); 2060 else 2061 r = r100_cs_parse_packet0(p, &pkt, 2062 p->rdev->config.r100.reg_safe_bm, 2063 p->rdev->config.r100.reg_safe_bm_size, 2064 &r100_packet0_check); 2065 break; 2066 case RADEON_PACKET_TYPE2: 2067 break; 2068 case RADEON_PACKET_TYPE3: 2069 r = r100_packet3_check(p, &pkt); 2070 break; 2071 default: 2072 DRM_ERROR("Unknown packet type %d !\n", 2073 pkt.type); 2074 return -EINVAL; 2075 } 2076 if (r) 2077 return r; 2078 } while (p->idx < p->chunk_ib->length_dw); 2079 return 0; 2080 } 2081 2082 static void r100_cs_track_texture_print(struct r100_cs_track_texture *t) 2083 { 2084 DRM_ERROR("pitch %d\n", t->pitch); 2085 DRM_ERROR("use_pitch %d\n", t->use_pitch); 2086 DRM_ERROR("width %d\n", t->width); 2087 DRM_ERROR("width_11 %d\n", t->width_11); 2088 DRM_ERROR("height %d\n", t->height); 2089 DRM_ERROR("height_11 %d\n", t->height_11); 2090 DRM_ERROR("num levels %d\n", t->num_levels); 2091 DRM_ERROR("depth %d\n", t->txdepth); 2092 DRM_ERROR("bpp %d\n", t->cpp); 2093 DRM_ERROR("coordinate type %d\n", t->tex_coord_type); 2094 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w); 2095 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h); 2096 DRM_ERROR("compress format %d\n", t->compress_format); 2097 } 2098 2099 static int r100_track_compress_size(int compress_format, int w, int h) 2100 { 2101 int block_width, block_height, block_bytes; 2102 int wblocks, hblocks; 2103 int min_wblocks; 2104 int sz; 2105 2106 block_width = 4; 2107 block_height = 4; 2108 2109 switch (compress_format) { 2110 case R100_TRACK_COMP_DXT1: 2111 block_bytes = 8; 2112 min_wblocks = 4; 2113 break; 2114 default: 2115 case R100_TRACK_COMP_DXT35: 2116 block_bytes = 16; 2117 min_wblocks = 2; 2118 break; 2119 } 2120 2121 hblocks = (h + block_height - 1) / block_height; 2122 wblocks = (w + block_width - 1) / block_width; 2123 if (wblocks < min_wblocks) 2124 wblocks = min_wblocks; 2125 sz = wblocks * hblocks * block_bytes; 2126 return sz; 2127 } 2128 2129 static int r100_cs_track_cube(struct radeon_device *rdev, 2130 struct r100_cs_track *track, unsigned idx) 2131 { 2132 unsigned face, w, h; 2133 struct radeon_bo *cube_robj; 2134 unsigned long size; 2135 unsigned compress_format = track->textures[idx].compress_format; 2136 2137 for (face = 0; face < 5; face++) { 2138 cube_robj = track->textures[idx].cube_info[face].robj; 2139 w = track->textures[idx].cube_info[face].width; 2140 h = track->textures[idx].cube_info[face].height; 2141 2142 if (compress_format) { 2143 size = r100_track_compress_size(compress_format, w, h); 2144 } else 2145 size = w * h; 2146 size *= track->textures[idx].cpp; 2147 2148 size += track->textures[idx].cube_info[face].offset; 2149 2150 if (size > radeon_bo_size(cube_robj)) { 2151 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n", 2152 size, radeon_bo_size(cube_robj)); 2153 r100_cs_track_texture_print(&track->textures[idx]); 2154 return -1; 2155 } 2156 } 2157 return 0; 2158 } 2159 2160 static int r100_cs_track_texture_check(struct radeon_device *rdev, 2161 struct r100_cs_track *track) 2162 { 2163 struct radeon_bo *robj; 2164 unsigned long size; 2165 unsigned u, i, w, h, d; 2166 int ret; 2167 2168 for (u = 0; u < track->num_texture; u++) { 2169 if (!track->textures[u].enabled) 2170 continue; 2171 if (track->textures[u].lookup_disable) 2172 continue; 2173 robj = track->textures[u].robj; 2174 if (robj == NULL) { 2175 DRM_ERROR("No texture bound to unit %u\n", u); 2176 return -EINVAL; 2177 } 2178 size = 0; 2179 for (i = 0; i <= track->textures[u].num_levels; i++) { 2180 if (track->textures[u].use_pitch) { 2181 if (rdev->family < CHIP_R300) 2182 w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i); 2183 else 2184 w = track->textures[u].pitch / (1 << i); 2185 } else { 2186 w = track->textures[u].width; 2187 if (rdev->family >= CHIP_RV515) 2188 w |= track->textures[u].width_11; 2189 w = w / (1 << i); 2190 if (track->textures[u].roundup_w) 2191 w = roundup_pow_of_two(w); 2192 } 2193 h = track->textures[u].height; 2194 if (rdev->family >= CHIP_RV515) 2195 h |= track->textures[u].height_11; 2196 h = h / (1 << i); 2197 if (track->textures[u].roundup_h) 2198 h = roundup_pow_of_two(h); 2199 if (track->textures[u].tex_coord_type == 1) { 2200 d = (1 << track->textures[u].txdepth) / (1 << i); 2201 if (!d) 2202 d = 1; 2203 } else { 2204 d = 1; 2205 } 2206 if (track->textures[u].compress_format) { 2207 2208 size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d; 2209 /* compressed textures are block based */ 2210 } else 2211 size += w * h * d; 2212 } 2213 size *= track->textures[u].cpp; 2214 2215 switch (track->textures[u].tex_coord_type) { 2216 case 0: 2217 case 1: 2218 break; 2219 case 2: 2220 if (track->separate_cube) { 2221 ret = r100_cs_track_cube(rdev, track, u); 2222 if (ret) 2223 return ret; 2224 } else 2225 size *= 6; 2226 break; 2227 default: 2228 DRM_ERROR("Invalid texture coordinate type %u for unit " 2229 "%u\n", track->textures[u].tex_coord_type, u); 2230 return -EINVAL; 2231 } 2232 if (size > radeon_bo_size(robj)) { 2233 DRM_ERROR("Texture of unit %u needs %lu bytes but is " 2234 "%lu\n", u, size, radeon_bo_size(robj)); 2235 r100_cs_track_texture_print(&track->textures[u]); 2236 return -EINVAL; 2237 } 2238 } 2239 return 0; 2240 } 2241 2242 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track) 2243 { 2244 unsigned i; 2245 unsigned long size; 2246 unsigned prim_walk; 2247 unsigned nverts; 2248 unsigned num_cb = track->cb_dirty ? track->num_cb : 0; 2249 2250 if (num_cb && !track->zb_cb_clear && !track->color_channel_mask && 2251 !track->blend_read_enable) 2252 num_cb = 0; 2253 2254 for (i = 0; i < num_cb; i++) { 2255 if (track->cb[i].robj == NULL) { 2256 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i); 2257 return -EINVAL; 2258 } 2259 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy; 2260 size += track->cb[i].offset; 2261 if (size > radeon_bo_size(track->cb[i].robj)) { 2262 DRM_ERROR("[drm] Buffer too small for color buffer %d " 2263 "(need %lu have %lu) !\n", i, size, 2264 radeon_bo_size(track->cb[i].robj)); 2265 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n", 2266 i, track->cb[i].pitch, track->cb[i].cpp, 2267 track->cb[i].offset, track->maxy); 2268 return -EINVAL; 2269 } 2270 } 2271 track->cb_dirty = false; 2272 2273 if (track->zb_dirty && track->z_enabled) { 2274 if (track->zb.robj == NULL) { 2275 DRM_ERROR("[drm] No buffer for z buffer !\n"); 2276 return -EINVAL; 2277 } 2278 size = track->zb.pitch * track->zb.cpp * track->maxy; 2279 size += track->zb.offset; 2280 if (size > radeon_bo_size(track->zb.robj)) { 2281 DRM_ERROR("[drm] Buffer too small for z buffer " 2282 "(need %lu have %lu) !\n", size, 2283 radeon_bo_size(track->zb.robj)); 2284 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n", 2285 track->zb.pitch, track->zb.cpp, 2286 track->zb.offset, track->maxy); 2287 return -EINVAL; 2288 } 2289 } 2290 track->zb_dirty = false; 2291 2292 if (track->aa_dirty && track->aaresolve) { 2293 if (track->aa.robj == NULL) { 2294 DRM_ERROR("[drm] No buffer for AA resolve buffer %d !\n", i); 2295 return -EINVAL; 2296 } 2297 /* I believe the format comes from colorbuffer0. */ 2298 size = track->aa.pitch * track->cb[0].cpp * track->maxy; 2299 size += track->aa.offset; 2300 if (size > radeon_bo_size(track->aa.robj)) { 2301 DRM_ERROR("[drm] Buffer too small for AA resolve buffer %d " 2302 "(need %lu have %lu) !\n", i, size, 2303 radeon_bo_size(track->aa.robj)); 2304 DRM_ERROR("[drm] AA resolve buffer %d (%u %u %u %u)\n", 2305 i, track->aa.pitch, track->cb[0].cpp, 2306 track->aa.offset, track->maxy); 2307 return -EINVAL; 2308 } 2309 } 2310 track->aa_dirty = false; 2311 2312 prim_walk = (track->vap_vf_cntl >> 4) & 0x3; 2313 if (track->vap_vf_cntl & (1 << 14)) { 2314 nverts = track->vap_alt_nverts; 2315 } else { 2316 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF; 2317 } 2318 switch (prim_walk) { 2319 case 1: 2320 for (i = 0; i < track->num_arrays; i++) { 2321 size = track->arrays[i].esize * track->max_indx * 4; 2322 if (track->arrays[i].robj == NULL) { 2323 DRM_ERROR("(PW %u) Vertex array %u no buffer " 2324 "bound\n", prim_walk, i); 2325 return -EINVAL; 2326 } 2327 if (size > radeon_bo_size(track->arrays[i].robj)) { 2328 dev_err(rdev->dev, "(PW %u) Vertex array %u " 2329 "need %lu dwords have %lu dwords\n", 2330 prim_walk, i, size >> 2, 2331 radeon_bo_size(track->arrays[i].robj) 2332 >> 2); 2333 DRM_ERROR("Max indices %u\n", track->max_indx); 2334 return -EINVAL; 2335 } 2336 } 2337 break; 2338 case 2: 2339 for (i = 0; i < track->num_arrays; i++) { 2340 size = track->arrays[i].esize * (nverts - 1) * 4; 2341 if (track->arrays[i].robj == NULL) { 2342 DRM_ERROR("(PW %u) Vertex array %u no buffer " 2343 "bound\n", prim_walk, i); 2344 return -EINVAL; 2345 } 2346 if (size > radeon_bo_size(track->arrays[i].robj)) { 2347 dev_err(rdev->dev, "(PW %u) Vertex array %u " 2348 "need %lu dwords have %lu dwords\n", 2349 prim_walk, i, size >> 2, 2350 radeon_bo_size(track->arrays[i].robj) 2351 >> 2); 2352 return -EINVAL; 2353 } 2354 } 2355 break; 2356 case 3: 2357 size = track->vtx_size * nverts; 2358 if (size != track->immd_dwords) { 2359 DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n", 2360 track->immd_dwords, size); 2361 DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n", 2362 nverts, track->vtx_size); 2363 return -EINVAL; 2364 } 2365 break; 2366 default: 2367 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n", 2368 prim_walk); 2369 return -EINVAL; 2370 } 2371 2372 if (track->tex_dirty) { 2373 track->tex_dirty = false; 2374 return r100_cs_track_texture_check(rdev, track); 2375 } 2376 return 0; 2377 } 2378 2379 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track) 2380 { 2381 unsigned i, face; 2382 2383 track->cb_dirty = true; 2384 track->zb_dirty = true; 2385 track->tex_dirty = true; 2386 track->aa_dirty = true; 2387 2388 if (rdev->family < CHIP_R300) { 2389 track->num_cb = 1; 2390 if (rdev->family <= CHIP_RS200) 2391 track->num_texture = 3; 2392 else 2393 track->num_texture = 6; 2394 track->maxy = 2048; 2395 track->separate_cube = true; 2396 } else { 2397 track->num_cb = 4; 2398 track->num_texture = 16; 2399 track->maxy = 4096; 2400 track->separate_cube = false; 2401 track->aaresolve = false; 2402 track->aa.robj = NULL; 2403 } 2404 2405 for (i = 0; i < track->num_cb; i++) { 2406 track->cb[i].robj = NULL; 2407 track->cb[i].pitch = 8192; 2408 track->cb[i].cpp = 16; 2409 track->cb[i].offset = 0; 2410 } 2411 track->z_enabled = true; 2412 track->zb.robj = NULL; 2413 track->zb.pitch = 8192; 2414 track->zb.cpp = 4; 2415 track->zb.offset = 0; 2416 track->vtx_size = 0x7F; 2417 track->immd_dwords = 0xFFFFFFFFUL; 2418 track->num_arrays = 11; 2419 track->max_indx = 0x00FFFFFFUL; 2420 for (i = 0; i < track->num_arrays; i++) { 2421 track->arrays[i].robj = NULL; 2422 track->arrays[i].esize = 0x7F; 2423 } 2424 for (i = 0; i < track->num_texture; i++) { 2425 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 2426 track->textures[i].pitch = 16536; 2427 track->textures[i].width = 16536; 2428 track->textures[i].height = 16536; 2429 track->textures[i].width_11 = 1 << 11; 2430 track->textures[i].height_11 = 1 << 11; 2431 track->textures[i].num_levels = 12; 2432 if (rdev->family <= CHIP_RS200) { 2433 track->textures[i].tex_coord_type = 0; 2434 track->textures[i].txdepth = 0; 2435 } else { 2436 track->textures[i].txdepth = 16; 2437 track->textures[i].tex_coord_type = 1; 2438 } 2439 track->textures[i].cpp = 64; 2440 track->textures[i].robj = NULL; 2441 /* CS IB emission code makes sure texture unit are disabled */ 2442 track->textures[i].enabled = false; 2443 track->textures[i].lookup_disable = false; 2444 track->textures[i].roundup_w = true; 2445 track->textures[i].roundup_h = true; 2446 if (track->separate_cube) 2447 for (face = 0; face < 5; face++) { 2448 track->textures[i].cube_info[face].robj = NULL; 2449 track->textures[i].cube_info[face].width = 16536; 2450 track->textures[i].cube_info[face].height = 16536; 2451 track->textures[i].cube_info[face].offset = 0; 2452 } 2453 } 2454 } 2455 2456 /* 2457 * Global GPU functions 2458 */ 2459 static void r100_errata(struct radeon_device *rdev) 2460 { 2461 rdev->pll_errata = 0; 2462 2463 if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) { 2464 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS; 2465 } 2466 2467 if (rdev->family == CHIP_RV100 || 2468 rdev->family == CHIP_RS100 || 2469 rdev->family == CHIP_RS200) { 2470 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY; 2471 } 2472 } 2473 2474 static int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n) 2475 { 2476 unsigned i; 2477 uint32_t tmp; 2478 2479 for (i = 0; i < rdev->usec_timeout; i++) { 2480 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK; 2481 if (tmp >= n) { 2482 return 0; 2483 } 2484 udelay(1); 2485 } 2486 return -1; 2487 } 2488 2489 int r100_gui_wait_for_idle(struct radeon_device *rdev) 2490 { 2491 unsigned i; 2492 uint32_t tmp; 2493 2494 if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) { 2495 pr_warn("radeon: wait for empty RBBM fifo failed! Bad things might happen.\n"); 2496 } 2497 for (i = 0; i < rdev->usec_timeout; i++) { 2498 tmp = RREG32(RADEON_RBBM_STATUS); 2499 if (!(tmp & RADEON_RBBM_ACTIVE)) { 2500 return 0; 2501 } 2502 udelay(1); 2503 } 2504 return -1; 2505 } 2506 2507 int r100_mc_wait_for_idle(struct radeon_device *rdev) 2508 { 2509 unsigned i; 2510 uint32_t tmp; 2511 2512 for (i = 0; i < rdev->usec_timeout; i++) { 2513 /* read MC_STATUS */ 2514 tmp = RREG32(RADEON_MC_STATUS); 2515 if (tmp & RADEON_MC_IDLE) { 2516 return 0; 2517 } 2518 udelay(1); 2519 } 2520 return -1; 2521 } 2522 2523 bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) 2524 { 2525 u32 rbbm_status; 2526 2527 rbbm_status = RREG32(R_000E40_RBBM_STATUS); 2528 if (!G_000E40_GUI_ACTIVE(rbbm_status)) { 2529 radeon_ring_lockup_update(rdev, ring); 2530 return false; 2531 } 2532 return radeon_ring_test_lockup(rdev, ring); 2533 } 2534 2535 /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */ 2536 void r100_enable_bm(struct radeon_device *rdev) 2537 { 2538 uint32_t tmp; 2539 /* Enable bus mastering */ 2540 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; 2541 WREG32(RADEON_BUS_CNTL, tmp); 2542 } 2543 2544 void r100_bm_disable(struct radeon_device *rdev) 2545 { 2546 u32 tmp; 2547 2548 /* disable bus mastering */ 2549 tmp = RREG32(R_000030_BUS_CNTL); 2550 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044); 2551 mdelay(1); 2552 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042); 2553 mdelay(1); 2554 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040); 2555 tmp = RREG32(RADEON_BUS_CNTL); 2556 mdelay(1); 2557 pci_clear_master(rdev->pdev); 2558 mdelay(1); 2559 } 2560 2561 int r100_asic_reset(struct radeon_device *rdev, bool hard) 2562 { 2563 struct r100_mc_save save; 2564 u32 status, tmp; 2565 int ret = 0; 2566 2567 status = RREG32(R_000E40_RBBM_STATUS); 2568 if (!G_000E40_GUI_ACTIVE(status)) { 2569 return 0; 2570 } 2571 r100_mc_stop(rdev, &save); 2572 status = RREG32(R_000E40_RBBM_STATUS); 2573 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 2574 /* stop CP */ 2575 WREG32(RADEON_CP_CSQ_CNTL, 0); 2576 tmp = RREG32(RADEON_CP_RB_CNTL); 2577 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); 2578 WREG32(RADEON_CP_RB_RPTR_WR, 0); 2579 WREG32(RADEON_CP_RB_WPTR, 0); 2580 WREG32(RADEON_CP_RB_CNTL, tmp); 2581 /* save PCI state */ 2582 pci_save_state(rdev->pdev); 2583 /* disable bus mastering */ 2584 r100_bm_disable(rdev); 2585 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) | 2586 S_0000F0_SOFT_RESET_RE(1) | 2587 S_0000F0_SOFT_RESET_PP(1) | 2588 S_0000F0_SOFT_RESET_RB(1)); 2589 RREG32(R_0000F0_RBBM_SOFT_RESET); 2590 mdelay(500); 2591 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 2592 mdelay(1); 2593 status = RREG32(R_000E40_RBBM_STATUS); 2594 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 2595 /* reset CP */ 2596 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1)); 2597 RREG32(R_0000F0_RBBM_SOFT_RESET); 2598 mdelay(500); 2599 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 2600 mdelay(1); 2601 status = RREG32(R_000E40_RBBM_STATUS); 2602 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 2603 /* restore PCI & busmastering */ 2604 pci_restore_state(rdev->pdev); 2605 r100_enable_bm(rdev); 2606 /* Check if GPU is idle */ 2607 if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) || 2608 G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) { 2609 dev_err(rdev->dev, "failed to reset GPU\n"); 2610 ret = -1; 2611 } else 2612 dev_info(rdev->dev, "GPU reset succeed\n"); 2613 r100_mc_resume(rdev, &save); 2614 return ret; 2615 } 2616 2617 void r100_set_common_regs(struct radeon_device *rdev) 2618 { 2619 struct drm_device *dev = rdev->ddev; 2620 bool force_dac2 = false; 2621 u32 tmp; 2622 2623 /* set these so they don't interfere with anything */ 2624 WREG32(RADEON_OV0_SCALE_CNTL, 0); 2625 WREG32(RADEON_SUBPIC_CNTL, 0); 2626 WREG32(RADEON_VIPH_CONTROL, 0); 2627 WREG32(RADEON_I2C_CNTL_1, 0); 2628 WREG32(RADEON_DVI_I2C_CNTL_1, 0); 2629 WREG32(RADEON_CAP0_TRIG_CNTL, 0); 2630 WREG32(RADEON_CAP1_TRIG_CNTL, 0); 2631 2632 /* always set up dac2 on rn50 and some rv100 as lots 2633 * of servers seem to wire it up to a VGA port but 2634 * don't report it in the bios connector 2635 * table. 2636 */ 2637 switch (dev->pdev->device) { 2638 /* RN50 */ 2639 case 0x515e: 2640 case 0x5969: 2641 force_dac2 = true; 2642 break; 2643 /* RV100*/ 2644 case 0x5159: 2645 case 0x515a: 2646 /* DELL triple head servers */ 2647 if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) && 2648 ((dev->pdev->subsystem_device == 0x016c) || 2649 (dev->pdev->subsystem_device == 0x016d) || 2650 (dev->pdev->subsystem_device == 0x016e) || 2651 (dev->pdev->subsystem_device == 0x016f) || 2652 (dev->pdev->subsystem_device == 0x0170) || 2653 (dev->pdev->subsystem_device == 0x017d) || 2654 (dev->pdev->subsystem_device == 0x017e) || 2655 (dev->pdev->subsystem_device == 0x0183) || 2656 (dev->pdev->subsystem_device == 0x018a) || 2657 (dev->pdev->subsystem_device == 0x019a))) 2658 force_dac2 = true; 2659 break; 2660 } 2661 2662 if (force_dac2) { 2663 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG); 2664 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); 2665 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2); 2666 2667 /* For CRT on DAC2, don't turn it on if BIOS didn't 2668 enable it, even it's detected. 2669 */ 2670 2671 /* force it to crtc0 */ 2672 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL; 2673 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL; 2674 disp_hw_debug |= RADEON_CRT2_DISP1_SEL; 2675 2676 /* set up the TV DAC */ 2677 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL | 2678 RADEON_TV_DAC_STD_MASK | 2679 RADEON_TV_DAC_RDACPD | 2680 RADEON_TV_DAC_GDACPD | 2681 RADEON_TV_DAC_BDACPD | 2682 RADEON_TV_DAC_BGADJ_MASK | 2683 RADEON_TV_DAC_DACADJ_MASK); 2684 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK | 2685 RADEON_TV_DAC_NHOLD | 2686 RADEON_TV_DAC_STD_PS2 | 2687 (0x58 << 16)); 2688 2689 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); 2690 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug); 2691 WREG32(RADEON_DAC_CNTL2, dac2_cntl); 2692 } 2693 2694 /* switch PM block to ACPI mode */ 2695 tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL); 2696 tmp &= ~RADEON_PM_MODE_SEL; 2697 WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp); 2698 2699 } 2700 2701 /* 2702 * VRAM info 2703 */ 2704 static void r100_vram_get_type(struct radeon_device *rdev) 2705 { 2706 uint32_t tmp; 2707 2708 rdev->mc.vram_is_ddr = false; 2709 if (rdev->flags & RADEON_IS_IGP) 2710 rdev->mc.vram_is_ddr = true; 2711 else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR) 2712 rdev->mc.vram_is_ddr = true; 2713 if ((rdev->family == CHIP_RV100) || 2714 (rdev->family == CHIP_RS100) || 2715 (rdev->family == CHIP_RS200)) { 2716 tmp = RREG32(RADEON_MEM_CNTL); 2717 if (tmp & RV100_HALF_MODE) { 2718 rdev->mc.vram_width = 32; 2719 } else { 2720 rdev->mc.vram_width = 64; 2721 } 2722 if (rdev->flags & RADEON_SINGLE_CRTC) { 2723 rdev->mc.vram_width /= 4; 2724 rdev->mc.vram_is_ddr = true; 2725 } 2726 } else if (rdev->family <= CHIP_RV280) { 2727 tmp = RREG32(RADEON_MEM_CNTL); 2728 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) { 2729 rdev->mc.vram_width = 128; 2730 } else { 2731 rdev->mc.vram_width = 64; 2732 } 2733 } else { 2734 /* newer IGPs */ 2735 rdev->mc.vram_width = 128; 2736 } 2737 } 2738 2739 static u32 r100_get_accessible_vram(struct radeon_device *rdev) 2740 { 2741 u32 aper_size; 2742 u8 byte; 2743 2744 aper_size = RREG32(RADEON_CONFIG_APER_SIZE); 2745 2746 /* Set HDP_APER_CNTL only on cards that are known not to be broken, 2747 * that is has the 2nd generation multifunction PCI interface 2748 */ 2749 if (rdev->family == CHIP_RV280 || 2750 rdev->family >= CHIP_RV350) { 2751 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL, 2752 ~RADEON_HDP_APER_CNTL); 2753 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n"); 2754 return aper_size * 2; 2755 } 2756 2757 /* Older cards have all sorts of funny issues to deal with. First 2758 * check if it's a multifunction card by reading the PCI config 2759 * header type... Limit those to one aperture size 2760 */ 2761 pci_read_config_byte(rdev->pdev, 0xe, &byte); 2762 if (byte & 0x80) { 2763 DRM_INFO("Generation 1 PCI interface in multifunction mode\n"); 2764 DRM_INFO("Limiting VRAM to one aperture\n"); 2765 return aper_size; 2766 } 2767 2768 /* Single function older card. We read HDP_APER_CNTL to see how the BIOS 2769 * have set it up. We don't write this as it's broken on some ASICs but 2770 * we expect the BIOS to have done the right thing (might be too optimistic...) 2771 */ 2772 if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL) 2773 return aper_size * 2; 2774 return aper_size; 2775 } 2776 2777 void r100_vram_init_sizes(struct radeon_device *rdev) 2778 { 2779 u64 config_aper_size; 2780 2781 /* work out accessible VRAM */ 2782 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); 2783 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); 2784 rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev); 2785 /* FIXME we don't use the second aperture yet when we could use it */ 2786 if (rdev->mc.visible_vram_size > rdev->mc.aper_size) 2787 rdev->mc.visible_vram_size = rdev->mc.aper_size; 2788 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE); 2789 if (rdev->flags & RADEON_IS_IGP) { 2790 uint32_t tom; 2791 /* read NB_TOM to get the amount of ram stolen for the GPU */ 2792 tom = RREG32(RADEON_NB_TOM); 2793 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16); 2794 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); 2795 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; 2796 } else { 2797 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); 2798 /* Some production boards of m6 will report 0 2799 * if it's 8 MB 2800 */ 2801 if (rdev->mc.real_vram_size == 0) { 2802 rdev->mc.real_vram_size = 8192 * 1024; 2803 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); 2804 } 2805 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM - 2806 * Novell bug 204882 + along with lots of ubuntu ones 2807 */ 2808 if (rdev->mc.aper_size > config_aper_size) 2809 config_aper_size = rdev->mc.aper_size; 2810 2811 if (config_aper_size > rdev->mc.real_vram_size) 2812 rdev->mc.mc_vram_size = config_aper_size; 2813 else 2814 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; 2815 } 2816 } 2817 2818 void r100_vga_set_state(struct radeon_device *rdev, bool state) 2819 { 2820 uint32_t temp; 2821 2822 temp = RREG32(RADEON_CONFIG_CNTL); 2823 if (!state) { 2824 temp &= ~RADEON_CFG_VGA_RAM_EN; 2825 temp |= RADEON_CFG_VGA_IO_DIS; 2826 } else { 2827 temp &= ~RADEON_CFG_VGA_IO_DIS; 2828 } 2829 WREG32(RADEON_CONFIG_CNTL, temp); 2830 } 2831 2832 static void r100_mc_init(struct radeon_device *rdev) 2833 { 2834 u64 base; 2835 2836 r100_vram_get_type(rdev); 2837 r100_vram_init_sizes(rdev); 2838 base = rdev->mc.aper_base; 2839 if (rdev->flags & RADEON_IS_IGP) 2840 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; 2841 radeon_vram_location(rdev, &rdev->mc, base); 2842 rdev->mc.gtt_base_align = 0; 2843 if (!(rdev->flags & RADEON_IS_AGP)) 2844 radeon_gtt_location(rdev, &rdev->mc); 2845 radeon_update_bandwidth_info(rdev); 2846 } 2847 2848 2849 /* 2850 * Indirect registers accessor 2851 */ 2852 void r100_pll_errata_after_index(struct radeon_device *rdev) 2853 { 2854 if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) { 2855 (void)RREG32(RADEON_CLOCK_CNTL_DATA); 2856 (void)RREG32(RADEON_CRTC_GEN_CNTL); 2857 } 2858 } 2859 2860 static void r100_pll_errata_after_data(struct radeon_device *rdev) 2861 { 2862 /* This workarounds is necessary on RV100, RS100 and RS200 chips 2863 * or the chip could hang on a subsequent access 2864 */ 2865 if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) { 2866 mdelay(5); 2867 } 2868 2869 /* This function is required to workaround a hardware bug in some (all?) 2870 * revisions of the R300. This workaround should be called after every 2871 * CLOCK_CNTL_INDEX register access. If not, register reads afterward 2872 * may not be correct. 2873 */ 2874 if (rdev->pll_errata & CHIP_ERRATA_R300_CG) { 2875 uint32_t save, tmp; 2876 2877 save = RREG32(RADEON_CLOCK_CNTL_INDEX); 2878 tmp = save & ~(0x3f | RADEON_PLL_WR_EN); 2879 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp); 2880 tmp = RREG32(RADEON_CLOCK_CNTL_DATA); 2881 WREG32(RADEON_CLOCK_CNTL_INDEX, save); 2882 } 2883 } 2884 2885 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg) 2886 { 2887 unsigned long flags; 2888 uint32_t data; 2889 2890 spin_lock_irqsave(&rdev->pll_idx_lock, flags); 2891 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f); 2892 r100_pll_errata_after_index(rdev); 2893 data = RREG32(RADEON_CLOCK_CNTL_DATA); 2894 r100_pll_errata_after_data(rdev); 2895 spin_unlock_irqrestore(&rdev->pll_idx_lock, flags); 2896 return data; 2897 } 2898 2899 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 2900 { 2901 unsigned long flags; 2902 2903 spin_lock_irqsave(&rdev->pll_idx_lock, flags); 2904 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN)); 2905 r100_pll_errata_after_index(rdev); 2906 WREG32(RADEON_CLOCK_CNTL_DATA, v); 2907 r100_pll_errata_after_data(rdev); 2908 spin_unlock_irqrestore(&rdev->pll_idx_lock, flags); 2909 } 2910 2911 static void r100_set_safe_registers(struct radeon_device *rdev) 2912 { 2913 if (ASIC_IS_RN50(rdev)) { 2914 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm; 2915 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm); 2916 } else if (rdev->family < CHIP_R200) { 2917 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm; 2918 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm); 2919 } else { 2920 r200_set_safe_registers(rdev); 2921 } 2922 } 2923 2924 /* 2925 * Debugfs info 2926 */ 2927 #if defined(CONFIG_DEBUG_FS) 2928 static int r100_debugfs_rbbm_info(struct seq_file *m, void *data) 2929 { 2930 struct drm_info_node *node = (struct drm_info_node *) m->private; 2931 struct drm_device *dev = node->minor->dev; 2932 struct radeon_device *rdev = dev->dev_private; 2933 uint32_t reg, value; 2934 unsigned i; 2935 2936 seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS)); 2937 seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C)); 2938 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); 2939 for (i = 0; i < 64; i++) { 2940 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100); 2941 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2; 2942 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i); 2943 value = RREG32(RADEON_RBBM_CMDFIFO_DATA); 2944 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value); 2945 } 2946 return 0; 2947 } 2948 2949 static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data) 2950 { 2951 struct drm_info_node *node = (struct drm_info_node *) m->private; 2952 struct drm_device *dev = node->minor->dev; 2953 struct radeon_device *rdev = dev->dev_private; 2954 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2955 uint32_t rdp, wdp; 2956 unsigned count, i, j; 2957 2958 radeon_ring_free_size(rdev, ring); 2959 rdp = RREG32(RADEON_CP_RB_RPTR); 2960 wdp = RREG32(RADEON_CP_RB_WPTR); 2961 count = (rdp + ring->ring_size - wdp) & ring->ptr_mask; 2962 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); 2963 seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp); 2964 seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp); 2965 seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw); 2966 seq_printf(m, "%u dwords in ring\n", count); 2967 if (ring->ready) { 2968 for (j = 0; j <= count; j++) { 2969 i = (rdp + j) & ring->ptr_mask; 2970 seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]); 2971 } 2972 } 2973 return 0; 2974 } 2975 2976 2977 static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data) 2978 { 2979 struct drm_info_node *node = (struct drm_info_node *) m->private; 2980 struct drm_device *dev = node->minor->dev; 2981 struct radeon_device *rdev = dev->dev_private; 2982 uint32_t csq_stat, csq2_stat, tmp; 2983 unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr; 2984 unsigned i; 2985 2986 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); 2987 seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE)); 2988 csq_stat = RREG32(RADEON_CP_CSQ_STAT); 2989 csq2_stat = RREG32(RADEON_CP_CSQ2_STAT); 2990 r_rptr = (csq_stat >> 0) & 0x3ff; 2991 r_wptr = (csq_stat >> 10) & 0x3ff; 2992 ib1_rptr = (csq_stat >> 20) & 0x3ff; 2993 ib1_wptr = (csq2_stat >> 0) & 0x3ff; 2994 ib2_rptr = (csq2_stat >> 10) & 0x3ff; 2995 ib2_wptr = (csq2_stat >> 20) & 0x3ff; 2996 seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat); 2997 seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat); 2998 seq_printf(m, "Ring rptr %u\n", r_rptr); 2999 seq_printf(m, "Ring wptr %u\n", r_wptr); 3000 seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr); 3001 seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr); 3002 seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr); 3003 seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr); 3004 /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms 3005 * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */ 3006 seq_printf(m, "Ring fifo:\n"); 3007 for (i = 0; i < 256; i++) { 3008 WREG32(RADEON_CP_CSQ_ADDR, i << 2); 3009 tmp = RREG32(RADEON_CP_CSQ_DATA); 3010 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp); 3011 } 3012 seq_printf(m, "Indirect1 fifo:\n"); 3013 for (i = 256; i <= 512; i++) { 3014 WREG32(RADEON_CP_CSQ_ADDR, i << 2); 3015 tmp = RREG32(RADEON_CP_CSQ_DATA); 3016 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp); 3017 } 3018 seq_printf(m, "Indirect2 fifo:\n"); 3019 for (i = 640; i < ib1_wptr; i++) { 3020 WREG32(RADEON_CP_CSQ_ADDR, i << 2); 3021 tmp = RREG32(RADEON_CP_CSQ_DATA); 3022 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp); 3023 } 3024 return 0; 3025 } 3026 3027 static int r100_debugfs_mc_info(struct seq_file *m, void *data) 3028 { 3029 struct drm_info_node *node = (struct drm_info_node *) m->private; 3030 struct drm_device *dev = node->minor->dev; 3031 struct radeon_device *rdev = dev->dev_private; 3032 uint32_t tmp; 3033 3034 tmp = RREG32(RADEON_CONFIG_MEMSIZE); 3035 seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp); 3036 tmp = RREG32(RADEON_MC_FB_LOCATION); 3037 seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp); 3038 tmp = RREG32(RADEON_BUS_CNTL); 3039 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp); 3040 tmp = RREG32(RADEON_MC_AGP_LOCATION); 3041 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp); 3042 tmp = RREG32(RADEON_AGP_BASE); 3043 seq_printf(m, "AGP_BASE 0x%08x\n", tmp); 3044 tmp = RREG32(RADEON_HOST_PATH_CNTL); 3045 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp); 3046 tmp = RREG32(0x01D0); 3047 seq_printf(m, "AIC_CTRL 0x%08x\n", tmp); 3048 tmp = RREG32(RADEON_AIC_LO_ADDR); 3049 seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp); 3050 tmp = RREG32(RADEON_AIC_HI_ADDR); 3051 seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp); 3052 tmp = RREG32(0x01E4); 3053 seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp); 3054 return 0; 3055 } 3056 3057 static struct drm_info_list r100_debugfs_rbbm_list[] = { 3058 {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL}, 3059 }; 3060 3061 static struct drm_info_list r100_debugfs_cp_list[] = { 3062 {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL}, 3063 {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL}, 3064 }; 3065 3066 static struct drm_info_list r100_debugfs_mc_info_list[] = { 3067 {"r100_mc_info", r100_debugfs_mc_info, 0, NULL}, 3068 }; 3069 #endif 3070 3071 int r100_debugfs_rbbm_init(struct radeon_device *rdev) 3072 { 3073 #if defined(CONFIG_DEBUG_FS) 3074 return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1); 3075 #else 3076 return 0; 3077 #endif 3078 } 3079 3080 int r100_debugfs_cp_init(struct radeon_device *rdev) 3081 { 3082 #if defined(CONFIG_DEBUG_FS) 3083 return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2); 3084 #else 3085 return 0; 3086 #endif 3087 } 3088 3089 int r100_debugfs_mc_info_init(struct radeon_device *rdev) 3090 { 3091 #if defined(CONFIG_DEBUG_FS) 3092 return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1); 3093 #else 3094 return 0; 3095 #endif 3096 } 3097 3098 int r100_set_surface_reg(struct radeon_device *rdev, int reg, 3099 uint32_t tiling_flags, uint32_t pitch, 3100 uint32_t offset, uint32_t obj_size) 3101 { 3102 int surf_index = reg * 16; 3103 int flags = 0; 3104 3105 if (rdev->family <= CHIP_RS200) { 3106 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) 3107 == (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) 3108 flags |= RADEON_SURF_TILE_COLOR_BOTH; 3109 if (tiling_flags & RADEON_TILING_MACRO) 3110 flags |= RADEON_SURF_TILE_COLOR_MACRO; 3111 /* setting pitch to 0 disables tiling */ 3112 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) 3113 == 0) 3114 pitch = 0; 3115 } else if (rdev->family <= CHIP_RV280) { 3116 if (tiling_flags & (RADEON_TILING_MACRO)) 3117 flags |= R200_SURF_TILE_COLOR_MACRO; 3118 if (tiling_flags & RADEON_TILING_MICRO) 3119 flags |= R200_SURF_TILE_COLOR_MICRO; 3120 } else { 3121 if (tiling_flags & RADEON_TILING_MACRO) 3122 flags |= R300_SURF_TILE_MACRO; 3123 if (tiling_flags & RADEON_TILING_MICRO) 3124 flags |= R300_SURF_TILE_MICRO; 3125 } 3126 3127 if (tiling_flags & RADEON_TILING_SWAP_16BIT) 3128 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP; 3129 if (tiling_flags & RADEON_TILING_SWAP_32BIT) 3130 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP; 3131 3132 /* r100/r200 divide by 16 */ 3133 if (rdev->family < CHIP_R300) 3134 flags |= pitch / 16; 3135 else 3136 flags |= pitch / 8; 3137 3138 3139 DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1); 3140 WREG32(RADEON_SURFACE0_INFO + surf_index, flags); 3141 WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset); 3142 WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1); 3143 return 0; 3144 } 3145 3146 void r100_clear_surface_reg(struct radeon_device *rdev, int reg) 3147 { 3148 int surf_index = reg * 16; 3149 WREG32(RADEON_SURFACE0_INFO + surf_index, 0); 3150 } 3151 3152 void r100_bandwidth_update(struct radeon_device *rdev) 3153 { 3154 fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff; 3155 fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff; 3156 fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff; 3157 fixed20_12 crit_point_ff = {0}; 3158 uint32_t temp, data, mem_trcd, mem_trp, mem_tras; 3159 fixed20_12 memtcas_ff[8] = { 3160 dfixed_init(1), 3161 dfixed_init(2), 3162 dfixed_init(3), 3163 dfixed_init(0), 3164 dfixed_init_half(1), 3165 dfixed_init_half(2), 3166 dfixed_init(0), 3167 }; 3168 fixed20_12 memtcas_rs480_ff[8] = { 3169 dfixed_init(0), 3170 dfixed_init(1), 3171 dfixed_init(2), 3172 dfixed_init(3), 3173 dfixed_init(0), 3174 dfixed_init_half(1), 3175 dfixed_init_half(2), 3176 dfixed_init_half(3), 3177 }; 3178 fixed20_12 memtcas2_ff[8] = { 3179 dfixed_init(0), 3180 dfixed_init(1), 3181 dfixed_init(2), 3182 dfixed_init(3), 3183 dfixed_init(4), 3184 dfixed_init(5), 3185 dfixed_init(6), 3186 dfixed_init(7), 3187 }; 3188 fixed20_12 memtrbs[8] = { 3189 dfixed_init(1), 3190 dfixed_init_half(1), 3191 dfixed_init(2), 3192 dfixed_init_half(2), 3193 dfixed_init(3), 3194 dfixed_init_half(3), 3195 dfixed_init(4), 3196 dfixed_init_half(4) 3197 }; 3198 fixed20_12 memtrbs_r4xx[8] = { 3199 dfixed_init(4), 3200 dfixed_init(5), 3201 dfixed_init(6), 3202 dfixed_init(7), 3203 dfixed_init(8), 3204 dfixed_init(9), 3205 dfixed_init(10), 3206 dfixed_init(11) 3207 }; 3208 fixed20_12 min_mem_eff; 3209 fixed20_12 mc_latency_sclk, mc_latency_mclk, k1; 3210 fixed20_12 cur_latency_mclk, cur_latency_sclk; 3211 fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate = {0}, 3212 disp_drain_rate2, read_return_rate; 3213 fixed20_12 time_disp1_drop_priority; 3214 int c; 3215 int cur_size = 16; /* in octawords */ 3216 int critical_point = 0, critical_point2; 3217 /* uint32_t read_return_rate, time_disp1_drop_priority; */ 3218 int stop_req, max_stop_req; 3219 struct drm_display_mode *mode1 = NULL; 3220 struct drm_display_mode *mode2 = NULL; 3221 uint32_t pixel_bytes1 = 0; 3222 uint32_t pixel_bytes2 = 0; 3223 3224 /* Guess line buffer size to be 8192 pixels */ 3225 u32 lb_size = 8192; 3226 3227 if (!rdev->mode_info.mode_config_initialized) 3228 return; 3229 3230 radeon_update_display_priority(rdev); 3231 3232 if (rdev->mode_info.crtcs[0]->base.enabled) { 3233 const struct drm_framebuffer *fb = 3234 rdev->mode_info.crtcs[0]->base.primary->fb; 3235 3236 mode1 = &rdev->mode_info.crtcs[0]->base.mode; 3237 pixel_bytes1 = fb->format->cpp[0]; 3238 } 3239 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 3240 if (rdev->mode_info.crtcs[1]->base.enabled) { 3241 const struct drm_framebuffer *fb = 3242 rdev->mode_info.crtcs[1]->base.primary->fb; 3243 3244 mode2 = &rdev->mode_info.crtcs[1]->base.mode; 3245 pixel_bytes2 = fb->format->cpp[0]; 3246 } 3247 } 3248 3249 min_mem_eff.full = dfixed_const_8(0); 3250 /* get modes */ 3251 if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) { 3252 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER); 3253 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT); 3254 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT); 3255 /* check crtc enables */ 3256 if (mode2) 3257 mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT); 3258 if (mode1) 3259 mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT); 3260 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer); 3261 } 3262 3263 /* 3264 * determine is there is enough bw for current mode 3265 */ 3266 sclk_ff = rdev->pm.sclk; 3267 mclk_ff = rdev->pm.mclk; 3268 3269 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1); 3270 temp_ff.full = dfixed_const(temp); 3271 mem_bw.full = dfixed_mul(mclk_ff, temp_ff); 3272 3273 pix_clk.full = 0; 3274 pix_clk2.full = 0; 3275 peak_disp_bw.full = 0; 3276 if (mode1) { 3277 temp_ff.full = dfixed_const(1000); 3278 pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */ 3279 pix_clk.full = dfixed_div(pix_clk, temp_ff); 3280 temp_ff.full = dfixed_const(pixel_bytes1); 3281 peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff); 3282 } 3283 if (mode2) { 3284 temp_ff.full = dfixed_const(1000); 3285 pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */ 3286 pix_clk2.full = dfixed_div(pix_clk2, temp_ff); 3287 temp_ff.full = dfixed_const(pixel_bytes2); 3288 peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff); 3289 } 3290 3291 mem_bw.full = dfixed_mul(mem_bw, min_mem_eff); 3292 if (peak_disp_bw.full >= mem_bw.full) { 3293 DRM_ERROR("You may not have enough display bandwidth for current mode\n" 3294 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n"); 3295 } 3296 3297 /* Get values from the EXT_MEM_CNTL register...converting its contents. */ 3298 temp = RREG32(RADEON_MEM_TIMING_CNTL); 3299 if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */ 3300 mem_trcd = ((temp >> 2) & 0x3) + 1; 3301 mem_trp = ((temp & 0x3)) + 1; 3302 mem_tras = ((temp & 0x70) >> 4) + 1; 3303 } else if (rdev->family == CHIP_R300 || 3304 rdev->family == CHIP_R350) { /* r300, r350 */ 3305 mem_trcd = (temp & 0x7) + 1; 3306 mem_trp = ((temp >> 8) & 0x7) + 1; 3307 mem_tras = ((temp >> 11) & 0xf) + 4; 3308 } else if (rdev->family == CHIP_RV350 || 3309 rdev->family == CHIP_RV380) { 3310 /* rv3x0 */ 3311 mem_trcd = (temp & 0x7) + 3; 3312 mem_trp = ((temp >> 8) & 0x7) + 3; 3313 mem_tras = ((temp >> 11) & 0xf) + 6; 3314 } else if (rdev->family == CHIP_R420 || 3315 rdev->family == CHIP_R423 || 3316 rdev->family == CHIP_RV410) { 3317 /* r4xx */ 3318 mem_trcd = (temp & 0xf) + 3; 3319 if (mem_trcd > 15) 3320 mem_trcd = 15; 3321 mem_trp = ((temp >> 8) & 0xf) + 3; 3322 if (mem_trp > 15) 3323 mem_trp = 15; 3324 mem_tras = ((temp >> 12) & 0x1f) + 6; 3325 if (mem_tras > 31) 3326 mem_tras = 31; 3327 } else { /* RV200, R200 */ 3328 mem_trcd = (temp & 0x7) + 1; 3329 mem_trp = ((temp >> 8) & 0x7) + 1; 3330 mem_tras = ((temp >> 12) & 0xf) + 4; 3331 } 3332 /* convert to FF */ 3333 trcd_ff.full = dfixed_const(mem_trcd); 3334 trp_ff.full = dfixed_const(mem_trp); 3335 tras_ff.full = dfixed_const(mem_tras); 3336 3337 /* Get values from the MEM_SDRAM_MODE_REG register...converting its */ 3338 temp = RREG32(RADEON_MEM_SDRAM_MODE_REG); 3339 data = (temp & (7 << 20)) >> 20; 3340 if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) { 3341 if (rdev->family == CHIP_RS480) /* don't think rs400 */ 3342 tcas_ff = memtcas_rs480_ff[data]; 3343 else 3344 tcas_ff = memtcas_ff[data]; 3345 } else 3346 tcas_ff = memtcas2_ff[data]; 3347 3348 if (rdev->family == CHIP_RS400 || 3349 rdev->family == CHIP_RS480) { 3350 /* extra cas latency stored in bits 23-25 0-4 clocks */ 3351 data = (temp >> 23) & 0x7; 3352 if (data < 5) 3353 tcas_ff.full += dfixed_const(data); 3354 } 3355 3356 if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) { 3357 /* on the R300, Tcas is included in Trbs. 3358 */ 3359 temp = RREG32(RADEON_MEM_CNTL); 3360 data = (R300_MEM_NUM_CHANNELS_MASK & temp); 3361 if (data == 1) { 3362 if (R300_MEM_USE_CD_CH_ONLY & temp) { 3363 temp = RREG32(R300_MC_IND_INDEX); 3364 temp &= ~R300_MC_IND_ADDR_MASK; 3365 temp |= R300_MC_READ_CNTL_CD_mcind; 3366 WREG32(R300_MC_IND_INDEX, temp); 3367 temp = RREG32(R300_MC_IND_DATA); 3368 data = (R300_MEM_RBS_POSITION_C_MASK & temp); 3369 } else { 3370 temp = RREG32(R300_MC_READ_CNTL_AB); 3371 data = (R300_MEM_RBS_POSITION_A_MASK & temp); 3372 } 3373 } else { 3374 temp = RREG32(R300_MC_READ_CNTL_AB); 3375 data = (R300_MEM_RBS_POSITION_A_MASK & temp); 3376 } 3377 if (rdev->family == CHIP_RV410 || 3378 rdev->family == CHIP_R420 || 3379 rdev->family == CHIP_R423) 3380 trbs_ff = memtrbs_r4xx[data]; 3381 else 3382 trbs_ff = memtrbs[data]; 3383 tcas_ff.full += trbs_ff.full; 3384 } 3385 3386 sclk_eff_ff.full = sclk_ff.full; 3387 3388 if (rdev->flags & RADEON_IS_AGP) { 3389 fixed20_12 agpmode_ff; 3390 agpmode_ff.full = dfixed_const(radeon_agpmode); 3391 temp_ff.full = dfixed_const_666(16); 3392 sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff); 3393 } 3394 /* TODO PCIE lanes may affect this - agpmode == 16?? */ 3395 3396 if (ASIC_IS_R300(rdev)) { 3397 sclk_delay_ff.full = dfixed_const(250); 3398 } else { 3399 if ((rdev->family == CHIP_RV100) || 3400 rdev->flags & RADEON_IS_IGP) { 3401 if (rdev->mc.vram_is_ddr) 3402 sclk_delay_ff.full = dfixed_const(41); 3403 else 3404 sclk_delay_ff.full = dfixed_const(33); 3405 } else { 3406 if (rdev->mc.vram_width == 128) 3407 sclk_delay_ff.full = dfixed_const(57); 3408 else 3409 sclk_delay_ff.full = dfixed_const(41); 3410 } 3411 } 3412 3413 mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff); 3414 3415 if (rdev->mc.vram_is_ddr) { 3416 if (rdev->mc.vram_width == 32) { 3417 k1.full = dfixed_const(40); 3418 c = 3; 3419 } else { 3420 k1.full = dfixed_const(20); 3421 c = 1; 3422 } 3423 } else { 3424 k1.full = dfixed_const(40); 3425 c = 3; 3426 } 3427 3428 temp_ff.full = dfixed_const(2); 3429 mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff); 3430 temp_ff.full = dfixed_const(c); 3431 mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff); 3432 temp_ff.full = dfixed_const(4); 3433 mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff); 3434 mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff); 3435 mc_latency_mclk.full += k1.full; 3436 3437 mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff); 3438 mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff); 3439 3440 /* 3441 HW cursor time assuming worst case of full size colour cursor. 3442 */ 3443 temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1)))); 3444 temp_ff.full += trcd_ff.full; 3445 if (temp_ff.full < tras_ff.full) 3446 temp_ff.full = tras_ff.full; 3447 cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff); 3448 3449 temp_ff.full = dfixed_const(cur_size); 3450 cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff); 3451 /* 3452 Find the total latency for the display data. 3453 */ 3454 disp_latency_overhead.full = dfixed_const(8); 3455 disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff); 3456 mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full; 3457 mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full; 3458 3459 if (mc_latency_mclk.full > mc_latency_sclk.full) 3460 disp_latency.full = mc_latency_mclk.full; 3461 else 3462 disp_latency.full = mc_latency_sclk.full; 3463 3464 /* setup Max GRPH_STOP_REQ default value */ 3465 if (ASIC_IS_RV100(rdev)) 3466 max_stop_req = 0x5c; 3467 else 3468 max_stop_req = 0x7c; 3469 3470 if (mode1) { 3471 /* CRTC1 3472 Set GRPH_BUFFER_CNTL register using h/w defined optimal values. 3473 GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ] 3474 */ 3475 stop_req = mode1->hdisplay * pixel_bytes1 / 16; 3476 3477 if (stop_req > max_stop_req) 3478 stop_req = max_stop_req; 3479 3480 /* 3481 Find the drain rate of the display buffer. 3482 */ 3483 temp_ff.full = dfixed_const((16/pixel_bytes1)); 3484 disp_drain_rate.full = dfixed_div(pix_clk, temp_ff); 3485 3486 /* 3487 Find the critical point of the display buffer. 3488 */ 3489 crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency); 3490 crit_point_ff.full += dfixed_const_half(0); 3491 3492 critical_point = dfixed_trunc(crit_point_ff); 3493 3494 if (rdev->disp_priority == 2) { 3495 critical_point = 0; 3496 } 3497 3498 /* 3499 The critical point should never be above max_stop_req-4. Setting 3500 GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time. 3501 */ 3502 if (max_stop_req - critical_point < 4) 3503 critical_point = 0; 3504 3505 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) { 3506 /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/ 3507 critical_point = 0x10; 3508 } 3509 3510 temp = RREG32(RADEON_GRPH_BUFFER_CNTL); 3511 temp &= ~(RADEON_GRPH_STOP_REQ_MASK); 3512 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); 3513 temp &= ~(RADEON_GRPH_START_REQ_MASK); 3514 if ((rdev->family == CHIP_R350) && 3515 (stop_req > 0x15)) { 3516 stop_req -= 0x10; 3517 } 3518 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT); 3519 temp |= RADEON_GRPH_BUFFER_SIZE; 3520 temp &= ~(RADEON_GRPH_CRITICAL_CNTL | 3521 RADEON_GRPH_CRITICAL_AT_SOF | 3522 RADEON_GRPH_STOP_CNTL); 3523 /* 3524 Write the result into the register. 3525 */ 3526 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) | 3527 (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT))); 3528 3529 #if 0 3530 if ((rdev->family == CHIP_RS400) || 3531 (rdev->family == CHIP_RS480)) { 3532 /* attempt to program RS400 disp regs correctly ??? */ 3533 temp = RREG32(RS400_DISP1_REG_CNTL); 3534 temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK | 3535 RS400_DISP1_STOP_REQ_LEVEL_MASK); 3536 WREG32(RS400_DISP1_REQ_CNTL1, (temp | 3537 (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) | 3538 (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT))); 3539 temp = RREG32(RS400_DMIF_MEM_CNTL1); 3540 temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK | 3541 RS400_DISP1_CRITICAL_POINT_STOP_MASK); 3542 WREG32(RS400_DMIF_MEM_CNTL1, (temp | 3543 (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) | 3544 (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT))); 3545 } 3546 #endif 3547 3548 DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n", 3549 /* (unsigned int)info->SavedReg->grph_buffer_cntl, */ 3550 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL)); 3551 } 3552 3553 if (mode2) { 3554 u32 grph2_cntl; 3555 stop_req = mode2->hdisplay * pixel_bytes2 / 16; 3556 3557 if (stop_req > max_stop_req) 3558 stop_req = max_stop_req; 3559 3560 /* 3561 Find the drain rate of the display buffer. 3562 */ 3563 temp_ff.full = dfixed_const((16/pixel_bytes2)); 3564 disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff); 3565 3566 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL); 3567 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK); 3568 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); 3569 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK); 3570 if ((rdev->family == CHIP_R350) && 3571 (stop_req > 0x15)) { 3572 stop_req -= 0x10; 3573 } 3574 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT); 3575 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE; 3576 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL | 3577 RADEON_GRPH_CRITICAL_AT_SOF | 3578 RADEON_GRPH_STOP_CNTL); 3579 3580 if ((rdev->family == CHIP_RS100) || 3581 (rdev->family == CHIP_RS200)) 3582 critical_point2 = 0; 3583 else { 3584 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128; 3585 temp_ff.full = dfixed_const(temp); 3586 temp_ff.full = dfixed_mul(mclk_ff, temp_ff); 3587 if (sclk_ff.full < temp_ff.full) 3588 temp_ff.full = sclk_ff.full; 3589 3590 read_return_rate.full = temp_ff.full; 3591 3592 if (mode1) { 3593 temp_ff.full = read_return_rate.full - disp_drain_rate.full; 3594 time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff); 3595 } else { 3596 time_disp1_drop_priority.full = 0; 3597 } 3598 crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full; 3599 crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2); 3600 crit_point_ff.full += dfixed_const_half(0); 3601 3602 critical_point2 = dfixed_trunc(crit_point_ff); 3603 3604 if (rdev->disp_priority == 2) { 3605 critical_point2 = 0; 3606 } 3607 3608 if (max_stop_req - critical_point2 < 4) 3609 critical_point2 = 0; 3610 3611 } 3612 3613 if (critical_point2 == 0 && rdev->family == CHIP_R300) { 3614 /* some R300 cards have problem with this set to 0 */ 3615 critical_point2 = 0x10; 3616 } 3617 3618 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) | 3619 (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT))); 3620 3621 if ((rdev->family == CHIP_RS400) || 3622 (rdev->family == CHIP_RS480)) { 3623 #if 0 3624 /* attempt to program RS400 disp2 regs correctly ??? */ 3625 temp = RREG32(RS400_DISP2_REQ_CNTL1); 3626 temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK | 3627 RS400_DISP2_STOP_REQ_LEVEL_MASK); 3628 WREG32(RS400_DISP2_REQ_CNTL1, (temp | 3629 (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) | 3630 (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT))); 3631 temp = RREG32(RS400_DISP2_REQ_CNTL2); 3632 temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK | 3633 RS400_DISP2_CRITICAL_POINT_STOP_MASK); 3634 WREG32(RS400_DISP2_REQ_CNTL2, (temp | 3635 (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) | 3636 (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT))); 3637 #endif 3638 WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC); 3639 WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000); 3640 WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC); 3641 WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC); 3642 } 3643 3644 DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n", 3645 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL)); 3646 } 3647 3648 /* Save number of lines the linebuffer leads before the scanout */ 3649 if (mode1) 3650 rdev->mode_info.crtcs[0]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode1->crtc_hdisplay); 3651 3652 if (mode2) 3653 rdev->mode_info.crtcs[1]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode2->crtc_hdisplay); 3654 } 3655 3656 int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *ring) 3657 { 3658 uint32_t scratch; 3659 uint32_t tmp = 0; 3660 unsigned i; 3661 int r; 3662 3663 r = radeon_scratch_get(rdev, &scratch); 3664 if (r) { 3665 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r); 3666 return r; 3667 } 3668 WREG32(scratch, 0xCAFEDEAD); 3669 r = radeon_ring_lock(rdev, ring, 2); 3670 if (r) { 3671 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); 3672 radeon_scratch_free(rdev, scratch); 3673 return r; 3674 } 3675 radeon_ring_write(ring, PACKET0(scratch, 0)); 3676 radeon_ring_write(ring, 0xDEADBEEF); 3677 radeon_ring_unlock_commit(rdev, ring, false); 3678 for (i = 0; i < rdev->usec_timeout; i++) { 3679 tmp = RREG32(scratch); 3680 if (tmp == 0xDEADBEEF) { 3681 break; 3682 } 3683 udelay(1); 3684 } 3685 if (i < rdev->usec_timeout) { 3686 DRM_INFO("ring test succeeded in %d usecs\n", i); 3687 } else { 3688 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n", 3689 scratch, tmp); 3690 r = -EINVAL; 3691 } 3692 radeon_scratch_free(rdev, scratch); 3693 return r; 3694 } 3695 3696 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) 3697 { 3698 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 3699 3700 if (ring->rptr_save_reg) { 3701 u32 next_rptr = ring->wptr + 2 + 3; 3702 radeon_ring_write(ring, PACKET0(ring->rptr_save_reg, 0)); 3703 radeon_ring_write(ring, next_rptr); 3704 } 3705 3706 radeon_ring_write(ring, PACKET0(RADEON_CP_IB_BASE, 1)); 3707 radeon_ring_write(ring, ib->gpu_addr); 3708 radeon_ring_write(ring, ib->length_dw); 3709 } 3710 3711 int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) 3712 { 3713 struct radeon_ib ib; 3714 uint32_t scratch; 3715 uint32_t tmp = 0; 3716 unsigned i; 3717 int r; 3718 3719 r = radeon_scratch_get(rdev, &scratch); 3720 if (r) { 3721 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r); 3722 return r; 3723 } 3724 WREG32(scratch, 0xCAFEDEAD); 3725 r = radeon_ib_get(rdev, RADEON_RING_TYPE_GFX_INDEX, &ib, NULL, 256); 3726 if (r) { 3727 DRM_ERROR("radeon: failed to get ib (%d).\n", r); 3728 goto free_scratch; 3729 } 3730 ib.ptr[0] = PACKET0(scratch, 0); 3731 ib.ptr[1] = 0xDEADBEEF; 3732 ib.ptr[2] = PACKET2(0); 3733 ib.ptr[3] = PACKET2(0); 3734 ib.ptr[4] = PACKET2(0); 3735 ib.ptr[5] = PACKET2(0); 3736 ib.ptr[6] = PACKET2(0); 3737 ib.ptr[7] = PACKET2(0); 3738 ib.length_dw = 8; 3739 r = radeon_ib_schedule(rdev, &ib, NULL, false); 3740 if (r) { 3741 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); 3742 goto free_ib; 3743 } 3744 r = radeon_fence_wait_timeout(ib.fence, false, usecs_to_jiffies( 3745 RADEON_USEC_IB_TEST_TIMEOUT)); 3746 if (r < 0) { 3747 DRM_ERROR("radeon: fence wait failed (%d).\n", r); 3748 goto free_ib; 3749 } else if (r == 0) { 3750 DRM_ERROR("radeon: fence wait timed out.\n"); 3751 r = -ETIMEDOUT; 3752 goto free_ib; 3753 } 3754 r = 0; 3755 for (i = 0; i < rdev->usec_timeout; i++) { 3756 tmp = RREG32(scratch); 3757 if (tmp == 0xDEADBEEF) { 3758 break; 3759 } 3760 udelay(1); 3761 } 3762 if (i < rdev->usec_timeout) { 3763 DRM_INFO("ib test succeeded in %u usecs\n", i); 3764 } else { 3765 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n", 3766 scratch, tmp); 3767 r = -EINVAL; 3768 } 3769 free_ib: 3770 radeon_ib_free(rdev, &ib); 3771 free_scratch: 3772 radeon_scratch_free(rdev, scratch); 3773 return r; 3774 } 3775 3776 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save) 3777 { 3778 /* Shutdown CP we shouldn't need to do that but better be safe than 3779 * sorry 3780 */ 3781 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; 3782 WREG32(R_000740_CP_CSQ_CNTL, 0); 3783 3784 /* Save few CRTC registers */ 3785 save->GENMO_WT = RREG8(R_0003C2_GENMO_WT); 3786 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL); 3787 save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL); 3788 save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET); 3789 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 3790 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL); 3791 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET); 3792 } 3793 3794 /* Disable VGA aperture access */ 3795 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT); 3796 /* Disable cursor, overlay, crtc */ 3797 WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1)); 3798 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL | 3799 S_000054_CRTC_DISPLAY_DIS(1)); 3800 WREG32(R_000050_CRTC_GEN_CNTL, 3801 (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) | 3802 S_000050_CRTC_DISP_REQ_EN_B(1)); 3803 WREG32(R_000420_OV0_SCALE_CNTL, 3804 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL)); 3805 WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET); 3806 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 3807 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET | 3808 S_000360_CUR2_LOCK(1)); 3809 WREG32(R_0003F8_CRTC2_GEN_CNTL, 3810 (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) | 3811 S_0003F8_CRTC2_DISPLAY_DIS(1) | 3812 S_0003F8_CRTC2_DISP_REQ_EN_B(1)); 3813 WREG32(R_000360_CUR2_OFFSET, 3814 C_000360_CUR2_LOCK & save->CUR2_OFFSET); 3815 } 3816 } 3817 3818 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save) 3819 { 3820 /* Update base address for crtc */ 3821 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start); 3822 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 3823 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start); 3824 } 3825 /* Restore CRTC registers */ 3826 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT); 3827 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL); 3828 WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL); 3829 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 3830 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL); 3831 } 3832 } 3833 3834 void r100_vga_render_disable(struct radeon_device *rdev) 3835 { 3836 u32 tmp; 3837 3838 tmp = RREG8(R_0003C2_GENMO_WT); 3839 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp); 3840 } 3841 3842 static void r100_debugfs(struct radeon_device *rdev) 3843 { 3844 int r; 3845 3846 r = r100_debugfs_mc_info_init(rdev); 3847 if (r) 3848 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n"); 3849 } 3850 3851 static void r100_mc_program(struct radeon_device *rdev) 3852 { 3853 struct r100_mc_save save; 3854 3855 /* Stops all mc clients */ 3856 r100_mc_stop(rdev, &save); 3857 if (rdev->flags & RADEON_IS_AGP) { 3858 WREG32(R_00014C_MC_AGP_LOCATION, 3859 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) | 3860 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); 3861 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); 3862 if (rdev->family > CHIP_RV200) 3863 WREG32(R_00015C_AGP_BASE_2, 3864 upper_32_bits(rdev->mc.agp_base) & 0xff); 3865 } else { 3866 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF); 3867 WREG32(R_000170_AGP_BASE, 0); 3868 if (rdev->family > CHIP_RV200) 3869 WREG32(R_00015C_AGP_BASE_2, 0); 3870 } 3871 /* Wait for mc idle */ 3872 if (r100_mc_wait_for_idle(rdev)) 3873 dev_warn(rdev->dev, "Wait for MC idle timeout.\n"); 3874 /* Program MC, should be a 32bits limited address space */ 3875 WREG32(R_000148_MC_FB_LOCATION, 3876 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | 3877 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); 3878 r100_mc_resume(rdev, &save); 3879 } 3880 3881 static void r100_clock_startup(struct radeon_device *rdev) 3882 { 3883 u32 tmp; 3884 3885 if (radeon_dynclks != -1 && radeon_dynclks) 3886 radeon_legacy_set_clock_gating(rdev, 1); 3887 /* We need to force on some of the block */ 3888 tmp = RREG32_PLL(R_00000D_SCLK_CNTL); 3889 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1); 3890 if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280)) 3891 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1); 3892 WREG32_PLL(R_00000D_SCLK_CNTL, tmp); 3893 } 3894 3895 static int r100_startup(struct radeon_device *rdev) 3896 { 3897 int r; 3898 3899 /* set common regs */ 3900 r100_set_common_regs(rdev); 3901 /* program mc */ 3902 r100_mc_program(rdev); 3903 /* Resume clock */ 3904 r100_clock_startup(rdev); 3905 /* Initialize GART (initialize after TTM so we can allocate 3906 * memory through TTM but finalize after TTM) */ 3907 r100_enable_bm(rdev); 3908 if (rdev->flags & RADEON_IS_PCI) { 3909 r = r100_pci_gart_enable(rdev); 3910 if (r) 3911 return r; 3912 } 3913 3914 /* allocate wb buffer */ 3915 r = radeon_wb_init(rdev); 3916 if (r) 3917 return r; 3918 3919 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 3920 if (r) { 3921 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 3922 return r; 3923 } 3924 3925 /* Enable IRQ */ 3926 if (!rdev->irq.installed) { 3927 r = radeon_irq_kms_init(rdev); 3928 if (r) 3929 return r; 3930 } 3931 3932 r100_irq_set(rdev); 3933 rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 3934 /* 1M ring buffer */ 3935 r = r100_cp_init(rdev, 1024 * 1024); 3936 if (r) { 3937 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); 3938 return r; 3939 } 3940 3941 r = radeon_ib_pool_init(rdev); 3942 if (r) { 3943 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 3944 return r; 3945 } 3946 3947 return 0; 3948 } 3949 3950 int r100_resume(struct radeon_device *rdev) 3951 { 3952 int r; 3953 3954 /* Make sur GART are not working */ 3955 if (rdev->flags & RADEON_IS_PCI) 3956 r100_pci_gart_disable(rdev); 3957 /* Resume clock before doing reset */ 3958 r100_clock_startup(rdev); 3959 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 3960 if (radeon_asic_reset(rdev)) { 3961 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 3962 RREG32(R_000E40_RBBM_STATUS), 3963 RREG32(R_0007C0_CP_STAT)); 3964 } 3965 /* post */ 3966 radeon_combios_asic_init(rdev->ddev); 3967 /* Resume clock after posting */ 3968 r100_clock_startup(rdev); 3969 /* Initialize surface registers */ 3970 radeon_surface_init(rdev); 3971 3972 rdev->accel_working = true; 3973 r = r100_startup(rdev); 3974 if (r) { 3975 rdev->accel_working = false; 3976 } 3977 return r; 3978 } 3979 3980 int r100_suspend(struct radeon_device *rdev) 3981 { 3982 radeon_pm_suspend(rdev); 3983 r100_cp_disable(rdev); 3984 radeon_wb_disable(rdev); 3985 r100_irq_disable(rdev); 3986 if (rdev->flags & RADEON_IS_PCI) 3987 r100_pci_gart_disable(rdev); 3988 return 0; 3989 } 3990 3991 void r100_fini(struct radeon_device *rdev) 3992 { 3993 radeon_pm_fini(rdev); 3994 r100_cp_fini(rdev); 3995 radeon_wb_fini(rdev); 3996 radeon_ib_pool_fini(rdev); 3997 radeon_gem_fini(rdev); 3998 if (rdev->flags & RADEON_IS_PCI) 3999 r100_pci_gart_fini(rdev); 4000 radeon_agp_fini(rdev); 4001 radeon_irq_kms_fini(rdev); 4002 radeon_fence_driver_fini(rdev); 4003 radeon_bo_fini(rdev); 4004 radeon_atombios_fini(rdev); 4005 kfree(rdev->bios); 4006 rdev->bios = NULL; 4007 } 4008 4009 /* 4010 * Due to how kexec works, it can leave the hw fully initialised when it 4011 * boots the new kernel. However doing our init sequence with the CP and 4012 * WB stuff setup causes GPU hangs on the RN50 at least. So at startup 4013 * do some quick sanity checks and restore sane values to avoid this 4014 * problem. 4015 */ 4016 void r100_restore_sanity(struct radeon_device *rdev) 4017 { 4018 u32 tmp; 4019 4020 tmp = RREG32(RADEON_CP_CSQ_CNTL); 4021 if (tmp) { 4022 WREG32(RADEON_CP_CSQ_CNTL, 0); 4023 } 4024 tmp = RREG32(RADEON_CP_RB_CNTL); 4025 if (tmp) { 4026 WREG32(RADEON_CP_RB_CNTL, 0); 4027 } 4028 tmp = RREG32(RADEON_SCRATCH_UMSK); 4029 if (tmp) { 4030 WREG32(RADEON_SCRATCH_UMSK, 0); 4031 } 4032 } 4033 4034 int r100_init(struct radeon_device *rdev) 4035 { 4036 int r; 4037 4038 /* Register debugfs file specific to this group of asics */ 4039 r100_debugfs(rdev); 4040 /* Disable VGA */ 4041 r100_vga_render_disable(rdev); 4042 /* Initialize scratch registers */ 4043 radeon_scratch_init(rdev); 4044 /* Initialize surface registers */ 4045 radeon_surface_init(rdev); 4046 /* sanity check some register to avoid hangs like after kexec */ 4047 r100_restore_sanity(rdev); 4048 /* TODO: disable VGA need to use VGA request */ 4049 /* BIOS*/ 4050 if (!radeon_get_bios(rdev)) { 4051 if (ASIC_IS_AVIVO(rdev)) 4052 return -EINVAL; 4053 } 4054 if (rdev->is_atom_bios) { 4055 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n"); 4056 return -EINVAL; 4057 } else { 4058 r = radeon_combios_init(rdev); 4059 if (r) 4060 return r; 4061 } 4062 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 4063 if (radeon_asic_reset(rdev)) { 4064 dev_warn(rdev->dev, 4065 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 4066 RREG32(R_000E40_RBBM_STATUS), 4067 RREG32(R_0007C0_CP_STAT)); 4068 } 4069 /* check if cards are posted or not */ 4070 if (radeon_boot_test_post_card(rdev) == false) 4071 return -EINVAL; 4072 /* Set asic errata */ 4073 r100_errata(rdev); 4074 /* Initialize clocks */ 4075 radeon_get_clock_info(rdev->ddev); 4076 /* initialize AGP */ 4077 if (rdev->flags & RADEON_IS_AGP) { 4078 r = radeon_agp_init(rdev); 4079 if (r) { 4080 radeon_agp_disable(rdev); 4081 } 4082 } 4083 /* initialize VRAM */ 4084 r100_mc_init(rdev); 4085 /* Fence driver */ 4086 r = radeon_fence_driver_init(rdev); 4087 if (r) 4088 return r; 4089 /* Memory manager */ 4090 r = radeon_bo_init(rdev); 4091 if (r) 4092 return r; 4093 if (rdev->flags & RADEON_IS_PCI) { 4094 r = r100_pci_gart_init(rdev); 4095 if (r) 4096 return r; 4097 } 4098 r100_set_safe_registers(rdev); 4099 4100 /* Initialize power management */ 4101 radeon_pm_init(rdev); 4102 4103 rdev->accel_working = true; 4104 r = r100_startup(rdev); 4105 if (r) { 4106 /* Somethings want wront with the accel init stop accel */ 4107 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 4108 r100_cp_fini(rdev); 4109 radeon_wb_fini(rdev); 4110 radeon_ib_pool_fini(rdev); 4111 radeon_irq_kms_fini(rdev); 4112 if (rdev->flags & RADEON_IS_PCI) 4113 r100_pci_gart_fini(rdev); 4114 rdev->accel_working = false; 4115 } 4116 return 0; 4117 } 4118 4119 uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg) 4120 { 4121 unsigned long flags; 4122 uint32_t ret; 4123 4124 spin_lock_irqsave(&rdev->mmio_idx_lock, flags); 4125 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); 4126 ret = readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); 4127 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags); 4128 return ret; 4129 } 4130 4131 void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v) 4132 { 4133 unsigned long flags; 4134 4135 spin_lock_irqsave(&rdev->mmio_idx_lock, flags); 4136 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); 4137 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); 4138 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags); 4139 } 4140 4141 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg) 4142 { 4143 if (reg < rdev->rio_mem_size) 4144 return ioread32(rdev->rio_mem + reg); 4145 else { 4146 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX); 4147 return ioread32(rdev->rio_mem + RADEON_MM_DATA); 4148 } 4149 } 4150 4151 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v) 4152 { 4153 if (reg < rdev->rio_mem_size) 4154 iowrite32(v, rdev->rio_mem + reg); 4155 else { 4156 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX); 4157 iowrite32(v, rdev->rio_mem + RADEON_MM_DATA); 4158 } 4159 } 4160
Indexes created Sun Oct 26 21:10:03 GMT 2025