radeon_r100.c revision 1.1.2.2
1 /* $NetBSD: radeon_r100.c,v 1.1.2.2 2018/09/06 06:56:32 pgoyette Exp $ */ 2 3 /* 4 * Copyright 2008 Advanced Micro Devices, Inc. 5 * Copyright 2008 Red Hat Inc. 6 * Copyright 2009 Jerome Glisse. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: Dave Airlie 27 * Alex Deucher 28 * Jerome Glisse 29 */ 30 #include <sys/cdefs.h> 31 __KERNEL_RCSID(0, "$NetBSD: radeon_r100.c,v 1.1.2.2 2018/09/06 06:56:32 pgoyette Exp $"); 32 33 #include <linux/seq_file.h> 34 #include <linux/slab.h> 35 #include <drm/drmP.h> 36 #include <drm/radeon_drm.h> 37 #include "radeon_reg.h" 38 #include "radeon.h" 39 #include "radeon_asic.h" 40 #include "r100d.h" 41 #include "rs100d.h" 42 #include "rv200d.h" 43 #include "rv250d.h" 44 #include "atom.h" 45 46 #include <linux/firmware.h> 47 #include <linux/module.h> 48 49 #include "r100_reg_safe.h" 50 #include "rn50_reg_safe.h" 51 52 /* Firmware Names */ 53 #define FIRMWARE_R100 "radeon/R100_cp.bin" 54 #define FIRMWARE_R200 "radeon/R200_cp.bin" 55 #define FIRMWARE_R300 "radeon/R300_cp.bin" 56 #define FIRMWARE_R420 "radeon/R420_cp.bin" 57 #define FIRMWARE_RS690 "radeon/RS690_cp.bin" 58 #define FIRMWARE_RS600 "radeon/RS600_cp.bin" 59 #define FIRMWARE_R520 "radeon/R520_cp.bin" 60 61 MODULE_FIRMWARE(FIRMWARE_R100); 62 MODULE_FIRMWARE(FIRMWARE_R200); 63 MODULE_FIRMWARE(FIRMWARE_R300); 64 MODULE_FIRMWARE(FIRMWARE_R420); 65 MODULE_FIRMWARE(FIRMWARE_RS690); 66 MODULE_FIRMWARE(FIRMWARE_RS600); 67 MODULE_FIRMWARE(FIRMWARE_R520); 68 69 #include "r100_track.h" 70 71 /* This files gather functions specifics to: 72 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 73 * and others in some cases. 74 */ 75 76 static bool r100_is_in_vblank(struct radeon_device *rdev, int crtc) 77 { 78 if (crtc == 0) { 79 if (RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR) 80 return true; 81 else 82 return false; 83 } else { 84 if (RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR) 85 return true; 86 else 87 return false; 88 } 89 } 90 91 static bool r100_is_counter_moving(struct radeon_device *rdev, int crtc) 92 { 93 u32 vline1, vline2; 94 95 if (crtc == 0) { 96 vline1 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; 97 vline2 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; 98 } else { 99 vline1 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; 100 vline2 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; 101 } 102 if (vline1 != vline2) 103 return true; 104 else 105 return false; 106 } 107 108 /** 109 * r100_wait_for_vblank - vblank wait asic callback. 110 * 111 * @rdev: radeon_device pointer 112 * @crtc: crtc to wait for vblank on 113 * 114 * Wait for vblank on the requested crtc (r1xx-r4xx). 115 */ 116 void r100_wait_for_vblank(struct radeon_device *rdev, int crtc) 117 { 118 unsigned i = 0; 119 120 if (crtc >= rdev->num_crtc) 121 return; 122 123 if (crtc == 0) { 124 if (!(RREG32(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EN)) 125 return; 126 } else { 127 if (!(RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN)) 128 return; 129 } 130 131 /* depending on when we hit vblank, we may be close to active; if so, 132 * wait for another frame. 133 */ 134 while (r100_is_in_vblank(rdev, crtc)) { 135 if (i++ % 100 == 0) { 136 if (!r100_is_counter_moving(rdev, crtc)) 137 break; 138 } 139 } 140 141 while (!r100_is_in_vblank(rdev, crtc)) { 142 if (i++ % 100 == 0) { 143 if (!r100_is_counter_moving(rdev, crtc)) 144 break; 145 } 146 } 147 } 148 149 /** 150 * r100_page_flip - pageflip callback. 151 * 152 * @rdev: radeon_device pointer 153 * @crtc_id: crtc to cleanup pageflip on 154 * @crtc_base: new address of the crtc (GPU MC address) 155 * 156 * Does the actual pageflip (r1xx-r4xx). 157 * During vblank we take the crtc lock and wait for the update_pending 158 * bit to go high, when it does, we release the lock, and allow the 159 * double buffered update to take place. 160 */ 161 void r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base) 162 { 163 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 164 u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK; 165 int i; 166 167 /* Lock the graphics update lock */ 168 /* update the scanout addresses */ 169 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp); 170 171 /* Wait for update_pending to go high. */ 172 for (i = 0; i < rdev->usec_timeout; i++) { 173 if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET) 174 break; 175 udelay(1); 176 } 177 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n"); 178 179 /* Unlock the lock, so double-buffering can take place inside vblank */ 180 tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK; 181 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp); 182 183 } 184 185 /** 186 * r100_page_flip_pending - check if page flip is still pending 187 * 188 * @rdev: radeon_device pointer 189 * @crtc_id: crtc to check 190 * 191 * Check if the last pagefilp is still pending (r1xx-r4xx). 192 * Returns the current update pending status. 193 */ 194 bool r100_page_flip_pending(struct radeon_device *rdev, int crtc_id) 195 { 196 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 197 198 /* Return current update_pending status: */ 199 return !!(RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & 200 RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET); 201 } 202 203 /** 204 * r100_pm_get_dynpm_state - look up dynpm power state callback. 205 * 206 * @rdev: radeon_device pointer 207 * 208 * Look up the optimal power state based on the 209 * current state of the GPU (r1xx-r5xx). 210 * Used for dynpm only. 211 */ 212 void r100_pm_get_dynpm_state(struct radeon_device *rdev) 213 { 214 int i; 215 rdev->pm.dynpm_can_upclock = true; 216 rdev->pm.dynpm_can_downclock = true; 217 218 switch (rdev->pm.dynpm_planned_action) { 219 case DYNPM_ACTION_MINIMUM: 220 rdev->pm.requested_power_state_index = 0; 221 rdev->pm.dynpm_can_downclock = false; 222 break; 223 case DYNPM_ACTION_DOWNCLOCK: 224 if (rdev->pm.current_power_state_index == 0) { 225 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 226 rdev->pm.dynpm_can_downclock = false; 227 } else { 228 if (rdev->pm.active_crtc_count > 1) { 229 for (i = 0; i < rdev->pm.num_power_states; i++) { 230 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 231 continue; 232 else if (i >= rdev->pm.current_power_state_index) { 233 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 234 break; 235 } else { 236 rdev->pm.requested_power_state_index = i; 237 break; 238 } 239 } 240 } else 241 rdev->pm.requested_power_state_index = 242 rdev->pm.current_power_state_index - 1; 243 } 244 /* don't use the power state if crtcs are active and no display flag is set */ 245 if ((rdev->pm.active_crtc_count > 0) && 246 (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags & 247 RADEON_PM_MODE_NO_DISPLAY)) { 248 rdev->pm.requested_power_state_index++; 249 } 250 break; 251 case DYNPM_ACTION_UPCLOCK: 252 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) { 253 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 254 rdev->pm.dynpm_can_upclock = false; 255 } else { 256 if (rdev->pm.active_crtc_count > 1) { 257 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) { 258 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 259 continue; 260 else if (i <= rdev->pm.current_power_state_index) { 261 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 262 break; 263 } else { 264 rdev->pm.requested_power_state_index = i; 265 break; 266 } 267 } 268 } else 269 rdev->pm.requested_power_state_index = 270 rdev->pm.current_power_state_index + 1; 271 } 272 break; 273 case DYNPM_ACTION_DEFAULT: 274 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; 275 rdev->pm.dynpm_can_upclock = false; 276 break; 277 case DYNPM_ACTION_NONE: 278 default: 279 DRM_ERROR("Requested mode for not defined action\n"); 280 return; 281 } 282 /* only one clock mode per power state */ 283 rdev->pm.requested_clock_mode_index = 0; 284 285 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n", 286 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 287 clock_info[rdev->pm.requested_clock_mode_index].sclk, 288 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 289 clock_info[rdev->pm.requested_clock_mode_index].mclk, 290 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 291 pcie_lanes); 292 } 293 294 /** 295 * r100_pm_init_profile - Initialize power profiles callback. 296 * 297 * @rdev: radeon_device pointer 298 * 299 * Initialize the power states used in profile mode 300 * (r1xx-r3xx). 301 * Used for profile mode only. 302 */ 303 void r100_pm_init_profile(struct radeon_device *rdev) 304 { 305 /* default */ 306 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 307 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 308 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 309 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 310 /* low sh */ 311 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0; 312 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0; 313 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 314 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 315 /* mid sh */ 316 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0; 317 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0; 318 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 319 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 320 /* high sh */ 321 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0; 322 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 323 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 324 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 325 /* low mh */ 326 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0; 327 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 328 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 329 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 330 /* mid mh */ 331 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0; 332 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 333 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 334 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 335 /* high mh */ 336 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0; 337 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 338 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 339 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 340 } 341 342 /** 343 * r100_pm_misc - set additional pm hw parameters callback. 344 * 345 * @rdev: radeon_device pointer 346 * 347 * Set non-clock parameters associated with a power state 348 * (voltage, pcie lanes, etc.) (r1xx-r4xx). 349 */ 350 void r100_pm_misc(struct radeon_device *rdev) 351 { 352 int requested_index = rdev->pm.requested_power_state_index; 353 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index]; 354 struct radeon_voltage *voltage = &ps->clock_info[0].voltage; 355 u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl; 356 357 if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) { 358 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) { 359 tmp = RREG32(voltage->gpio.reg); 360 if (voltage->active_high) 361 tmp |= voltage->gpio.mask; 362 else 363 tmp &= ~(voltage->gpio.mask); 364 WREG32(voltage->gpio.reg, tmp); 365 if (voltage->delay) 366 udelay(voltage->delay); 367 } else { 368 tmp = RREG32(voltage->gpio.reg); 369 if (voltage->active_high) 370 tmp &= ~voltage->gpio.mask; 371 else 372 tmp |= voltage->gpio.mask; 373 WREG32(voltage->gpio.reg, tmp); 374 if (voltage->delay) 375 udelay(voltage->delay); 376 } 377 } 378 379 sclk_cntl = RREG32_PLL(SCLK_CNTL); 380 sclk_cntl2 = RREG32_PLL(SCLK_CNTL2); 381 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3); 382 sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL); 383 sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3); 384 if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) { 385 sclk_more_cntl |= REDUCED_SPEED_SCLK_EN; 386 if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE) 387 sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE; 388 else 389 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE; 390 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2) 391 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0); 392 else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4) 393 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2); 394 } else 395 sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN; 396 397 if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) { 398 sclk_more_cntl |= IO_CG_VOLTAGE_DROP; 399 if (voltage->delay) { 400 sclk_more_cntl |= VOLTAGE_DROP_SYNC; 401 switch (voltage->delay) { 402 case 33: 403 sclk_more_cntl |= VOLTAGE_DELAY_SEL(0); 404 break; 405 case 66: 406 sclk_more_cntl |= VOLTAGE_DELAY_SEL(1); 407 break; 408 case 99: 409 sclk_more_cntl |= VOLTAGE_DELAY_SEL(2); 410 break; 411 case 132: 412 sclk_more_cntl |= VOLTAGE_DELAY_SEL(3); 413 break; 414 } 415 } else 416 sclk_more_cntl &= ~VOLTAGE_DROP_SYNC; 417 } else 418 sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP; 419 420 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN) 421 sclk_cntl &= ~FORCE_HDP; 422 else 423 sclk_cntl |= FORCE_HDP; 424 425 WREG32_PLL(SCLK_CNTL, sclk_cntl); 426 WREG32_PLL(SCLK_CNTL2, sclk_cntl2); 427 WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl); 428 429 /* set pcie lanes */ 430 if ((rdev->flags & RADEON_IS_PCIE) && 431 !(rdev->flags & RADEON_IS_IGP) && 432 rdev->asic->pm.set_pcie_lanes && 433 (ps->pcie_lanes != 434 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) { 435 radeon_set_pcie_lanes(rdev, 436 ps->pcie_lanes); 437 DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes); 438 } 439 } 440 441 /** 442 * r100_pm_prepare - pre-power state change callback. 443 * 444 * @rdev: radeon_device pointer 445 * 446 * Prepare for a power state change (r1xx-r4xx). 447 */ 448 void r100_pm_prepare(struct radeon_device *rdev) 449 { 450 struct drm_device *ddev = rdev->ddev; 451 struct drm_crtc *crtc; 452 struct radeon_crtc *radeon_crtc; 453 u32 tmp; 454 455 /* disable any active CRTCs */ 456 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { 457 radeon_crtc = to_radeon_crtc(crtc); 458 if (radeon_crtc->enabled) { 459 if (radeon_crtc->crtc_id) { 460 tmp = RREG32(RADEON_CRTC2_GEN_CNTL); 461 tmp |= RADEON_CRTC2_DISP_REQ_EN_B; 462 WREG32(RADEON_CRTC2_GEN_CNTL, tmp); 463 } else { 464 tmp = RREG32(RADEON_CRTC_GEN_CNTL); 465 tmp |= RADEON_CRTC_DISP_REQ_EN_B; 466 WREG32(RADEON_CRTC_GEN_CNTL, tmp); 467 } 468 } 469 } 470 } 471 472 /** 473 * r100_pm_finish - post-power state change callback. 474 * 475 * @rdev: radeon_device pointer 476 * 477 * Clean up after a power state change (r1xx-r4xx). 478 */ 479 void r100_pm_finish(struct radeon_device *rdev) 480 { 481 struct drm_device *ddev = rdev->ddev; 482 struct drm_crtc *crtc; 483 struct radeon_crtc *radeon_crtc; 484 u32 tmp; 485 486 /* enable any active CRTCs */ 487 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { 488 radeon_crtc = to_radeon_crtc(crtc); 489 if (radeon_crtc->enabled) { 490 if (radeon_crtc->crtc_id) { 491 tmp = RREG32(RADEON_CRTC2_GEN_CNTL); 492 tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B; 493 WREG32(RADEON_CRTC2_GEN_CNTL, tmp); 494 } else { 495 tmp = RREG32(RADEON_CRTC_GEN_CNTL); 496 tmp &= ~RADEON_CRTC_DISP_REQ_EN_B; 497 WREG32(RADEON_CRTC_GEN_CNTL, tmp); 498 } 499 } 500 } 501 } 502 503 /** 504 * r100_gui_idle - gui idle callback. 505 * 506 * @rdev: radeon_device pointer 507 * 508 * Check of the GUI (2D/3D engines) are idle (r1xx-r5xx). 509 * Returns true if idle, false if not. 510 */ 511 bool r100_gui_idle(struct radeon_device *rdev) 512 { 513 if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE) 514 return false; 515 else 516 return true; 517 } 518 519 /* hpd for digital panel detect/disconnect */ 520 /** 521 * r100_hpd_sense - hpd sense callback. 522 * 523 * @rdev: radeon_device pointer 524 * @hpd: hpd (hotplug detect) pin 525 * 526 * Checks if a digital monitor is connected (r1xx-r4xx). 527 * Returns true if connected, false if not connected. 528 */ 529 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) 530 { 531 bool connected = false; 532 533 switch (hpd) { 534 case RADEON_HPD_1: 535 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE) 536 connected = true; 537 break; 538 case RADEON_HPD_2: 539 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE) 540 connected = true; 541 break; 542 default: 543 break; 544 } 545 return connected; 546 } 547 548 /** 549 * r100_hpd_set_polarity - hpd set polarity callback. 550 * 551 * @rdev: radeon_device pointer 552 * @hpd: hpd (hotplug detect) pin 553 * 554 * Set the polarity of the hpd pin (r1xx-r4xx). 555 */ 556 void r100_hpd_set_polarity(struct radeon_device *rdev, 557 enum radeon_hpd_id hpd) 558 { 559 u32 tmp; 560 bool connected = r100_hpd_sense(rdev, hpd); 561 562 switch (hpd) { 563 case RADEON_HPD_1: 564 tmp = RREG32(RADEON_FP_GEN_CNTL); 565 if (connected) 566 tmp &= ~RADEON_FP_DETECT_INT_POL; 567 else 568 tmp |= RADEON_FP_DETECT_INT_POL; 569 WREG32(RADEON_FP_GEN_CNTL, tmp); 570 break; 571 case RADEON_HPD_2: 572 tmp = RREG32(RADEON_FP2_GEN_CNTL); 573 if (connected) 574 tmp &= ~RADEON_FP2_DETECT_INT_POL; 575 else 576 tmp |= RADEON_FP2_DETECT_INT_POL; 577 WREG32(RADEON_FP2_GEN_CNTL, tmp); 578 break; 579 default: 580 break; 581 } 582 } 583 584 /** 585 * r100_hpd_init - hpd setup callback. 586 * 587 * @rdev: radeon_device pointer 588 * 589 * Setup the hpd pins used by the card (r1xx-r4xx). 590 * Set the polarity, and enable the hpd interrupts. 591 */ 592 void r100_hpd_init(struct radeon_device *rdev) 593 { 594 struct drm_device *dev = rdev->ddev; 595 struct drm_connector *connector; 596 unsigned enable = 0; 597 598 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 599 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 600 enable |= 1 << radeon_connector->hpd.hpd; 601 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); 602 } 603 radeon_irq_kms_enable_hpd(rdev, enable); 604 } 605 606 /** 607 * r100_hpd_fini - hpd tear down callback. 608 * 609 * @rdev: radeon_device pointer 610 * 611 * Tear down the hpd pins used by the card (r1xx-r4xx). 612 * Disable the hpd interrupts. 613 */ 614 void r100_hpd_fini(struct radeon_device *rdev) 615 { 616 struct drm_device *dev = rdev->ddev; 617 struct drm_connector *connector; 618 unsigned disable = 0; 619 620 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 621 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 622 disable |= 1 << radeon_connector->hpd.hpd; 623 } 624 radeon_irq_kms_disable_hpd(rdev, disable); 625 } 626 627 /* 628 * PCI GART 629 */ 630 void r100_pci_gart_tlb_flush(struct radeon_device *rdev) 631 { 632 /* TODO: can we do somethings here ? */ 633 /* It seems hw only cache one entry so we should discard this 634 * entry otherwise if first GPU GART read hit this entry it 635 * could end up in wrong address. */ 636 } 637 638 int r100_pci_gart_init(struct radeon_device *rdev) 639 { 640 int r; 641 642 if (rdev->gart.ptr) { 643 WARN(1, "R100 PCI GART already initialized\n"); 644 return 0; 645 } 646 /* Initialize common gart structure */ 647 r = radeon_gart_init(rdev); 648 if (r) 649 return r; 650 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; 651 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush; 652 rdev->asic->gart.get_page_entry = &r100_pci_gart_get_page_entry; 653 rdev->asic->gart.set_page = &r100_pci_gart_set_page; 654 return radeon_gart_table_ram_alloc(rdev); 655 } 656 657 int r100_pci_gart_enable(struct radeon_device *rdev) 658 { 659 uint32_t tmp; 660 661 /* discard memory request outside of configured range */ 662 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS; 663 WREG32(RADEON_AIC_CNTL, tmp); 664 /* set address range for PCI address translate */ 665 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start); 666 WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end); 667 /* set PCI GART page-table base address */ 668 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr); 669 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN; 670 WREG32(RADEON_AIC_CNTL, tmp); 671 r100_pci_gart_tlb_flush(rdev); 672 DRM_INFO("PCI GART of %uM enabled (table at 0x%016llX).\n", 673 (unsigned)(rdev->mc.gtt_size >> 20), 674 (unsigned long long)rdev->gart.table_addr); 675 rdev->gart.ready = true; 676 return 0; 677 } 678 679 void r100_pci_gart_disable(struct radeon_device *rdev) 680 { 681 uint32_t tmp; 682 683 /* discard memory request outside of configured range */ 684 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS; 685 WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN); 686 WREG32(RADEON_AIC_LO_ADDR, 0); 687 WREG32(RADEON_AIC_HI_ADDR, 0); 688 } 689 690 uint64_t r100_pci_gart_get_page_entry(uint64_t addr, uint32_t flags) 691 { 692 return addr; 693 } 694 695 void r100_pci_gart_set_page(struct radeon_device *rdev, unsigned i, 696 uint64_t entry) 697 { 698 u32 *gtt = rdev->gart.ptr; 699 gtt[i] = cpu_to_le32(lower_32_bits(entry)); 700 } 701 702 void r100_pci_gart_fini(struct radeon_device *rdev) 703 { 704 radeon_gart_fini(rdev); 705 r100_pci_gart_disable(rdev); 706 radeon_gart_table_ram_free(rdev); 707 } 708 709 int r100_irq_set(struct radeon_device *rdev) 710 { 711 uint32_t tmp = 0; 712 713 if (!rdev->irq.installed) { 714 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); 715 WREG32(R_000040_GEN_INT_CNTL, 0); 716 return -EINVAL; 717 } 718 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { 719 tmp |= RADEON_SW_INT_ENABLE; 720 } 721 if (rdev->irq.crtc_vblank_int[0] || 722 atomic_read(&rdev->irq.pflip[0])) { 723 tmp |= RADEON_CRTC_VBLANK_MASK; 724 } 725 if (rdev->irq.crtc_vblank_int[1] || 726 atomic_read(&rdev->irq.pflip[1])) { 727 tmp |= RADEON_CRTC2_VBLANK_MASK; 728 } 729 if (rdev->irq.hpd[0]) { 730 tmp |= RADEON_FP_DETECT_MASK; 731 } 732 if (rdev->irq.hpd[1]) { 733 tmp |= RADEON_FP2_DETECT_MASK; 734 } 735 WREG32(RADEON_GEN_INT_CNTL, tmp); 736 737 /* read back to post the write */ 738 RREG32(RADEON_GEN_INT_CNTL); 739 740 return 0; 741 } 742 743 void r100_irq_disable(struct radeon_device *rdev) 744 { 745 u32 tmp; 746 747 WREG32(R_000040_GEN_INT_CNTL, 0); 748 /* Wait and acknowledge irq */ 749 mdelay(1); 750 tmp = RREG32(R_000044_GEN_INT_STATUS); 751 WREG32(R_000044_GEN_INT_STATUS, tmp); 752 } 753 754 static uint32_t r100_irq_ack(struct radeon_device *rdev) 755 { 756 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS); 757 uint32_t irq_mask = RADEON_SW_INT_TEST | 758 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT | 759 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT; 760 761 if (irqs) { 762 WREG32(RADEON_GEN_INT_STATUS, irqs); 763 } 764 return irqs & irq_mask; 765 } 766 767 int r100_irq_process(struct radeon_device *rdev) 768 { 769 uint32_t status, msi_rearm; 770 bool queue_hotplug = false; 771 772 status = r100_irq_ack(rdev); 773 if (!status) { 774 return IRQ_NONE; 775 } 776 if (rdev->shutdown) { 777 return IRQ_NONE; 778 } 779 while (status) { 780 /* SW interrupt */ 781 if (status & RADEON_SW_INT_TEST) { 782 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); 783 } 784 /* Vertical blank interrupts */ 785 if (status & RADEON_CRTC_VBLANK_STAT) { 786 if (rdev->irq.crtc_vblank_int[0]) { 787 drm_handle_vblank(rdev->ddev, 0); 788 #ifdef __NetBSD__ 789 spin_lock(&rdev->irq.vblank_lock); 790 rdev->pm.vblank_sync = true; 791 DRM_SPIN_WAKEUP_ONE(&rdev->irq.vblank_queue, &rdev->irq.vblank_lock); 792 spin_unlock(&rdev->irq.vblank_lock); 793 #else 794 rdev->pm.vblank_sync = true; 795 wake_up(&rdev->irq.vblank_queue); 796 #endif 797 } 798 if (atomic_read(&rdev->irq.pflip[0])) 799 radeon_crtc_handle_vblank(rdev, 0); 800 } 801 if (status & RADEON_CRTC2_VBLANK_STAT) { 802 if (rdev->irq.crtc_vblank_int[1]) { 803 drm_handle_vblank(rdev->ddev, 1); 804 #ifdef __NetBSD__ 805 spin_lock(&rdev->irq.vblank_lock); 806 rdev->pm.vblank_sync = true; 807 DRM_SPIN_WAKEUP_ONE(&rdev->irq.vblank_queue, &rdev->irq.vblank_lock); 808 spin_unlock(&rdev->irq.vblank_lock); 809 #else 810 rdev->pm.vblank_sync = true; 811 wake_up(&rdev->irq.vblank_queue); 812 #endif 813 } 814 if (atomic_read(&rdev->irq.pflip[1])) 815 radeon_crtc_handle_vblank(rdev, 1); 816 } 817 if (status & RADEON_FP_DETECT_STAT) { 818 queue_hotplug = true; 819 DRM_DEBUG("HPD1\n"); 820 } 821 if (status & RADEON_FP2_DETECT_STAT) { 822 queue_hotplug = true; 823 DRM_DEBUG("HPD2\n"); 824 } 825 status = r100_irq_ack(rdev); 826 } 827 if (queue_hotplug) 828 schedule_delayed_work(&rdev->hotplug_work, 0); 829 if (rdev->msi_enabled) { 830 switch (rdev->family) { 831 case CHIP_RS400: 832 case CHIP_RS480: 833 msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM; 834 WREG32(RADEON_AIC_CNTL, msi_rearm); 835 WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM); 836 break; 837 default: 838 WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN); 839 break; 840 } 841 } 842 return IRQ_HANDLED; 843 } 844 845 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc) 846 { 847 if (crtc == 0) 848 return RREG32(RADEON_CRTC_CRNT_FRAME); 849 else 850 return RREG32(RADEON_CRTC2_CRNT_FRAME); 851 } 852 853 /** 854 * r100_ring_hdp_flush - flush Host Data Path via the ring buffer 855 * rdev: radeon device structure 856 * ring: ring buffer struct for emitting packets 857 */ 858 static void r100_ring_hdp_flush(struct radeon_device *rdev, struct radeon_ring *ring) 859 { 860 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); 861 radeon_ring_write(ring, rdev->config.r100.hdp_cntl | 862 RADEON_HDP_READ_BUFFER_INVALIDATE); 863 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); 864 radeon_ring_write(ring, rdev->config.r100.hdp_cntl); 865 } 866 867 /* Who ever call radeon_fence_emit should call ring_lock and ask 868 * for enough space (today caller are ib schedule and buffer move) */ 869 void r100_fence_ring_emit(struct radeon_device *rdev, 870 struct radeon_fence *fence) 871 { 872 struct radeon_ring *ring = &rdev->ring[fence->ring]; 873 874 /* We have to make sure that caches are flushed before 875 * CPU might read something from VRAM. */ 876 radeon_ring_write(ring, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); 877 radeon_ring_write(ring, RADEON_RB3D_DC_FLUSH_ALL); 878 radeon_ring_write(ring, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); 879 radeon_ring_write(ring, RADEON_RB3D_ZC_FLUSH_ALL); 880 /* Wait until IDLE & CLEAN */ 881 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); 882 radeon_ring_write(ring, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); 883 r100_ring_hdp_flush(rdev, ring); 884 /* Emit fence sequence & fire IRQ */ 885 radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0)); 886 radeon_ring_write(ring, fence->seq); 887 radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0)); 888 radeon_ring_write(ring, RADEON_SW_INT_FIRE); 889 } 890 891 bool r100_semaphore_ring_emit(struct radeon_device *rdev, 892 struct radeon_ring *ring, 893 struct radeon_semaphore *semaphore, 894 bool emit_wait) 895 { 896 /* Unused on older asics, since we don't have semaphores or multiple rings */ 897 BUG(); 898 return false; 899 } 900 901 struct radeon_fence *r100_copy_blit(struct radeon_device *rdev, 902 uint64_t src_offset, 903 uint64_t dst_offset, 904 unsigned num_gpu_pages, 905 struct reservation_object *resv) 906 { 907 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 908 struct radeon_fence *fence; 909 uint32_t cur_pages; 910 uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE; 911 uint32_t pitch; 912 uint32_t stride_pixels; 913 unsigned ndw; 914 int num_loops; 915 int r = 0; 916 917 /* radeon limited to 16k stride */ 918 stride_bytes &= 0x3fff; 919 /* radeon pitch is /64 */ 920 pitch = stride_bytes / 64; 921 stride_pixels = stride_bytes / 4; 922 num_loops = DIV_ROUND_UP(num_gpu_pages, 8191); 923 924 /* Ask for enough room for blit + flush + fence */ 925 ndw = 64 + (10 * num_loops); 926 r = radeon_ring_lock(rdev, ring, ndw); 927 if (r) { 928 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw); 929 return ERR_PTR(-EINVAL); 930 } 931 while (num_gpu_pages > 0) { 932 cur_pages = num_gpu_pages; 933 if (cur_pages > 8191) { 934 cur_pages = 8191; 935 } 936 num_gpu_pages -= cur_pages; 937 938 /* pages are in Y direction - height 939 page width in X direction - width */ 940 radeon_ring_write(ring, PACKET3(PACKET3_BITBLT_MULTI, 8)); 941 radeon_ring_write(ring, 942 RADEON_GMC_SRC_PITCH_OFFSET_CNTL | 943 RADEON_GMC_DST_PITCH_OFFSET_CNTL | 944 RADEON_GMC_SRC_CLIPPING | 945 RADEON_GMC_DST_CLIPPING | 946 RADEON_GMC_BRUSH_NONE | 947 (RADEON_COLOR_FORMAT_ARGB8888 << 8) | 948 RADEON_GMC_SRC_DATATYPE_COLOR | 949 RADEON_ROP3_S | 950 RADEON_DP_SRC_SOURCE_MEMORY | 951 RADEON_GMC_CLR_CMP_CNTL_DIS | 952 RADEON_GMC_WR_MSK_DIS); 953 radeon_ring_write(ring, (pitch << 22) | (src_offset >> 10)); 954 radeon_ring_write(ring, (pitch << 22) | (dst_offset >> 10)); 955 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16)); 956 radeon_ring_write(ring, 0); 957 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16)); 958 radeon_ring_write(ring, num_gpu_pages); 959 radeon_ring_write(ring, num_gpu_pages); 960 radeon_ring_write(ring, cur_pages | (stride_pixels << 16)); 961 } 962 radeon_ring_write(ring, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0)); 963 radeon_ring_write(ring, RADEON_RB2D_DC_FLUSH_ALL); 964 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); 965 radeon_ring_write(ring, 966 RADEON_WAIT_2D_IDLECLEAN | 967 RADEON_WAIT_HOST_IDLECLEAN | 968 RADEON_WAIT_DMA_GUI_IDLE); 969 r = radeon_fence_emit(rdev, &fence, RADEON_RING_TYPE_GFX_INDEX); 970 if (r) { 971 radeon_ring_unlock_undo(rdev, ring); 972 return ERR_PTR(r); 973 } 974 radeon_ring_unlock_commit(rdev, ring, false); 975 return fence; 976 } 977 978 static int r100_cp_wait_for_idle(struct radeon_device *rdev) 979 { 980 unsigned i; 981 u32 tmp; 982 983 for (i = 0; i < rdev->usec_timeout; i++) { 984 tmp = RREG32(R_000E40_RBBM_STATUS); 985 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) { 986 return 0; 987 } 988 udelay(1); 989 } 990 return -1; 991 } 992 993 void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring) 994 { 995 int r; 996 997 r = radeon_ring_lock(rdev, ring, 2); 998 if (r) { 999 return; 1000 } 1001 radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0)); 1002 radeon_ring_write(ring, 1003 RADEON_ISYNC_ANY2D_IDLE3D | 1004 RADEON_ISYNC_ANY3D_IDLE2D | 1005 RADEON_ISYNC_WAIT_IDLEGUI | 1006 RADEON_ISYNC_CPSCRATCH_IDLEGUI); 1007 radeon_ring_unlock_commit(rdev, ring, false); 1008 } 1009 1010 1011 /* Load the microcode for the CP */ 1012 static int r100_cp_init_microcode(struct radeon_device *rdev) 1013 { 1014 const char *fw_name = NULL; 1015 int err; 1016 1017 DRM_DEBUG_KMS("\n"); 1018 1019 if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) || 1020 (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) || 1021 (rdev->family == CHIP_RS200)) { 1022 DRM_INFO("Loading R100 Microcode\n"); 1023 fw_name = FIRMWARE_R100; 1024 } else if ((rdev->family == CHIP_R200) || 1025 (rdev->family == CHIP_RV250) || 1026 (rdev->family == CHIP_RV280) || 1027 (rdev->family == CHIP_RS300)) { 1028 DRM_INFO("Loading R200 Microcode\n"); 1029 fw_name = FIRMWARE_R200; 1030 } else if ((rdev->family == CHIP_R300) || 1031 (rdev->family == CHIP_R350) || 1032 (rdev->family == CHIP_RV350) || 1033 (rdev->family == CHIP_RV380) || 1034 (rdev->family == CHIP_RS400) || 1035 (rdev->family == CHIP_RS480)) { 1036 DRM_INFO("Loading R300 Microcode\n"); 1037 fw_name = FIRMWARE_R300; 1038 } else if ((rdev->family == CHIP_R420) || 1039 (rdev->family == CHIP_R423) || 1040 (rdev->family == CHIP_RV410)) { 1041 DRM_INFO("Loading R400 Microcode\n"); 1042 fw_name = FIRMWARE_R420; 1043 } else if ((rdev->family == CHIP_RS690) || 1044 (rdev->family == CHIP_RS740)) { 1045 DRM_INFO("Loading RS690/RS740 Microcode\n"); 1046 fw_name = FIRMWARE_RS690; 1047 } else if (rdev->family == CHIP_RS600) { 1048 DRM_INFO("Loading RS600 Microcode\n"); 1049 fw_name = FIRMWARE_RS600; 1050 } else if ((rdev->family == CHIP_RV515) || 1051 (rdev->family == CHIP_R520) || 1052 (rdev->family == CHIP_RV530) || 1053 (rdev->family == CHIP_R580) || 1054 (rdev->family == CHIP_RV560) || 1055 (rdev->family == CHIP_RV570)) { 1056 DRM_INFO("Loading R500 Microcode\n"); 1057 fw_name = FIRMWARE_R520; 1058 } 1059 1060 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev); 1061 if (err) { 1062 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n", 1063 fw_name); 1064 } else if (rdev->me_fw->size % 8) { 1065 printk(KERN_ERR 1066 "radeon_cp: Bogus length %zu in firmware \"%s\"\n", 1067 rdev->me_fw->size, fw_name); 1068 err = -EINVAL; 1069 release_firmware(rdev->me_fw); 1070 rdev->me_fw = NULL; 1071 } 1072 return err; 1073 } 1074 1075 u32 r100_gfx_get_rptr(struct radeon_device *rdev, 1076 struct radeon_ring *ring) 1077 { 1078 u32 rptr; 1079 1080 if (rdev->wb.enabled) 1081 rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]); 1082 else 1083 rptr = RREG32(RADEON_CP_RB_RPTR); 1084 1085 return rptr; 1086 } 1087 1088 u32 r100_gfx_get_wptr(struct radeon_device *rdev, 1089 struct radeon_ring *ring) 1090 { 1091 u32 wptr; 1092 1093 wptr = RREG32(RADEON_CP_RB_WPTR); 1094 1095 return wptr; 1096 } 1097 1098 void r100_gfx_set_wptr(struct radeon_device *rdev, 1099 struct radeon_ring *ring) 1100 { 1101 WREG32(RADEON_CP_RB_WPTR, ring->wptr); 1102 (void)RREG32(RADEON_CP_RB_WPTR); 1103 } 1104 1105 static void r100_cp_load_microcode(struct radeon_device *rdev) 1106 { 1107 const __be32 *fw_data; 1108 int i, size; 1109 1110 if (r100_gui_wait_for_idle(rdev)) { 1111 printk(KERN_WARNING "Failed to wait GUI idle while " 1112 "programming pipes. Bad things might happen.\n"); 1113 } 1114 1115 if (rdev->me_fw) { 1116 size = rdev->me_fw->size / 4; 1117 fw_data = (const __be32 *)rdev->me_fw->data; 1118 WREG32(RADEON_CP_ME_RAM_ADDR, 0); 1119 for (i = 0; i < size; i += 2) { 1120 WREG32(RADEON_CP_ME_RAM_DATAH, 1121 be32_to_cpup(&fw_data[i])); 1122 WREG32(RADEON_CP_ME_RAM_DATAL, 1123 be32_to_cpup(&fw_data[i + 1])); 1124 } 1125 } 1126 } 1127 1128 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size) 1129 { 1130 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 1131 unsigned rb_bufsz; 1132 unsigned rb_blksz; 1133 unsigned max_fetch; 1134 unsigned pre_write_timer; 1135 unsigned pre_write_limit; 1136 unsigned indirect2_start; 1137 unsigned indirect1_start; 1138 uint32_t tmp; 1139 int r; 1140 1141 if (r100_debugfs_cp_init(rdev)) { 1142 DRM_ERROR("Failed to register debugfs file for CP !\n"); 1143 } 1144 if (!rdev->me_fw) { 1145 r = r100_cp_init_microcode(rdev); 1146 if (r) { 1147 DRM_ERROR("Failed to load firmware!\n"); 1148 return r; 1149 } 1150 } 1151 1152 /* Align ring size */ 1153 rb_bufsz = order_base_2(ring_size / 8); 1154 ring_size = (1 << (rb_bufsz + 1)) * 4; 1155 r100_cp_load_microcode(rdev); 1156 r = radeon_ring_init(rdev, ring, ring_size, RADEON_WB_CP_RPTR_OFFSET, 1157 RADEON_CP_PACKET2); 1158 if (r) { 1159 return r; 1160 } 1161 /* Each time the cp read 1024 bytes (16 dword/quadword) update 1162 * the rptr copy in system ram */ 1163 rb_blksz = 9; 1164 /* cp will read 128bytes at a time (4 dwords) */ 1165 max_fetch = 1; 1166 ring->align_mask = 16 - 1; 1167 /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */ 1168 pre_write_timer = 64; 1169 /* Force CP_RB_WPTR write if written more than one time before the 1170 * delay expire 1171 */ 1172 pre_write_limit = 0; 1173 /* Setup the cp cache like this (cache size is 96 dwords) : 1174 * RING 0 to 15 1175 * INDIRECT1 16 to 79 1176 * INDIRECT2 80 to 95 1177 * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords)) 1178 * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords)) 1179 * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords)) 1180 * Idea being that most of the gpu cmd will be through indirect1 buffer 1181 * so it gets the bigger cache. 1182 */ 1183 indirect2_start = 80; 1184 indirect1_start = 16; 1185 /* cp setup */ 1186 WREG32(0x718, pre_write_timer | (pre_write_limit << 28)); 1187 tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) | 1188 REG_SET(RADEON_RB_BLKSZ, rb_blksz) | 1189 REG_SET(RADEON_MAX_FETCH, max_fetch)); 1190 #ifdef __BIG_ENDIAN 1191 tmp |= RADEON_BUF_SWAP_32BIT; 1192 #endif 1193 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE); 1194 1195 /* Set ring address */ 1196 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)ring->gpu_addr); 1197 WREG32(RADEON_CP_RB_BASE, ring->gpu_addr); 1198 /* Force read & write ptr to 0 */ 1199 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE); 1200 WREG32(RADEON_CP_RB_RPTR_WR, 0); 1201 ring->wptr = 0; 1202 WREG32(RADEON_CP_RB_WPTR, ring->wptr); 1203 1204 /* set the wb address whether it's enabled or not */ 1205 WREG32(R_00070C_CP_RB_RPTR_ADDR, 1206 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2)); 1207 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET); 1208 1209 if (rdev->wb.enabled) 1210 WREG32(R_000770_SCRATCH_UMSK, 0xff); 1211 else { 1212 tmp |= RADEON_RB_NO_UPDATE; 1213 WREG32(R_000770_SCRATCH_UMSK, 0); 1214 } 1215 1216 WREG32(RADEON_CP_RB_CNTL, tmp); 1217 udelay(10); 1218 /* Set cp mode to bus mastering & enable cp*/ 1219 WREG32(RADEON_CP_CSQ_MODE, 1220 REG_SET(RADEON_INDIRECT2_START, indirect2_start) | 1221 REG_SET(RADEON_INDIRECT1_START, indirect1_start)); 1222 WREG32(RADEON_CP_RB_WPTR_DELAY, 0); 1223 WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D); 1224 WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM); 1225 1226 /* at this point everything should be setup correctly to enable master */ 1227 pci_set_master(rdev->pdev); 1228 1229 radeon_ring_start(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); 1230 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring); 1231 if (r) { 1232 DRM_ERROR("radeon: cp isn't working (%d).\n", r); 1233 return r; 1234 } 1235 ring->ready = true; 1236 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); 1237 1238 if (!ring->rptr_save_reg /* not resuming from suspend */ 1239 && radeon_ring_supports_scratch_reg(rdev, ring)) { 1240 r = radeon_scratch_get(rdev, &ring->rptr_save_reg); 1241 if (r) { 1242 DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r); 1243 ring->rptr_save_reg = 0; 1244 } 1245 } 1246 return 0; 1247 } 1248 1249 void r100_cp_fini(struct radeon_device *rdev) 1250 { 1251 if (r100_cp_wait_for_idle(rdev)) { 1252 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n"); 1253 } 1254 /* Disable ring */ 1255 r100_cp_disable(rdev); 1256 radeon_scratch_free(rdev, rdev->ring[RADEON_RING_TYPE_GFX_INDEX].rptr_save_reg); 1257 radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); 1258 DRM_INFO("radeon: cp finalized\n"); 1259 } 1260 1261 void r100_cp_disable(struct radeon_device *rdev) 1262 { 1263 /* Disable ring */ 1264 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 1265 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; 1266 WREG32(RADEON_CP_CSQ_MODE, 0); 1267 WREG32(RADEON_CP_CSQ_CNTL, 0); 1268 WREG32(R_000770_SCRATCH_UMSK, 0); 1269 if (r100_gui_wait_for_idle(rdev)) { 1270 printk(KERN_WARNING "Failed to wait GUI idle while " 1271 "programming pipes. Bad things might happen.\n"); 1272 } 1273 } 1274 1275 /* 1276 * CS functions 1277 */ 1278 int r100_reloc_pitch_offset(struct radeon_cs_parser *p, 1279 struct radeon_cs_packet *pkt, 1280 unsigned idx, 1281 unsigned reg) 1282 { 1283 int r; 1284 u32 tile_flags = 0; 1285 u32 tmp; 1286 struct radeon_bo_list *reloc; 1287 u32 value; 1288 1289 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1290 if (r) { 1291 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1292 idx, reg); 1293 radeon_cs_dump_packet(p, pkt); 1294 return r; 1295 } 1296 1297 value = radeon_get_ib_value(p, idx); 1298 tmp = value & 0x003fffff; 1299 tmp += (((u32)reloc->gpu_offset) >> 10); 1300 1301 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 1302 if (reloc->tiling_flags & RADEON_TILING_MACRO) 1303 tile_flags |= RADEON_DST_TILE_MACRO; 1304 if (reloc->tiling_flags & RADEON_TILING_MICRO) { 1305 if (reg == RADEON_SRC_PITCH_OFFSET) { 1306 DRM_ERROR("Cannot src blit from microtiled surface\n"); 1307 radeon_cs_dump_packet(p, pkt); 1308 return -EINVAL; 1309 } 1310 tile_flags |= RADEON_DST_TILE_MICRO; 1311 } 1312 1313 tmp |= tile_flags; 1314 p->ib.ptr[idx] = (value & 0x3fc00000) | tmp; 1315 } else 1316 p->ib.ptr[idx] = (value & 0xffc00000) | tmp; 1317 return 0; 1318 } 1319 1320 int r100_packet3_load_vbpntr(struct radeon_cs_parser *p, 1321 struct radeon_cs_packet *pkt, 1322 int idx) 1323 { 1324 unsigned c, i; 1325 struct radeon_bo_list *reloc; 1326 struct r100_cs_track *track; 1327 int r = 0; 1328 volatile uint32_t *ib; 1329 u32 idx_value; 1330 1331 ib = p->ib.ptr; 1332 track = (struct r100_cs_track *)p->track; 1333 c = radeon_get_ib_value(p, idx++) & 0x1F; 1334 if (c > 16) { 1335 DRM_ERROR("Only 16 vertex buffers are allowed %d\n", 1336 pkt->opcode); 1337 radeon_cs_dump_packet(p, pkt); 1338 return -EINVAL; 1339 } 1340 track->num_arrays = c; 1341 for (i = 0; i < (c - 1); i+=2, idx+=3) { 1342 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1343 if (r) { 1344 DRM_ERROR("No reloc for packet3 %d\n", 1345 pkt->opcode); 1346 radeon_cs_dump_packet(p, pkt); 1347 return r; 1348 } 1349 idx_value = radeon_get_ib_value(p, idx); 1350 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset); 1351 1352 track->arrays[i + 0].esize = idx_value >> 8; 1353 track->arrays[i + 0].robj = reloc->robj; 1354 track->arrays[i + 0].esize &= 0x7F; 1355 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1356 if (r) { 1357 DRM_ERROR("No reloc for packet3 %d\n", 1358 pkt->opcode); 1359 radeon_cs_dump_packet(p, pkt); 1360 return r; 1361 } 1362 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->gpu_offset); 1363 track->arrays[i + 1].robj = reloc->robj; 1364 track->arrays[i + 1].esize = idx_value >> 24; 1365 track->arrays[i + 1].esize &= 0x7F; 1366 } 1367 if (c & 1) { 1368 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1369 if (r) { 1370 DRM_ERROR("No reloc for packet3 %d\n", 1371 pkt->opcode); 1372 radeon_cs_dump_packet(p, pkt); 1373 return r; 1374 } 1375 idx_value = radeon_get_ib_value(p, idx); 1376 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset); 1377 track->arrays[i + 0].robj = reloc->robj; 1378 track->arrays[i + 0].esize = idx_value >> 8; 1379 track->arrays[i + 0].esize &= 0x7F; 1380 } 1381 return r; 1382 } 1383 1384 int r100_cs_parse_packet0(struct radeon_cs_parser *p, 1385 struct radeon_cs_packet *pkt, 1386 const unsigned *auth, unsigned n, 1387 radeon_packet0_check_t check) 1388 { 1389 unsigned reg; 1390 unsigned i, j, m; 1391 unsigned idx; 1392 int r; 1393 1394 idx = pkt->idx + 1; 1395 reg = pkt->reg; 1396 /* Check that register fall into register range 1397 * determined by the number of entry (n) in the 1398 * safe register bitmap. 1399 */ 1400 if (pkt->one_reg_wr) { 1401 if ((reg >> 7) > n) { 1402 return -EINVAL; 1403 } 1404 } else { 1405 if (((reg + (pkt->count << 2)) >> 7) > n) { 1406 return -EINVAL; 1407 } 1408 } 1409 for (i = 0; i <= pkt->count; i++, idx++) { 1410 j = (reg >> 7); 1411 m = 1 << ((reg >> 2) & 31); 1412 if (auth[j] & m) { 1413 r = check(p, pkt, idx, reg); 1414 if (r) { 1415 return r; 1416 } 1417 } 1418 if (pkt->one_reg_wr) { 1419 if (!(auth[j] & m)) { 1420 break; 1421 } 1422 } else { 1423 reg += 4; 1424 } 1425 } 1426 return 0; 1427 } 1428 1429 /** 1430 * r100_cs_packet_next_vline() - parse userspace VLINE packet 1431 * @parser: parser structure holding parsing context. 1432 * 1433 * Userspace sends a special sequence for VLINE waits. 1434 * PACKET0 - VLINE_START_END + value 1435 * PACKET0 - WAIT_UNTIL +_value 1436 * RELOC (P3) - crtc_id in reloc. 1437 * 1438 * This function parses this and relocates the VLINE START END 1439 * and WAIT UNTIL packets to the correct crtc. 1440 * It also detects a switched off crtc and nulls out the 1441 * wait in that case. 1442 */ 1443 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p) 1444 { 1445 struct drm_crtc *crtc; 1446 struct radeon_crtc *radeon_crtc; 1447 struct radeon_cs_packet p3reloc, waitreloc; 1448 int crtc_id; 1449 int r; 1450 uint32_t header, h_idx, reg; 1451 volatile uint32_t *ib; 1452 1453 ib = p->ib.ptr; 1454 1455 /* parse the wait until */ 1456 r = radeon_cs_packet_parse(p, &waitreloc, p->idx); 1457 if (r) 1458 return r; 1459 1460 /* check its a wait until and only 1 count */ 1461 if (waitreloc.reg != RADEON_WAIT_UNTIL || 1462 waitreloc.count != 0) { 1463 DRM_ERROR("vline wait had illegal wait until segment\n"); 1464 return -EINVAL; 1465 } 1466 1467 if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) { 1468 DRM_ERROR("vline wait had illegal wait until\n"); 1469 return -EINVAL; 1470 } 1471 1472 /* jump over the NOP */ 1473 r = radeon_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2); 1474 if (r) 1475 return r; 1476 1477 h_idx = p->idx - 2; 1478 p->idx += waitreloc.count + 2; 1479 p->idx += p3reloc.count + 2; 1480 1481 header = radeon_get_ib_value(p, h_idx); 1482 crtc_id = radeon_get_ib_value(p, h_idx + 5); 1483 reg = R100_CP_PACKET0_GET_REG(header); 1484 crtc = drm_crtc_find(p->rdev->ddev, crtc_id); 1485 if (!crtc) { 1486 DRM_ERROR("cannot find crtc %d\n", crtc_id); 1487 return -ENOENT; 1488 } 1489 radeon_crtc = to_radeon_crtc(crtc); 1490 crtc_id = radeon_crtc->crtc_id; 1491 1492 if (!crtc->enabled) { 1493 /* if the CRTC isn't enabled - we need to nop out the wait until */ 1494 ib[h_idx + 2] = PACKET2(0); 1495 ib[h_idx + 3] = PACKET2(0); 1496 } else if (crtc_id == 1) { 1497 switch (reg) { 1498 case AVIVO_D1MODE_VLINE_START_END: 1499 header &= ~R300_CP_PACKET0_REG_MASK; 1500 header |= AVIVO_D2MODE_VLINE_START_END >> 2; 1501 break; 1502 case RADEON_CRTC_GUI_TRIG_VLINE: 1503 header &= ~R300_CP_PACKET0_REG_MASK; 1504 header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2; 1505 break; 1506 default: 1507 DRM_ERROR("unknown crtc reloc\n"); 1508 return -EINVAL; 1509 } 1510 ib[h_idx] = header; 1511 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1; 1512 } 1513 1514 return 0; 1515 } 1516 1517 static int r100_get_vtx_size(uint32_t vtx_fmt) 1518 { 1519 int vtx_size; 1520 vtx_size = 2; 1521 /* ordered according to bits in spec */ 1522 if (vtx_fmt & RADEON_SE_VTX_FMT_W0) 1523 vtx_size++; 1524 if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR) 1525 vtx_size += 3; 1526 if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA) 1527 vtx_size++; 1528 if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR) 1529 vtx_size++; 1530 if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC) 1531 vtx_size += 3; 1532 if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG) 1533 vtx_size++; 1534 if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC) 1535 vtx_size++; 1536 if (vtx_fmt & RADEON_SE_VTX_FMT_ST0) 1537 vtx_size += 2; 1538 if (vtx_fmt & RADEON_SE_VTX_FMT_ST1) 1539 vtx_size += 2; 1540 if (vtx_fmt & RADEON_SE_VTX_FMT_Q1) 1541 vtx_size++; 1542 if (vtx_fmt & RADEON_SE_VTX_FMT_ST2) 1543 vtx_size += 2; 1544 if (vtx_fmt & RADEON_SE_VTX_FMT_Q2) 1545 vtx_size++; 1546 if (vtx_fmt & RADEON_SE_VTX_FMT_ST3) 1547 vtx_size += 2; 1548 if (vtx_fmt & RADEON_SE_VTX_FMT_Q3) 1549 vtx_size++; 1550 if (vtx_fmt & RADEON_SE_VTX_FMT_Q0) 1551 vtx_size++; 1552 /* blend weight */ 1553 if (vtx_fmt & (0x7 << 15)) 1554 vtx_size += (vtx_fmt >> 15) & 0x7; 1555 if (vtx_fmt & RADEON_SE_VTX_FMT_N0) 1556 vtx_size += 3; 1557 if (vtx_fmt & RADEON_SE_VTX_FMT_XY1) 1558 vtx_size += 2; 1559 if (vtx_fmt & RADEON_SE_VTX_FMT_Z1) 1560 vtx_size++; 1561 if (vtx_fmt & RADEON_SE_VTX_FMT_W1) 1562 vtx_size++; 1563 if (vtx_fmt & RADEON_SE_VTX_FMT_N1) 1564 vtx_size++; 1565 if (vtx_fmt & RADEON_SE_VTX_FMT_Z) 1566 vtx_size++; 1567 return vtx_size; 1568 } 1569 1570 static int r100_packet0_check(struct radeon_cs_parser *p, 1571 struct radeon_cs_packet *pkt, 1572 unsigned idx, unsigned reg) 1573 { 1574 struct radeon_bo_list *reloc; 1575 struct r100_cs_track *track; 1576 volatile uint32_t *ib; 1577 uint32_t tmp; 1578 int r; 1579 int i, face; 1580 u32 tile_flags = 0; 1581 u32 idx_value; 1582 1583 ib = p->ib.ptr; 1584 track = (struct r100_cs_track *)p->track; 1585 1586 idx_value = radeon_get_ib_value(p, idx); 1587 1588 switch (reg) { 1589 case RADEON_CRTC_GUI_TRIG_VLINE: 1590 r = r100_cs_packet_parse_vline(p); 1591 if (r) { 1592 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1593 idx, reg); 1594 radeon_cs_dump_packet(p, pkt); 1595 return r; 1596 } 1597 break; 1598 /* FIXME: only allow PACKET3 blit? easier to check for out of 1599 * range access */ 1600 case RADEON_DST_PITCH_OFFSET: 1601 case RADEON_SRC_PITCH_OFFSET: 1602 r = r100_reloc_pitch_offset(p, pkt, idx, reg); 1603 if (r) 1604 return r; 1605 break; 1606 case RADEON_RB3D_DEPTHOFFSET: 1607 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1608 if (r) { 1609 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1610 idx, reg); 1611 radeon_cs_dump_packet(p, pkt); 1612 return r; 1613 } 1614 track->zb.robj = reloc->robj; 1615 track->zb.offset = idx_value; 1616 track->zb_dirty = true; 1617 ib[idx] = idx_value + ((u32)reloc->gpu_offset); 1618 break; 1619 case RADEON_RB3D_COLOROFFSET: 1620 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1621 if (r) { 1622 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1623 idx, reg); 1624 radeon_cs_dump_packet(p, pkt); 1625 return r; 1626 } 1627 track->cb[0].robj = reloc->robj; 1628 track->cb[0].offset = idx_value; 1629 track->cb_dirty = true; 1630 ib[idx] = idx_value + ((u32)reloc->gpu_offset); 1631 break; 1632 case RADEON_PP_TXOFFSET_0: 1633 case RADEON_PP_TXOFFSET_1: 1634 case RADEON_PP_TXOFFSET_2: 1635 i = (reg - RADEON_PP_TXOFFSET_0) / 24; 1636 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1637 if (r) { 1638 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1639 idx, reg); 1640 radeon_cs_dump_packet(p, pkt); 1641 return r; 1642 } 1643 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 1644 if (reloc->tiling_flags & RADEON_TILING_MACRO) 1645 tile_flags |= RADEON_TXO_MACRO_TILE; 1646 if (reloc->tiling_flags & RADEON_TILING_MICRO) 1647 tile_flags |= RADEON_TXO_MICRO_TILE_X2; 1648 1649 tmp = idx_value & ~(0x7 << 2); 1650 tmp |= tile_flags; 1651 ib[idx] = tmp + ((u32)reloc->gpu_offset); 1652 } else 1653 ib[idx] = idx_value + ((u32)reloc->gpu_offset); 1654 track->textures[i].robj = reloc->robj; 1655 track->tex_dirty = true; 1656 break; 1657 case RADEON_PP_CUBIC_OFFSET_T0_0: 1658 case RADEON_PP_CUBIC_OFFSET_T0_1: 1659 case RADEON_PP_CUBIC_OFFSET_T0_2: 1660 case RADEON_PP_CUBIC_OFFSET_T0_3: 1661 case RADEON_PP_CUBIC_OFFSET_T0_4: 1662 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4; 1663 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1664 if (r) { 1665 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1666 idx, reg); 1667 radeon_cs_dump_packet(p, pkt); 1668 return r; 1669 } 1670 track->textures[0].cube_info[i].offset = idx_value; 1671 ib[idx] = idx_value + ((u32)reloc->gpu_offset); 1672 track->textures[0].cube_info[i].robj = reloc->robj; 1673 track->tex_dirty = true; 1674 break; 1675 case RADEON_PP_CUBIC_OFFSET_T1_0: 1676 case RADEON_PP_CUBIC_OFFSET_T1_1: 1677 case RADEON_PP_CUBIC_OFFSET_T1_2: 1678 case RADEON_PP_CUBIC_OFFSET_T1_3: 1679 case RADEON_PP_CUBIC_OFFSET_T1_4: 1680 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4; 1681 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1682 if (r) { 1683 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1684 idx, reg); 1685 radeon_cs_dump_packet(p, pkt); 1686 return r; 1687 } 1688 track->textures[1].cube_info[i].offset = idx_value; 1689 ib[idx] = idx_value + ((u32)reloc->gpu_offset); 1690 track->textures[1].cube_info[i].robj = reloc->robj; 1691 track->tex_dirty = true; 1692 break; 1693 case RADEON_PP_CUBIC_OFFSET_T2_0: 1694 case RADEON_PP_CUBIC_OFFSET_T2_1: 1695 case RADEON_PP_CUBIC_OFFSET_T2_2: 1696 case RADEON_PP_CUBIC_OFFSET_T2_3: 1697 case RADEON_PP_CUBIC_OFFSET_T2_4: 1698 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4; 1699 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1700 if (r) { 1701 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1702 idx, reg); 1703 radeon_cs_dump_packet(p, pkt); 1704 return r; 1705 } 1706 track->textures[2].cube_info[i].offset = idx_value; 1707 ib[idx] = idx_value + ((u32)reloc->gpu_offset); 1708 track->textures[2].cube_info[i].robj = reloc->robj; 1709 track->tex_dirty = true; 1710 break; 1711 case RADEON_RE_WIDTH_HEIGHT: 1712 track->maxy = ((idx_value >> 16) & 0x7FF); 1713 track->cb_dirty = true; 1714 track->zb_dirty = true; 1715 break; 1716 case RADEON_RB3D_COLORPITCH: 1717 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1718 if (r) { 1719 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1720 idx, reg); 1721 radeon_cs_dump_packet(p, pkt); 1722 return r; 1723 } 1724 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 1725 if (reloc->tiling_flags & RADEON_TILING_MACRO) 1726 tile_flags |= RADEON_COLOR_TILE_ENABLE; 1727 if (reloc->tiling_flags & RADEON_TILING_MICRO) 1728 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE; 1729 1730 tmp = idx_value & ~(0x7 << 16); 1731 tmp |= tile_flags; 1732 ib[idx] = tmp; 1733 } else 1734 ib[idx] = idx_value; 1735 1736 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK; 1737 track->cb_dirty = true; 1738 break; 1739 case RADEON_RB3D_DEPTHPITCH: 1740 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK; 1741 track->zb_dirty = true; 1742 break; 1743 case RADEON_RB3D_CNTL: 1744 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) { 1745 case 7: 1746 case 8: 1747 case 9: 1748 case 11: 1749 case 12: 1750 track->cb[0].cpp = 1; 1751 break; 1752 case 3: 1753 case 4: 1754 case 15: 1755 track->cb[0].cpp = 2; 1756 break; 1757 case 6: 1758 track->cb[0].cpp = 4; 1759 break; 1760 default: 1761 DRM_ERROR("Invalid color buffer format (%d) !\n", 1762 ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f)); 1763 return -EINVAL; 1764 } 1765 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE); 1766 track->cb_dirty = true; 1767 track->zb_dirty = true; 1768 break; 1769 case RADEON_RB3D_ZSTENCILCNTL: 1770 switch (idx_value & 0xf) { 1771 case 0: 1772 track->zb.cpp = 2; 1773 break; 1774 case 2: 1775 case 3: 1776 case 4: 1777 case 5: 1778 case 9: 1779 case 11: 1780 track->zb.cpp = 4; 1781 break; 1782 default: 1783 break; 1784 } 1785 track->zb_dirty = true; 1786 break; 1787 case RADEON_RB3D_ZPASS_ADDR: 1788 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1789 if (r) { 1790 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1791 idx, reg); 1792 radeon_cs_dump_packet(p, pkt); 1793 return r; 1794 } 1795 ib[idx] = idx_value + ((u32)reloc->gpu_offset); 1796 break; 1797 case RADEON_PP_CNTL: 1798 { 1799 uint32_t temp = idx_value >> 4; 1800 for (i = 0; i < track->num_texture; i++) 1801 track->textures[i].enabled = !!(temp & (1 << i)); 1802 track->tex_dirty = true; 1803 } 1804 break; 1805 case RADEON_SE_VF_CNTL: 1806 track->vap_vf_cntl = idx_value; 1807 break; 1808 case RADEON_SE_VTX_FMT: 1809 track->vtx_size = r100_get_vtx_size(idx_value); 1810 break; 1811 case RADEON_PP_TEX_SIZE_0: 1812 case RADEON_PP_TEX_SIZE_1: 1813 case RADEON_PP_TEX_SIZE_2: 1814 i = (reg - RADEON_PP_TEX_SIZE_0) / 8; 1815 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1; 1816 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1; 1817 track->tex_dirty = true; 1818 break; 1819 case RADEON_PP_TEX_PITCH_0: 1820 case RADEON_PP_TEX_PITCH_1: 1821 case RADEON_PP_TEX_PITCH_2: 1822 i = (reg - RADEON_PP_TEX_PITCH_0) / 8; 1823 track->textures[i].pitch = idx_value + 32; 1824 track->tex_dirty = true; 1825 break; 1826 case RADEON_PP_TXFILTER_0: 1827 case RADEON_PP_TXFILTER_1: 1828 case RADEON_PP_TXFILTER_2: 1829 i = (reg - RADEON_PP_TXFILTER_0) / 24; 1830 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK) 1831 >> RADEON_MAX_MIP_LEVEL_SHIFT); 1832 tmp = (idx_value >> 23) & 0x7; 1833 if (tmp == 2 || tmp == 6) 1834 track->textures[i].roundup_w = false; 1835 tmp = (idx_value >> 27) & 0x7; 1836 if (tmp == 2 || tmp == 6) 1837 track->textures[i].roundup_h = false; 1838 track->tex_dirty = true; 1839 break; 1840 case RADEON_PP_TXFORMAT_0: 1841 case RADEON_PP_TXFORMAT_1: 1842 case RADEON_PP_TXFORMAT_2: 1843 i = (reg - RADEON_PP_TXFORMAT_0) / 24; 1844 if (idx_value & RADEON_TXFORMAT_NON_POWER2) { 1845 track->textures[i].use_pitch = 1; 1846 } else { 1847 track->textures[i].use_pitch = 0; 1848 track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK); 1849 track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK); 1850 } 1851 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE) 1852 track->textures[i].tex_coord_type = 2; 1853 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) { 1854 case RADEON_TXFORMAT_I8: 1855 case RADEON_TXFORMAT_RGB332: 1856 case RADEON_TXFORMAT_Y8: 1857 track->textures[i].cpp = 1; 1858 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 1859 break; 1860 case RADEON_TXFORMAT_AI88: 1861 case RADEON_TXFORMAT_ARGB1555: 1862 case RADEON_TXFORMAT_RGB565: 1863 case RADEON_TXFORMAT_ARGB4444: 1864 case RADEON_TXFORMAT_VYUY422: 1865 case RADEON_TXFORMAT_YVYU422: 1866 case RADEON_TXFORMAT_SHADOW16: 1867 case RADEON_TXFORMAT_LDUDV655: 1868 case RADEON_TXFORMAT_DUDV88: 1869 track->textures[i].cpp = 2; 1870 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 1871 break; 1872 case RADEON_TXFORMAT_ARGB8888: 1873 case RADEON_TXFORMAT_RGBA8888: 1874 case RADEON_TXFORMAT_SHADOW32: 1875 case RADEON_TXFORMAT_LDUDUV8888: 1876 track->textures[i].cpp = 4; 1877 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 1878 break; 1879 case RADEON_TXFORMAT_DXT1: 1880 track->textures[i].cpp = 1; 1881 track->textures[i].compress_format = R100_TRACK_COMP_DXT1; 1882 break; 1883 case RADEON_TXFORMAT_DXT23: 1884 case RADEON_TXFORMAT_DXT45: 1885 track->textures[i].cpp = 1; 1886 track->textures[i].compress_format = R100_TRACK_COMP_DXT35; 1887 break; 1888 } 1889 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf); 1890 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf); 1891 track->tex_dirty = true; 1892 break; 1893 case RADEON_PP_CUBIC_FACES_0: 1894 case RADEON_PP_CUBIC_FACES_1: 1895 case RADEON_PP_CUBIC_FACES_2: 1896 tmp = idx_value; 1897 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4; 1898 for (face = 0; face < 4; face++) { 1899 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf); 1900 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf); 1901 } 1902 track->tex_dirty = true; 1903 break; 1904 default: 1905 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n", 1906 reg, idx); 1907 return -EINVAL; 1908 } 1909 return 0; 1910 } 1911 1912 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, 1913 struct radeon_cs_packet *pkt, 1914 struct radeon_bo *robj) 1915 { 1916 unsigned idx; 1917 u32 value; 1918 idx = pkt->idx + 1; 1919 value = radeon_get_ib_value(p, idx + 2); 1920 if ((value + 1) > radeon_bo_size(robj)) { 1921 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER " 1922 "(need %u have %lu) !\n", 1923 value + 1, 1924 radeon_bo_size(robj)); 1925 return -EINVAL; 1926 } 1927 return 0; 1928 } 1929 1930 static int r100_packet3_check(struct radeon_cs_parser *p, 1931 struct radeon_cs_packet *pkt) 1932 { 1933 struct radeon_bo_list *reloc; 1934 struct r100_cs_track *track; 1935 unsigned idx; 1936 volatile uint32_t *ib; 1937 int r; 1938 1939 ib = p->ib.ptr; 1940 idx = pkt->idx + 1; 1941 track = (struct r100_cs_track *)p->track; 1942 switch (pkt->opcode) { 1943 case PACKET3_3D_LOAD_VBPNTR: 1944 r = r100_packet3_load_vbpntr(p, pkt, idx); 1945 if (r) 1946 return r; 1947 break; 1948 case PACKET3_INDX_BUFFER: 1949 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1950 if (r) { 1951 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); 1952 radeon_cs_dump_packet(p, pkt); 1953 return r; 1954 } 1955 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->gpu_offset); 1956 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj); 1957 if (r) { 1958 return r; 1959 } 1960 break; 1961 case 0x23: 1962 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */ 1963 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1964 if (r) { 1965 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); 1966 radeon_cs_dump_packet(p, pkt); 1967 return r; 1968 } 1969 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->gpu_offset); 1970 track->num_arrays = 1; 1971 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2)); 1972 1973 track->arrays[0].robj = reloc->robj; 1974 track->arrays[0].esize = track->vtx_size; 1975 1976 track->max_indx = radeon_get_ib_value(p, idx+1); 1977 1978 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3); 1979 track->immd_dwords = pkt->count - 1; 1980 r = r100_cs_track_check(p->rdev, track); 1981 if (r) 1982 return r; 1983 break; 1984 case PACKET3_3D_DRAW_IMMD: 1985 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) { 1986 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); 1987 return -EINVAL; 1988 } 1989 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0)); 1990 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 1991 track->immd_dwords = pkt->count - 1; 1992 r = r100_cs_track_check(p->rdev, track); 1993 if (r) 1994 return r; 1995 break; 1996 /* triggers drawing using in-packet vertex data */ 1997 case PACKET3_3D_DRAW_IMMD_2: 1998 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) { 1999 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); 2000 return -EINVAL; 2001 } 2002 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 2003 track->immd_dwords = pkt->count; 2004 r = r100_cs_track_check(p->rdev, track); 2005 if (r) 2006 return r; 2007 break; 2008 /* triggers drawing using in-packet vertex data */ 2009 case PACKET3_3D_DRAW_VBUF_2: 2010 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 2011 r = r100_cs_track_check(p->rdev, track); 2012 if (r) 2013 return r; 2014 break; 2015 /* triggers drawing of vertex buffers setup elsewhere */ 2016 case PACKET3_3D_DRAW_INDX_2: 2017 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 2018 r = r100_cs_track_check(p->rdev, track); 2019 if (r) 2020 return r; 2021 break; 2022 /* triggers drawing using indices to vertex buffer */ 2023 case PACKET3_3D_DRAW_VBUF: 2024 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 2025 r = r100_cs_track_check(p->rdev, track); 2026 if (r) 2027 return r; 2028 break; 2029 /* triggers drawing of vertex buffers setup elsewhere */ 2030 case PACKET3_3D_DRAW_INDX: 2031 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 2032 r = r100_cs_track_check(p->rdev, track); 2033 if (r) 2034 return r; 2035 break; 2036 /* triggers drawing using indices to vertex buffer */ 2037 case PACKET3_3D_CLEAR_HIZ: 2038 case PACKET3_3D_CLEAR_ZMASK: 2039 if (p->rdev->hyperz_filp != p->filp) 2040 return -EINVAL; 2041 break; 2042 case PACKET3_NOP: 2043 break; 2044 default: 2045 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode); 2046 return -EINVAL; 2047 } 2048 return 0; 2049 } 2050 2051 int r100_cs_parse(struct radeon_cs_parser *p) 2052 { 2053 struct radeon_cs_packet pkt; 2054 struct r100_cs_track *track; 2055 int r; 2056 2057 track = kzalloc(sizeof(*track), GFP_KERNEL); 2058 if (!track) 2059 return -ENOMEM; 2060 r100_cs_track_clear(p->rdev, track); 2061 p->track = track; 2062 do { 2063 r = radeon_cs_packet_parse(p, &pkt, p->idx); 2064 if (r) { 2065 return r; 2066 } 2067 p->idx += pkt.count + 2; 2068 switch (pkt.type) { 2069 case RADEON_PACKET_TYPE0: 2070 if (p->rdev->family >= CHIP_R200) 2071 r = r100_cs_parse_packet0(p, &pkt, 2072 p->rdev->config.r100.reg_safe_bm, 2073 p->rdev->config.r100.reg_safe_bm_size, 2074 &r200_packet0_check); 2075 else 2076 r = r100_cs_parse_packet0(p, &pkt, 2077 p->rdev->config.r100.reg_safe_bm, 2078 p->rdev->config.r100.reg_safe_bm_size, 2079 &r100_packet0_check); 2080 break; 2081 case RADEON_PACKET_TYPE2: 2082 break; 2083 case RADEON_PACKET_TYPE3: 2084 r = r100_packet3_check(p, &pkt); 2085 break; 2086 default: 2087 DRM_ERROR("Unknown packet type %d !\n", 2088 pkt.type); 2089 return -EINVAL; 2090 } 2091 if (r) 2092 return r; 2093 } while (p->idx < p->chunk_ib->length_dw); 2094 return 0; 2095 } 2096 2097 static void r100_cs_track_texture_print(struct r100_cs_track_texture *t) 2098 { 2099 DRM_ERROR("pitch %d\n", t->pitch); 2100 DRM_ERROR("use_pitch %d\n", t->use_pitch); 2101 DRM_ERROR("width %d\n", t->width); 2102 DRM_ERROR("width_11 %d\n", t->width_11); 2103 DRM_ERROR("height %d\n", t->height); 2104 DRM_ERROR("height_11 %d\n", t->height_11); 2105 DRM_ERROR("num levels %d\n", t->num_levels); 2106 DRM_ERROR("depth %d\n", t->txdepth); 2107 DRM_ERROR("bpp %d\n", t->cpp); 2108 DRM_ERROR("coordinate type %d\n", t->tex_coord_type); 2109 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w); 2110 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h); 2111 DRM_ERROR("compress format %d\n", t->compress_format); 2112 } 2113 2114 static int r100_track_compress_size(int compress_format, int w, int h) 2115 { 2116 int block_width, block_height, block_bytes; 2117 int wblocks, hblocks; 2118 int min_wblocks; 2119 int sz; 2120 2121 block_width = 4; 2122 block_height = 4; 2123 2124 switch (compress_format) { 2125 case R100_TRACK_COMP_DXT1: 2126 block_bytes = 8; 2127 min_wblocks = 4; 2128 break; 2129 default: 2130 case R100_TRACK_COMP_DXT35: 2131 block_bytes = 16; 2132 min_wblocks = 2; 2133 break; 2134 } 2135 2136 hblocks = (h + block_height - 1) / block_height; 2137 wblocks = (w + block_width - 1) / block_width; 2138 if (wblocks < min_wblocks) 2139 wblocks = min_wblocks; 2140 sz = wblocks * hblocks * block_bytes; 2141 return sz; 2142 } 2143 2144 static int r100_cs_track_cube(struct radeon_device *rdev, 2145 struct r100_cs_track *track, unsigned idx) 2146 { 2147 unsigned face, w, h; 2148 struct radeon_bo *cube_robj; 2149 unsigned long size; 2150 unsigned compress_format = track->textures[idx].compress_format; 2151 2152 for (face = 0; face < 5; face++) { 2153 cube_robj = track->textures[idx].cube_info[face].robj; 2154 w = track->textures[idx].cube_info[face].width; 2155 h = track->textures[idx].cube_info[face].height; 2156 2157 if (compress_format) { 2158 size = r100_track_compress_size(compress_format, w, h); 2159 } else 2160 size = w * h; 2161 size *= track->textures[idx].cpp; 2162 2163 size += track->textures[idx].cube_info[face].offset; 2164 2165 if (size > radeon_bo_size(cube_robj)) { 2166 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n", 2167 size, radeon_bo_size(cube_robj)); 2168 r100_cs_track_texture_print(&track->textures[idx]); 2169 return -1; 2170 } 2171 } 2172 return 0; 2173 } 2174 2175 static int r100_cs_track_texture_check(struct radeon_device *rdev, 2176 struct r100_cs_track *track) 2177 { 2178 struct radeon_bo *robj; 2179 unsigned long size; 2180 unsigned u, i, w, h, d; 2181 int ret; 2182 2183 for (u = 0; u < track->num_texture; u++) { 2184 if (!track->textures[u].enabled) 2185 continue; 2186 if (track->textures[u].lookup_disable) 2187 continue; 2188 robj = track->textures[u].robj; 2189 if (robj == NULL) { 2190 DRM_ERROR("No texture bound to unit %u\n", u); 2191 return -EINVAL; 2192 } 2193 size = 0; 2194 for (i = 0; i <= track->textures[u].num_levels; i++) { 2195 if (track->textures[u].use_pitch) { 2196 if (rdev->family < CHIP_R300) 2197 w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i); 2198 else 2199 w = track->textures[u].pitch / (1 << i); 2200 } else { 2201 w = track->textures[u].width; 2202 if (rdev->family >= CHIP_RV515) 2203 w |= track->textures[u].width_11; 2204 w = w / (1 << i); 2205 if (track->textures[u].roundup_w) 2206 w = roundup_pow_of_two(w); 2207 } 2208 h = track->textures[u].height; 2209 if (rdev->family >= CHIP_RV515) 2210 h |= track->textures[u].height_11; 2211 h = h / (1 << i); 2212 if (track->textures[u].roundup_h) 2213 h = roundup_pow_of_two(h); 2214 if (track->textures[u].tex_coord_type == 1) { 2215 d = (1 << track->textures[u].txdepth) / (1 << i); 2216 if (!d) 2217 d = 1; 2218 } else { 2219 d = 1; 2220 } 2221 if (track->textures[u].compress_format) { 2222 2223 size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d; 2224 /* compressed textures are block based */ 2225 } else 2226 size += w * h * d; 2227 } 2228 size *= track->textures[u].cpp; 2229 2230 switch (track->textures[u].tex_coord_type) { 2231 case 0: 2232 case 1: 2233 break; 2234 case 2: 2235 if (track->separate_cube) { 2236 ret = r100_cs_track_cube(rdev, track, u); 2237 if (ret) 2238 return ret; 2239 } else 2240 size *= 6; 2241 break; 2242 default: 2243 DRM_ERROR("Invalid texture coordinate type %u for unit " 2244 "%u\n", track->textures[u].tex_coord_type, u); 2245 return -EINVAL; 2246 } 2247 if (size > radeon_bo_size(robj)) { 2248 DRM_ERROR("Texture of unit %u needs %lu bytes but is " 2249 "%lu\n", u, size, radeon_bo_size(robj)); 2250 r100_cs_track_texture_print(&track->textures[u]); 2251 return -EINVAL; 2252 } 2253 } 2254 return 0; 2255 } 2256 2257 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track) 2258 { 2259 unsigned i; 2260 unsigned long size; 2261 unsigned prim_walk; 2262 unsigned nverts; 2263 unsigned num_cb = track->cb_dirty ? track->num_cb : 0; 2264 2265 if (num_cb && !track->zb_cb_clear && !track->color_channel_mask && 2266 !track->blend_read_enable) 2267 num_cb = 0; 2268 2269 for (i = 0; i < num_cb; i++) { 2270 if (track->cb[i].robj == NULL) { 2271 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i); 2272 return -EINVAL; 2273 } 2274 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy; 2275 size += track->cb[i].offset; 2276 if (size > radeon_bo_size(track->cb[i].robj)) { 2277 DRM_ERROR("[drm] Buffer too small for color buffer %d " 2278 "(need %lu have %lu) !\n", i, size, 2279 radeon_bo_size(track->cb[i].robj)); 2280 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n", 2281 i, track->cb[i].pitch, track->cb[i].cpp, 2282 track->cb[i].offset, track->maxy); 2283 return -EINVAL; 2284 } 2285 } 2286 track->cb_dirty = false; 2287 2288 if (track->zb_dirty && track->z_enabled) { 2289 if (track->zb.robj == NULL) { 2290 DRM_ERROR("[drm] No buffer for z buffer !\n"); 2291 return -EINVAL; 2292 } 2293 size = track->zb.pitch * track->zb.cpp * track->maxy; 2294 size += track->zb.offset; 2295 if (size > radeon_bo_size(track->zb.robj)) { 2296 DRM_ERROR("[drm] Buffer too small for z buffer " 2297 "(need %lu have %lu) !\n", size, 2298 radeon_bo_size(track->zb.robj)); 2299 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n", 2300 track->zb.pitch, track->zb.cpp, 2301 track->zb.offset, track->maxy); 2302 return -EINVAL; 2303 } 2304 } 2305 track->zb_dirty = false; 2306 2307 if (track->aa_dirty && track->aaresolve) { 2308 if (track->aa.robj == NULL) { 2309 DRM_ERROR("[drm] No buffer for AA resolve buffer %d !\n", i); 2310 return -EINVAL; 2311 } 2312 /* I believe the format comes from colorbuffer0. */ 2313 size = track->aa.pitch * track->cb[0].cpp * track->maxy; 2314 size += track->aa.offset; 2315 if (size > radeon_bo_size(track->aa.robj)) { 2316 DRM_ERROR("[drm] Buffer too small for AA resolve buffer %d " 2317 "(need %lu have %lu) !\n", i, size, 2318 radeon_bo_size(track->aa.robj)); 2319 DRM_ERROR("[drm] AA resolve buffer %d (%u %u %u %u)\n", 2320 i, track->aa.pitch, track->cb[0].cpp, 2321 track->aa.offset, track->maxy); 2322 return -EINVAL; 2323 } 2324 } 2325 track->aa_dirty = false; 2326 2327 prim_walk = (track->vap_vf_cntl >> 4) & 0x3; 2328 if (track->vap_vf_cntl & (1 << 14)) { 2329 nverts = track->vap_alt_nverts; 2330 } else { 2331 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF; 2332 } 2333 switch (prim_walk) { 2334 case 1: 2335 for (i = 0; i < track->num_arrays; i++) { 2336 size = track->arrays[i].esize * track->max_indx * 4; 2337 if (track->arrays[i].robj == NULL) { 2338 DRM_ERROR("(PW %u) Vertex array %u no buffer " 2339 "bound\n", prim_walk, i); 2340 return -EINVAL; 2341 } 2342 if (size > radeon_bo_size(track->arrays[i].robj)) { 2343 dev_err(rdev->dev, "(PW %u) Vertex array %u " 2344 "need %lu dwords have %lu dwords\n", 2345 prim_walk, i, size >> 2, 2346 radeon_bo_size(track->arrays[i].robj) 2347 >> 2); 2348 DRM_ERROR("Max indices %u\n", track->max_indx); 2349 return -EINVAL; 2350 } 2351 } 2352 break; 2353 case 2: 2354 for (i = 0; i < track->num_arrays; i++) { 2355 size = track->arrays[i].esize * (nverts - 1) * 4; 2356 if (track->arrays[i].robj == NULL) { 2357 DRM_ERROR("(PW %u) Vertex array %u no buffer " 2358 "bound\n", prim_walk, i); 2359 return -EINVAL; 2360 } 2361 if (size > radeon_bo_size(track->arrays[i].robj)) { 2362 dev_err(rdev->dev, "(PW %u) Vertex array %u " 2363 "need %lu dwords have %lu dwords\n", 2364 prim_walk, i, size >> 2, 2365 radeon_bo_size(track->arrays[i].robj) 2366 >> 2); 2367 return -EINVAL; 2368 } 2369 } 2370 break; 2371 case 3: 2372 size = track->vtx_size * nverts; 2373 if (size != track->immd_dwords) { 2374 DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n", 2375 track->immd_dwords, size); 2376 DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n", 2377 nverts, track->vtx_size); 2378 return -EINVAL; 2379 } 2380 break; 2381 default: 2382 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n", 2383 prim_walk); 2384 return -EINVAL; 2385 } 2386 2387 if (track->tex_dirty) { 2388 track->tex_dirty = false; 2389 return r100_cs_track_texture_check(rdev, track); 2390 } 2391 return 0; 2392 } 2393 2394 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track) 2395 { 2396 unsigned i, face; 2397 2398 track->cb_dirty = true; 2399 track->zb_dirty = true; 2400 track->tex_dirty = true; 2401 track->aa_dirty = true; 2402 2403 if (rdev->family < CHIP_R300) { 2404 track->num_cb = 1; 2405 if (rdev->family <= CHIP_RS200) 2406 track->num_texture = 3; 2407 else 2408 track->num_texture = 6; 2409 track->maxy = 2048; 2410 track->separate_cube = 1; 2411 } else { 2412 track->num_cb = 4; 2413 track->num_texture = 16; 2414 track->maxy = 4096; 2415 track->separate_cube = 0; 2416 track->aaresolve = false; 2417 track->aa.robj = NULL; 2418 } 2419 2420 for (i = 0; i < track->num_cb; i++) { 2421 track->cb[i].robj = NULL; 2422 track->cb[i].pitch = 8192; 2423 track->cb[i].cpp = 16; 2424 track->cb[i].offset = 0; 2425 } 2426 track->z_enabled = true; 2427 track->zb.robj = NULL; 2428 track->zb.pitch = 8192; 2429 track->zb.cpp = 4; 2430 track->zb.offset = 0; 2431 track->vtx_size = 0x7F; 2432 track->immd_dwords = 0xFFFFFFFFUL; 2433 track->num_arrays = 11; 2434 track->max_indx = 0x00FFFFFFUL; 2435 for (i = 0; i < track->num_arrays; i++) { 2436 track->arrays[i].robj = NULL; 2437 track->arrays[i].esize = 0x7F; 2438 } 2439 for (i = 0; i < track->num_texture; i++) { 2440 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 2441 track->textures[i].pitch = 16536; 2442 track->textures[i].width = 16536; 2443 track->textures[i].height = 16536; 2444 track->textures[i].width_11 = 1 << 11; 2445 track->textures[i].height_11 = 1 << 11; 2446 track->textures[i].num_levels = 12; 2447 if (rdev->family <= CHIP_RS200) { 2448 track->textures[i].tex_coord_type = 0; 2449 track->textures[i].txdepth = 0; 2450 } else { 2451 track->textures[i].txdepth = 16; 2452 track->textures[i].tex_coord_type = 1; 2453 } 2454 track->textures[i].cpp = 64; 2455 track->textures[i].robj = NULL; 2456 /* CS IB emission code makes sure texture unit are disabled */ 2457 track->textures[i].enabled = false; 2458 track->textures[i].lookup_disable = false; 2459 track->textures[i].roundup_w = true; 2460 track->textures[i].roundup_h = true; 2461 if (track->separate_cube) 2462 for (face = 0; face < 5; face++) { 2463 track->textures[i].cube_info[face].robj = NULL; 2464 track->textures[i].cube_info[face].width = 16536; 2465 track->textures[i].cube_info[face].height = 16536; 2466 track->textures[i].cube_info[face].offset = 0; 2467 } 2468 } 2469 } 2470 2471 /* 2472 * Global GPU functions 2473 */ 2474 static void r100_errata(struct radeon_device *rdev) 2475 { 2476 rdev->pll_errata = 0; 2477 2478 if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) { 2479 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS; 2480 } 2481 2482 if (rdev->family == CHIP_RV100 || 2483 rdev->family == CHIP_RS100 || 2484 rdev->family == CHIP_RS200) { 2485 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY; 2486 } 2487 } 2488 2489 static int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n) 2490 { 2491 unsigned i; 2492 uint32_t tmp; 2493 2494 for (i = 0; i < rdev->usec_timeout; i++) { 2495 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK; 2496 if (tmp >= n) { 2497 return 0; 2498 } 2499 DRM_UDELAY(1); 2500 } 2501 return -1; 2502 } 2503 2504 int r100_gui_wait_for_idle(struct radeon_device *rdev) 2505 { 2506 unsigned i; 2507 uint32_t tmp; 2508 2509 if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) { 2510 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !" 2511 " Bad things might happen.\n"); 2512 } 2513 for (i = 0; i < rdev->usec_timeout; i++) { 2514 tmp = RREG32(RADEON_RBBM_STATUS); 2515 if (!(tmp & RADEON_RBBM_ACTIVE)) { 2516 return 0; 2517 } 2518 DRM_UDELAY(1); 2519 } 2520 return -1; 2521 } 2522 2523 int r100_mc_wait_for_idle(struct radeon_device *rdev) 2524 { 2525 unsigned i; 2526 uint32_t tmp; 2527 2528 for (i = 0; i < rdev->usec_timeout; i++) { 2529 /* read MC_STATUS */ 2530 tmp = RREG32(RADEON_MC_STATUS); 2531 if (tmp & RADEON_MC_IDLE) { 2532 return 0; 2533 } 2534 DRM_UDELAY(1); 2535 } 2536 return -1; 2537 } 2538 2539 bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) 2540 { 2541 u32 rbbm_status; 2542 2543 rbbm_status = RREG32(R_000E40_RBBM_STATUS); 2544 if (!G_000E40_GUI_ACTIVE(rbbm_status)) { 2545 radeon_ring_lockup_update(rdev, ring); 2546 return false; 2547 } 2548 return radeon_ring_test_lockup(rdev, ring); 2549 } 2550 2551 /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */ 2552 void r100_enable_bm(struct radeon_device *rdev) 2553 { 2554 uint32_t tmp; 2555 /* Enable bus mastering */ 2556 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; 2557 WREG32(RADEON_BUS_CNTL, tmp); 2558 } 2559 2560 void r100_bm_disable(struct radeon_device *rdev) 2561 { 2562 u32 tmp; 2563 2564 /* disable bus mastering */ 2565 tmp = RREG32(R_000030_BUS_CNTL); 2566 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044); 2567 mdelay(1); 2568 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042); 2569 mdelay(1); 2570 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040); 2571 tmp = RREG32(RADEON_BUS_CNTL); 2572 mdelay(1); 2573 pci_clear_master(rdev->pdev); 2574 mdelay(1); 2575 } 2576 2577 int r100_asic_reset(struct radeon_device *rdev) 2578 { 2579 struct r100_mc_save save; 2580 u32 status, tmp; 2581 int ret = 0; 2582 2583 status = RREG32(R_000E40_RBBM_STATUS); 2584 if (!G_000E40_GUI_ACTIVE(status)) { 2585 return 0; 2586 } 2587 r100_mc_stop(rdev, &save); 2588 status = RREG32(R_000E40_RBBM_STATUS); 2589 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 2590 /* stop CP */ 2591 WREG32(RADEON_CP_CSQ_CNTL, 0); 2592 tmp = RREG32(RADEON_CP_RB_CNTL); 2593 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); 2594 WREG32(RADEON_CP_RB_RPTR_WR, 0); 2595 WREG32(RADEON_CP_RB_WPTR, 0); 2596 WREG32(RADEON_CP_RB_CNTL, tmp); 2597 /* save PCI state */ 2598 pci_save_state(rdev->pdev); 2599 /* disable bus mastering */ 2600 r100_bm_disable(rdev); 2601 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) | 2602 S_0000F0_SOFT_RESET_RE(1) | 2603 S_0000F0_SOFT_RESET_PP(1) | 2604 S_0000F0_SOFT_RESET_RB(1)); 2605 RREG32(R_0000F0_RBBM_SOFT_RESET); 2606 mdelay(500); 2607 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 2608 mdelay(1); 2609 status = RREG32(R_000E40_RBBM_STATUS); 2610 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 2611 /* reset CP */ 2612 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1)); 2613 RREG32(R_0000F0_RBBM_SOFT_RESET); 2614 mdelay(500); 2615 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 2616 mdelay(1); 2617 status = RREG32(R_000E40_RBBM_STATUS); 2618 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 2619 /* restore PCI & busmastering */ 2620 pci_restore_state(rdev->pdev); 2621 r100_enable_bm(rdev); 2622 /* Check if GPU is idle */ 2623 if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) || 2624 G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) { 2625 dev_err(rdev->dev, "failed to reset GPU\n"); 2626 ret = -1; 2627 } else 2628 dev_info(rdev->dev, "GPU reset succeed\n"); 2629 r100_mc_resume(rdev, &save); 2630 return ret; 2631 } 2632 2633 void r100_set_common_regs(struct radeon_device *rdev) 2634 { 2635 struct drm_device *dev = rdev->ddev; 2636 bool force_dac2 = false; 2637 u32 tmp; 2638 2639 /* set these so they don't interfere with anything */ 2640 WREG32(RADEON_OV0_SCALE_CNTL, 0); 2641 WREG32(RADEON_SUBPIC_CNTL, 0); 2642 WREG32(RADEON_VIPH_CONTROL, 0); 2643 WREG32(RADEON_I2C_CNTL_1, 0); 2644 WREG32(RADEON_DVI_I2C_CNTL_1, 0); 2645 WREG32(RADEON_CAP0_TRIG_CNTL, 0); 2646 WREG32(RADEON_CAP1_TRIG_CNTL, 0); 2647 2648 /* always set up dac2 on rn50 and some rv100 as lots 2649 * of servers seem to wire it up to a VGA port but 2650 * don't report it in the bios connector 2651 * table. 2652 */ 2653 switch (dev->pdev->device) { 2654 /* RN50 */ 2655 case 0x515e: 2656 case 0x5969: 2657 force_dac2 = true; 2658 break; 2659 /* RV100*/ 2660 case 0x5159: 2661 case 0x515a: 2662 /* DELL triple head servers */ 2663 if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) && 2664 ((dev->pdev->subsystem_device == 0x016c) || 2665 (dev->pdev->subsystem_device == 0x016d) || 2666 (dev->pdev->subsystem_device == 0x016e) || 2667 (dev->pdev->subsystem_device == 0x016f) || 2668 (dev->pdev->subsystem_device == 0x0170) || 2669 (dev->pdev->subsystem_device == 0x017d) || 2670 (dev->pdev->subsystem_device == 0x017e) || 2671 (dev->pdev->subsystem_device == 0x0183) || 2672 (dev->pdev->subsystem_device == 0x018a) || 2673 (dev->pdev->subsystem_device == 0x019a))) 2674 force_dac2 = true; 2675 break; 2676 } 2677 2678 if (force_dac2) { 2679 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG); 2680 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); 2681 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2); 2682 2683 /* For CRT on DAC2, don't turn it on if BIOS didn't 2684 enable it, even it's detected. 2685 */ 2686 2687 /* force it to crtc0 */ 2688 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL; 2689 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL; 2690 disp_hw_debug |= RADEON_CRT2_DISP1_SEL; 2691 2692 /* set up the TV DAC */ 2693 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL | 2694 RADEON_TV_DAC_STD_MASK | 2695 RADEON_TV_DAC_RDACPD | 2696 RADEON_TV_DAC_GDACPD | 2697 RADEON_TV_DAC_BDACPD | 2698 RADEON_TV_DAC_BGADJ_MASK | 2699 RADEON_TV_DAC_DACADJ_MASK); 2700 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK | 2701 RADEON_TV_DAC_NHOLD | 2702 RADEON_TV_DAC_STD_PS2 | 2703 (0x58 << 16)); 2704 2705 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); 2706 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug); 2707 WREG32(RADEON_DAC_CNTL2, dac2_cntl); 2708 } 2709 2710 /* switch PM block to ACPI mode */ 2711 tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL); 2712 tmp &= ~RADEON_PM_MODE_SEL; 2713 WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp); 2714 2715 } 2716 2717 /* 2718 * VRAM info 2719 */ 2720 static void r100_vram_get_type(struct radeon_device *rdev) 2721 { 2722 uint32_t tmp; 2723 2724 rdev->mc.vram_is_ddr = false; 2725 if (rdev->flags & RADEON_IS_IGP) 2726 rdev->mc.vram_is_ddr = true; 2727 else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR) 2728 rdev->mc.vram_is_ddr = true; 2729 if ((rdev->family == CHIP_RV100) || 2730 (rdev->family == CHIP_RS100) || 2731 (rdev->family == CHIP_RS200)) { 2732 tmp = RREG32(RADEON_MEM_CNTL); 2733 if (tmp & RV100_HALF_MODE) { 2734 rdev->mc.vram_width = 32; 2735 } else { 2736 rdev->mc.vram_width = 64; 2737 } 2738 if (rdev->flags & RADEON_SINGLE_CRTC) { 2739 rdev->mc.vram_width /= 4; 2740 rdev->mc.vram_is_ddr = true; 2741 } 2742 } else if (rdev->family <= CHIP_RV280) { 2743 tmp = RREG32(RADEON_MEM_CNTL); 2744 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) { 2745 rdev->mc.vram_width = 128; 2746 } else { 2747 rdev->mc.vram_width = 64; 2748 } 2749 } else { 2750 /* newer IGPs */ 2751 rdev->mc.vram_width = 128; 2752 } 2753 } 2754 2755 static u32 r100_get_accessible_vram(struct radeon_device *rdev) 2756 { 2757 u32 aper_size; 2758 u8 byte; 2759 2760 aper_size = RREG32(RADEON_CONFIG_APER_SIZE); 2761 2762 /* Set HDP_APER_CNTL only on cards that are known not to be broken, 2763 * that is has the 2nd generation multifunction PCI interface 2764 */ 2765 if (rdev->family == CHIP_RV280 || 2766 rdev->family >= CHIP_RV350) { 2767 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL, 2768 ~RADEON_HDP_APER_CNTL); 2769 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n"); 2770 return aper_size * 2; 2771 } 2772 2773 /* Older cards have all sorts of funny issues to deal with. First 2774 * check if it's a multifunction card by reading the PCI config 2775 * header type... Limit those to one aperture size 2776 */ 2777 pci_read_config_byte(rdev->pdev, 0xe, &byte); 2778 if (byte & 0x80) { 2779 DRM_INFO("Generation 1 PCI interface in multifunction mode\n"); 2780 DRM_INFO("Limiting VRAM to one aperture\n"); 2781 return aper_size; 2782 } 2783 2784 /* Single function older card. We read HDP_APER_CNTL to see how the BIOS 2785 * have set it up. We don't write this as it's broken on some ASICs but 2786 * we expect the BIOS to have done the right thing (might be too optimistic...) 2787 */ 2788 if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL) 2789 return aper_size * 2; 2790 return aper_size; 2791 } 2792 2793 void r100_vram_init_sizes(struct radeon_device *rdev) 2794 { 2795 u64 config_aper_size; 2796 2797 /* work out accessible VRAM */ 2798 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); 2799 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); 2800 rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev); 2801 /* FIXME we don't use the second aperture yet when we could use it */ 2802 if (rdev->mc.visible_vram_size > rdev->mc.aper_size) 2803 rdev->mc.visible_vram_size = rdev->mc.aper_size; 2804 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE); 2805 if (rdev->flags & RADEON_IS_IGP) { 2806 uint32_t tom; 2807 /* read NB_TOM to get the amount of ram stolen for the GPU */ 2808 tom = RREG32(RADEON_NB_TOM); 2809 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16); 2810 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); 2811 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; 2812 } else { 2813 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); 2814 /* Some production boards of m6 will report 0 2815 * if it's 8 MB 2816 */ 2817 if (rdev->mc.real_vram_size == 0) { 2818 rdev->mc.real_vram_size = 8192 * 1024; 2819 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); 2820 } 2821 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM - 2822 * Novell bug 204882 + along with lots of ubuntu ones 2823 */ 2824 if (rdev->mc.aper_size > config_aper_size) 2825 config_aper_size = rdev->mc.aper_size; 2826 2827 if (config_aper_size > rdev->mc.real_vram_size) 2828 rdev->mc.mc_vram_size = config_aper_size; 2829 else 2830 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; 2831 } 2832 } 2833 2834 void r100_vga_set_state(struct radeon_device *rdev, bool state) 2835 { 2836 uint32_t temp; 2837 2838 temp = RREG32(RADEON_CONFIG_CNTL); 2839 if (state == false) { 2840 temp &= ~RADEON_CFG_VGA_RAM_EN; 2841 temp |= RADEON_CFG_VGA_IO_DIS; 2842 } else { 2843 temp &= ~RADEON_CFG_VGA_IO_DIS; 2844 } 2845 WREG32(RADEON_CONFIG_CNTL, temp); 2846 } 2847 2848 static void r100_mc_init(struct radeon_device *rdev) 2849 { 2850 u64 base; 2851 2852 r100_vram_get_type(rdev); 2853 r100_vram_init_sizes(rdev); 2854 base = rdev->mc.aper_base; 2855 if (rdev->flags & RADEON_IS_IGP) 2856 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; 2857 radeon_vram_location(rdev, &rdev->mc, base); 2858 rdev->mc.gtt_base_align = 0; 2859 if (!(rdev->flags & RADEON_IS_AGP)) 2860 radeon_gtt_location(rdev, &rdev->mc); 2861 radeon_update_bandwidth_info(rdev); 2862 } 2863 2864 2865 /* 2866 * Indirect registers accessor 2867 */ 2868 void r100_pll_errata_after_index(struct radeon_device *rdev) 2869 { 2870 if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) { 2871 (void)RREG32(RADEON_CLOCK_CNTL_DATA); 2872 (void)RREG32(RADEON_CRTC_GEN_CNTL); 2873 } 2874 } 2875 2876 static void r100_pll_errata_after_data(struct radeon_device *rdev) 2877 { 2878 /* This workarounds is necessary on RV100, RS100 and RS200 chips 2879 * or the chip could hang on a subsequent access 2880 */ 2881 if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) { 2882 mdelay(5); 2883 } 2884 2885 /* This function is required to workaround a hardware bug in some (all?) 2886 * revisions of the R300. This workaround should be called after every 2887 * CLOCK_CNTL_INDEX register access. If not, register reads afterward 2888 * may not be correct. 2889 */ 2890 if (rdev->pll_errata & CHIP_ERRATA_R300_CG) { 2891 uint32_t save, tmp; 2892 2893 save = RREG32(RADEON_CLOCK_CNTL_INDEX); 2894 tmp = save & ~(0x3f | RADEON_PLL_WR_EN); 2895 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp); 2896 tmp = RREG32(RADEON_CLOCK_CNTL_DATA); 2897 WREG32(RADEON_CLOCK_CNTL_INDEX, save); 2898 } 2899 } 2900 2901 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg) 2902 { 2903 unsigned long flags; 2904 uint32_t data; 2905 2906 spin_lock_irqsave(&rdev->pll_idx_lock, flags); 2907 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f); 2908 r100_pll_errata_after_index(rdev); 2909 data = RREG32(RADEON_CLOCK_CNTL_DATA); 2910 r100_pll_errata_after_data(rdev); 2911 spin_unlock_irqrestore(&rdev->pll_idx_lock, flags); 2912 return data; 2913 } 2914 2915 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 2916 { 2917 unsigned long flags; 2918 2919 spin_lock_irqsave(&rdev->pll_idx_lock, flags); 2920 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN)); 2921 r100_pll_errata_after_index(rdev); 2922 WREG32(RADEON_CLOCK_CNTL_DATA, v); 2923 r100_pll_errata_after_data(rdev); 2924 spin_unlock_irqrestore(&rdev->pll_idx_lock, flags); 2925 } 2926 2927 static void r100_set_safe_registers(struct radeon_device *rdev) 2928 { 2929 if (ASIC_IS_RN50(rdev)) { 2930 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm; 2931 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm); 2932 } else if (rdev->family < CHIP_R200) { 2933 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm; 2934 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm); 2935 } else { 2936 r200_set_safe_registers(rdev); 2937 } 2938 } 2939 2940 /* 2941 * Debugfs info 2942 */ 2943 #if defined(CONFIG_DEBUG_FS) 2944 static int r100_debugfs_rbbm_info(struct seq_file *m, void *data) 2945 { 2946 struct drm_info_node *node = (struct drm_info_node *) m->private; 2947 struct drm_device *dev = node->minor->dev; 2948 struct radeon_device *rdev = dev->dev_private; 2949 uint32_t reg, value; 2950 unsigned i; 2951 2952 seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS)); 2953 seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C)); 2954 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); 2955 for (i = 0; i < 64; i++) { 2956 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100); 2957 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2; 2958 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i); 2959 value = RREG32(RADEON_RBBM_CMDFIFO_DATA); 2960 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value); 2961 } 2962 return 0; 2963 } 2964 2965 static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data) 2966 { 2967 struct drm_info_node *node = (struct drm_info_node *) m->private; 2968 struct drm_device *dev = node->minor->dev; 2969 struct radeon_device *rdev = dev->dev_private; 2970 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2971 uint32_t rdp, wdp; 2972 unsigned count, i, j; 2973 2974 radeon_ring_free_size(rdev, ring); 2975 rdp = RREG32(RADEON_CP_RB_RPTR); 2976 wdp = RREG32(RADEON_CP_RB_WPTR); 2977 count = (rdp + ring->ring_size - wdp) & ring->ptr_mask; 2978 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); 2979 seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp); 2980 seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp); 2981 seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw); 2982 seq_printf(m, "%u dwords in ring\n", count); 2983 if (ring->ready) { 2984 for (j = 0; j <= count; j++) { 2985 i = (rdp + j) & ring->ptr_mask; 2986 seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]); 2987 } 2988 } 2989 return 0; 2990 } 2991 2992 2993 static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data) 2994 { 2995 struct drm_info_node *node = (struct drm_info_node *) m->private; 2996 struct drm_device *dev = node->minor->dev; 2997 struct radeon_device *rdev = dev->dev_private; 2998 uint32_t csq_stat, csq2_stat, tmp; 2999 unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr; 3000 unsigned i; 3001 3002 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); 3003 seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE)); 3004 csq_stat = RREG32(RADEON_CP_CSQ_STAT); 3005 csq2_stat = RREG32(RADEON_CP_CSQ2_STAT); 3006 r_rptr = (csq_stat >> 0) & 0x3ff; 3007 r_wptr = (csq_stat >> 10) & 0x3ff; 3008 ib1_rptr = (csq_stat >> 20) & 0x3ff; 3009 ib1_wptr = (csq2_stat >> 0) & 0x3ff; 3010 ib2_rptr = (csq2_stat >> 10) & 0x3ff; 3011 ib2_wptr = (csq2_stat >> 20) & 0x3ff; 3012 seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat); 3013 seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat); 3014 seq_printf(m, "Ring rptr %u\n", r_rptr); 3015 seq_printf(m, "Ring wptr %u\n", r_wptr); 3016 seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr); 3017 seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr); 3018 seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr); 3019 seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr); 3020 /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms 3021 * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */ 3022 seq_printf(m, "Ring fifo:\n"); 3023 for (i = 0; i < 256; i++) { 3024 WREG32(RADEON_CP_CSQ_ADDR, i << 2); 3025 tmp = RREG32(RADEON_CP_CSQ_DATA); 3026 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp); 3027 } 3028 seq_printf(m, "Indirect1 fifo:\n"); 3029 for (i = 256; i <= 512; i++) { 3030 WREG32(RADEON_CP_CSQ_ADDR, i << 2); 3031 tmp = RREG32(RADEON_CP_CSQ_DATA); 3032 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp); 3033 } 3034 seq_printf(m, "Indirect2 fifo:\n"); 3035 for (i = 640; i < ib1_wptr; i++) { 3036 WREG32(RADEON_CP_CSQ_ADDR, i << 2); 3037 tmp = RREG32(RADEON_CP_CSQ_DATA); 3038 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp); 3039 } 3040 return 0; 3041 } 3042 3043 static int r100_debugfs_mc_info(struct seq_file *m, void *data) 3044 { 3045 struct drm_info_node *node = (struct drm_info_node *) m->private; 3046 struct drm_device *dev = node->minor->dev; 3047 struct radeon_device *rdev = dev->dev_private; 3048 uint32_t tmp; 3049 3050 tmp = RREG32(RADEON_CONFIG_MEMSIZE); 3051 seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp); 3052 tmp = RREG32(RADEON_MC_FB_LOCATION); 3053 seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp); 3054 tmp = RREG32(RADEON_BUS_CNTL); 3055 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp); 3056 tmp = RREG32(RADEON_MC_AGP_LOCATION); 3057 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp); 3058 tmp = RREG32(RADEON_AGP_BASE); 3059 seq_printf(m, "AGP_BASE 0x%08x\n", tmp); 3060 tmp = RREG32(RADEON_HOST_PATH_CNTL); 3061 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp); 3062 tmp = RREG32(0x01D0); 3063 seq_printf(m, "AIC_CTRL 0x%08x\n", tmp); 3064 tmp = RREG32(RADEON_AIC_LO_ADDR); 3065 seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp); 3066 tmp = RREG32(RADEON_AIC_HI_ADDR); 3067 seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp); 3068 tmp = RREG32(0x01E4); 3069 seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp); 3070 return 0; 3071 } 3072 3073 static struct drm_info_list r100_debugfs_rbbm_list[] = { 3074 {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL}, 3075 }; 3076 3077 static struct drm_info_list r100_debugfs_cp_list[] = { 3078 {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL}, 3079 {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL}, 3080 }; 3081 3082 static struct drm_info_list r100_debugfs_mc_info_list[] = { 3083 {"r100_mc_info", r100_debugfs_mc_info, 0, NULL}, 3084 }; 3085 #endif 3086 3087 int r100_debugfs_rbbm_init(struct radeon_device *rdev) 3088 { 3089 #if defined(CONFIG_DEBUG_FS) 3090 return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1); 3091 #else 3092 return 0; 3093 #endif 3094 } 3095 3096 int r100_debugfs_cp_init(struct radeon_device *rdev) 3097 { 3098 #if defined(CONFIG_DEBUG_FS) 3099 return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2); 3100 #else 3101 return 0; 3102 #endif 3103 } 3104 3105 int r100_debugfs_mc_info_init(struct radeon_device *rdev) 3106 { 3107 #if defined(CONFIG_DEBUG_FS) 3108 return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1); 3109 #else 3110 return 0; 3111 #endif 3112 } 3113 3114 int r100_set_surface_reg(struct radeon_device *rdev, int reg, 3115 uint32_t tiling_flags, uint32_t pitch, 3116 uint32_t offset, uint32_t obj_size) 3117 { 3118 int surf_index = reg * 16; 3119 int flags = 0; 3120 3121 if (rdev->family <= CHIP_RS200) { 3122 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) 3123 == (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) 3124 flags |= RADEON_SURF_TILE_COLOR_BOTH; 3125 if (tiling_flags & RADEON_TILING_MACRO) 3126 flags |= RADEON_SURF_TILE_COLOR_MACRO; 3127 /* setting pitch to 0 disables tiling */ 3128 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) 3129 == 0) 3130 pitch = 0; 3131 } else if (rdev->family <= CHIP_RV280) { 3132 if (tiling_flags & (RADEON_TILING_MACRO)) 3133 flags |= R200_SURF_TILE_COLOR_MACRO; 3134 if (tiling_flags & RADEON_TILING_MICRO) 3135 flags |= R200_SURF_TILE_COLOR_MICRO; 3136 } else { 3137 if (tiling_flags & RADEON_TILING_MACRO) 3138 flags |= R300_SURF_TILE_MACRO; 3139 if (tiling_flags & RADEON_TILING_MICRO) 3140 flags |= R300_SURF_TILE_MICRO; 3141 } 3142 3143 if (tiling_flags & RADEON_TILING_SWAP_16BIT) 3144 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP; 3145 if (tiling_flags & RADEON_TILING_SWAP_32BIT) 3146 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP; 3147 3148 /* r100/r200 divide by 16 */ 3149 if (rdev->family < CHIP_R300) 3150 flags |= pitch / 16; 3151 else 3152 flags |= pitch / 8; 3153 3154 3155 DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1); 3156 WREG32(RADEON_SURFACE0_INFO + surf_index, flags); 3157 WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset); 3158 WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1); 3159 return 0; 3160 } 3161 3162 void r100_clear_surface_reg(struct radeon_device *rdev, int reg) 3163 { 3164 int surf_index = reg * 16; 3165 WREG32(RADEON_SURFACE0_INFO + surf_index, 0); 3166 } 3167 3168 void r100_bandwidth_update(struct radeon_device *rdev) 3169 { 3170 fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff; 3171 fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff; 3172 fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff; 3173 uint32_t temp, data, mem_trcd, mem_trp, mem_tras; 3174 fixed20_12 memtcas_ff[8] = { 3175 dfixed_init(1), 3176 dfixed_init(2), 3177 dfixed_init(3), 3178 dfixed_init(0), 3179 dfixed_init_half(1), 3180 dfixed_init_half(2), 3181 dfixed_init(0), 3182 }; 3183 fixed20_12 memtcas_rs480_ff[8] = { 3184 dfixed_init(0), 3185 dfixed_init(1), 3186 dfixed_init(2), 3187 dfixed_init(3), 3188 dfixed_init(0), 3189 dfixed_init_half(1), 3190 dfixed_init_half(2), 3191 dfixed_init_half(3), 3192 }; 3193 fixed20_12 memtcas2_ff[8] = { 3194 dfixed_init(0), 3195 dfixed_init(1), 3196 dfixed_init(2), 3197 dfixed_init(3), 3198 dfixed_init(4), 3199 dfixed_init(5), 3200 dfixed_init(6), 3201 dfixed_init(7), 3202 }; 3203 fixed20_12 memtrbs[8] = { 3204 dfixed_init(1), 3205 dfixed_init_half(1), 3206 dfixed_init(2), 3207 dfixed_init_half(2), 3208 dfixed_init(3), 3209 dfixed_init_half(3), 3210 dfixed_init(4), 3211 dfixed_init_half(4) 3212 }; 3213 fixed20_12 memtrbs_r4xx[8] = { 3214 dfixed_init(4), 3215 dfixed_init(5), 3216 dfixed_init(6), 3217 dfixed_init(7), 3218 dfixed_init(8), 3219 dfixed_init(9), 3220 dfixed_init(10), 3221 dfixed_init(11) 3222 }; 3223 fixed20_12 min_mem_eff; 3224 fixed20_12 mc_latency_sclk, mc_latency_mclk, k1; 3225 fixed20_12 cur_latency_mclk, cur_latency_sclk; 3226 fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate, 3227 disp_drain_rate2, read_return_rate; 3228 fixed20_12 time_disp1_drop_priority; 3229 int c; 3230 int cur_size = 16; /* in octawords */ 3231 int critical_point = 0, critical_point2; 3232 /* uint32_t read_return_rate, time_disp1_drop_priority; */ 3233 int stop_req, max_stop_req; 3234 struct drm_display_mode *mode1 = NULL; 3235 struct drm_display_mode *mode2 = NULL; 3236 uint32_t pixel_bytes1 = 0; 3237 uint32_t pixel_bytes2 = 0; 3238 3239 /* Guess line buffer size to be 8192 pixels */ 3240 u32 lb_size = 8192; 3241 3242 if (!rdev->mode_info.mode_config_initialized) 3243 return; 3244 3245 crit_point_ff.full = 0; 3246 disp_drain_rate.full = 0; 3247 3248 radeon_update_display_priority(rdev); 3249 3250 if (rdev->mode_info.crtcs[0]->base.enabled) { 3251 mode1 = &rdev->mode_info.crtcs[0]->base.mode; 3252 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.primary->fb->bits_per_pixel / 8; 3253 } 3254 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 3255 if (rdev->mode_info.crtcs[1]->base.enabled) { 3256 mode2 = &rdev->mode_info.crtcs[1]->base.mode; 3257 pixel_bytes2 = rdev->mode_info.crtcs[1]->base.primary->fb->bits_per_pixel / 8; 3258 } 3259 } 3260 3261 min_mem_eff.full = dfixed_const_8(0); 3262 /* get modes */ 3263 if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) { 3264 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER); 3265 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT); 3266 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT); 3267 /* check crtc enables */ 3268 if (mode2) 3269 mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT); 3270 if (mode1) 3271 mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT); 3272 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer); 3273 } 3274 3275 /* 3276 * determine is there is enough bw for current mode 3277 */ 3278 sclk_ff = rdev->pm.sclk; 3279 mclk_ff = rdev->pm.mclk; 3280 3281 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1); 3282 temp_ff.full = dfixed_const(temp); 3283 mem_bw.full = dfixed_mul(mclk_ff, temp_ff); 3284 3285 pix_clk.full = 0; 3286 pix_clk2.full = 0; 3287 peak_disp_bw.full = 0; 3288 if (mode1) { 3289 temp_ff.full = dfixed_const(1000); 3290 pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */ 3291 pix_clk.full = dfixed_div(pix_clk, temp_ff); 3292 temp_ff.full = dfixed_const(pixel_bytes1); 3293 peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff); 3294 } 3295 if (mode2) { 3296 temp_ff.full = dfixed_const(1000); 3297 pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */ 3298 pix_clk2.full = dfixed_div(pix_clk2, temp_ff); 3299 temp_ff.full = dfixed_const(pixel_bytes2); 3300 peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff); 3301 } 3302 3303 mem_bw.full = dfixed_mul(mem_bw, min_mem_eff); 3304 if (peak_disp_bw.full >= mem_bw.full) { 3305 DRM_ERROR("You may not have enough display bandwidth for current mode\n" 3306 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n"); 3307 } 3308 3309 /* Get values from the EXT_MEM_CNTL register...converting its contents. */ 3310 temp = RREG32(RADEON_MEM_TIMING_CNTL); 3311 if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */ 3312 mem_trcd = ((temp >> 2) & 0x3) + 1; 3313 mem_trp = ((temp & 0x3)) + 1; 3314 mem_tras = ((temp & 0x70) >> 4) + 1; 3315 } else if (rdev->family == CHIP_R300 || 3316 rdev->family == CHIP_R350) { /* r300, r350 */ 3317 mem_trcd = (temp & 0x7) + 1; 3318 mem_trp = ((temp >> 8) & 0x7) + 1; 3319 mem_tras = ((temp >> 11) & 0xf) + 4; 3320 } else if (rdev->family == CHIP_RV350 || 3321 rdev->family <= CHIP_RV380) { 3322 /* rv3x0 */ 3323 mem_trcd = (temp & 0x7) + 3; 3324 mem_trp = ((temp >> 8) & 0x7) + 3; 3325 mem_tras = ((temp >> 11) & 0xf) + 6; 3326 } else if (rdev->family == CHIP_R420 || 3327 rdev->family == CHIP_R423 || 3328 rdev->family == CHIP_RV410) { 3329 /* r4xx */ 3330 mem_trcd = (temp & 0xf) + 3; 3331 if (mem_trcd > 15) 3332 mem_trcd = 15; 3333 mem_trp = ((temp >> 8) & 0xf) + 3; 3334 if (mem_trp > 15) 3335 mem_trp = 15; 3336 mem_tras = ((temp >> 12) & 0x1f) + 6; 3337 if (mem_tras > 31) 3338 mem_tras = 31; 3339 } else { /* RV200, R200 */ 3340 mem_trcd = (temp & 0x7) + 1; 3341 mem_trp = ((temp >> 8) & 0x7) + 1; 3342 mem_tras = ((temp >> 12) & 0xf) + 4; 3343 } 3344 /* convert to FF */ 3345 trcd_ff.full = dfixed_const(mem_trcd); 3346 trp_ff.full = dfixed_const(mem_trp); 3347 tras_ff.full = dfixed_const(mem_tras); 3348 3349 /* Get values from the MEM_SDRAM_MODE_REG register...converting its */ 3350 temp = RREG32(RADEON_MEM_SDRAM_MODE_REG); 3351 data = (temp & (7 << 20)) >> 20; 3352 if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) { 3353 if (rdev->family == CHIP_RS480) /* don't think rs400 */ 3354 tcas_ff = memtcas_rs480_ff[data]; 3355 else 3356 tcas_ff = memtcas_ff[data]; 3357 } else 3358 tcas_ff = memtcas2_ff[data]; 3359 3360 if (rdev->family == CHIP_RS400 || 3361 rdev->family == CHIP_RS480) { 3362 /* extra cas latency stored in bits 23-25 0-4 clocks */ 3363 data = (temp >> 23) & 0x7; 3364 if (data < 5) 3365 tcas_ff.full += dfixed_const(data); 3366 } 3367 3368 if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) { 3369 /* on the R300, Tcas is included in Trbs. 3370 */ 3371 temp = RREG32(RADEON_MEM_CNTL); 3372 data = (R300_MEM_NUM_CHANNELS_MASK & temp); 3373 if (data == 1) { 3374 if (R300_MEM_USE_CD_CH_ONLY & temp) { 3375 temp = RREG32(R300_MC_IND_INDEX); 3376 temp &= ~R300_MC_IND_ADDR_MASK; 3377 temp |= R300_MC_READ_CNTL_CD_mcind; 3378 WREG32(R300_MC_IND_INDEX, temp); 3379 temp = RREG32(R300_MC_IND_DATA); 3380 data = (R300_MEM_RBS_POSITION_C_MASK & temp); 3381 } else { 3382 temp = RREG32(R300_MC_READ_CNTL_AB); 3383 data = (R300_MEM_RBS_POSITION_A_MASK & temp); 3384 } 3385 } else { 3386 temp = RREG32(R300_MC_READ_CNTL_AB); 3387 data = (R300_MEM_RBS_POSITION_A_MASK & temp); 3388 } 3389 if (rdev->family == CHIP_RV410 || 3390 rdev->family == CHIP_R420 || 3391 rdev->family == CHIP_R423) 3392 trbs_ff = memtrbs_r4xx[data]; 3393 else 3394 trbs_ff = memtrbs[data]; 3395 tcas_ff.full += trbs_ff.full; 3396 } 3397 3398 sclk_eff_ff.full = sclk_ff.full; 3399 3400 if (rdev->flags & RADEON_IS_AGP) { 3401 fixed20_12 agpmode_ff; 3402 agpmode_ff.full = dfixed_const(radeon_agpmode); 3403 temp_ff.full = dfixed_const_666(16); 3404 sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff); 3405 } 3406 /* TODO PCIE lanes may affect this - agpmode == 16?? */ 3407 3408 if (ASIC_IS_R300(rdev)) { 3409 sclk_delay_ff.full = dfixed_const(250); 3410 } else { 3411 if ((rdev->family == CHIP_RV100) || 3412 rdev->flags & RADEON_IS_IGP) { 3413 if (rdev->mc.vram_is_ddr) 3414 sclk_delay_ff.full = dfixed_const(41); 3415 else 3416 sclk_delay_ff.full = dfixed_const(33); 3417 } else { 3418 if (rdev->mc.vram_width == 128) 3419 sclk_delay_ff.full = dfixed_const(57); 3420 else 3421 sclk_delay_ff.full = dfixed_const(41); 3422 } 3423 } 3424 3425 mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff); 3426 3427 if (rdev->mc.vram_is_ddr) { 3428 if (rdev->mc.vram_width == 32) { 3429 k1.full = dfixed_const(40); 3430 c = 3; 3431 } else { 3432 k1.full = dfixed_const(20); 3433 c = 1; 3434 } 3435 } else { 3436 k1.full = dfixed_const(40); 3437 c = 3; 3438 } 3439 3440 temp_ff.full = dfixed_const(2); 3441 mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff); 3442 temp_ff.full = dfixed_const(c); 3443 mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff); 3444 temp_ff.full = dfixed_const(4); 3445 mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff); 3446 mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff); 3447 mc_latency_mclk.full += k1.full; 3448 3449 mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff); 3450 mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff); 3451 3452 /* 3453 HW cursor time assuming worst case of full size colour cursor. 3454 */ 3455 temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1)))); 3456 temp_ff.full += trcd_ff.full; 3457 if (temp_ff.full < tras_ff.full) 3458 temp_ff.full = tras_ff.full; 3459 cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff); 3460 3461 temp_ff.full = dfixed_const(cur_size); 3462 cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff); 3463 /* 3464 Find the total latency for the display data. 3465 */ 3466 disp_latency_overhead.full = dfixed_const(8); 3467 disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff); 3468 mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full; 3469 mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full; 3470 3471 if (mc_latency_mclk.full > mc_latency_sclk.full) 3472 disp_latency.full = mc_latency_mclk.full; 3473 else 3474 disp_latency.full = mc_latency_sclk.full; 3475 3476 /* setup Max GRPH_STOP_REQ default value */ 3477 if (ASIC_IS_RV100(rdev)) 3478 max_stop_req = 0x5c; 3479 else 3480 max_stop_req = 0x7c; 3481 3482 if (mode1) { 3483 /* CRTC1 3484 Set GRPH_BUFFER_CNTL register using h/w defined optimal values. 3485 GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ] 3486 */ 3487 stop_req = mode1->hdisplay * pixel_bytes1 / 16; 3488 3489 if (stop_req > max_stop_req) 3490 stop_req = max_stop_req; 3491 3492 /* 3493 Find the drain rate of the display buffer. 3494 */ 3495 temp_ff.full = dfixed_const((16/pixel_bytes1)); 3496 disp_drain_rate.full = dfixed_div(pix_clk, temp_ff); 3497 3498 /* 3499 Find the critical point of the display buffer. 3500 */ 3501 crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency); 3502 crit_point_ff.full += dfixed_const_half(0); 3503 3504 critical_point = dfixed_trunc(crit_point_ff); 3505 3506 if (rdev->disp_priority == 2) { 3507 critical_point = 0; 3508 } 3509 3510 /* 3511 The critical point should never be above max_stop_req-4. Setting 3512 GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time. 3513 */ 3514 if (max_stop_req - critical_point < 4) 3515 critical_point = 0; 3516 3517 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) { 3518 /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/ 3519 critical_point = 0x10; 3520 } 3521 3522 temp = RREG32(RADEON_GRPH_BUFFER_CNTL); 3523 temp &= ~(RADEON_GRPH_STOP_REQ_MASK); 3524 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); 3525 temp &= ~(RADEON_GRPH_START_REQ_MASK); 3526 if ((rdev->family == CHIP_R350) && 3527 (stop_req > 0x15)) { 3528 stop_req -= 0x10; 3529 } 3530 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT); 3531 temp |= RADEON_GRPH_BUFFER_SIZE; 3532 temp &= ~(RADEON_GRPH_CRITICAL_CNTL | 3533 RADEON_GRPH_CRITICAL_AT_SOF | 3534 RADEON_GRPH_STOP_CNTL); 3535 /* 3536 Write the result into the register. 3537 */ 3538 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) | 3539 (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT))); 3540 3541 #if 0 3542 if ((rdev->family == CHIP_RS400) || 3543 (rdev->family == CHIP_RS480)) { 3544 /* attempt to program RS400 disp regs correctly ??? */ 3545 temp = RREG32(RS400_DISP1_REG_CNTL); 3546 temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK | 3547 RS400_DISP1_STOP_REQ_LEVEL_MASK); 3548 WREG32(RS400_DISP1_REQ_CNTL1, (temp | 3549 (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) | 3550 (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT))); 3551 temp = RREG32(RS400_DMIF_MEM_CNTL1); 3552 temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK | 3553 RS400_DISP1_CRITICAL_POINT_STOP_MASK); 3554 WREG32(RS400_DMIF_MEM_CNTL1, (temp | 3555 (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) | 3556 (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT))); 3557 } 3558 #endif 3559 3560 DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n", 3561 /* (unsigned int)info->SavedReg->grph_buffer_cntl, */ 3562 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL)); 3563 } 3564 3565 if (mode2) { 3566 u32 grph2_cntl; 3567 stop_req = mode2->hdisplay * pixel_bytes2 / 16; 3568 3569 if (stop_req > max_stop_req) 3570 stop_req = max_stop_req; 3571 3572 /* 3573 Find the drain rate of the display buffer. 3574 */ 3575 temp_ff.full = dfixed_const((16/pixel_bytes2)); 3576 disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff); 3577 3578 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL); 3579 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK); 3580 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); 3581 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK); 3582 if ((rdev->family == CHIP_R350) && 3583 (stop_req > 0x15)) { 3584 stop_req -= 0x10; 3585 } 3586 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT); 3587 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE; 3588 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL | 3589 RADEON_GRPH_CRITICAL_AT_SOF | 3590 RADEON_GRPH_STOP_CNTL); 3591 3592 if ((rdev->family == CHIP_RS100) || 3593 (rdev->family == CHIP_RS200)) 3594 critical_point2 = 0; 3595 else { 3596 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128; 3597 temp_ff.full = dfixed_const(temp); 3598 temp_ff.full = dfixed_mul(mclk_ff, temp_ff); 3599 if (sclk_ff.full < temp_ff.full) 3600 temp_ff.full = sclk_ff.full; 3601 3602 read_return_rate.full = temp_ff.full; 3603 3604 if (mode1) { 3605 temp_ff.full = read_return_rate.full - disp_drain_rate.full; 3606 time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff); 3607 } else { 3608 time_disp1_drop_priority.full = 0; 3609 } 3610 crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full; 3611 crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2); 3612 crit_point_ff.full += dfixed_const_half(0); 3613 3614 critical_point2 = dfixed_trunc(crit_point_ff); 3615 3616 if (rdev->disp_priority == 2) { 3617 critical_point2 = 0; 3618 } 3619 3620 if (max_stop_req - critical_point2 < 4) 3621 critical_point2 = 0; 3622 3623 } 3624 3625 if (critical_point2 == 0 && rdev->family == CHIP_R300) { 3626 /* some R300 cards have problem with this set to 0 */ 3627 critical_point2 = 0x10; 3628 } 3629 3630 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) | 3631 (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT))); 3632 3633 if ((rdev->family == CHIP_RS400) || 3634 (rdev->family == CHIP_RS480)) { 3635 #if 0 3636 /* attempt to program RS400 disp2 regs correctly ??? */ 3637 temp = RREG32(RS400_DISP2_REQ_CNTL1); 3638 temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK | 3639 RS400_DISP2_STOP_REQ_LEVEL_MASK); 3640 WREG32(RS400_DISP2_REQ_CNTL1, (temp | 3641 (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) | 3642 (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT))); 3643 temp = RREG32(RS400_DISP2_REQ_CNTL2); 3644 temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK | 3645 RS400_DISP2_CRITICAL_POINT_STOP_MASK); 3646 WREG32(RS400_DISP2_REQ_CNTL2, (temp | 3647 (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) | 3648 (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT))); 3649 #endif 3650 WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC); 3651 WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000); 3652 WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC); 3653 WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC); 3654 } 3655 3656 DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n", 3657 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL)); 3658 } 3659 3660 /* Save number of lines the linebuffer leads before the scanout */ 3661 if (mode1) 3662 rdev->mode_info.crtcs[0]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode1->crtc_hdisplay); 3663 3664 if (mode2) 3665 rdev->mode_info.crtcs[1]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode2->crtc_hdisplay); 3666 } 3667 3668 int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *ring) 3669 { 3670 uint32_t scratch; 3671 uint32_t tmp = 0; 3672 unsigned i; 3673 int r; 3674 3675 r = radeon_scratch_get(rdev, &scratch); 3676 if (r) { 3677 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r); 3678 return r; 3679 } 3680 WREG32(scratch, 0xCAFEDEAD); 3681 r = radeon_ring_lock(rdev, ring, 2); 3682 if (r) { 3683 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); 3684 radeon_scratch_free(rdev, scratch); 3685 return r; 3686 } 3687 radeon_ring_write(ring, PACKET0(scratch, 0)); 3688 radeon_ring_write(ring, 0xDEADBEEF); 3689 radeon_ring_unlock_commit(rdev, ring, false); 3690 for (i = 0; i < rdev->usec_timeout; i++) { 3691 tmp = RREG32(scratch); 3692 if (tmp == 0xDEADBEEF) { 3693 break; 3694 } 3695 DRM_UDELAY(1); 3696 } 3697 if (i < rdev->usec_timeout) { 3698 DRM_INFO("ring test succeeded in %d usecs\n", i); 3699 } else { 3700 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n", 3701 scratch, tmp); 3702 r = -EINVAL; 3703 } 3704 radeon_scratch_free(rdev, scratch); 3705 return r; 3706 } 3707 3708 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) 3709 { 3710 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 3711 3712 if (ring->rptr_save_reg) { 3713 u32 next_rptr = ring->wptr + 2 + 3; 3714 radeon_ring_write(ring, PACKET0(ring->rptr_save_reg, 0)); 3715 radeon_ring_write(ring, next_rptr); 3716 } 3717 3718 radeon_ring_write(ring, PACKET0(RADEON_CP_IB_BASE, 1)); 3719 radeon_ring_write(ring, ib->gpu_addr); 3720 radeon_ring_write(ring, ib->length_dw); 3721 } 3722 3723 int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) 3724 { 3725 struct radeon_ib ib; 3726 uint32_t scratch; 3727 uint32_t tmp = 0; 3728 unsigned i; 3729 int r; 3730 3731 r = radeon_scratch_get(rdev, &scratch); 3732 if (r) { 3733 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r); 3734 return r; 3735 } 3736 WREG32(scratch, 0xCAFEDEAD); 3737 r = radeon_ib_get(rdev, RADEON_RING_TYPE_GFX_INDEX, &ib, NULL, 256); 3738 if (r) { 3739 DRM_ERROR("radeon: failed to get ib (%d).\n", r); 3740 goto free_scratch; 3741 } 3742 ib.ptr[0] = PACKET0(scratch, 0); 3743 ib.ptr[1] = 0xDEADBEEF; 3744 ib.ptr[2] = PACKET2(0); 3745 ib.ptr[3] = PACKET2(0); 3746 ib.ptr[4] = PACKET2(0); 3747 ib.ptr[5] = PACKET2(0); 3748 ib.ptr[6] = PACKET2(0); 3749 ib.ptr[7] = PACKET2(0); 3750 ib.length_dw = 8; 3751 r = radeon_ib_schedule(rdev, &ib, NULL, false); 3752 if (r) { 3753 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); 3754 goto free_ib; 3755 } 3756 r = radeon_fence_wait(ib.fence, false); 3757 if (r) { 3758 DRM_ERROR("radeon: fence wait failed (%d).\n", r); 3759 goto free_ib; 3760 } 3761 for (i = 0; i < rdev->usec_timeout; i++) { 3762 tmp = RREG32(scratch); 3763 if (tmp == 0xDEADBEEF) { 3764 break; 3765 } 3766 DRM_UDELAY(1); 3767 } 3768 if (i < rdev->usec_timeout) { 3769 DRM_INFO("ib test succeeded in %u usecs\n", i); 3770 } else { 3771 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n", 3772 scratch, tmp); 3773 r = -EINVAL; 3774 } 3775 free_ib: 3776 radeon_ib_free(rdev, &ib); 3777 free_scratch: 3778 radeon_scratch_free(rdev, scratch); 3779 return r; 3780 } 3781 3782 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save) 3783 { 3784 /* Shutdown CP we shouldn't need to do that but better be safe than 3785 * sorry 3786 */ 3787 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; 3788 WREG32(R_000740_CP_CSQ_CNTL, 0); 3789 3790 /* Save few CRTC registers */ 3791 save->GENMO_WT = RREG8(R_0003C2_GENMO_WT); 3792 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL); 3793 save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL); 3794 save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET); 3795 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 3796 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL); 3797 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET); 3798 } 3799 3800 /* Disable VGA aperture access */ 3801 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT); 3802 /* Disable cursor, overlay, crtc */ 3803 WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1)); 3804 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL | 3805 S_000054_CRTC_DISPLAY_DIS(1)); 3806 WREG32(R_000050_CRTC_GEN_CNTL, 3807 (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) | 3808 S_000050_CRTC_DISP_REQ_EN_B(1)); 3809 WREG32(R_000420_OV0_SCALE_CNTL, 3810 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL)); 3811 WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET); 3812 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 3813 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET | 3814 S_000360_CUR2_LOCK(1)); 3815 WREG32(R_0003F8_CRTC2_GEN_CNTL, 3816 (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) | 3817 S_0003F8_CRTC2_DISPLAY_DIS(1) | 3818 S_0003F8_CRTC2_DISP_REQ_EN_B(1)); 3819 WREG32(R_000360_CUR2_OFFSET, 3820 C_000360_CUR2_LOCK & save->CUR2_OFFSET); 3821 } 3822 } 3823 3824 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save) 3825 { 3826 /* Update base address for crtc */ 3827 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start); 3828 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 3829 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start); 3830 } 3831 /* Restore CRTC registers */ 3832 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT); 3833 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL); 3834 WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL); 3835 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 3836 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL); 3837 } 3838 } 3839 3840 void r100_vga_render_disable(struct radeon_device *rdev) 3841 { 3842 u32 tmp; 3843 3844 tmp = RREG8(R_0003C2_GENMO_WT); 3845 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp); 3846 } 3847 3848 static void r100_debugfs(struct radeon_device *rdev) 3849 { 3850 int r; 3851 3852 r = r100_debugfs_mc_info_init(rdev); 3853 if (r) 3854 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n"); 3855 } 3856 3857 static void r100_mc_program(struct radeon_device *rdev) 3858 { 3859 struct r100_mc_save save; 3860 3861 /* Stops all mc clients */ 3862 r100_mc_stop(rdev, &save); 3863 if (rdev->flags & RADEON_IS_AGP) { 3864 WREG32(R_00014C_MC_AGP_LOCATION, 3865 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) | 3866 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); 3867 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); 3868 if (rdev->family > CHIP_RV200) 3869 WREG32(R_00015C_AGP_BASE_2, 3870 upper_32_bits(rdev->mc.agp_base) & 0xff); 3871 } else { 3872 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF); 3873 WREG32(R_000170_AGP_BASE, 0); 3874 if (rdev->family > CHIP_RV200) 3875 WREG32(R_00015C_AGP_BASE_2, 0); 3876 } 3877 /* Wait for mc idle */ 3878 if (r100_mc_wait_for_idle(rdev)) 3879 dev_warn(rdev->dev, "Wait for MC idle timeout.\n"); 3880 /* Program MC, should be a 32bits limited address space */ 3881 WREG32(R_000148_MC_FB_LOCATION, 3882 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | 3883 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); 3884 r100_mc_resume(rdev, &save); 3885 } 3886 3887 static void r100_clock_startup(struct radeon_device *rdev) 3888 { 3889 u32 tmp; 3890 3891 if (radeon_dynclks != -1 && radeon_dynclks) 3892 radeon_legacy_set_clock_gating(rdev, 1); 3893 /* We need to force on some of the block */ 3894 tmp = RREG32_PLL(R_00000D_SCLK_CNTL); 3895 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1); 3896 if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280)) 3897 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1); 3898 WREG32_PLL(R_00000D_SCLK_CNTL, tmp); 3899 } 3900 3901 static int r100_startup(struct radeon_device *rdev) 3902 { 3903 int r; 3904 3905 /* set common regs */ 3906 r100_set_common_regs(rdev); 3907 /* program mc */ 3908 r100_mc_program(rdev); 3909 /* Resume clock */ 3910 r100_clock_startup(rdev); 3911 /* Initialize GART (initialize after TTM so we can allocate 3912 * memory through TTM but finalize after TTM) */ 3913 r100_enable_bm(rdev); 3914 if (rdev->flags & RADEON_IS_PCI) { 3915 r = r100_pci_gart_enable(rdev); 3916 if (r) 3917 return r; 3918 } 3919 3920 /* allocate wb buffer */ 3921 r = radeon_wb_init(rdev); 3922 if (r) 3923 return r; 3924 3925 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 3926 if (r) { 3927 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 3928 return r; 3929 } 3930 3931 /* Enable IRQ */ 3932 if (!rdev->irq.installed) { 3933 r = radeon_irq_kms_init(rdev); 3934 if (r) 3935 return r; 3936 } 3937 3938 r100_irq_set(rdev); 3939 rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 3940 /* 1M ring buffer */ 3941 r = r100_cp_init(rdev, 1024 * 1024); 3942 if (r) { 3943 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); 3944 return r; 3945 } 3946 3947 r = radeon_ib_pool_init(rdev); 3948 if (r) { 3949 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 3950 return r; 3951 } 3952 3953 return 0; 3954 } 3955 3956 int r100_resume(struct radeon_device *rdev) 3957 { 3958 int r; 3959 3960 /* Make sur GART are not working */ 3961 if (rdev->flags & RADEON_IS_PCI) 3962 r100_pci_gart_disable(rdev); 3963 /* Resume clock before doing reset */ 3964 r100_clock_startup(rdev); 3965 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 3966 if (radeon_asic_reset(rdev)) { 3967 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 3968 RREG32(R_000E40_RBBM_STATUS), 3969 RREG32(R_0007C0_CP_STAT)); 3970 } 3971 /* post */ 3972 radeon_combios_asic_init(rdev->ddev); 3973 /* Resume clock after posting */ 3974 r100_clock_startup(rdev); 3975 /* Initialize surface registers */ 3976 radeon_surface_init(rdev); 3977 3978 rdev->accel_working = true; 3979 r = r100_startup(rdev); 3980 if (r) { 3981 rdev->accel_working = false; 3982 } 3983 return r; 3984 } 3985 3986 int r100_suspend(struct radeon_device *rdev) 3987 { 3988 radeon_pm_suspend(rdev); 3989 r100_cp_disable(rdev); 3990 radeon_wb_disable(rdev); 3991 r100_irq_disable(rdev); 3992 if (rdev->flags & RADEON_IS_PCI) 3993 r100_pci_gart_disable(rdev); 3994 return 0; 3995 } 3996 3997 void r100_fini(struct radeon_device *rdev) 3998 { 3999 radeon_pm_fini(rdev); 4000 r100_cp_fini(rdev); 4001 radeon_wb_fini(rdev); 4002 radeon_ib_pool_fini(rdev); 4003 radeon_gem_fini(rdev); 4004 if (rdev->flags & RADEON_IS_PCI) 4005 r100_pci_gart_fini(rdev); 4006 radeon_agp_fini(rdev); 4007 radeon_irq_kms_fini(rdev); 4008 radeon_fence_driver_fini(rdev); 4009 radeon_bo_fini(rdev); 4010 radeon_atombios_fini(rdev); 4011 kfree(rdev->bios); 4012 rdev->bios = NULL; 4013 } 4014 4015 /* 4016 * Due to how kexec works, it can leave the hw fully initialised when it 4017 * boots the new kernel. However doing our init sequence with the CP and 4018 * WB stuff setup causes GPU hangs on the RN50 at least. So at startup 4019 * do some quick sanity checks and restore sane values to avoid this 4020 * problem. 4021 */ 4022 void r100_restore_sanity(struct radeon_device *rdev) 4023 { 4024 u32 tmp; 4025 4026 tmp = RREG32(RADEON_CP_CSQ_CNTL); 4027 if (tmp) { 4028 WREG32(RADEON_CP_CSQ_CNTL, 0); 4029 } 4030 tmp = RREG32(RADEON_CP_RB_CNTL); 4031 if (tmp) { 4032 WREG32(RADEON_CP_RB_CNTL, 0); 4033 } 4034 tmp = RREG32(RADEON_SCRATCH_UMSK); 4035 if (tmp) { 4036 WREG32(RADEON_SCRATCH_UMSK, 0); 4037 } 4038 } 4039 4040 int r100_init(struct radeon_device *rdev) 4041 { 4042 int r; 4043 4044 /* Register debugfs file specific to this group of asics */ 4045 r100_debugfs(rdev); 4046 /* Disable VGA */ 4047 r100_vga_render_disable(rdev); 4048 /* Initialize scratch registers */ 4049 radeon_scratch_init(rdev); 4050 /* Initialize surface registers */ 4051 radeon_surface_init(rdev); 4052 /* sanity check some register to avoid hangs like after kexec */ 4053 r100_restore_sanity(rdev); 4054 /* TODO: disable VGA need to use VGA request */ 4055 /* BIOS*/ 4056 if (!radeon_get_bios(rdev)) { 4057 if (ASIC_IS_AVIVO(rdev)) 4058 return -EINVAL; 4059 } 4060 if (rdev->is_atom_bios) { 4061 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n"); 4062 return -EINVAL; 4063 } else { 4064 r = radeon_combios_init(rdev); 4065 if (r) 4066 return r; 4067 } 4068 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 4069 if (radeon_asic_reset(rdev)) { 4070 dev_warn(rdev->dev, 4071 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 4072 RREG32(R_000E40_RBBM_STATUS), 4073 RREG32(R_0007C0_CP_STAT)); 4074 } 4075 /* check if cards are posted or not */ 4076 if (radeon_boot_test_post_card(rdev) == false) 4077 return -EINVAL; 4078 /* Set asic errata */ 4079 r100_errata(rdev); 4080 /* Initialize clocks */ 4081 radeon_get_clock_info(rdev->ddev); 4082 /* initialize AGP */ 4083 if (rdev->flags & RADEON_IS_AGP) { 4084 r = radeon_agp_init(rdev); 4085 if (r) { 4086 radeon_agp_disable(rdev); 4087 } 4088 } 4089 /* initialize VRAM */ 4090 r100_mc_init(rdev); 4091 /* Fence driver */ 4092 r = radeon_fence_driver_init(rdev); 4093 if (r) 4094 return r; 4095 /* Memory manager */ 4096 r = radeon_bo_init(rdev); 4097 if (r) 4098 return r; 4099 if (rdev->flags & RADEON_IS_PCI) { 4100 r = r100_pci_gart_init(rdev); 4101 if (r) 4102 return r; 4103 } 4104 r100_set_safe_registers(rdev); 4105 4106 /* Initialize power management */ 4107 radeon_pm_init(rdev); 4108 4109 rdev->accel_working = true; 4110 r = r100_startup(rdev); 4111 if (r) { 4112 /* Somethings want wront with the accel init stop accel */ 4113 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 4114 r100_cp_fini(rdev); 4115 radeon_wb_fini(rdev); 4116 radeon_ib_pool_fini(rdev); 4117 radeon_irq_kms_fini(rdev); 4118 if (rdev->flags & RADEON_IS_PCI) 4119 r100_pci_gart_fini(rdev); 4120 rdev->accel_working = false; 4121 } 4122 return 0; 4123 } 4124 4125 uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg) 4126 { 4127 unsigned long flags; 4128 uint32_t ret; 4129 4130 spin_lock_irqsave(&rdev->mmio_idx_lock, flags); 4131 #ifdef __NetBSD__ 4132 bus_space_write_4(rdev->rmmio_bst, rdev->rmmio_bsh, 4133 RADEON_MM_INDEX, reg); 4134 ret = bus_space_read_4(rdev->rmmio_bst, rdev->rmmio_bsh, 4135 RADEON_MM_DATA); 4136 #else 4137 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); 4138 ret = readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); 4139 #endif 4140 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags); 4141 return ret; 4142 } 4143 4144 void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v) 4145 { 4146 unsigned long flags; 4147 4148 spin_lock_irqsave(&rdev->mmio_idx_lock, flags); 4149 #ifdef __NetBSD__ 4150 bus_space_write_4(rdev->rmmio_bst, rdev->rmmio_bsh, 4151 RADEON_MM_INDEX, reg); 4152 bus_space_write_4(rdev->rmmio_bst, rdev->rmmio_bsh, 4153 RADEON_MM_DATA, v); 4154 #else 4155 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); 4156 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); 4157 #endif 4158 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags); 4159 } 4160 4161 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg) 4162 { 4163 #ifdef __NetBSD__ 4164 if (reg < rdev->rio_mem_size) { 4165 return bus_space_read_4(rdev->rio_mem_bst, rdev->rio_mem_bsh, 4166 reg); 4167 } else { 4168 bus_space_write_4(rdev->rio_mem_bst, rdev->rio_mem_bsh, 4169 RADEON_MM_INDEX, reg); 4170 return bus_space_read_4(rdev->rio_mem_bst, rdev->rio_mem_bsh, 4171 RADEON_MM_DATA); 4172 } 4173 #else 4174 if (reg < rdev->rio_mem_size) 4175 return ioread32(rdev->rio_mem + reg); 4176 else { 4177 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX); 4178 return ioread32(rdev->rio_mem + RADEON_MM_DATA); 4179 } 4180 #endif 4181 } 4182 4183 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v) 4184 { 4185 #ifdef __NetBSD__ 4186 if (reg < rdev->rio_mem_size) { 4187 bus_space_write_4(rdev->rio_mem_bst, rdev->rio_mem_bsh, reg, 4188 v); 4189 } else { 4190 bus_space_write_4(rdev->rio_mem_bst, rdev->rio_mem_bsh, 4191 RADEON_MM_INDEX, reg); 4192 bus_space_write_4(rdev->rio_mem_bst, rdev->rio_mem_bsh, 4193 RADEON_MM_DATA, v); 4194 } 4195 #else 4196 if (reg < rdev->rio_mem_size) 4197 iowrite32(v, rdev->rio_mem + reg); 4198 else { 4199 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX); 4200 iowrite32(v, rdev->rio_mem + RADEON_MM_DATA); 4201 } 4202 #endif 4203 } 4204
Indexes created Thu Oct 23 22:10:10 GMT 2025