radeon_r420.c revision 1.1
1 /* $NetBSD: radeon_r420.c,v 1.1 2018/08/27 14:38:20 riastradh Exp $ */ 2 3 /* 4 * Copyright 2008 Advanced Micro Devices, Inc. 5 * Copyright 2008 Red Hat Inc. 6 * Copyright 2009 Jerome Glisse. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: Dave Airlie 27 * Alex Deucher 28 * Jerome Glisse 29 */ 30 #include <sys/cdefs.h> 31 __KERNEL_RCSID(0, "$NetBSD: radeon_r420.c,v 1.1 2018/08/27 14:38:20 riastradh Exp $"); 32 33 #include <linux/seq_file.h> 34 #include <linux/slab.h> 35 #include <drm/drmP.h> 36 #include "radeon_reg.h" 37 #include "radeon.h" 38 #include "radeon_asic.h" 39 #include "atom.h" 40 #include "r100d.h" 41 #include "r420d.h" 42 #include "r420_reg_safe.h" 43 44 void r420_pm_init_profile(struct radeon_device *rdev) 45 { 46 /* default */ 47 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 48 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 49 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 50 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 51 /* low sh */ 52 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0; 53 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0; 54 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 55 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 56 /* mid sh */ 57 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0; 58 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; 59 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 60 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 61 /* high sh */ 62 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0; 63 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 64 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 65 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 66 /* low mh */ 67 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0; 68 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 69 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 70 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 71 /* mid mh */ 72 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0; 73 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 74 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 75 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 76 /* high mh */ 77 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0; 78 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 79 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 80 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 81 } 82 83 static void r420_set_reg_safe(struct radeon_device *rdev) 84 { 85 rdev->config.r300.reg_safe_bm = r420_reg_safe_bm; 86 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r420_reg_safe_bm); 87 } 88 89 void r420_pipes_init(struct radeon_device *rdev) 90 { 91 unsigned tmp; 92 unsigned gb_pipe_select; 93 unsigned num_pipes; 94 95 /* GA_ENHANCE workaround TCL deadlock issue */ 96 WREG32(R300_GA_ENHANCE, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL | 97 (1 << 2) | (1 << 3)); 98 /* add idle wait as per freedesktop.org bug 24041 */ 99 if (r100_gui_wait_for_idle(rdev)) { 100 printk(KERN_WARNING "Failed to wait GUI idle while " 101 "programming pipes. Bad things might happen.\n"); 102 } 103 /* get max number of pipes */ 104 gb_pipe_select = RREG32(R400_GB_PIPE_SELECT); 105 num_pipes = ((gb_pipe_select >> 12) & 3) + 1; 106 107 /* SE chips have 1 pipe */ 108 if ((rdev->pdev->device == 0x5e4c) || 109 (rdev->pdev->device == 0x5e4f)) 110 num_pipes = 1; 111 112 rdev->num_gb_pipes = num_pipes; 113 tmp = 0; 114 switch (num_pipes) { 115 default: 116 /* force to 1 pipe */ 117 num_pipes = 1; 118 case 1: 119 tmp = (0 << 1); 120 break; 121 case 2: 122 tmp = (3 << 1); 123 break; 124 case 3: 125 tmp = (6 << 1); 126 break; 127 case 4: 128 tmp = (7 << 1); 129 break; 130 } 131 WREG32(R500_SU_REG_DEST, (1 << num_pipes) - 1); 132 /* Sub pixel 1/12 so we can have 4K rendering according to doc */ 133 tmp |= R300_TILE_SIZE_16 | R300_ENABLE_TILING; 134 WREG32(R300_GB_TILE_CONFIG, tmp); 135 if (r100_gui_wait_for_idle(rdev)) { 136 printk(KERN_WARNING "Failed to wait GUI idle while " 137 "programming pipes. Bad things might happen.\n"); 138 } 139 140 tmp = RREG32(R300_DST_PIPE_CONFIG); 141 WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG); 142 143 WREG32(R300_RB2D_DSTCACHE_MODE, 144 RREG32(R300_RB2D_DSTCACHE_MODE) | 145 R300_DC_AUTOFLUSH_ENABLE | 146 R300_DC_DC_DISABLE_IGNORE_PE); 147 148 if (r100_gui_wait_for_idle(rdev)) { 149 printk(KERN_WARNING "Failed to wait GUI idle while " 150 "programming pipes. Bad things might happen.\n"); 151 } 152 153 if (rdev->family == CHIP_RV530) { 154 tmp = RREG32(RV530_GB_PIPE_SELECT2); 155 if ((tmp & 3) == 3) 156 rdev->num_z_pipes = 2; 157 else 158 rdev->num_z_pipes = 1; 159 } else 160 rdev->num_z_pipes = 1; 161 162 DRM_INFO("radeon: %d quad pipes, %d z pipes initialized.\n", 163 rdev->num_gb_pipes, rdev->num_z_pipes); 164 } 165 166 u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg) 167 { 168 unsigned long flags; 169 u32 r; 170 171 spin_lock_irqsave(&rdev->mc_idx_lock, flags); 172 WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg)); 173 r = RREG32(R_0001FC_MC_IND_DATA); 174 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); 175 return r; 176 } 177 178 void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v) 179 { 180 unsigned long flags; 181 182 spin_lock_irqsave(&rdev->mc_idx_lock, flags); 183 WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg) | 184 S_0001F8_MC_IND_WR_EN(1)); 185 WREG32(R_0001FC_MC_IND_DATA, v); 186 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); 187 } 188 189 static void r420_debugfs(struct radeon_device *rdev) 190 { 191 if (r100_debugfs_rbbm_init(rdev)) { 192 DRM_ERROR("Failed to register debugfs file for RBBM !\n"); 193 } 194 if (r420_debugfs_pipes_info_init(rdev)) { 195 DRM_ERROR("Failed to register debugfs file for pipes !\n"); 196 } 197 } 198 199 static void r420_clock_resume(struct radeon_device *rdev) 200 { 201 u32 sclk_cntl; 202 203 if (radeon_dynclks != -1 && radeon_dynclks) 204 radeon_atom_set_clock_gating(rdev, 1); 205 sclk_cntl = RREG32_PLL(R_00000D_SCLK_CNTL); 206 sclk_cntl |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1); 207 if (rdev->family == CHIP_R420) 208 sclk_cntl |= S_00000D_FORCE_PX(1) | S_00000D_FORCE_TX(1); 209 WREG32_PLL(R_00000D_SCLK_CNTL, sclk_cntl); 210 } 211 212 static void r420_cp_errata_init(struct radeon_device *rdev) 213 { 214 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 215 216 /* RV410 and R420 can lock up if CP DMA to host memory happens 217 * while the 2D engine is busy. 218 * 219 * The proper workaround is to queue a RESYNC at the beginning 220 * of the CP init, apparently. 221 */ 222 radeon_scratch_get(rdev, &rdev->config.r300.resync_scratch); 223 radeon_ring_lock(rdev, ring, 8); 224 radeon_ring_write(ring, PACKET0(R300_CP_RESYNC_ADDR, 1)); 225 radeon_ring_write(ring, rdev->config.r300.resync_scratch); 226 radeon_ring_write(ring, 0xDEADBEEF); 227 radeon_ring_unlock_commit(rdev, ring, false); 228 } 229 230 static void r420_cp_errata_fini(struct radeon_device *rdev) 231 { 232 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 233 234 /* Catch the RESYNC we dispatched all the way back, 235 * at the very beginning of the CP init. 236 */ 237 radeon_ring_lock(rdev, ring, 8); 238 radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); 239 radeon_ring_write(ring, R300_RB3D_DC_FINISH); 240 radeon_ring_unlock_commit(rdev, ring, false); 241 radeon_scratch_free(rdev, rdev->config.r300.resync_scratch); 242 } 243 244 static int r420_startup(struct radeon_device *rdev) 245 { 246 int r; 247 248 /* set common regs */ 249 r100_set_common_regs(rdev); 250 /* program mc */ 251 r300_mc_program(rdev); 252 /* Resume clock */ 253 r420_clock_resume(rdev); 254 /* Initialize GART (initialize after TTM so we can allocate 255 * memory through TTM but finalize after TTM) */ 256 if (rdev->flags & RADEON_IS_PCIE) { 257 r = rv370_pcie_gart_enable(rdev); 258 if (r) 259 return r; 260 } 261 if (rdev->flags & RADEON_IS_PCI) { 262 r = r100_pci_gart_enable(rdev); 263 if (r) 264 return r; 265 } 266 r420_pipes_init(rdev); 267 268 /* allocate wb buffer */ 269 r = radeon_wb_init(rdev); 270 if (r) 271 return r; 272 273 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 274 if (r) { 275 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 276 return r; 277 } 278 279 /* Enable IRQ */ 280 if (!rdev->irq.installed) { 281 r = radeon_irq_kms_init(rdev); 282 if (r) 283 return r; 284 } 285 286 r100_irq_set(rdev); 287 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 288 /* 1M ring buffer */ 289 r = r100_cp_init(rdev, 1024 * 1024); 290 if (r) { 291 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); 292 return r; 293 } 294 r420_cp_errata_init(rdev); 295 296 r = radeon_ib_pool_init(rdev); 297 if (r) { 298 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 299 return r; 300 } 301 302 return 0; 303 } 304 305 int r420_resume(struct radeon_device *rdev) 306 { 307 int r; 308 309 /* Make sur GART are not working */ 310 if (rdev->flags & RADEON_IS_PCIE) 311 rv370_pcie_gart_disable(rdev); 312 if (rdev->flags & RADEON_IS_PCI) 313 r100_pci_gart_disable(rdev); 314 /* Resume clock before doing reset */ 315 r420_clock_resume(rdev); 316 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 317 if (radeon_asic_reset(rdev)) { 318 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 319 RREG32(R_000E40_RBBM_STATUS), 320 RREG32(R_0007C0_CP_STAT)); 321 } 322 /* check if cards are posted or not */ 323 if (rdev->is_atom_bios) { 324 atom_asic_init(rdev->mode_info.atom_context); 325 } else { 326 radeon_combios_asic_init(rdev->ddev); 327 } 328 /* Resume clock after posting */ 329 r420_clock_resume(rdev); 330 /* Initialize surface registers */ 331 radeon_surface_init(rdev); 332 333 rdev->accel_working = true; 334 r = r420_startup(rdev); 335 if (r) { 336 rdev->accel_working = false; 337 } 338 return r; 339 } 340 341 int r420_suspend(struct radeon_device *rdev) 342 { 343 radeon_pm_suspend(rdev); 344 r420_cp_errata_fini(rdev); 345 r100_cp_disable(rdev); 346 radeon_wb_disable(rdev); 347 r100_irq_disable(rdev); 348 if (rdev->flags & RADEON_IS_PCIE) 349 rv370_pcie_gart_disable(rdev); 350 if (rdev->flags & RADEON_IS_PCI) 351 r100_pci_gart_disable(rdev); 352 return 0; 353 } 354 355 void r420_fini(struct radeon_device *rdev) 356 { 357 radeon_pm_fini(rdev); 358 r100_cp_fini(rdev); 359 radeon_wb_fini(rdev); 360 radeon_ib_pool_fini(rdev); 361 radeon_gem_fini(rdev); 362 if (rdev->flags & RADEON_IS_PCIE) 363 rv370_pcie_gart_fini(rdev); 364 if (rdev->flags & RADEON_IS_PCI) 365 r100_pci_gart_fini(rdev); 366 radeon_agp_fini(rdev); 367 radeon_irq_kms_fini(rdev); 368 radeon_fence_driver_fini(rdev); 369 radeon_bo_fini(rdev); 370 if (rdev->is_atom_bios) { 371 radeon_atombios_fini(rdev); 372 } else { 373 radeon_combios_fini(rdev); 374 } 375 kfree(rdev->bios); 376 rdev->bios = NULL; 377 } 378 379 int r420_init(struct radeon_device *rdev) 380 { 381 int r; 382 383 /* Initialize scratch registers */ 384 radeon_scratch_init(rdev); 385 /* Initialize surface registers */ 386 radeon_surface_init(rdev); 387 /* TODO: disable VGA need to use VGA request */ 388 /* restore some register to sane defaults */ 389 r100_restore_sanity(rdev); 390 /* BIOS*/ 391 if (!radeon_get_bios(rdev)) { 392 if (ASIC_IS_AVIVO(rdev)) 393 return -EINVAL; 394 } 395 if (rdev->is_atom_bios) { 396 r = radeon_atombios_init(rdev); 397 if (r) { 398 return r; 399 } 400 } else { 401 r = radeon_combios_init(rdev); 402 if (r) { 403 return r; 404 } 405 } 406 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 407 if (radeon_asic_reset(rdev)) { 408 dev_warn(rdev->dev, 409 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 410 RREG32(R_000E40_RBBM_STATUS), 411 RREG32(R_0007C0_CP_STAT)); 412 } 413 /* check if cards are posted or not */ 414 if (radeon_boot_test_post_card(rdev) == false) 415 return -EINVAL; 416 417 /* Initialize clocks */ 418 radeon_get_clock_info(rdev->ddev); 419 /* initialize AGP */ 420 if (rdev->flags & RADEON_IS_AGP) { 421 r = radeon_agp_init(rdev); 422 if (r) { 423 radeon_agp_disable(rdev); 424 } 425 } 426 /* initialize memory controller */ 427 r300_mc_init(rdev); 428 r420_debugfs(rdev); 429 /* Fence driver */ 430 r = radeon_fence_driver_init(rdev); 431 if (r) { 432 return r; 433 } 434 /* Memory manager */ 435 r = radeon_bo_init(rdev); 436 if (r) { 437 return r; 438 } 439 if (rdev->family == CHIP_R420) 440 r100_enable_bm(rdev); 441 442 if (rdev->flags & RADEON_IS_PCIE) { 443 r = rv370_pcie_gart_init(rdev); 444 if (r) 445 return r; 446 } 447 if (rdev->flags & RADEON_IS_PCI) { 448 r = r100_pci_gart_init(rdev); 449 if (r) 450 return r; 451 } 452 r420_set_reg_safe(rdev); 453 454 /* Initialize power management */ 455 radeon_pm_init(rdev); 456 457 rdev->accel_working = true; 458 r = r420_startup(rdev); 459 if (r) { 460 /* Somethings want wront with the accel init stop accel */ 461 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 462 r100_cp_fini(rdev); 463 radeon_wb_fini(rdev); 464 radeon_ib_pool_fini(rdev); 465 radeon_irq_kms_fini(rdev); 466 if (rdev->flags & RADEON_IS_PCIE) 467 rv370_pcie_gart_fini(rdev); 468 if (rdev->flags & RADEON_IS_PCI) 469 r100_pci_gart_fini(rdev); 470 radeon_agp_fini(rdev); 471 rdev->accel_working = false; 472 } 473 return 0; 474 } 475 476 /* 477 * Debugfs info 478 */ 479 #if defined(CONFIG_DEBUG_FS) 480 static int r420_debugfs_pipes_info(struct seq_file *m, void *data) 481 { 482 struct drm_info_node *node = (struct drm_info_node *) m->private; 483 struct drm_device *dev = node->minor->dev; 484 struct radeon_device *rdev = dev->dev_private; 485 uint32_t tmp; 486 487 tmp = RREG32(R400_GB_PIPE_SELECT); 488 seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp); 489 tmp = RREG32(R300_GB_TILE_CONFIG); 490 seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp); 491 tmp = RREG32(R300_DST_PIPE_CONFIG); 492 seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp); 493 return 0; 494 } 495 496 static struct drm_info_list r420_pipes_info_list[] = { 497 {"r420_pipes_info", r420_debugfs_pipes_info, 0, NULL}, 498 }; 499 #endif 500 501 int r420_debugfs_pipes_info_init(struct radeon_device *rdev) 502 { 503 #if defined(CONFIG_DEBUG_FS) 504 return radeon_debugfs_add_files(rdev, r420_pipes_info_list, 1); 505 #else 506 return 0; 507 #endif 508 } 509
Indexes created Tue Oct 28 12:10:06 GMT 2025