radeon_r420.c revision 1.2.4.2
1 /* $NetBSD: radeon_r420.c,v 1.2.4.2 2019/06/10 22:08:26 christos Exp $ */ 2 3 /* 4 * Copyright 2008 Advanced Micro Devices, Inc. 5 * Copyright 2008 Red Hat Inc. 6 * Copyright 2009 Jerome Glisse. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: Dave Airlie 27 * Alex Deucher 28 * Jerome Glisse 29 */ 30 #include <sys/cdefs.h> 31 __KERNEL_RCSID(0, "$NetBSD: radeon_r420.c,v 1.2.4.2 2019/06/10 22:08:26 christos Exp $"); 32 33 #include <linux/seq_file.h> 34 #include <linux/slab.h> 35 #include <drm/drmP.h> 36 #include "radeon_reg.h" 37 #include "radeon.h" 38 #include "radeon_asic.h" 39 #include "atom.h" 40 #include "r100d.h" 41 #include "r420d.h" 42 #include "r420_reg_safe.h" 43 44 void r420_pm_init_profile(struct radeon_device *rdev) 45 { 46 /* default */ 47 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 48 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 49 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 50 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 51 /* low sh */ 52 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0; 53 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0; 54 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 55 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 56 /* mid sh */ 57 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0; 58 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; 59 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 60 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 61 /* high sh */ 62 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0; 63 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 64 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 65 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 66 /* low mh */ 67 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0; 68 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 69 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 70 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 71 /* mid mh */ 72 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0; 73 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 74 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 75 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 76 /* high mh */ 77 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0; 78 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 79 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 80 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 81 } 82 83 static void r420_set_reg_safe(struct radeon_device *rdev) 84 { 85 rdev->config.r300.reg_safe_bm = r420_reg_safe_bm; 86 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r420_reg_safe_bm); 87 } 88 89 void r420_pipes_init(struct radeon_device *rdev) 90 { 91 unsigned tmp; 92 unsigned gb_pipe_select; 93 unsigned num_pipes; 94 95 /* GA_ENHANCE workaround TCL deadlock issue */ 96 WREG32(R300_GA_ENHANCE, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL | 97 (1 << 2) | (1 << 3)); 98 /* add idle wait as per freedesktop.org bug 24041 */ 99 if (r100_gui_wait_for_idle(rdev)) { 100 printk(KERN_WARNING "Failed to wait GUI idle while " 101 "programming pipes. Bad things might happen.\n"); 102 } 103 /* get max number of pipes */ 104 gb_pipe_select = RREG32(R400_GB_PIPE_SELECT); 105 num_pipes = ((gb_pipe_select >> 12) & 3) + 1; 106 107 /* SE chips have 1 pipe */ 108 if ((rdev->pdev->device == 0x5e4c) || 109 (rdev->pdev->device == 0x5e4f)) 110 num_pipes = 1; 111 112 rdev->num_gb_pipes = num_pipes; 113 tmp = 0; 114 switch (num_pipes) { 115 default: 116 /* force to 1 pipe */ 117 num_pipes = 1; 118 /* FALLTHROUGH */ 119 case 1: 120 tmp = (0 << 1); 121 break; 122 case 2: 123 tmp = (3 << 1); 124 break; 125 case 3: 126 tmp = (6 << 1); 127 break; 128 case 4: 129 tmp = (7 << 1); 130 break; 131 } 132 WREG32(R500_SU_REG_DEST, (1 << num_pipes) - 1); 133 /* Sub pixel 1/12 so we can have 4K rendering according to doc */ 134 tmp |= R300_TILE_SIZE_16 | R300_ENABLE_TILING; 135 WREG32(R300_GB_TILE_CONFIG, tmp); 136 if (r100_gui_wait_for_idle(rdev)) { 137 printk(KERN_WARNING "Failed to wait GUI idle while " 138 "programming pipes. Bad things might happen.\n"); 139 } 140 141 tmp = RREG32(R300_DST_PIPE_CONFIG); 142 WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG); 143 144 WREG32(R300_RB2D_DSTCACHE_MODE, 145 RREG32(R300_RB2D_DSTCACHE_MODE) | 146 R300_DC_AUTOFLUSH_ENABLE | 147 R300_DC_DC_DISABLE_IGNORE_PE); 148 149 if (r100_gui_wait_for_idle(rdev)) { 150 printk(KERN_WARNING "Failed to wait GUI idle while " 151 "programming pipes. Bad things might happen.\n"); 152 } 153 154 if (rdev->family == CHIP_RV530) { 155 tmp = RREG32(RV530_GB_PIPE_SELECT2); 156 if ((tmp & 3) == 3) 157 rdev->num_z_pipes = 2; 158 else 159 rdev->num_z_pipes = 1; 160 } else 161 rdev->num_z_pipes = 1; 162 163 DRM_INFO("radeon: %d quad pipes, %d z pipes initialized.\n", 164 rdev->num_gb_pipes, rdev->num_z_pipes); 165 } 166 167 u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg) 168 { 169 unsigned long flags; 170 u32 r; 171 172 spin_lock_irqsave(&rdev->mc_idx_lock, flags); 173 WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg)); 174 r = RREG32(R_0001FC_MC_IND_DATA); 175 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); 176 return r; 177 } 178 179 void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v) 180 { 181 unsigned long flags; 182 183 spin_lock_irqsave(&rdev->mc_idx_lock, flags); 184 WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg) | 185 S_0001F8_MC_IND_WR_EN(1)); 186 WREG32(R_0001FC_MC_IND_DATA, v); 187 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); 188 } 189 190 static void r420_debugfs(struct radeon_device *rdev) 191 { 192 if (r100_debugfs_rbbm_init(rdev)) { 193 DRM_ERROR("Failed to register debugfs file for RBBM !\n"); 194 } 195 if (r420_debugfs_pipes_info_init(rdev)) { 196 DRM_ERROR("Failed to register debugfs file for pipes !\n"); 197 } 198 } 199 200 static void r420_clock_resume(struct radeon_device *rdev) 201 { 202 u32 sclk_cntl; 203 204 if (radeon_dynclks != -1 && radeon_dynclks) 205 radeon_atom_set_clock_gating(rdev, 1); 206 sclk_cntl = RREG32_PLL(R_00000D_SCLK_CNTL); 207 sclk_cntl |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1); 208 if (rdev->family == CHIP_R420) 209 sclk_cntl |= S_00000D_FORCE_PX(1) | S_00000D_FORCE_TX(1); 210 WREG32_PLL(R_00000D_SCLK_CNTL, sclk_cntl); 211 } 212 213 static void r420_cp_errata_init(struct radeon_device *rdev) 214 { 215 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 216 217 /* RV410 and R420 can lock up if CP DMA to host memory happens 218 * while the 2D engine is busy. 219 * 220 * The proper workaround is to queue a RESYNC at the beginning 221 * of the CP init, apparently. 222 */ 223 radeon_scratch_get(rdev, &rdev->config.r300.resync_scratch); 224 radeon_ring_lock(rdev, ring, 8); 225 radeon_ring_write(ring, PACKET0(R300_CP_RESYNC_ADDR, 1)); 226 radeon_ring_write(ring, rdev->config.r300.resync_scratch); 227 radeon_ring_write(ring, 0xDEADBEEF); 228 radeon_ring_unlock_commit(rdev, ring, false); 229 } 230 231 static void r420_cp_errata_fini(struct radeon_device *rdev) 232 { 233 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 234 235 /* Catch the RESYNC we dispatched all the way back, 236 * at the very beginning of the CP init. 237 */ 238 radeon_ring_lock(rdev, ring, 8); 239 radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); 240 radeon_ring_write(ring, R300_RB3D_DC_FINISH); 241 radeon_ring_unlock_commit(rdev, ring, false); 242 radeon_scratch_free(rdev, rdev->config.r300.resync_scratch); 243 } 244 245 static int r420_startup(struct radeon_device *rdev) 246 { 247 int r; 248 249 /* set common regs */ 250 r100_set_common_regs(rdev); 251 /* program mc */ 252 r300_mc_program(rdev); 253 /* Resume clock */ 254 r420_clock_resume(rdev); 255 /* Initialize GART (initialize after TTM so we can allocate 256 * memory through TTM but finalize after TTM) */ 257 if (rdev->flags & RADEON_IS_PCIE) { 258 r = rv370_pcie_gart_enable(rdev); 259 if (r) 260 return r; 261 } 262 if (rdev->flags & RADEON_IS_PCI) { 263 r = r100_pci_gart_enable(rdev); 264 if (r) 265 return r; 266 } 267 r420_pipes_init(rdev); 268 269 /* allocate wb buffer */ 270 r = radeon_wb_init(rdev); 271 if (r) 272 return r; 273 274 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 275 if (r) { 276 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 277 return r; 278 } 279 280 /* Enable IRQ */ 281 if (!rdev->irq.installed) { 282 r = radeon_irq_kms_init(rdev); 283 if (r) 284 return r; 285 } 286 287 r100_irq_set(rdev); 288 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 289 /* 1M ring buffer */ 290 r = r100_cp_init(rdev, 1024 * 1024); 291 if (r) { 292 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); 293 return r; 294 } 295 r420_cp_errata_init(rdev); 296 297 r = radeon_ib_pool_init(rdev); 298 if (r) { 299 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 300 return r; 301 } 302 303 return 0; 304 } 305 306 int r420_resume(struct radeon_device *rdev) 307 { 308 int r; 309 310 /* Make sur GART are not working */ 311 if (rdev->flags & RADEON_IS_PCIE) 312 rv370_pcie_gart_disable(rdev); 313 if (rdev->flags & RADEON_IS_PCI) 314 r100_pci_gart_disable(rdev); 315 /* Resume clock before doing reset */ 316 r420_clock_resume(rdev); 317 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 318 if (radeon_asic_reset(rdev)) { 319 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 320 RREG32(R_000E40_RBBM_STATUS), 321 RREG32(R_0007C0_CP_STAT)); 322 } 323 /* check if cards are posted or not */ 324 if (rdev->is_atom_bios) { 325 atom_asic_init(rdev->mode_info.atom_context); 326 } else { 327 radeon_combios_asic_init(rdev->ddev); 328 } 329 /* Resume clock after posting */ 330 r420_clock_resume(rdev); 331 /* Initialize surface registers */ 332 radeon_surface_init(rdev); 333 334 rdev->accel_working = true; 335 r = r420_startup(rdev); 336 if (r) { 337 rdev->accel_working = false; 338 } 339 return r; 340 } 341 342 int r420_suspend(struct radeon_device *rdev) 343 { 344 radeon_pm_suspend(rdev); 345 r420_cp_errata_fini(rdev); 346 r100_cp_disable(rdev); 347 radeon_wb_disable(rdev); 348 r100_irq_disable(rdev); 349 if (rdev->flags & RADEON_IS_PCIE) 350 rv370_pcie_gart_disable(rdev); 351 if (rdev->flags & RADEON_IS_PCI) 352 r100_pci_gart_disable(rdev); 353 return 0; 354 } 355 356 void r420_fini(struct radeon_device *rdev) 357 { 358 radeon_pm_fini(rdev); 359 r100_cp_fini(rdev); 360 radeon_wb_fini(rdev); 361 radeon_ib_pool_fini(rdev); 362 radeon_gem_fini(rdev); 363 if (rdev->flags & RADEON_IS_PCIE) 364 rv370_pcie_gart_fini(rdev); 365 if (rdev->flags & RADEON_IS_PCI) 366 r100_pci_gart_fini(rdev); 367 radeon_agp_fini(rdev); 368 radeon_irq_kms_fini(rdev); 369 radeon_fence_driver_fini(rdev); 370 radeon_bo_fini(rdev); 371 if (rdev->is_atom_bios) { 372 radeon_atombios_fini(rdev); 373 } else { 374 radeon_combios_fini(rdev); 375 } 376 kfree(rdev->bios); 377 rdev->bios = NULL; 378 } 379 380 int r420_init(struct radeon_device *rdev) 381 { 382 int r; 383 384 /* Initialize scratch registers */ 385 radeon_scratch_init(rdev); 386 /* Initialize surface registers */ 387 radeon_surface_init(rdev); 388 /* TODO: disable VGA need to use VGA request */ 389 /* restore some register to sane defaults */ 390 r100_restore_sanity(rdev); 391 /* BIOS*/ 392 if (!radeon_get_bios(rdev)) { 393 if (ASIC_IS_AVIVO(rdev)) 394 return -EINVAL; 395 } 396 if (rdev->is_atom_bios) { 397 r = radeon_atombios_init(rdev); 398 if (r) { 399 return r; 400 } 401 } else { 402 r = radeon_combios_init(rdev); 403 if (r) { 404 return r; 405 } 406 } 407 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 408 if (radeon_asic_reset(rdev)) { 409 dev_warn(rdev->dev, 410 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 411 RREG32(R_000E40_RBBM_STATUS), 412 RREG32(R_0007C0_CP_STAT)); 413 } 414 /* check if cards are posted or not */ 415 if (radeon_boot_test_post_card(rdev) == false) 416 return -EINVAL; 417 418 /* Initialize clocks */ 419 radeon_get_clock_info(rdev->ddev); 420 /* initialize AGP */ 421 if (rdev->flags & RADEON_IS_AGP) { 422 r = radeon_agp_init(rdev); 423 if (r) { 424 radeon_agp_disable(rdev); 425 } 426 } 427 /* initialize memory controller */ 428 r300_mc_init(rdev); 429 r420_debugfs(rdev); 430 /* Fence driver */ 431 r = radeon_fence_driver_init(rdev); 432 if (r) { 433 return r; 434 } 435 /* Memory manager */ 436 r = radeon_bo_init(rdev); 437 if (r) { 438 return r; 439 } 440 if (rdev->family == CHIP_R420) 441 r100_enable_bm(rdev); 442 443 if (rdev->flags & RADEON_IS_PCIE) { 444 r = rv370_pcie_gart_init(rdev); 445 if (r) 446 return r; 447 } 448 if (rdev->flags & RADEON_IS_PCI) { 449 r = r100_pci_gart_init(rdev); 450 if (r) 451 return r; 452 } 453 r420_set_reg_safe(rdev); 454 455 /* Initialize power management */ 456 radeon_pm_init(rdev); 457 458 rdev->accel_working = true; 459 r = r420_startup(rdev); 460 if (r) { 461 /* Somethings want wront with the accel init stop accel */ 462 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 463 r100_cp_fini(rdev); 464 radeon_wb_fini(rdev); 465 radeon_ib_pool_fini(rdev); 466 radeon_irq_kms_fini(rdev); 467 if (rdev->flags & RADEON_IS_PCIE) 468 rv370_pcie_gart_fini(rdev); 469 if (rdev->flags & RADEON_IS_PCI) 470 r100_pci_gart_fini(rdev); 471 radeon_agp_fini(rdev); 472 rdev->accel_working = false; 473 } 474 return 0; 475 } 476 477 /* 478 * Debugfs info 479 */ 480 #if defined(CONFIG_DEBUG_FS) 481 static int r420_debugfs_pipes_info(struct seq_file *m, void *data) 482 { 483 struct drm_info_node *node = (struct drm_info_node *) m->private; 484 struct drm_device *dev = node->minor->dev; 485 struct radeon_device *rdev = dev->dev_private; 486 uint32_t tmp; 487 488 tmp = RREG32(R400_GB_PIPE_SELECT); 489 seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp); 490 tmp = RREG32(R300_GB_TILE_CONFIG); 491 seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp); 492 tmp = RREG32(R300_DST_PIPE_CONFIG); 493 seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp); 494 return 0; 495 } 496 497 static struct drm_info_list r420_pipes_info_list[] = { 498 {"r420_pipes_info", r420_debugfs_pipes_info, 0, NULL}, 499 }; 500 #endif 501 502 int r420_debugfs_pipes_info_init(struct radeon_device *rdev) 503 { 504 #if defined(CONFIG_DEBUG_FS) 505 return radeon_debugfs_add_files(rdev, r420_pipes_info_list, 1); 506 #else 507 return 0; 508 #endif 509 } 510
Indexes created Mon Oct 27 08:10:08 GMT 2025