radeon_r520.c revision 1.1.2.2
1 /* $NetBSD: radeon_r520.c,v 1.1.2.2 2018/09/06 06:56:33 pgoyette Exp $ */ 2 3 /* 4 * Copyright 2008 Advanced Micro Devices, Inc. 5 * Copyright 2008 Red Hat Inc. 6 * Copyright 2009 Jerome Glisse. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: Dave Airlie 27 * Alex Deucher 28 * Jerome Glisse 29 */ 30 #include <sys/cdefs.h> 31 __KERNEL_RCSID(0, "$NetBSD: radeon_r520.c,v 1.1.2.2 2018/09/06 06:56:33 pgoyette Exp $"); 32 33 #include <drm/drmP.h> 34 #include "radeon.h" 35 #include "radeon_asic.h" 36 #include "atom.h" 37 #include "r520d.h" 38 39 /* This files gather functions specifics to: r520,rv530,rv560,rv570,r580 */ 40 41 int r520_mc_wait_for_idle(struct radeon_device *rdev) 42 { 43 unsigned i; 44 uint32_t tmp; 45 46 for (i = 0; i < rdev->usec_timeout; i++) { 47 /* read MC_STATUS */ 48 tmp = RREG32_MC(R520_MC_STATUS); 49 if (tmp & R520_MC_STATUS_IDLE) { 50 return 0; 51 } 52 DRM_UDELAY(1); 53 } 54 return -1; 55 } 56 57 static void r520_gpu_init(struct radeon_device *rdev) 58 { 59 unsigned pipe_select_current, gb_pipe_select, tmp; 60 61 rv515_vga_render_disable(rdev); 62 /* 63 * DST_PIPE_CONFIG 0x170C 64 * GB_TILE_CONFIG 0x4018 65 * GB_FIFO_SIZE 0x4024 66 * GB_PIPE_SELECT 0x402C 67 * GB_PIPE_SELECT2 0x4124 68 * Z_PIPE_SHIFT 0 69 * Z_PIPE_MASK 0x000000003 70 * GB_FIFO_SIZE2 0x4128 71 * SC_SFIFO_SIZE_SHIFT 0 72 * SC_SFIFO_SIZE_MASK 0x000000003 73 * SC_MFIFO_SIZE_SHIFT 2 74 * SC_MFIFO_SIZE_MASK 0x00000000C 75 * FG_SFIFO_SIZE_SHIFT 4 76 * FG_SFIFO_SIZE_MASK 0x000000030 77 * ZB_MFIFO_SIZE_SHIFT 6 78 * ZB_MFIFO_SIZE_MASK 0x0000000C0 79 * GA_ENHANCE 0x4274 80 * SU_REG_DEST 0x42C8 81 */ 82 /* workaround for RV530 */ 83 if (rdev->family == CHIP_RV530) { 84 WREG32(0x4128, 0xFF); 85 } 86 r420_pipes_init(rdev); 87 gb_pipe_select = RREG32(R400_GB_PIPE_SELECT); 88 tmp = RREG32(R300_DST_PIPE_CONFIG); 89 pipe_select_current = (tmp >> 2) & 3; 90 tmp = (1 << pipe_select_current) | 91 (((gb_pipe_select >> 8) & 0xF) << 4); 92 WREG32_PLL(0x000D, tmp); 93 if (r520_mc_wait_for_idle(rdev)) { 94 printk(KERN_WARNING "Failed to wait MC idle while " 95 "programming pipes. Bad things might happen.\n"); 96 } 97 } 98 99 static void r520_vram_get_type(struct radeon_device *rdev) 100 { 101 uint32_t tmp; 102 103 rdev->mc.vram_width = 128; 104 rdev->mc.vram_is_ddr = true; 105 tmp = RREG32_MC(R520_MC_CNTL0); 106 switch ((tmp & R520_MEM_NUM_CHANNELS_MASK) >> R520_MEM_NUM_CHANNELS_SHIFT) { 107 case 0: 108 rdev->mc.vram_width = 32; 109 break; 110 case 1: 111 rdev->mc.vram_width = 64; 112 break; 113 case 2: 114 rdev->mc.vram_width = 128; 115 break; 116 case 3: 117 rdev->mc.vram_width = 256; 118 break; 119 default: 120 rdev->mc.vram_width = 128; 121 break; 122 } 123 if (tmp & R520_MC_CHANNEL_SIZE) 124 rdev->mc.vram_width *= 2; 125 } 126 127 static void r520_mc_init(struct radeon_device *rdev) 128 { 129 130 r520_vram_get_type(rdev); 131 r100_vram_init_sizes(rdev); 132 radeon_vram_location(rdev, &rdev->mc, 0); 133 rdev->mc.gtt_base_align = 0; 134 if (!(rdev->flags & RADEON_IS_AGP)) 135 radeon_gtt_location(rdev, &rdev->mc); 136 radeon_update_bandwidth_info(rdev); 137 } 138 139 static void r520_mc_program(struct radeon_device *rdev) 140 { 141 struct rv515_mc_save save; 142 143 /* Stops all mc clients */ 144 rv515_mc_stop(rdev, &save); 145 146 /* Wait for mc idle */ 147 if (r520_mc_wait_for_idle(rdev)) 148 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); 149 /* Write VRAM size in case we are limiting it */ 150 WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size); 151 /* Program MC, should be a 32bits limited address space */ 152 WREG32_MC(R_000004_MC_FB_LOCATION, 153 S_000004_MC_FB_START(rdev->mc.vram_start >> 16) | 154 S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16)); 155 WREG32(R_000134_HDP_FB_LOCATION, 156 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); 157 if (rdev->flags & RADEON_IS_AGP) { 158 WREG32_MC(R_000005_MC_AGP_LOCATION, 159 S_000005_MC_AGP_START(rdev->mc.gtt_start >> 16) | 160 S_000005_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); 161 WREG32_MC(R_000006_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); 162 WREG32_MC(R_000007_AGP_BASE_2, 163 S_000007_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base))); 164 } else { 165 WREG32_MC(R_000005_MC_AGP_LOCATION, 0xFFFFFFFF); 166 WREG32_MC(R_000006_AGP_BASE, 0); 167 WREG32_MC(R_000007_AGP_BASE_2, 0); 168 } 169 170 rv515_mc_resume(rdev, &save); 171 } 172 173 static int r520_startup(struct radeon_device *rdev) 174 { 175 int r; 176 177 r520_mc_program(rdev); 178 /* Resume clock */ 179 rv515_clock_startup(rdev); 180 /* Initialize GPU configuration (# pipes, ...) */ 181 r520_gpu_init(rdev); 182 /* Initialize GART (initialize after TTM so we can allocate 183 * memory through TTM but finalize after TTM) */ 184 if (rdev->flags & RADEON_IS_PCIE) { 185 r = rv370_pcie_gart_enable(rdev); 186 if (r) 187 return r; 188 } 189 190 /* allocate wb buffer */ 191 r = radeon_wb_init(rdev); 192 if (r) 193 return r; 194 195 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 196 if (r) { 197 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 198 return r; 199 } 200 201 /* Enable IRQ */ 202 if (!rdev->irq.installed) { 203 r = radeon_irq_kms_init(rdev); 204 if (r) 205 return r; 206 } 207 208 rs600_irq_set(rdev); 209 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 210 /* 1M ring buffer */ 211 r = r100_cp_init(rdev, 1024 * 1024); 212 if (r) { 213 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); 214 return r; 215 } 216 217 r = radeon_ib_pool_init(rdev); 218 if (r) { 219 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 220 return r; 221 } 222 223 return 0; 224 } 225 226 int r520_resume(struct radeon_device *rdev) 227 { 228 int r; 229 230 /* Make sur GART are not working */ 231 if (rdev->flags & RADEON_IS_PCIE) 232 rv370_pcie_gart_disable(rdev); 233 /* Resume clock before doing reset */ 234 rv515_clock_startup(rdev); 235 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 236 if (radeon_asic_reset(rdev)) { 237 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 238 RREG32(R_000E40_RBBM_STATUS), 239 RREG32(R_0007C0_CP_STAT)); 240 } 241 /* post */ 242 atom_asic_init(rdev->mode_info.atom_context); 243 /* Resume clock after posting */ 244 rv515_clock_startup(rdev); 245 /* Initialize surface registers */ 246 radeon_surface_init(rdev); 247 248 rdev->accel_working = true; 249 r = r520_startup(rdev); 250 if (r) { 251 rdev->accel_working = false; 252 } 253 return r; 254 } 255 256 int r520_init(struct radeon_device *rdev) 257 { 258 int r; 259 260 /* Initialize scratch registers */ 261 radeon_scratch_init(rdev); 262 /* Initialize surface registers */ 263 radeon_surface_init(rdev); 264 /* restore some register to sane defaults */ 265 r100_restore_sanity(rdev); 266 /* TODO: disable VGA need to use VGA request */ 267 /* BIOS*/ 268 if (!radeon_get_bios(rdev)) { 269 if (ASIC_IS_AVIVO(rdev)) 270 return -EINVAL; 271 } 272 if (rdev->is_atom_bios) { 273 r = radeon_atombios_init(rdev); 274 if (r) 275 return r; 276 } else { 277 dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n"); 278 return -EINVAL; 279 } 280 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 281 if (radeon_asic_reset(rdev)) { 282 dev_warn(rdev->dev, 283 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 284 RREG32(R_000E40_RBBM_STATUS), 285 RREG32(R_0007C0_CP_STAT)); 286 } 287 /* check if cards are posted or not */ 288 if (radeon_boot_test_post_card(rdev) == false) 289 return -EINVAL; 290 291 if (!radeon_card_posted(rdev) && rdev->bios) { 292 DRM_INFO("GPU not posted. posting now...\n"); 293 atom_asic_init(rdev->mode_info.atom_context); 294 } 295 /* Initialize clocks */ 296 radeon_get_clock_info(rdev->ddev); 297 /* initialize AGP */ 298 if (rdev->flags & RADEON_IS_AGP) { 299 r = radeon_agp_init(rdev); 300 if (r) { 301 radeon_agp_disable(rdev); 302 } 303 } 304 /* initialize memory controller */ 305 r520_mc_init(rdev); 306 rv515_debugfs(rdev); 307 /* Fence driver */ 308 r = radeon_fence_driver_init(rdev); 309 if (r) 310 return r; 311 /* Memory manager */ 312 r = radeon_bo_init(rdev); 313 if (r) 314 return r; 315 r = rv370_pcie_gart_init(rdev); 316 if (r) 317 return r; 318 rv515_set_safe_registers(rdev); 319 320 /* Initialize power management */ 321 radeon_pm_init(rdev); 322 323 rdev->accel_working = true; 324 r = r520_startup(rdev); 325 if (r) { 326 /* Somethings want wront with the accel init stop accel */ 327 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 328 r100_cp_fini(rdev); 329 radeon_wb_fini(rdev); 330 radeon_ib_pool_fini(rdev); 331 radeon_irq_kms_fini(rdev); 332 rv370_pcie_gart_fini(rdev); 333 radeon_agp_fini(rdev); 334 rdev->accel_working = false; 335 } 336 return 0; 337 } 338
Indexes created Sat Oct 25 16:10:12 GMT 2025