radeon_r600.c revision 1.1
1 /* $NetBSD: radeon_r600.c,v 1.1 2018/08/27 14:38:20 riastradh Exp $ */ 2 3 /* 4 * Copyright 2008 Advanced Micro Devices, Inc. 5 * Copyright 2008 Red Hat Inc. 6 * Copyright 2009 Jerome Glisse. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: Dave Airlie 27 * Alex Deucher 28 * Jerome Glisse 29 */ 30 #include <sys/cdefs.h> 31 __KERNEL_RCSID(0, "$NetBSD: radeon_r600.c,v 1.1 2018/08/27 14:38:20 riastradh Exp $"); 32 33 #include <linux/bitops.h> 34 #include <linux/slab.h> 35 #include <linux/seq_file.h> 36 #include <linux/firmware.h> 37 #include <linux/module.h> 38 #include <drm/drmP.h> 39 #include <drm/radeon_drm.h> 40 #include "radeon.h" 41 #include "radeon_asic.h" 42 #include "radeon_audio.h" 43 #include "radeon_mode.h" 44 #include "r600d.h" 45 #include "atom.h" 46 #include "avivod.h" 47 #include "radeon_ucode.h" 48 49 /* Firmware Names */ 50 MODULE_FIRMWARE("radeon/R600_pfp.bin"); 51 MODULE_FIRMWARE("radeon/R600_me.bin"); 52 MODULE_FIRMWARE("radeon/RV610_pfp.bin"); 53 MODULE_FIRMWARE("radeon/RV610_me.bin"); 54 MODULE_FIRMWARE("radeon/RV630_pfp.bin"); 55 MODULE_FIRMWARE("radeon/RV630_me.bin"); 56 MODULE_FIRMWARE("radeon/RV620_pfp.bin"); 57 MODULE_FIRMWARE("radeon/RV620_me.bin"); 58 MODULE_FIRMWARE("radeon/RV635_pfp.bin"); 59 MODULE_FIRMWARE("radeon/RV635_me.bin"); 60 MODULE_FIRMWARE("radeon/RV670_pfp.bin"); 61 MODULE_FIRMWARE("radeon/RV670_me.bin"); 62 MODULE_FIRMWARE("radeon/RS780_pfp.bin"); 63 MODULE_FIRMWARE("radeon/RS780_me.bin"); 64 MODULE_FIRMWARE("radeon/RV770_pfp.bin"); 65 MODULE_FIRMWARE("radeon/RV770_me.bin"); 66 MODULE_FIRMWARE("radeon/RV770_smc.bin"); 67 MODULE_FIRMWARE("radeon/RV730_pfp.bin"); 68 MODULE_FIRMWARE("radeon/RV730_me.bin"); 69 MODULE_FIRMWARE("radeon/RV730_smc.bin"); 70 MODULE_FIRMWARE("radeon/RV740_smc.bin"); 71 MODULE_FIRMWARE("radeon/RV710_pfp.bin"); 72 MODULE_FIRMWARE("radeon/RV710_me.bin"); 73 MODULE_FIRMWARE("radeon/RV710_smc.bin"); 74 MODULE_FIRMWARE("radeon/R600_rlc.bin"); 75 MODULE_FIRMWARE("radeon/R700_rlc.bin"); 76 MODULE_FIRMWARE("radeon/CEDAR_pfp.bin"); 77 MODULE_FIRMWARE("radeon/CEDAR_me.bin"); 78 MODULE_FIRMWARE("radeon/CEDAR_rlc.bin"); 79 MODULE_FIRMWARE("radeon/CEDAR_smc.bin"); 80 MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin"); 81 MODULE_FIRMWARE("radeon/REDWOOD_me.bin"); 82 MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin"); 83 MODULE_FIRMWARE("radeon/REDWOOD_smc.bin"); 84 MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin"); 85 MODULE_FIRMWARE("radeon/JUNIPER_me.bin"); 86 MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin"); 87 MODULE_FIRMWARE("radeon/JUNIPER_smc.bin"); 88 MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin"); 89 MODULE_FIRMWARE("radeon/CYPRESS_me.bin"); 90 MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin"); 91 MODULE_FIRMWARE("radeon/CYPRESS_smc.bin"); 92 MODULE_FIRMWARE("radeon/PALM_pfp.bin"); 93 MODULE_FIRMWARE("radeon/PALM_me.bin"); 94 MODULE_FIRMWARE("radeon/SUMO_rlc.bin"); 95 MODULE_FIRMWARE("radeon/SUMO_pfp.bin"); 96 MODULE_FIRMWARE("radeon/SUMO_me.bin"); 97 MODULE_FIRMWARE("radeon/SUMO2_pfp.bin"); 98 MODULE_FIRMWARE("radeon/SUMO2_me.bin"); 99 100 static const u32 crtc_offsets[2] = 101 { 102 0, 103 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL 104 }; 105 106 int r600_debugfs_mc_info_init(struct radeon_device *rdev); 107 108 /* r600,rv610,rv630,rv620,rv635,rv670 */ 109 int r600_mc_wait_for_idle(struct radeon_device *rdev); 110 static void r600_gpu_init(struct radeon_device *rdev); 111 void r600_fini(struct radeon_device *rdev); 112 void r600_irq_disable(struct radeon_device *rdev); 113 static void r600_pcie_gen2_enable(struct radeon_device *rdev); 114 extern int evergreen_rlc_resume(struct radeon_device *rdev); 115 extern void rv770_set_clk_bypass_mode(struct radeon_device *rdev); 116 117 /* 118 * Indirect registers accessor 119 */ 120 u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg) 121 { 122 unsigned long flags; 123 u32 r; 124 125 spin_lock_irqsave(&rdev->rcu_idx_lock, flags); 126 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff)); 127 r = RREG32(R600_RCU_DATA); 128 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags); 129 return r; 130 } 131 132 void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v) 133 { 134 unsigned long flags; 135 136 spin_lock_irqsave(&rdev->rcu_idx_lock, flags); 137 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff)); 138 WREG32(R600_RCU_DATA, (v)); 139 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags); 140 } 141 142 u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg) 143 { 144 unsigned long flags; 145 u32 r; 146 147 spin_lock_irqsave(&rdev->uvd_idx_lock, flags); 148 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff)); 149 r = RREG32(R600_UVD_CTX_DATA); 150 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags); 151 return r; 152 } 153 154 void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v) 155 { 156 unsigned long flags; 157 158 spin_lock_irqsave(&rdev->uvd_idx_lock, flags); 159 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff)); 160 WREG32(R600_UVD_CTX_DATA, (v)); 161 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags); 162 } 163 164 /** 165 * r600_get_allowed_info_register - fetch the register for the info ioctl 166 * 167 * @rdev: radeon_device pointer 168 * @reg: register offset in bytes 169 * @val: register value 170 * 171 * Returns 0 for success or -EINVAL for an invalid register 172 * 173 */ 174 int r600_get_allowed_info_register(struct radeon_device *rdev, 175 u32 reg, u32 *val) 176 { 177 switch (reg) { 178 case GRBM_STATUS: 179 case GRBM_STATUS2: 180 case R_000E50_SRBM_STATUS: 181 case DMA_STATUS_REG: 182 case UVD_STATUS: 183 *val = RREG32(reg); 184 return 0; 185 default: 186 return -EINVAL; 187 } 188 } 189 190 /** 191 * r600_get_xclk - get the xclk 192 * 193 * @rdev: radeon_device pointer 194 * 195 * Returns the reference clock used by the gfx engine 196 * (r6xx, IGPs, APUs). 197 */ 198 u32 r600_get_xclk(struct radeon_device *rdev) 199 { 200 return rdev->clock.spll.reference_freq; 201 } 202 203 int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) 204 { 205 unsigned fb_div = 0, ref_div, vclk_div = 0, dclk_div = 0; 206 int r; 207 208 /* bypass vclk and dclk with bclk */ 209 WREG32_P(CG_UPLL_FUNC_CNTL_2, 210 VCLK_SRC_SEL(1) | DCLK_SRC_SEL(1), 211 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK)); 212 213 /* assert BYPASS_EN, deassert UPLL_RESET, UPLL_SLEEP and UPLL_CTLREQ */ 214 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~( 215 UPLL_RESET_MASK | UPLL_SLEEP_MASK | UPLL_CTLREQ_MASK)); 216 217 if (rdev->family >= CHIP_RS780) 218 WREG32_P(GFX_MACRO_BYPASS_CNTL, UPLL_BYPASS_CNTL, 219 ~UPLL_BYPASS_CNTL); 220 221 if (!vclk || !dclk) { 222 /* keep the Bypass mode, put PLL to sleep */ 223 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK); 224 return 0; 225 } 226 227 if (rdev->clock.spll.reference_freq == 10000) 228 ref_div = 34; 229 else 230 ref_div = 4; 231 232 r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 50000, 160000, 233 ref_div + 1, 0xFFF, 2, 30, ~0, 234 &fb_div, &vclk_div, &dclk_div); 235 if (r) 236 return r; 237 238 if (rdev->family >= CHIP_RV670 && rdev->family < CHIP_RS780) 239 fb_div >>= 1; 240 else 241 fb_div |= 1; 242 243 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL); 244 if (r) 245 return r; 246 247 /* assert PLL_RESET */ 248 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK); 249 250 /* For RS780 we have to choose ref clk */ 251 if (rdev->family >= CHIP_RS780) 252 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_REFCLK_SRC_SEL_MASK, 253 ~UPLL_REFCLK_SRC_SEL_MASK); 254 255 /* set the required fb, ref and post divder values */ 256 WREG32_P(CG_UPLL_FUNC_CNTL, 257 UPLL_FB_DIV(fb_div) | 258 UPLL_REF_DIV(ref_div), 259 ~(UPLL_FB_DIV_MASK | UPLL_REF_DIV_MASK)); 260 WREG32_P(CG_UPLL_FUNC_CNTL_2, 261 UPLL_SW_HILEN(vclk_div >> 1) | 262 UPLL_SW_LOLEN((vclk_div >> 1) + (vclk_div & 1)) | 263 UPLL_SW_HILEN2(dclk_div >> 1) | 264 UPLL_SW_LOLEN2((dclk_div >> 1) + (dclk_div & 1)) | 265 UPLL_DIVEN_MASK | UPLL_DIVEN2_MASK, 266 ~UPLL_SW_MASK); 267 268 /* give the PLL some time to settle */ 269 mdelay(15); 270 271 /* deassert PLL_RESET */ 272 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); 273 274 mdelay(15); 275 276 /* deassert BYPASS EN */ 277 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK); 278 279 if (rdev->family >= CHIP_RS780) 280 WREG32_P(GFX_MACRO_BYPASS_CNTL, 0, ~UPLL_BYPASS_CNTL); 281 282 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL); 283 if (r) 284 return r; 285 286 /* switch VCLK and DCLK selection */ 287 WREG32_P(CG_UPLL_FUNC_CNTL_2, 288 VCLK_SRC_SEL(2) | DCLK_SRC_SEL(2), 289 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK)); 290 291 mdelay(100); 292 293 return 0; 294 } 295 296 void dce3_program_fmt(struct drm_encoder *encoder) 297 { 298 struct drm_device *dev = encoder->dev; 299 struct radeon_device *rdev = dev->dev_private; 300 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 301 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 302 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 303 int bpc = 0; 304 u32 tmp = 0; 305 enum radeon_connector_dither dither = RADEON_FMT_DITHER_DISABLE; 306 307 if (connector) { 308 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 309 bpc = radeon_get_monitor_bpc(connector); 310 dither = radeon_connector->dither; 311 } 312 313 /* LVDS FMT is set up by atom */ 314 if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) 315 return; 316 317 /* not needed for analog */ 318 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) || 319 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2)) 320 return; 321 322 if (bpc == 0) 323 return; 324 325 switch (bpc) { 326 case 6: 327 if (dither == RADEON_FMT_DITHER_ENABLE) 328 /* XXX sort out optimal dither settings */ 329 tmp |= FMT_SPATIAL_DITHER_EN; 330 else 331 tmp |= FMT_TRUNCATE_EN; 332 break; 333 case 8: 334 if (dither == RADEON_FMT_DITHER_ENABLE) 335 /* XXX sort out optimal dither settings */ 336 tmp |= (FMT_SPATIAL_DITHER_EN | FMT_SPATIAL_DITHER_DEPTH); 337 else 338 tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH); 339 break; 340 case 10: 341 default: 342 /* not needed */ 343 break; 344 } 345 346 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp); 347 } 348 349 /* get temperature in millidegrees */ 350 int rv6xx_get_temp(struct radeon_device *rdev) 351 { 352 u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >> 353 ASIC_T_SHIFT; 354 int actual_temp = temp & 0xff; 355 356 if (temp & 0x100) 357 actual_temp -= 256; 358 359 return actual_temp * 1000; 360 } 361 362 void r600_pm_get_dynpm_state(struct radeon_device *rdev) 363 { 364 int i; 365 366 rdev->pm.dynpm_can_upclock = true; 367 rdev->pm.dynpm_can_downclock = true; 368 369 /* power state array is low to high, default is first */ 370 if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) { 371 int min_power_state_index = 0; 372 373 if (rdev->pm.num_power_states > 2) 374 min_power_state_index = 1; 375 376 switch (rdev->pm.dynpm_planned_action) { 377 case DYNPM_ACTION_MINIMUM: 378 rdev->pm.requested_power_state_index = min_power_state_index; 379 rdev->pm.requested_clock_mode_index = 0; 380 rdev->pm.dynpm_can_downclock = false; 381 break; 382 case DYNPM_ACTION_DOWNCLOCK: 383 if (rdev->pm.current_power_state_index == min_power_state_index) { 384 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 385 rdev->pm.dynpm_can_downclock = false; 386 } else { 387 if (rdev->pm.active_crtc_count > 1) { 388 for (i = 0; i < rdev->pm.num_power_states; i++) { 389 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 390 continue; 391 else if (i >= rdev->pm.current_power_state_index) { 392 rdev->pm.requested_power_state_index = 393 rdev->pm.current_power_state_index; 394 break; 395 } else { 396 rdev->pm.requested_power_state_index = i; 397 break; 398 } 399 } 400 } else { 401 if (rdev->pm.current_power_state_index == 0) 402 rdev->pm.requested_power_state_index = 403 rdev->pm.num_power_states - 1; 404 else 405 rdev->pm.requested_power_state_index = 406 rdev->pm.current_power_state_index - 1; 407 } 408 } 409 rdev->pm.requested_clock_mode_index = 0; 410 /* don't use the power state if crtcs are active and no display flag is set */ 411 if ((rdev->pm.active_crtc_count > 0) && 412 (rdev->pm.power_state[rdev->pm.requested_power_state_index]. 413 clock_info[rdev->pm.requested_clock_mode_index].flags & 414 RADEON_PM_MODE_NO_DISPLAY)) { 415 rdev->pm.requested_power_state_index++; 416 } 417 break; 418 case DYNPM_ACTION_UPCLOCK: 419 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) { 420 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 421 rdev->pm.dynpm_can_upclock = false; 422 } else { 423 if (rdev->pm.active_crtc_count > 1) { 424 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) { 425 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 426 continue; 427 else if (i <= rdev->pm.current_power_state_index) { 428 rdev->pm.requested_power_state_index = 429 rdev->pm.current_power_state_index; 430 break; 431 } else { 432 rdev->pm.requested_power_state_index = i; 433 break; 434 } 435 } 436 } else 437 rdev->pm.requested_power_state_index = 438 rdev->pm.current_power_state_index + 1; 439 } 440 rdev->pm.requested_clock_mode_index = 0; 441 break; 442 case DYNPM_ACTION_DEFAULT: 443 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; 444 rdev->pm.requested_clock_mode_index = 0; 445 rdev->pm.dynpm_can_upclock = false; 446 break; 447 case DYNPM_ACTION_NONE: 448 default: 449 DRM_ERROR("Requested mode for not defined action\n"); 450 return; 451 } 452 } else { 453 /* XXX select a power state based on AC/DC, single/dualhead, etc. */ 454 /* for now just select the first power state and switch between clock modes */ 455 /* power state array is low to high, default is first (0) */ 456 if (rdev->pm.active_crtc_count > 1) { 457 rdev->pm.requested_power_state_index = -1; 458 /* start at 1 as we don't want the default mode */ 459 for (i = 1; i < rdev->pm.num_power_states; i++) { 460 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 461 continue; 462 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) || 463 (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) { 464 rdev->pm.requested_power_state_index = i; 465 break; 466 } 467 } 468 /* if nothing selected, grab the default state. */ 469 if (rdev->pm.requested_power_state_index == -1) 470 rdev->pm.requested_power_state_index = 0; 471 } else 472 rdev->pm.requested_power_state_index = 1; 473 474 switch (rdev->pm.dynpm_planned_action) { 475 case DYNPM_ACTION_MINIMUM: 476 rdev->pm.requested_clock_mode_index = 0; 477 rdev->pm.dynpm_can_downclock = false; 478 break; 479 case DYNPM_ACTION_DOWNCLOCK: 480 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) { 481 if (rdev->pm.current_clock_mode_index == 0) { 482 rdev->pm.requested_clock_mode_index = 0; 483 rdev->pm.dynpm_can_downclock = false; 484 } else 485 rdev->pm.requested_clock_mode_index = 486 rdev->pm.current_clock_mode_index - 1; 487 } else { 488 rdev->pm.requested_clock_mode_index = 0; 489 rdev->pm.dynpm_can_downclock = false; 490 } 491 /* don't use the power state if crtcs are active and no display flag is set */ 492 if ((rdev->pm.active_crtc_count > 0) && 493 (rdev->pm.power_state[rdev->pm.requested_power_state_index]. 494 clock_info[rdev->pm.requested_clock_mode_index].flags & 495 RADEON_PM_MODE_NO_DISPLAY)) { 496 rdev->pm.requested_clock_mode_index++; 497 } 498 break; 499 case DYNPM_ACTION_UPCLOCK: 500 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) { 501 if (rdev->pm.current_clock_mode_index == 502 (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) { 503 rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index; 504 rdev->pm.dynpm_can_upclock = false; 505 } else 506 rdev->pm.requested_clock_mode_index = 507 rdev->pm.current_clock_mode_index + 1; 508 } else { 509 rdev->pm.requested_clock_mode_index = 510 rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1; 511 rdev->pm.dynpm_can_upclock = false; 512 } 513 break; 514 case DYNPM_ACTION_DEFAULT: 515 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; 516 rdev->pm.requested_clock_mode_index = 0; 517 rdev->pm.dynpm_can_upclock = false; 518 break; 519 case DYNPM_ACTION_NONE: 520 default: 521 DRM_ERROR("Requested mode for not defined action\n"); 522 return; 523 } 524 } 525 526 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n", 527 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 528 clock_info[rdev->pm.requested_clock_mode_index].sclk, 529 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 530 clock_info[rdev->pm.requested_clock_mode_index].mclk, 531 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 532 pcie_lanes); 533 } 534 535 void rs780_pm_init_profile(struct radeon_device *rdev) 536 { 537 if (rdev->pm.num_power_states == 2) { 538 /* default */ 539 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 540 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 541 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 542 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 543 /* low sh */ 544 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0; 545 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0; 546 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 547 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 548 /* mid sh */ 549 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0; 550 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0; 551 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 552 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 553 /* high sh */ 554 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0; 555 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1; 556 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 557 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 558 /* low mh */ 559 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0; 560 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0; 561 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 562 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 563 /* mid mh */ 564 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0; 565 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0; 566 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 567 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 568 /* high mh */ 569 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0; 570 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1; 571 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 572 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 573 } else if (rdev->pm.num_power_states == 3) { 574 /* default */ 575 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 576 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 577 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 578 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 579 /* low sh */ 580 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1; 581 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1; 582 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 583 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 584 /* mid sh */ 585 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1; 586 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; 587 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 588 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 589 /* high sh */ 590 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1; 591 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2; 592 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 593 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 594 /* low mh */ 595 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1; 596 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1; 597 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 598 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 599 /* mid mh */ 600 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1; 601 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1; 602 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 603 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 604 /* high mh */ 605 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1; 606 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2; 607 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 608 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 609 } else { 610 /* default */ 611 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 612 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 613 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 614 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 615 /* low sh */ 616 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2; 617 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2; 618 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 619 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 620 /* mid sh */ 621 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2; 622 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2; 623 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 624 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 625 /* high sh */ 626 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2; 627 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3; 628 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 629 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 630 /* low mh */ 631 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2; 632 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0; 633 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 634 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 635 /* mid mh */ 636 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2; 637 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0; 638 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 639 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 640 /* high mh */ 641 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2; 642 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3; 643 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 644 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 645 } 646 } 647 648 void r600_pm_init_profile(struct radeon_device *rdev) 649 { 650 int idx; 651 652 if (rdev->family == CHIP_R600) { 653 /* XXX */ 654 /* default */ 655 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 656 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 657 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 658 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 659 /* low sh */ 660 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 661 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 662 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 663 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 664 /* mid sh */ 665 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 666 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 667 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 668 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 669 /* high sh */ 670 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 671 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 672 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 673 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 674 /* low mh */ 675 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 676 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 677 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 678 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 679 /* mid mh */ 680 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 681 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 682 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 683 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 684 /* high mh */ 685 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 686 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 687 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 688 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 689 } else { 690 if (rdev->pm.num_power_states < 4) { 691 /* default */ 692 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 693 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 694 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 695 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2; 696 /* low sh */ 697 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1; 698 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1; 699 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 700 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 701 /* mid sh */ 702 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1; 703 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; 704 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 705 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1; 706 /* high sh */ 707 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1; 708 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1; 709 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 710 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2; 711 /* low mh */ 712 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2; 713 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2; 714 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 715 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 716 /* low mh */ 717 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2; 718 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2; 719 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 720 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1; 721 /* high mh */ 722 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2; 723 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2; 724 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 725 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2; 726 } else { 727 /* default */ 728 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 729 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 730 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 731 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2; 732 /* low sh */ 733 if (rdev->flags & RADEON_IS_MOBILITY) 734 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0); 735 else 736 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); 737 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx; 738 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx; 739 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 740 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 741 /* mid sh */ 742 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx; 743 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx; 744 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 745 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1; 746 /* high sh */ 747 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); 748 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx; 749 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx; 750 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 751 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2; 752 /* low mh */ 753 if (rdev->flags & RADEON_IS_MOBILITY) 754 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1); 755 else 756 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1); 757 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx; 758 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx; 759 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 760 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 761 /* mid mh */ 762 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx; 763 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx; 764 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 765 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1; 766 /* high mh */ 767 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1); 768 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx; 769 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx; 770 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 771 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2; 772 } 773 } 774 } 775 776 void r600_pm_misc(struct radeon_device *rdev) 777 { 778 int req_ps_idx = rdev->pm.requested_power_state_index; 779 int req_cm_idx = rdev->pm.requested_clock_mode_index; 780 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx]; 781 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage; 782 783 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) { 784 /* 0xff01 is a flag rather then an actual voltage */ 785 if (voltage->voltage == 0xff01) 786 return; 787 if (voltage->voltage != rdev->pm.current_vddc) { 788 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC); 789 rdev->pm.current_vddc = voltage->voltage; 790 DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage->voltage); 791 } 792 } 793 } 794 795 bool r600_gui_idle(struct radeon_device *rdev) 796 { 797 if (RREG32(GRBM_STATUS) & GUI_ACTIVE) 798 return false; 799 else 800 return true; 801 } 802 803 /* hpd for digital panel detect/disconnect */ 804 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) 805 { 806 bool connected = false; 807 808 if (ASIC_IS_DCE3(rdev)) { 809 switch (hpd) { 810 case RADEON_HPD_1: 811 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE) 812 connected = true; 813 break; 814 case RADEON_HPD_2: 815 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE) 816 connected = true; 817 break; 818 case RADEON_HPD_3: 819 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE) 820 connected = true; 821 break; 822 case RADEON_HPD_4: 823 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE) 824 connected = true; 825 break; 826 /* DCE 3.2 */ 827 case RADEON_HPD_5: 828 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE) 829 connected = true; 830 break; 831 case RADEON_HPD_6: 832 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE) 833 connected = true; 834 break; 835 default: 836 break; 837 } 838 } else { 839 switch (hpd) { 840 case RADEON_HPD_1: 841 if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) 842 connected = true; 843 break; 844 case RADEON_HPD_2: 845 if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) 846 connected = true; 847 break; 848 case RADEON_HPD_3: 849 if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) 850 connected = true; 851 break; 852 default: 853 break; 854 } 855 } 856 return connected; 857 } 858 859 void r600_hpd_set_polarity(struct radeon_device *rdev, 860 enum radeon_hpd_id hpd) 861 { 862 u32 tmp; 863 bool connected = r600_hpd_sense(rdev, hpd); 864 865 if (ASIC_IS_DCE3(rdev)) { 866 switch (hpd) { 867 case RADEON_HPD_1: 868 tmp = RREG32(DC_HPD1_INT_CONTROL); 869 if (connected) 870 tmp &= ~DC_HPDx_INT_POLARITY; 871 else 872 tmp |= DC_HPDx_INT_POLARITY; 873 WREG32(DC_HPD1_INT_CONTROL, tmp); 874 break; 875 case RADEON_HPD_2: 876 tmp = RREG32(DC_HPD2_INT_CONTROL); 877 if (connected) 878 tmp &= ~DC_HPDx_INT_POLARITY; 879 else 880 tmp |= DC_HPDx_INT_POLARITY; 881 WREG32(DC_HPD2_INT_CONTROL, tmp); 882 break; 883 case RADEON_HPD_3: 884 tmp = RREG32(DC_HPD3_INT_CONTROL); 885 if (connected) 886 tmp &= ~DC_HPDx_INT_POLARITY; 887 else 888 tmp |= DC_HPDx_INT_POLARITY; 889 WREG32(DC_HPD3_INT_CONTROL, tmp); 890 break; 891 case RADEON_HPD_4: 892 tmp = RREG32(DC_HPD4_INT_CONTROL); 893 if (connected) 894 tmp &= ~DC_HPDx_INT_POLARITY; 895 else 896 tmp |= DC_HPDx_INT_POLARITY; 897 WREG32(DC_HPD4_INT_CONTROL, tmp); 898 break; 899 case RADEON_HPD_5: 900 tmp = RREG32(DC_HPD5_INT_CONTROL); 901 if (connected) 902 tmp &= ~DC_HPDx_INT_POLARITY; 903 else 904 tmp |= DC_HPDx_INT_POLARITY; 905 WREG32(DC_HPD5_INT_CONTROL, tmp); 906 break; 907 /* DCE 3.2 */ 908 case RADEON_HPD_6: 909 tmp = RREG32(DC_HPD6_INT_CONTROL); 910 if (connected) 911 tmp &= ~DC_HPDx_INT_POLARITY; 912 else 913 tmp |= DC_HPDx_INT_POLARITY; 914 WREG32(DC_HPD6_INT_CONTROL, tmp); 915 break; 916 default: 917 break; 918 } 919 } else { 920 switch (hpd) { 921 case RADEON_HPD_1: 922 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL); 923 if (connected) 924 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; 925 else 926 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; 927 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); 928 break; 929 case RADEON_HPD_2: 930 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL); 931 if (connected) 932 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; 933 else 934 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; 935 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); 936 break; 937 case RADEON_HPD_3: 938 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL); 939 if (connected) 940 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; 941 else 942 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; 943 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); 944 break; 945 default: 946 break; 947 } 948 } 949 } 950 951 void r600_hpd_init(struct radeon_device *rdev) 952 { 953 struct drm_device *dev = rdev->ddev; 954 struct drm_connector *connector; 955 unsigned enable = 0; 956 957 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 958 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 959 960 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || 961 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { 962 /* don't try to enable hpd on eDP or LVDS avoid breaking the 963 * aux dp channel on imac and help (but not completely fix) 964 * https://bugzilla.redhat.com/show_bug.cgi?id=726143 965 */ 966 continue; 967 } 968 if (ASIC_IS_DCE3(rdev)) { 969 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa); 970 if (ASIC_IS_DCE32(rdev)) 971 tmp |= DC_HPDx_EN; 972 973 switch (radeon_connector->hpd.hpd) { 974 case RADEON_HPD_1: 975 WREG32(DC_HPD1_CONTROL, tmp); 976 break; 977 case RADEON_HPD_2: 978 WREG32(DC_HPD2_CONTROL, tmp); 979 break; 980 case RADEON_HPD_3: 981 WREG32(DC_HPD3_CONTROL, tmp); 982 break; 983 case RADEON_HPD_4: 984 WREG32(DC_HPD4_CONTROL, tmp); 985 break; 986 /* DCE 3.2 */ 987 case RADEON_HPD_5: 988 WREG32(DC_HPD5_CONTROL, tmp); 989 break; 990 case RADEON_HPD_6: 991 WREG32(DC_HPD6_CONTROL, tmp); 992 break; 993 default: 994 break; 995 } 996 } else { 997 switch (radeon_connector->hpd.hpd) { 998 case RADEON_HPD_1: 999 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN); 1000 break; 1001 case RADEON_HPD_2: 1002 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN); 1003 break; 1004 case RADEON_HPD_3: 1005 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN); 1006 break; 1007 default: 1008 break; 1009 } 1010 } 1011 enable |= 1 << radeon_connector->hpd.hpd; 1012 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); 1013 } 1014 radeon_irq_kms_enable_hpd(rdev, enable); 1015 } 1016 1017 void r600_hpd_fini(struct radeon_device *rdev) 1018 { 1019 struct drm_device *dev = rdev->ddev; 1020 struct drm_connector *connector; 1021 unsigned disable = 0; 1022 1023 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 1024 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1025 if (ASIC_IS_DCE3(rdev)) { 1026 switch (radeon_connector->hpd.hpd) { 1027 case RADEON_HPD_1: 1028 WREG32(DC_HPD1_CONTROL, 0); 1029 break; 1030 case RADEON_HPD_2: 1031 WREG32(DC_HPD2_CONTROL, 0); 1032 break; 1033 case RADEON_HPD_3: 1034 WREG32(DC_HPD3_CONTROL, 0); 1035 break; 1036 case RADEON_HPD_4: 1037 WREG32(DC_HPD4_CONTROL, 0); 1038 break; 1039 /* DCE 3.2 */ 1040 case RADEON_HPD_5: 1041 WREG32(DC_HPD5_CONTROL, 0); 1042 break; 1043 case RADEON_HPD_6: 1044 WREG32(DC_HPD6_CONTROL, 0); 1045 break; 1046 default: 1047 break; 1048 } 1049 } else { 1050 switch (radeon_connector->hpd.hpd) { 1051 case RADEON_HPD_1: 1052 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0); 1053 break; 1054 case RADEON_HPD_2: 1055 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0); 1056 break; 1057 case RADEON_HPD_3: 1058 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0); 1059 break; 1060 default: 1061 break; 1062 } 1063 } 1064 disable |= 1 << radeon_connector->hpd.hpd; 1065 } 1066 radeon_irq_kms_disable_hpd(rdev, disable); 1067 } 1068 1069 #ifdef __NetBSD__ 1070 /* 1071 * XXX Can't use bus_space here because this is all mapped through the 1072 * radeon_bo abstraction. Can't assume we're x86 because this is 1073 * AMD/ATI Radeon, not Intel. 1074 */ 1075 1076 # define __iomem volatile 1077 # define readl fake_readl 1078 1079 static inline uint32_t 1080 fake_readl(const void __iomem *ptr) 1081 { 1082 uint32_t v; 1083 1084 v = *(const uint32_t __iomem *)ptr; 1085 membar_consumer(); 1086 1087 return v; 1088 } 1089 #endif 1090 1091 /* 1092 * R600 PCIE GART 1093 */ 1094 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev) 1095 { 1096 unsigned i; 1097 u32 tmp; 1098 1099 /* flush hdp cache so updates hit vram */ 1100 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) && 1101 !(rdev->flags & RADEON_IS_AGP)) { 1102 void __iomem *ptr = rdev->gart.ptr; 1103 1104 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read 1105 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL 1106 * This seems to cause problems on some AGP cards. Just use the old 1107 * method for them. 1108 */ 1109 WREG32(HDP_DEBUG1, 0); 1110 (void)readl(ptr); 1111 } else 1112 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); 1113 1114 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12); 1115 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12); 1116 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1)); 1117 for (i = 0; i < rdev->usec_timeout; i++) { 1118 /* read MC_STATUS */ 1119 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE); 1120 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT; 1121 if (tmp == 2) { 1122 printk(KERN_WARNING "[drm] r600 flush TLB failed\n"); 1123 return; 1124 } 1125 if (tmp) { 1126 return; 1127 } 1128 udelay(1); 1129 } 1130 } 1131 1132 #ifdef __NetBSD__ 1133 # undef __iomem 1134 # undef readl 1135 #endif 1136 1137 int r600_pcie_gart_init(struct radeon_device *rdev) 1138 { 1139 int r; 1140 1141 if (rdev->gart.robj) { 1142 WARN(1, "R600 PCIE GART already initialized\n"); 1143 return 0; 1144 } 1145 /* Initialize common gart structure */ 1146 r = radeon_gart_init(rdev); 1147 if (r) 1148 return r; 1149 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; 1150 return radeon_gart_table_vram_alloc(rdev); 1151 } 1152 1153 static int r600_pcie_gart_enable(struct radeon_device *rdev) 1154 { 1155 u32 tmp; 1156 int r, i; 1157 1158 if (rdev->gart.robj == NULL) { 1159 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); 1160 return -EINVAL; 1161 } 1162 r = radeon_gart_table_vram_pin(rdev); 1163 if (r) 1164 return r; 1165 1166 /* Setup L2 cache */ 1167 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | 1168 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 1169 EFFECTIVE_L2_QUEUE_SIZE(7)); 1170 WREG32(VM_L2_CNTL2, 0); 1171 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); 1172 /* Setup TLB control */ 1173 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | 1174 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 1175 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | 1176 ENABLE_WAIT_L2_QUERY; 1177 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); 1178 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); 1179 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING); 1180 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); 1181 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); 1182 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); 1183 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); 1184 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); 1185 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); 1186 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); 1187 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); 1188 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); 1189 WREG32(MC_VM_L1_TLB_MCB_RD_UVD_CNTL, tmp); 1190 WREG32(MC_VM_L1_TLB_MCB_WR_UVD_CNTL, tmp); 1191 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); 1192 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); 1193 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); 1194 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); 1195 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); 1196 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | 1197 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); 1198 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 1199 (u32)(rdev->dummy_page.addr >> 12)); 1200 for (i = 1; i < 7; i++) 1201 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 1202 1203 r600_pcie_gart_tlb_flush(rdev); 1204 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 1205 (unsigned)(rdev->mc.gtt_size >> 20), 1206 (unsigned long long)rdev->gart.table_addr); 1207 rdev->gart.ready = true; 1208 return 0; 1209 } 1210 1211 static void r600_pcie_gart_disable(struct radeon_device *rdev) 1212 { 1213 u32 tmp; 1214 int i; 1215 1216 /* Disable all tables */ 1217 for (i = 0; i < 7; i++) 1218 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 1219 1220 /* Disable L2 cache */ 1221 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | 1222 EFFECTIVE_L2_QUEUE_SIZE(7)); 1223 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); 1224 /* Setup L1 TLB control */ 1225 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | 1226 ENABLE_WAIT_L2_QUERY; 1227 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); 1228 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); 1229 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); 1230 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); 1231 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); 1232 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); 1233 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); 1234 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); 1235 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp); 1236 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp); 1237 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); 1238 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); 1239 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp); 1240 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); 1241 WREG32(MC_VM_L1_TLB_MCB_RD_UVD_CNTL, tmp); 1242 WREG32(MC_VM_L1_TLB_MCB_WR_UVD_CNTL, tmp); 1243 radeon_gart_table_vram_unpin(rdev); 1244 } 1245 1246 static void r600_pcie_gart_fini(struct radeon_device *rdev) 1247 { 1248 radeon_gart_fini(rdev); 1249 r600_pcie_gart_disable(rdev); 1250 radeon_gart_table_vram_free(rdev); 1251 } 1252 1253 static void r600_agp_enable(struct radeon_device *rdev) 1254 { 1255 u32 tmp; 1256 int i; 1257 1258 /* Setup L2 cache */ 1259 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | 1260 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 1261 EFFECTIVE_L2_QUEUE_SIZE(7)); 1262 WREG32(VM_L2_CNTL2, 0); 1263 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); 1264 /* Setup TLB control */ 1265 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | 1266 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 1267 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | 1268 ENABLE_WAIT_L2_QUERY; 1269 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); 1270 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); 1271 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING); 1272 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); 1273 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); 1274 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); 1275 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); 1276 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); 1277 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); 1278 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); 1279 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); 1280 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); 1281 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); 1282 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); 1283 for (i = 0; i < 7; i++) 1284 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 1285 } 1286 1287 int r600_mc_wait_for_idle(struct radeon_device *rdev) 1288 { 1289 unsigned i; 1290 u32 tmp; 1291 1292 for (i = 0; i < rdev->usec_timeout; i++) { 1293 /* read MC_STATUS */ 1294 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00; 1295 if (!tmp) 1296 return 0; 1297 udelay(1); 1298 } 1299 return -1; 1300 } 1301 1302 uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg) 1303 { 1304 unsigned long flags; 1305 uint32_t r; 1306 1307 spin_lock_irqsave(&rdev->mc_idx_lock, flags); 1308 WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg)); 1309 r = RREG32(R_0028FC_MC_DATA); 1310 WREG32(R_0028F8_MC_INDEX, ~C_0028F8_MC_IND_ADDR); 1311 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); 1312 return r; 1313 } 1314 1315 void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 1316 { 1317 unsigned long flags; 1318 1319 spin_lock_irqsave(&rdev->mc_idx_lock, flags); 1320 WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg) | 1321 S_0028F8_MC_IND_WR_EN(1)); 1322 WREG32(R_0028FC_MC_DATA, v); 1323 WREG32(R_0028F8_MC_INDEX, 0x7F); 1324 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); 1325 } 1326 1327 static void r600_mc_program(struct radeon_device *rdev) 1328 { 1329 struct rv515_mc_save save; 1330 u32 tmp; 1331 int i, j; 1332 1333 /* Initialize HDP */ 1334 for (i = 0, j = 0; i < 32; i++, j += 0x18) { 1335 WREG32((0x2c14 + j), 0x00000000); 1336 WREG32((0x2c18 + j), 0x00000000); 1337 WREG32((0x2c1c + j), 0x00000000); 1338 WREG32((0x2c20 + j), 0x00000000); 1339 WREG32((0x2c24 + j), 0x00000000); 1340 } 1341 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0); 1342 1343 rv515_mc_stop(rdev, &save); 1344 if (r600_mc_wait_for_idle(rdev)) { 1345 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1346 } 1347 /* Lockout access through VGA aperture (doesn't exist before R600) */ 1348 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); 1349 /* Update configuration */ 1350 if (rdev->flags & RADEON_IS_AGP) { 1351 if (rdev->mc.vram_start < rdev->mc.gtt_start) { 1352 /* VRAM before AGP */ 1353 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 1354 rdev->mc.vram_start >> 12); 1355 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 1356 rdev->mc.gtt_end >> 12); 1357 } else { 1358 /* VRAM after AGP */ 1359 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 1360 rdev->mc.gtt_start >> 12); 1361 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 1362 rdev->mc.vram_end >> 12); 1363 } 1364 } else { 1365 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12); 1366 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12); 1367 } 1368 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12); 1369 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; 1370 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); 1371 WREG32(MC_VM_FB_LOCATION, tmp); 1372 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); 1373 WREG32(HDP_NONSURFACE_INFO, (2 << 7)); 1374 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF); 1375 if (rdev->flags & RADEON_IS_AGP) { 1376 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22); 1377 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22); 1378 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); 1379 } else { 1380 WREG32(MC_VM_AGP_BASE, 0); 1381 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); 1382 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); 1383 } 1384 if (r600_mc_wait_for_idle(rdev)) { 1385 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1386 } 1387 rv515_mc_resume(rdev, &save); 1388 /* we need to own VRAM, so turn off the VGA renderer here 1389 * to stop it overwriting our objects */ 1390 rv515_vga_render_disable(rdev); 1391 } 1392 1393 /** 1394 * r600_vram_gtt_location - try to find VRAM & GTT location 1395 * @rdev: radeon device structure holding all necessary informations 1396 * @mc: memory controller structure holding memory informations 1397 * 1398 * Function will place try to place VRAM at same place as in CPU (PCI) 1399 * address space as some GPU seems to have issue when we reprogram at 1400 * different address space. 1401 * 1402 * If there is not enough space to fit the unvisible VRAM after the 1403 * aperture then we limit the VRAM size to the aperture. 1404 * 1405 * If we are using AGP then place VRAM adjacent to AGP aperture are we need 1406 * them to be in one from GPU point of view so that we can program GPU to 1407 * catch access outside them (weird GPU policy see ??). 1408 * 1409 * This function will never fails, worst case are limiting VRAM or GTT. 1410 * 1411 * Note: GTT start, end, size should be initialized before calling this 1412 * function on AGP platform. 1413 */ 1414 static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) 1415 { 1416 u64 size_bf, size_af; 1417 1418 if (mc->mc_vram_size > 0xE0000000) { 1419 /* leave room for at least 512M GTT */ 1420 dev_warn(rdev->dev, "limiting VRAM\n"); 1421 mc->real_vram_size = 0xE0000000; 1422 mc->mc_vram_size = 0xE0000000; 1423 } 1424 if (rdev->flags & RADEON_IS_AGP) { 1425 size_bf = mc->gtt_start; 1426 size_af = mc->mc_mask - mc->gtt_end; 1427 if (size_bf > size_af) { 1428 if (mc->mc_vram_size > size_bf) { 1429 dev_warn(rdev->dev, "limiting VRAM\n"); 1430 mc->real_vram_size = size_bf; 1431 mc->mc_vram_size = size_bf; 1432 } 1433 mc->vram_start = mc->gtt_start - mc->mc_vram_size; 1434 } else { 1435 if (mc->mc_vram_size > size_af) { 1436 dev_warn(rdev->dev, "limiting VRAM\n"); 1437 mc->real_vram_size = size_af; 1438 mc->mc_vram_size = size_af; 1439 } 1440 mc->vram_start = mc->gtt_end + 1; 1441 } 1442 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; 1443 dev_info(rdev->dev, "VRAM: %"PRIu64"M 0x%08"PRIX64" - 0x%08"PRIX64" (%"PRIu64"M used)\n", 1444 mc->mc_vram_size >> 20, mc->vram_start, 1445 mc->vram_end, mc->real_vram_size >> 20); 1446 } else { 1447 u64 base = 0; 1448 if (rdev->flags & RADEON_IS_IGP) { 1449 base = RREG32(MC_VM_FB_LOCATION) & 0xFFFF; 1450 base <<= 24; 1451 } 1452 radeon_vram_location(rdev, &rdev->mc, base); 1453 rdev->mc.gtt_base_align = 0; 1454 radeon_gtt_location(rdev, mc); 1455 } 1456 } 1457 1458 static int r600_mc_init(struct radeon_device *rdev) 1459 { 1460 u32 tmp; 1461 int chansize, numchan; 1462 uint32_t h_addr, l_addr; 1463 unsigned long long k8_addr; 1464 1465 /* Get VRAM informations */ 1466 rdev->mc.vram_is_ddr = true; 1467 tmp = RREG32(RAMCFG); 1468 if (tmp & CHANSIZE_OVERRIDE) { 1469 chansize = 16; 1470 } else if (tmp & CHANSIZE_MASK) { 1471 chansize = 64; 1472 } else { 1473 chansize = 32; 1474 } 1475 tmp = RREG32(CHMAP); 1476 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { 1477 case 0: 1478 default: 1479 numchan = 1; 1480 break; 1481 case 1: 1482 numchan = 2; 1483 break; 1484 case 2: 1485 numchan = 4; 1486 break; 1487 case 3: 1488 numchan = 8; 1489 break; 1490 } 1491 rdev->mc.vram_width = numchan * chansize; 1492 /* Could aper size report 0 ? */ 1493 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); 1494 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); 1495 /* Setup GPU memory space */ 1496 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); 1497 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); 1498 rdev->mc.visible_vram_size = rdev->mc.aper_size; 1499 r600_vram_gtt_location(rdev, &rdev->mc); 1500 1501 if (rdev->flags & RADEON_IS_IGP) { 1502 rs690_pm_info(rdev); 1503 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); 1504 1505 if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) { 1506 /* Use K8 direct mapping for fast fb access. */ 1507 rdev->fastfb_working = false; 1508 h_addr = G_000012_K8_ADDR_EXT(RREG32_MC(R_000012_MC_MISC_UMA_CNTL)); 1509 l_addr = RREG32_MC(R_000011_K8_FB_LOCATION); 1510 k8_addr = ((unsigned long long)h_addr) << 32 | l_addr; 1511 #if defined(CONFIG_X86_32) && !defined(CONFIG_X86_PAE) 1512 if (k8_addr + rdev->mc.visible_vram_size < 0x100000000ULL) 1513 #endif 1514 { 1515 /* FastFB shall be used with UMA memory. Here it is simply disabled when sideport 1516 * memory is present. 1517 */ 1518 if (rdev->mc.igp_sideport_enabled == false && radeon_fastfb == 1) { 1519 DRM_INFO("Direct mapping: aper base at 0x%llx, replaced by direct mapping base 0x%llx.\n", 1520 (unsigned long long)rdev->mc.aper_base, k8_addr); 1521 rdev->mc.aper_base = (resource_size_t)k8_addr; 1522 rdev->fastfb_working = true; 1523 } 1524 } 1525 } 1526 } 1527 1528 radeon_update_bandwidth_info(rdev); 1529 return 0; 1530 } 1531 1532 int r600_vram_scratch_init(struct radeon_device *rdev) 1533 { 1534 int r; 1535 1536 if (rdev->vram_scratch.robj == NULL) { 1537 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, 1538 PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM, 1539 0, NULL, NULL, &rdev->vram_scratch.robj); 1540 if (r) { 1541 return r; 1542 } 1543 } 1544 1545 r = radeon_bo_reserve(rdev->vram_scratch.robj, false); 1546 if (unlikely(r != 0)) 1547 return r; 1548 r = radeon_bo_pin(rdev->vram_scratch.robj, 1549 RADEON_GEM_DOMAIN_VRAM, &rdev->vram_scratch.gpu_addr); 1550 if (r) { 1551 radeon_bo_unreserve(rdev->vram_scratch.robj); 1552 return r; 1553 } 1554 r = radeon_bo_kmap(rdev->vram_scratch.robj, 1555 (void **)__UNVOLATILE(&rdev->vram_scratch.ptr)); 1556 if (r) 1557 radeon_bo_unpin(rdev->vram_scratch.robj); 1558 radeon_bo_unreserve(rdev->vram_scratch.robj); 1559 1560 return r; 1561 } 1562 1563 void r600_vram_scratch_fini(struct radeon_device *rdev) 1564 { 1565 int r; 1566 1567 if (rdev->vram_scratch.robj == NULL) { 1568 return; 1569 } 1570 r = radeon_bo_reserve(rdev->vram_scratch.robj, false); 1571 if (likely(r == 0)) { 1572 radeon_bo_kunmap(rdev->vram_scratch.robj); 1573 radeon_bo_unpin(rdev->vram_scratch.robj); 1574 radeon_bo_unreserve(rdev->vram_scratch.robj); 1575 } 1576 radeon_bo_unref(&rdev->vram_scratch.robj); 1577 } 1578 1579 void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung) 1580 { 1581 u32 tmp = RREG32(R600_BIOS_3_SCRATCH); 1582 1583 if (hung) 1584 tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG; 1585 else 1586 tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG; 1587 1588 WREG32(R600_BIOS_3_SCRATCH, tmp); 1589 } 1590 1591 static void r600_print_gpu_status_regs(struct radeon_device *rdev) 1592 { 1593 dev_info(rdev->dev, " R_008010_GRBM_STATUS = 0x%08X\n", 1594 RREG32(R_008010_GRBM_STATUS)); 1595 dev_info(rdev->dev, " R_008014_GRBM_STATUS2 = 0x%08X\n", 1596 RREG32(R_008014_GRBM_STATUS2)); 1597 dev_info(rdev->dev, " R_000E50_SRBM_STATUS = 0x%08X\n", 1598 RREG32(R_000E50_SRBM_STATUS)); 1599 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n", 1600 RREG32(CP_STALLED_STAT1)); 1601 dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n", 1602 RREG32(CP_STALLED_STAT2)); 1603 dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n", 1604 RREG32(CP_BUSY_STAT)); 1605 dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n", 1606 RREG32(CP_STAT)); 1607 dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n", 1608 RREG32(DMA_STATUS_REG)); 1609 } 1610 1611 static bool r600_is_display_hung(struct radeon_device *rdev) 1612 { 1613 u32 crtc_hung = 0; 1614 u32 crtc_status[2]; 1615 u32 i, j, tmp; 1616 1617 for (i = 0; i < rdev->num_crtc; i++) { 1618 if (RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN) { 1619 crtc_status[i] = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]); 1620 crtc_hung |= (1 << i); 1621 } 1622 } 1623 1624 for (j = 0; j < 10; j++) { 1625 for (i = 0; i < rdev->num_crtc; i++) { 1626 if (crtc_hung & (1 << i)) { 1627 tmp = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]); 1628 if (tmp != crtc_status[i]) 1629 crtc_hung &= ~(1 << i); 1630 } 1631 } 1632 if (crtc_hung == 0) 1633 return false; 1634 udelay(100); 1635 } 1636 1637 return true; 1638 } 1639 1640 u32 r600_gpu_check_soft_reset(struct radeon_device *rdev) 1641 { 1642 u32 reset_mask = 0; 1643 u32 tmp; 1644 1645 /* GRBM_STATUS */ 1646 tmp = RREG32(R_008010_GRBM_STATUS); 1647 if (rdev->family >= CHIP_RV770) { 1648 if (G_008010_PA_BUSY(tmp) | G_008010_SC_BUSY(tmp) | 1649 G_008010_SH_BUSY(tmp) | G_008010_SX_BUSY(tmp) | 1650 G_008010_TA_BUSY(tmp) | G_008010_VGT_BUSY(tmp) | 1651 G_008010_DB03_BUSY(tmp) | G_008010_CB03_BUSY(tmp) | 1652 G_008010_SPI03_BUSY(tmp) | G_008010_VGT_BUSY_NO_DMA(tmp)) 1653 reset_mask |= RADEON_RESET_GFX; 1654 } else { 1655 if (G_008010_PA_BUSY(tmp) | G_008010_SC_BUSY(tmp) | 1656 G_008010_SH_BUSY(tmp) | G_008010_SX_BUSY(tmp) | 1657 G_008010_TA03_BUSY(tmp) | G_008010_VGT_BUSY(tmp) | 1658 G_008010_DB03_BUSY(tmp) | G_008010_CB03_BUSY(tmp) | 1659 G_008010_SPI03_BUSY(tmp) | G_008010_VGT_BUSY_NO_DMA(tmp)) 1660 reset_mask |= RADEON_RESET_GFX; 1661 } 1662 1663 if (G_008010_CF_RQ_PENDING(tmp) | G_008010_PF_RQ_PENDING(tmp) | 1664 G_008010_CP_BUSY(tmp) | G_008010_CP_COHERENCY_BUSY(tmp)) 1665 reset_mask |= RADEON_RESET_CP; 1666 1667 if (G_008010_GRBM_EE_BUSY(tmp)) 1668 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP; 1669 1670 /* DMA_STATUS_REG */ 1671 tmp = RREG32(DMA_STATUS_REG); 1672 if (!(tmp & DMA_IDLE)) 1673 reset_mask |= RADEON_RESET_DMA; 1674 1675 /* SRBM_STATUS */ 1676 tmp = RREG32(R_000E50_SRBM_STATUS); 1677 if (G_000E50_RLC_RQ_PENDING(tmp) | G_000E50_RLC_BUSY(tmp)) 1678 reset_mask |= RADEON_RESET_RLC; 1679 1680 if (G_000E50_IH_BUSY(tmp)) 1681 reset_mask |= RADEON_RESET_IH; 1682 1683 if (G_000E50_SEM_BUSY(tmp)) 1684 reset_mask |= RADEON_RESET_SEM; 1685 1686 if (G_000E50_GRBM_RQ_PENDING(tmp)) 1687 reset_mask |= RADEON_RESET_GRBM; 1688 1689 if (G_000E50_VMC_BUSY(tmp)) 1690 reset_mask |= RADEON_RESET_VMC; 1691 1692 if (G_000E50_MCB_BUSY(tmp) | G_000E50_MCDZ_BUSY(tmp) | 1693 G_000E50_MCDY_BUSY(tmp) | G_000E50_MCDX_BUSY(tmp) | 1694 G_000E50_MCDW_BUSY(tmp)) 1695 reset_mask |= RADEON_RESET_MC; 1696 1697 if (r600_is_display_hung(rdev)) 1698 reset_mask |= RADEON_RESET_DISPLAY; 1699 1700 /* Skip MC reset as it's mostly likely not hung, just busy */ 1701 if (reset_mask & RADEON_RESET_MC) { 1702 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask); 1703 reset_mask &= ~RADEON_RESET_MC; 1704 } 1705 1706 return reset_mask; 1707 } 1708 1709 static void r600_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask) 1710 { 1711 struct rv515_mc_save save; 1712 u32 grbm_soft_reset = 0, srbm_soft_reset = 0; 1713 u32 tmp; 1714 1715 if (reset_mask == 0) 1716 return; 1717 1718 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask); 1719 1720 r600_print_gpu_status_regs(rdev); 1721 1722 /* Disable CP parsing/prefetching */ 1723 if (rdev->family >= CHIP_RV770) 1724 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1) | S_0086D8_CP_PFP_HALT(1)); 1725 else 1726 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); 1727 1728 /* disable the RLC */ 1729 WREG32(RLC_CNTL, 0); 1730 1731 if (reset_mask & RADEON_RESET_DMA) { 1732 /* Disable DMA */ 1733 tmp = RREG32(DMA_RB_CNTL); 1734 tmp &= ~DMA_RB_ENABLE; 1735 WREG32(DMA_RB_CNTL, tmp); 1736 } 1737 1738 mdelay(50); 1739 1740 rv515_mc_stop(rdev, &save); 1741 if (r600_mc_wait_for_idle(rdev)) { 1742 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1743 } 1744 1745 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) { 1746 if (rdev->family >= CHIP_RV770) 1747 grbm_soft_reset |= S_008020_SOFT_RESET_DB(1) | 1748 S_008020_SOFT_RESET_CB(1) | 1749 S_008020_SOFT_RESET_PA(1) | 1750 S_008020_SOFT_RESET_SC(1) | 1751 S_008020_SOFT_RESET_SPI(1) | 1752 S_008020_SOFT_RESET_SX(1) | 1753 S_008020_SOFT_RESET_SH(1) | 1754 S_008020_SOFT_RESET_TC(1) | 1755 S_008020_SOFT_RESET_TA(1) | 1756 S_008020_SOFT_RESET_VC(1) | 1757 S_008020_SOFT_RESET_VGT(1); 1758 else 1759 grbm_soft_reset |= S_008020_SOFT_RESET_CR(1) | 1760 S_008020_SOFT_RESET_DB(1) | 1761 S_008020_SOFT_RESET_CB(1) | 1762 S_008020_SOFT_RESET_PA(1) | 1763 S_008020_SOFT_RESET_SC(1) | 1764 S_008020_SOFT_RESET_SMX(1) | 1765 S_008020_SOFT_RESET_SPI(1) | 1766 S_008020_SOFT_RESET_SX(1) | 1767 S_008020_SOFT_RESET_SH(1) | 1768 S_008020_SOFT_RESET_TC(1) | 1769 S_008020_SOFT_RESET_TA(1) | 1770 S_008020_SOFT_RESET_VC(1) | 1771 S_008020_SOFT_RESET_VGT(1); 1772 } 1773 1774 if (reset_mask & RADEON_RESET_CP) { 1775 grbm_soft_reset |= S_008020_SOFT_RESET_CP(1) | 1776 S_008020_SOFT_RESET_VGT(1); 1777 1778 srbm_soft_reset |= S_000E60_SOFT_RESET_GRBM(1); 1779 } 1780 1781 if (reset_mask & RADEON_RESET_DMA) { 1782 if (rdev->family >= CHIP_RV770) 1783 srbm_soft_reset |= RV770_SOFT_RESET_DMA; 1784 else 1785 srbm_soft_reset |= SOFT_RESET_DMA; 1786 } 1787 1788 if (reset_mask & RADEON_RESET_RLC) 1789 srbm_soft_reset |= S_000E60_SOFT_RESET_RLC(1); 1790 1791 if (reset_mask & RADEON_RESET_SEM) 1792 srbm_soft_reset |= S_000E60_SOFT_RESET_SEM(1); 1793 1794 if (reset_mask & RADEON_RESET_IH) 1795 srbm_soft_reset |= S_000E60_SOFT_RESET_IH(1); 1796 1797 if (reset_mask & RADEON_RESET_GRBM) 1798 srbm_soft_reset |= S_000E60_SOFT_RESET_GRBM(1); 1799 1800 if (!(rdev->flags & RADEON_IS_IGP)) { 1801 if (reset_mask & RADEON_RESET_MC) 1802 srbm_soft_reset |= S_000E60_SOFT_RESET_MC(1); 1803 } 1804 1805 if (reset_mask & RADEON_RESET_VMC) 1806 srbm_soft_reset |= S_000E60_SOFT_RESET_VMC(1); 1807 1808 if (grbm_soft_reset) { 1809 tmp = RREG32(R_008020_GRBM_SOFT_RESET); 1810 tmp |= grbm_soft_reset; 1811 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp); 1812 WREG32(R_008020_GRBM_SOFT_RESET, tmp); 1813 tmp = RREG32(R_008020_GRBM_SOFT_RESET); 1814 1815 udelay(50); 1816 1817 tmp &= ~grbm_soft_reset; 1818 WREG32(R_008020_GRBM_SOFT_RESET, tmp); 1819 tmp = RREG32(R_008020_GRBM_SOFT_RESET); 1820 } 1821 1822 if (srbm_soft_reset) { 1823 tmp = RREG32(SRBM_SOFT_RESET); 1824 tmp |= srbm_soft_reset; 1825 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1826 WREG32(SRBM_SOFT_RESET, tmp); 1827 tmp = RREG32(SRBM_SOFT_RESET); 1828 1829 udelay(50); 1830 1831 tmp &= ~srbm_soft_reset; 1832 WREG32(SRBM_SOFT_RESET, tmp); 1833 tmp = RREG32(SRBM_SOFT_RESET); 1834 } 1835 1836 /* Wait a little for things to settle down */ 1837 mdelay(1); 1838 1839 rv515_mc_resume(rdev, &save); 1840 udelay(50); 1841 1842 r600_print_gpu_status_regs(rdev); 1843 } 1844 1845 static void r600_gpu_pci_config_reset(struct radeon_device *rdev) 1846 { 1847 struct rv515_mc_save save; 1848 u32 tmp, i; 1849 1850 dev_info(rdev->dev, "GPU pci config reset\n"); 1851 1852 /* disable dpm? */ 1853 1854 /* Disable CP parsing/prefetching */ 1855 if (rdev->family >= CHIP_RV770) 1856 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1) | S_0086D8_CP_PFP_HALT(1)); 1857 else 1858 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); 1859 1860 /* disable the RLC */ 1861 WREG32(RLC_CNTL, 0); 1862 1863 /* Disable DMA */ 1864 tmp = RREG32(DMA_RB_CNTL); 1865 tmp &= ~DMA_RB_ENABLE; 1866 WREG32(DMA_RB_CNTL, tmp); 1867 1868 mdelay(50); 1869 1870 /* set mclk/sclk to bypass */ 1871 if (rdev->family >= CHIP_RV770) 1872 rv770_set_clk_bypass_mode(rdev); 1873 /* disable BM */ 1874 pci_clear_master(rdev->pdev); 1875 /* disable mem access */ 1876 rv515_mc_stop(rdev, &save); 1877 if (r600_mc_wait_for_idle(rdev)) { 1878 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1879 } 1880 1881 /* BIF reset workaround. Not sure if this is needed on 6xx */ 1882 tmp = RREG32(BUS_CNTL); 1883 tmp |= VGA_COHE_SPEC_TIMER_DIS; 1884 WREG32(BUS_CNTL, tmp); 1885 1886 tmp = RREG32(BIF_SCRATCH0); 1887 1888 /* reset */ 1889 radeon_pci_config_reset(rdev); 1890 mdelay(1); 1891 1892 /* BIF reset workaround. Not sure if this is needed on 6xx */ 1893 tmp = SOFT_RESET_BIF; 1894 WREG32(SRBM_SOFT_RESET, tmp); 1895 mdelay(1); 1896 WREG32(SRBM_SOFT_RESET, 0); 1897 1898 /* wait for asic to come out of reset */ 1899 for (i = 0; i < rdev->usec_timeout; i++) { 1900 if (RREG32(CONFIG_MEMSIZE) != 0xffffffff) 1901 break; 1902 udelay(1); 1903 } 1904 } 1905 1906 int r600_asic_reset(struct radeon_device *rdev) 1907 { 1908 u32 reset_mask; 1909 1910 reset_mask = r600_gpu_check_soft_reset(rdev); 1911 1912 if (reset_mask) 1913 r600_set_bios_scratch_engine_hung(rdev, true); 1914 1915 /* try soft reset */ 1916 r600_gpu_soft_reset(rdev, reset_mask); 1917 1918 reset_mask = r600_gpu_check_soft_reset(rdev); 1919 1920 /* try pci config reset */ 1921 if (reset_mask && radeon_hard_reset) 1922 r600_gpu_pci_config_reset(rdev); 1923 1924 reset_mask = r600_gpu_check_soft_reset(rdev); 1925 1926 if (!reset_mask) 1927 r600_set_bios_scratch_engine_hung(rdev, false); 1928 1929 return 0; 1930 } 1931 1932 /** 1933 * r600_gfx_is_lockup - Check if the GFX engine is locked up 1934 * 1935 * @rdev: radeon_device pointer 1936 * @ring: radeon_ring structure holding ring information 1937 * 1938 * Check if the GFX engine is locked up. 1939 * Returns true if the engine appears to be locked up, false if not. 1940 */ 1941 bool r600_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) 1942 { 1943 u32 reset_mask = r600_gpu_check_soft_reset(rdev); 1944 1945 if (!(reset_mask & (RADEON_RESET_GFX | 1946 RADEON_RESET_COMPUTE | 1947 RADEON_RESET_CP))) { 1948 radeon_ring_lockup_update(rdev, ring); 1949 return false; 1950 } 1951 return radeon_ring_test_lockup(rdev, ring); 1952 } 1953 1954 u32 r6xx_remap_render_backend(struct radeon_device *rdev, 1955 u32 tiling_pipe_num, 1956 u32 max_rb_num, 1957 u32 total_max_rb_num, 1958 u32 disabled_rb_mask) 1959 { 1960 u32 rendering_pipe_num, rb_num_width, req_rb_num; 1961 u32 pipe_rb_ratio, pipe_rb_remain, tmp; 1962 u32 data = 0, mask = 1 << (max_rb_num - 1); 1963 unsigned i, j; 1964 1965 /* mask out the RBs that don't exist on that asic */ 1966 tmp = disabled_rb_mask | ((0xff << max_rb_num) & 0xff); 1967 /* make sure at least one RB is available */ 1968 if ((tmp & 0xff) != 0xff) 1969 disabled_rb_mask = tmp; 1970 1971 rendering_pipe_num = 1 << tiling_pipe_num; 1972 req_rb_num = total_max_rb_num - r600_count_pipe_bits(disabled_rb_mask); 1973 BUG_ON(rendering_pipe_num < req_rb_num); 1974 1975 pipe_rb_ratio = rendering_pipe_num / req_rb_num; 1976 pipe_rb_remain = rendering_pipe_num - pipe_rb_ratio * req_rb_num; 1977 1978 if (rdev->family <= CHIP_RV740) { 1979 /* r6xx/r7xx */ 1980 rb_num_width = 2; 1981 } else { 1982 /* eg+ */ 1983 rb_num_width = 4; 1984 } 1985 1986 for (i = 0; i < max_rb_num; i++) { 1987 if (!(mask & disabled_rb_mask)) { 1988 for (j = 0; j < pipe_rb_ratio; j++) { 1989 data <<= rb_num_width; 1990 data |= max_rb_num - i - 1; 1991 } 1992 if (pipe_rb_remain) { 1993 data <<= rb_num_width; 1994 data |= max_rb_num - i - 1; 1995 pipe_rb_remain--; 1996 } 1997 } 1998 mask >>= 1; 1999 } 2000 2001 return data; 2002 } 2003 2004 int r600_count_pipe_bits(uint32_t val) 2005 { 2006 return hweight32(val); 2007 } 2008 2009 static void r600_gpu_init(struct radeon_device *rdev) 2010 { 2011 u32 tiling_config; 2012 u32 ramcfg; 2013 u32 cc_gc_shader_pipe_config; 2014 u32 tmp; 2015 int i, j; 2016 u32 sq_config; 2017 u32 sq_gpr_resource_mgmt_1 = 0; 2018 u32 sq_gpr_resource_mgmt_2 = 0; 2019 u32 sq_thread_resource_mgmt = 0; 2020 u32 sq_stack_resource_mgmt_1 = 0; 2021 u32 sq_stack_resource_mgmt_2 = 0; 2022 u32 disabled_rb_mask; 2023 2024 rdev->config.r600.tiling_group_size = 256; 2025 switch (rdev->family) { 2026 case CHIP_R600: 2027 rdev->config.r600.max_pipes = 4; 2028 rdev->config.r600.max_tile_pipes = 8; 2029 rdev->config.r600.max_simds = 4; 2030 rdev->config.r600.max_backends = 4; 2031 rdev->config.r600.max_gprs = 256; 2032 rdev->config.r600.max_threads = 192; 2033 rdev->config.r600.max_stack_entries = 256; 2034 rdev->config.r600.max_hw_contexts = 8; 2035 rdev->config.r600.max_gs_threads = 16; 2036 rdev->config.r600.sx_max_export_size = 128; 2037 rdev->config.r600.sx_max_export_pos_size = 16; 2038 rdev->config.r600.sx_max_export_smx_size = 128; 2039 rdev->config.r600.sq_num_cf_insts = 2; 2040 break; 2041 case CHIP_RV630: 2042 case CHIP_RV635: 2043 rdev->config.r600.max_pipes = 2; 2044 rdev->config.r600.max_tile_pipes = 2; 2045 rdev->config.r600.max_simds = 3; 2046 rdev->config.r600.max_backends = 1; 2047 rdev->config.r600.max_gprs = 128; 2048 rdev->config.r600.max_threads = 192; 2049 rdev->config.r600.max_stack_entries = 128; 2050 rdev->config.r600.max_hw_contexts = 8; 2051 rdev->config.r600.max_gs_threads = 4; 2052 rdev->config.r600.sx_max_export_size = 128; 2053 rdev->config.r600.sx_max_export_pos_size = 16; 2054 rdev->config.r600.sx_max_export_smx_size = 128; 2055 rdev->config.r600.sq_num_cf_insts = 2; 2056 break; 2057 case CHIP_RV610: 2058 case CHIP_RV620: 2059 case CHIP_RS780: 2060 case CHIP_RS880: 2061 rdev->config.r600.max_pipes = 1; 2062 rdev->config.r600.max_tile_pipes = 1; 2063 rdev->config.r600.max_simds = 2; 2064 rdev->config.r600.max_backends = 1; 2065 rdev->config.r600.max_gprs = 128; 2066 rdev->config.r600.max_threads = 192; 2067 rdev->config.r600.max_stack_entries = 128; 2068 rdev->config.r600.max_hw_contexts = 4; 2069 rdev->config.r600.max_gs_threads = 4; 2070 rdev->config.r600.sx_max_export_size = 128; 2071 rdev->config.r600.sx_max_export_pos_size = 16; 2072 rdev->config.r600.sx_max_export_smx_size = 128; 2073 rdev->config.r600.sq_num_cf_insts = 1; 2074 break; 2075 case CHIP_RV670: 2076 rdev->config.r600.max_pipes = 4; 2077 rdev->config.r600.max_tile_pipes = 4; 2078 rdev->config.r600.max_simds = 4; 2079 rdev->config.r600.max_backends = 4; 2080 rdev->config.r600.max_gprs = 192; 2081 rdev->config.r600.max_threads = 192; 2082 rdev->config.r600.max_stack_entries = 256; 2083 rdev->config.r600.max_hw_contexts = 8; 2084 rdev->config.r600.max_gs_threads = 16; 2085 rdev->config.r600.sx_max_export_size = 128; 2086 rdev->config.r600.sx_max_export_pos_size = 16; 2087 rdev->config.r600.sx_max_export_smx_size = 128; 2088 rdev->config.r600.sq_num_cf_insts = 2; 2089 break; 2090 default: 2091 break; 2092 } 2093 2094 /* Initialize HDP */ 2095 for (i = 0, j = 0; i < 32; i++, j += 0x18) { 2096 WREG32((0x2c14 + j), 0x00000000); 2097 WREG32((0x2c18 + j), 0x00000000); 2098 WREG32((0x2c1c + j), 0x00000000); 2099 WREG32((0x2c20 + j), 0x00000000); 2100 WREG32((0x2c24 + j), 0x00000000); 2101 } 2102 2103 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); 2104 2105 /* Setup tiling */ 2106 tiling_config = 0; 2107 ramcfg = RREG32(RAMCFG); 2108 switch (rdev->config.r600.max_tile_pipes) { 2109 case 1: 2110 tiling_config |= PIPE_TILING(0); 2111 break; 2112 case 2: 2113 tiling_config |= PIPE_TILING(1); 2114 break; 2115 case 4: 2116 tiling_config |= PIPE_TILING(2); 2117 break; 2118 case 8: 2119 tiling_config |= PIPE_TILING(3); 2120 break; 2121 default: 2122 break; 2123 } 2124 rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes; 2125 rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); 2126 tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); 2127 tiling_config |= GROUP_SIZE((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT); 2128 2129 tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT; 2130 if (tmp > 3) { 2131 tiling_config |= ROW_TILING(3); 2132 tiling_config |= SAMPLE_SPLIT(3); 2133 } else { 2134 tiling_config |= ROW_TILING(tmp); 2135 tiling_config |= SAMPLE_SPLIT(tmp); 2136 } 2137 tiling_config |= BANK_SWAPS(1); 2138 2139 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0x00ffff00; 2140 tmp = rdev->config.r600.max_simds - 2141 r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R6XX_MAX_SIMDS_MASK); 2142 rdev->config.r600.active_simds = tmp; 2143 2144 disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R6XX_MAX_BACKENDS_MASK; 2145 tmp = 0; 2146 for (i = 0; i < rdev->config.r600.max_backends; i++) 2147 tmp |= (1 << i); 2148 /* if all the backends are disabled, fix it up here */ 2149 if ((disabled_rb_mask & tmp) == tmp) { 2150 for (i = 0; i < rdev->config.r600.max_backends; i++) 2151 disabled_rb_mask &= ~(1 << i); 2152 } 2153 tmp = (tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT; 2154 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.r600.max_backends, 2155 R6XX_MAX_BACKENDS, disabled_rb_mask); 2156 tiling_config |= tmp << 16; 2157 rdev->config.r600.backend_map = tmp; 2158 2159 rdev->config.r600.tile_config = tiling_config; 2160 WREG32(GB_TILING_CONFIG, tiling_config); 2161 WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff); 2162 WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff); 2163 WREG32(DMA_TILING_CONFIG, tiling_config & 0xffff); 2164 2165 tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8); 2166 WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK); 2167 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK); 2168 2169 /* Setup some CP states */ 2170 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b))); 2171 WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40))); 2172 2173 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT | 2174 SYNC_WALKER | SYNC_ALIGNER)); 2175 /* Setup various GPU states */ 2176 if (rdev->family == CHIP_RV670) 2177 WREG32(ARB_GDEC_RD_CNTL, 0x00000021); 2178 2179 tmp = RREG32(SX_DEBUG_1); 2180 tmp |= SMX_EVENT_RELEASE; 2181 if ((rdev->family > CHIP_R600)) 2182 tmp |= ENABLE_NEW_SMX_ADDRESS; 2183 WREG32(SX_DEBUG_1, tmp); 2184 2185 if (((rdev->family) == CHIP_R600) || 2186 ((rdev->family) == CHIP_RV630) || 2187 ((rdev->family) == CHIP_RV610) || 2188 ((rdev->family) == CHIP_RV620) || 2189 ((rdev->family) == CHIP_RS780) || 2190 ((rdev->family) == CHIP_RS880)) { 2191 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE); 2192 } else { 2193 WREG32(DB_DEBUG, 0); 2194 } 2195 WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) | 2196 DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4))); 2197 2198 WREG32(PA_SC_MULTI_CHIP_CNTL, 0); 2199 WREG32(VGT_NUM_INSTANCES, 0); 2200 2201 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0)); 2202 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0)); 2203 2204 tmp = RREG32(SQ_MS_FIFO_SIZES); 2205 if (((rdev->family) == CHIP_RV610) || 2206 ((rdev->family) == CHIP_RV620) || 2207 ((rdev->family) == CHIP_RS780) || 2208 ((rdev->family) == CHIP_RS880)) { 2209 tmp = (CACHE_FIFO_SIZE(0xa) | 2210 FETCH_FIFO_HIWATER(0xa) | 2211 DONE_FIFO_HIWATER(0xe0) | 2212 ALU_UPDATE_FIFO_HIWATER(0x8)); 2213 } else if (((rdev->family) == CHIP_R600) || 2214 ((rdev->family) == CHIP_RV630)) { 2215 tmp &= ~DONE_FIFO_HIWATER(0xff); 2216 tmp |= DONE_FIFO_HIWATER(0x4); 2217 } 2218 WREG32(SQ_MS_FIFO_SIZES, tmp); 2219 2220 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT 2221 * should be adjusted as needed by the 2D/3D drivers. This just sets default values 2222 */ 2223 sq_config = RREG32(SQ_CONFIG); 2224 sq_config &= ~(PS_PRIO(3) | 2225 VS_PRIO(3) | 2226 GS_PRIO(3) | 2227 ES_PRIO(3)); 2228 sq_config |= (DX9_CONSTS | 2229 VC_ENABLE | 2230 PS_PRIO(0) | 2231 VS_PRIO(1) | 2232 GS_PRIO(2) | 2233 ES_PRIO(3)); 2234 2235 if ((rdev->family) == CHIP_R600) { 2236 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) | 2237 NUM_VS_GPRS(124) | 2238 NUM_CLAUSE_TEMP_GPRS(4)); 2239 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) | 2240 NUM_ES_GPRS(0)); 2241 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) | 2242 NUM_VS_THREADS(48) | 2243 NUM_GS_THREADS(4) | 2244 NUM_ES_THREADS(4)); 2245 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) | 2246 NUM_VS_STACK_ENTRIES(128)); 2247 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) | 2248 NUM_ES_STACK_ENTRIES(0)); 2249 } else if (((rdev->family) == CHIP_RV610) || 2250 ((rdev->family) == CHIP_RV620) || 2251 ((rdev->family) == CHIP_RS780) || 2252 ((rdev->family) == CHIP_RS880)) { 2253 /* no vertex cache */ 2254 sq_config &= ~VC_ENABLE; 2255 2256 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | 2257 NUM_VS_GPRS(44) | 2258 NUM_CLAUSE_TEMP_GPRS(2)); 2259 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) | 2260 NUM_ES_GPRS(17)); 2261 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | 2262 NUM_VS_THREADS(78) | 2263 NUM_GS_THREADS(4) | 2264 NUM_ES_THREADS(31)); 2265 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) | 2266 NUM_VS_STACK_ENTRIES(40)); 2267 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) | 2268 NUM_ES_STACK_ENTRIES(16)); 2269 } else if (((rdev->family) == CHIP_RV630) || 2270 ((rdev->family) == CHIP_RV635)) { 2271 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | 2272 NUM_VS_GPRS(44) | 2273 NUM_CLAUSE_TEMP_GPRS(2)); 2274 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) | 2275 NUM_ES_GPRS(18)); 2276 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | 2277 NUM_VS_THREADS(78) | 2278 NUM_GS_THREADS(4) | 2279 NUM_ES_THREADS(31)); 2280 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) | 2281 NUM_VS_STACK_ENTRIES(40)); 2282 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) | 2283 NUM_ES_STACK_ENTRIES(16)); 2284 } else if ((rdev->family) == CHIP_RV670) { 2285 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | 2286 NUM_VS_GPRS(44) | 2287 NUM_CLAUSE_TEMP_GPRS(2)); 2288 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) | 2289 NUM_ES_GPRS(17)); 2290 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | 2291 NUM_VS_THREADS(78) | 2292 NUM_GS_THREADS(4) | 2293 NUM_ES_THREADS(31)); 2294 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) | 2295 NUM_VS_STACK_ENTRIES(64)); 2296 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) | 2297 NUM_ES_STACK_ENTRIES(64)); 2298 } 2299 2300 WREG32(SQ_CONFIG, sq_config); 2301 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1); 2302 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2); 2303 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); 2304 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1); 2305 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2); 2306 2307 if (((rdev->family) == CHIP_RV610) || 2308 ((rdev->family) == CHIP_RV620) || 2309 ((rdev->family) == CHIP_RS780) || 2310 ((rdev->family) == CHIP_RS880)) { 2311 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY)); 2312 } else { 2313 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC)); 2314 } 2315 2316 /* More default values. 2D/3D driver should adjust as needed */ 2317 WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) | 2318 S1_X(0x4) | S1_Y(0xc))); 2319 WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) | 2320 S1_X(0x2) | S1_Y(0x2) | 2321 S2_X(0xa) | S2_Y(0x6) | 2322 S3_X(0x6) | S3_Y(0xa))); 2323 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) | 2324 S1_X(0x4) | S1_Y(0xc) | 2325 S2_X(0x1) | S2_Y(0x6) | 2326 S3_X(0xa) | S3_Y(0xe))); 2327 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) | 2328 S5_X(0x0) | S5_Y(0x0) | 2329 S6_X(0xb) | S6_Y(0x4) | 2330 S7_X(0x7) | S7_Y(0x8))); 2331 2332 WREG32(VGT_STRMOUT_EN, 0); 2333 tmp = rdev->config.r600.max_pipes * 16; 2334 switch (rdev->family) { 2335 case CHIP_RV610: 2336 case CHIP_RV620: 2337 case CHIP_RS780: 2338 case CHIP_RS880: 2339 tmp += 32; 2340 break; 2341 case CHIP_RV670: 2342 tmp += 128; 2343 break; 2344 default: 2345 break; 2346 } 2347 if (tmp > 256) { 2348 tmp = 256; 2349 } 2350 WREG32(VGT_ES_PER_GS, 128); 2351 WREG32(VGT_GS_PER_ES, tmp); 2352 WREG32(VGT_GS_PER_VS, 2); 2353 WREG32(VGT_GS_VERTEX_REUSE, 16); 2354 2355 /* more default values. 2D/3D driver should adjust as needed */ 2356 WREG32(PA_SC_LINE_STIPPLE_STATE, 0); 2357 WREG32(VGT_STRMOUT_EN, 0); 2358 WREG32(SX_MISC, 0); 2359 WREG32(PA_SC_MODE_CNTL, 0); 2360 WREG32(PA_SC_AA_CONFIG, 0); 2361 WREG32(PA_SC_LINE_STIPPLE, 0); 2362 WREG32(SPI_INPUT_Z, 0); 2363 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2)); 2364 WREG32(CB_COLOR7_FRAG, 0); 2365 2366 /* Clear render buffer base addresses */ 2367 WREG32(CB_COLOR0_BASE, 0); 2368 WREG32(CB_COLOR1_BASE, 0); 2369 WREG32(CB_COLOR2_BASE, 0); 2370 WREG32(CB_COLOR3_BASE, 0); 2371 WREG32(CB_COLOR4_BASE, 0); 2372 WREG32(CB_COLOR5_BASE, 0); 2373 WREG32(CB_COLOR6_BASE, 0); 2374 WREG32(CB_COLOR7_BASE, 0); 2375 WREG32(CB_COLOR7_FRAG, 0); 2376 2377 switch (rdev->family) { 2378 case CHIP_RV610: 2379 case CHIP_RV620: 2380 case CHIP_RS780: 2381 case CHIP_RS880: 2382 tmp = TC_L2_SIZE(8); 2383 break; 2384 case CHIP_RV630: 2385 case CHIP_RV635: 2386 tmp = TC_L2_SIZE(4); 2387 break; 2388 case CHIP_R600: 2389 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT; 2390 break; 2391 default: 2392 tmp = TC_L2_SIZE(0); 2393 break; 2394 } 2395 WREG32(TC_CNTL, tmp); 2396 2397 tmp = RREG32(HDP_HOST_PATH_CNTL); 2398 WREG32(HDP_HOST_PATH_CNTL, tmp); 2399 2400 tmp = RREG32(ARB_POP); 2401 tmp |= ENABLE_TC128; 2402 WREG32(ARB_POP, tmp); 2403 2404 WREG32(PA_SC_MULTI_CHIP_CNTL, 0); 2405 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA | 2406 NUM_CLIP_SEQ(3))); 2407 WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095)); 2408 WREG32(VC_ENHANCE, 0); 2409 } 2410 2411 2412 /* 2413 * Indirect registers accessor 2414 */ 2415 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg) 2416 { 2417 unsigned long flags; 2418 u32 r; 2419 2420 spin_lock_irqsave(&rdev->pciep_idx_lock, flags); 2421 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); 2422 (void)RREG32(PCIE_PORT_INDEX); 2423 r = RREG32(PCIE_PORT_DATA); 2424 spin_unlock_irqrestore(&rdev->pciep_idx_lock, flags); 2425 return r; 2426 } 2427 2428 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2429 { 2430 unsigned long flags; 2431 2432 spin_lock_irqsave(&rdev->pciep_idx_lock, flags); 2433 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); 2434 (void)RREG32(PCIE_PORT_INDEX); 2435 WREG32(PCIE_PORT_DATA, (v)); 2436 (void)RREG32(PCIE_PORT_DATA); 2437 spin_unlock_irqrestore(&rdev->pciep_idx_lock, flags); 2438 } 2439 2440 /* 2441 * CP & Ring 2442 */ 2443 void r600_cp_stop(struct radeon_device *rdev) 2444 { 2445 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX) 2446 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 2447 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); 2448 WREG32(SCRATCH_UMSK, 0); 2449 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; 2450 } 2451 2452 int r600_init_microcode(struct radeon_device *rdev) 2453 { 2454 const char *chip_name; 2455 const char *rlc_chip_name; 2456 const char *smc_chip_name = "RV770"; 2457 size_t pfp_req_size, me_req_size, rlc_req_size, smc_req_size = 0; 2458 char fw_name[30]; 2459 int err; 2460 2461 DRM_DEBUG("\n"); 2462 2463 switch (rdev->family) { 2464 case CHIP_R600: 2465 chip_name = "R600"; 2466 rlc_chip_name = "R600"; 2467 break; 2468 case CHIP_RV610: 2469 chip_name = "RV610"; 2470 rlc_chip_name = "R600"; 2471 break; 2472 case CHIP_RV630: 2473 chip_name = "RV630"; 2474 rlc_chip_name = "R600"; 2475 break; 2476 case CHIP_RV620: 2477 chip_name = "RV620"; 2478 rlc_chip_name = "R600"; 2479 break; 2480 case CHIP_RV635: 2481 chip_name = "RV635"; 2482 rlc_chip_name = "R600"; 2483 break; 2484 case CHIP_RV670: 2485 chip_name = "RV670"; 2486 rlc_chip_name = "R600"; 2487 break; 2488 case CHIP_RS780: 2489 case CHIP_RS880: 2490 chip_name = "RS780"; 2491 rlc_chip_name = "R600"; 2492 break; 2493 case CHIP_RV770: 2494 chip_name = "RV770"; 2495 rlc_chip_name = "R700"; 2496 smc_chip_name = "RV770"; 2497 #ifdef __NetBSD__ /* XXX ALIGN means something else. */ 2498 smc_req_size = round_up(RV770_SMC_UCODE_SIZE, 4); 2499 #else 2500 smc_req_size = ALIGN(RV770_SMC_UCODE_SIZE, 4); 2501 #endif 2502 break; 2503 case CHIP_RV730: 2504 chip_name = "RV730"; 2505 rlc_chip_name = "R700"; 2506 smc_chip_name = "RV730"; 2507 #ifdef __NetBSD__ /* XXX ALIGN means something else. */ 2508 smc_req_size = round_up(RV730_SMC_UCODE_SIZE, 4); 2509 #else 2510 smc_req_size = ALIGN(RV730_SMC_UCODE_SIZE, 4); 2511 #endif 2512 break; 2513 case CHIP_RV710: 2514 chip_name = "RV710"; 2515 rlc_chip_name = "R700"; 2516 smc_chip_name = "RV710"; 2517 #ifdef __NetBSD__ /* XXX ALIGN means something else. */ 2518 smc_req_size = round_up(RV710_SMC_UCODE_SIZE, 4); 2519 #else 2520 smc_req_size = ALIGN(RV710_SMC_UCODE_SIZE, 4); 2521 #endif 2522 break; 2523 case CHIP_RV740: 2524 chip_name = "RV730"; 2525 rlc_chip_name = "R700"; 2526 smc_chip_name = "RV740"; 2527 #ifdef __NetBSD__ /* XXX ALIGN means something else. */ 2528 smc_req_size = round_up(RV740_SMC_UCODE_SIZE, 4); 2529 #else 2530 smc_req_size = ALIGN(RV740_SMC_UCODE_SIZE, 4); 2531 #endif 2532 break; 2533 case CHIP_CEDAR: 2534 chip_name = "CEDAR"; 2535 rlc_chip_name = "CEDAR"; 2536 smc_chip_name = "CEDAR"; 2537 #ifdef __NetBSD__ /* XXX ALIGN means something else. */ 2538 smc_req_size = round_up(CEDAR_SMC_UCODE_SIZE, 4); 2539 #else 2540 smc_req_size = ALIGN(CEDAR_SMC_UCODE_SIZE, 4); 2541 #endif 2542 break; 2543 case CHIP_REDWOOD: 2544 chip_name = "REDWOOD"; 2545 rlc_chip_name = "REDWOOD"; 2546 smc_chip_name = "REDWOOD"; 2547 #ifdef __NetBSD__ /* XXX ALIGN means something else. */ 2548 smc_req_size = round_up(REDWOOD_SMC_UCODE_SIZE, 4); 2549 #else 2550 smc_req_size = ALIGN(REDWOOD_SMC_UCODE_SIZE, 4); 2551 #endif 2552 break; 2553 case CHIP_JUNIPER: 2554 chip_name = "JUNIPER"; 2555 rlc_chip_name = "JUNIPER"; 2556 smc_chip_name = "JUNIPER"; 2557 #ifdef __NetBSD__ /* XXX ALIGN means something else. */ 2558 smc_req_size = round_up(JUNIPER_SMC_UCODE_SIZE, 4); 2559 #else 2560 smc_req_size = ALIGN(JUNIPER_SMC_UCODE_SIZE, 4); 2561 #endif 2562 break; 2563 case CHIP_CYPRESS: 2564 case CHIP_HEMLOCK: 2565 chip_name = "CYPRESS"; 2566 rlc_chip_name = "CYPRESS"; 2567 smc_chip_name = "CYPRESS"; 2568 #ifdef __NetBSD__ /* XXX ALIGN means something else. */ 2569 smc_req_size = round_up(CYPRESS_SMC_UCODE_SIZE, 4); 2570 #else 2571 smc_req_size = ALIGN(CYPRESS_SMC_UCODE_SIZE, 4); 2572 #endif 2573 break; 2574 case CHIP_PALM: 2575 chip_name = "PALM"; 2576 rlc_chip_name = "SUMO"; 2577 break; 2578 case CHIP_SUMO: 2579 chip_name = "SUMO"; 2580 rlc_chip_name = "SUMO"; 2581 break; 2582 case CHIP_SUMO2: 2583 chip_name = "SUMO2"; 2584 rlc_chip_name = "SUMO"; 2585 break; 2586 default: BUG(); 2587 } 2588 2589 if (rdev->family >= CHIP_CEDAR) { 2590 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4; 2591 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4; 2592 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4; 2593 } else if (rdev->family >= CHIP_RV770) { 2594 pfp_req_size = R700_PFP_UCODE_SIZE * 4; 2595 me_req_size = R700_PM4_UCODE_SIZE * 4; 2596 rlc_req_size = R700_RLC_UCODE_SIZE * 4; 2597 } else { 2598 pfp_req_size = R600_PFP_UCODE_SIZE * 4; 2599 me_req_size = R600_PM4_UCODE_SIZE * 12; 2600 rlc_req_size = R600_RLC_UCODE_SIZE * 4; 2601 } 2602 2603 DRM_INFO("Loading %s Microcode\n", chip_name); 2604 2605 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name); 2606 err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev); 2607 if (err) 2608 goto out; 2609 if (rdev->pfp_fw->size != pfp_req_size) { 2610 printk(KERN_ERR 2611 "r600_cp: Bogus length %zu in firmware \"%s\"\n", 2612 rdev->pfp_fw->size, fw_name); 2613 err = -EINVAL; 2614 goto out; 2615 } 2616 2617 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name); 2618 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev); 2619 if (err) 2620 goto out; 2621 if (rdev->me_fw->size != me_req_size) { 2622 printk(KERN_ERR 2623 "r600_cp: Bogus length %zu in firmware \"%s\"\n", 2624 rdev->me_fw->size, fw_name); 2625 err = -EINVAL; 2626 } 2627 2628 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name); 2629 err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev); 2630 if (err) 2631 goto out; 2632 if (rdev->rlc_fw->size != rlc_req_size) { 2633 printk(KERN_ERR 2634 "r600_rlc: Bogus length %zu in firmware \"%s\"\n", 2635 rdev->rlc_fw->size, fw_name); 2636 err = -EINVAL; 2637 } 2638 2639 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_HEMLOCK)) { 2640 snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", smc_chip_name); 2641 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev); 2642 if (err) { 2643 printk(KERN_ERR 2644 "smc: error loading firmware \"%s\"\n", 2645 fw_name); 2646 release_firmware(rdev->smc_fw); 2647 rdev->smc_fw = NULL; 2648 err = 0; 2649 } else if (rdev->smc_fw->size != smc_req_size) { 2650 printk(KERN_ERR 2651 "smc: Bogus length %zu in firmware \"%s\"\n", 2652 rdev->smc_fw->size, fw_name); 2653 err = -EINVAL; 2654 } 2655 } 2656 2657 out: 2658 if (err) { 2659 if (err != -EINVAL) 2660 printk(KERN_ERR 2661 "r600_cp: Failed to load firmware \"%s\"\n", 2662 fw_name); 2663 release_firmware(rdev->pfp_fw); 2664 rdev->pfp_fw = NULL; 2665 release_firmware(rdev->me_fw); 2666 rdev->me_fw = NULL; 2667 release_firmware(rdev->rlc_fw); 2668 rdev->rlc_fw = NULL; 2669 release_firmware(rdev->smc_fw); 2670 rdev->smc_fw = NULL; 2671 } 2672 return err; 2673 } 2674 2675 u32 r600_gfx_get_rptr(struct radeon_device *rdev, 2676 struct radeon_ring *ring) 2677 { 2678 u32 rptr; 2679 2680 if (rdev->wb.enabled) 2681 rptr = rdev->wb.wb[ring->rptr_offs/4]; 2682 else 2683 rptr = RREG32(R600_CP_RB_RPTR); 2684 2685 return rptr; 2686 } 2687 2688 u32 r600_gfx_get_wptr(struct radeon_device *rdev, 2689 struct radeon_ring *ring) 2690 { 2691 u32 wptr; 2692 2693 wptr = RREG32(R600_CP_RB_WPTR); 2694 2695 return wptr; 2696 } 2697 2698 void r600_gfx_set_wptr(struct radeon_device *rdev, 2699 struct radeon_ring *ring) 2700 { 2701 WREG32(R600_CP_RB_WPTR, ring->wptr); 2702 (void)RREG32(R600_CP_RB_WPTR); 2703 } 2704 2705 static int r600_cp_load_microcode(struct radeon_device *rdev) 2706 { 2707 const __be32 *fw_data; 2708 int i; 2709 2710 if (!rdev->me_fw || !rdev->pfp_fw) 2711 return -EINVAL; 2712 2713 r600_cp_stop(rdev); 2714 2715 WREG32(CP_RB_CNTL, 2716 #ifdef __BIG_ENDIAN 2717 BUF_SWAP_32BIT | 2718 #endif 2719 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); 2720 2721 /* Reset cp */ 2722 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); 2723 RREG32(GRBM_SOFT_RESET); 2724 mdelay(15); 2725 WREG32(GRBM_SOFT_RESET, 0); 2726 2727 WREG32(CP_ME_RAM_WADDR, 0); 2728 2729 fw_data = (const __be32 *)rdev->me_fw->data; 2730 WREG32(CP_ME_RAM_WADDR, 0); 2731 for (i = 0; i < R600_PM4_UCODE_SIZE * 3; i++) 2732 WREG32(CP_ME_RAM_DATA, 2733 be32_to_cpup(fw_data++)); 2734 2735 fw_data = (const __be32 *)rdev->pfp_fw->data; 2736 WREG32(CP_PFP_UCODE_ADDR, 0); 2737 for (i = 0; i < R600_PFP_UCODE_SIZE; i++) 2738 WREG32(CP_PFP_UCODE_DATA, 2739 be32_to_cpup(fw_data++)); 2740 2741 WREG32(CP_PFP_UCODE_ADDR, 0); 2742 WREG32(CP_ME_RAM_WADDR, 0); 2743 WREG32(CP_ME_RAM_RADDR, 0); 2744 return 0; 2745 } 2746 2747 int r600_cp_start(struct radeon_device *rdev) 2748 { 2749 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2750 int r; 2751 uint32_t cp_me; 2752 2753 r = radeon_ring_lock(rdev, ring, 7); 2754 if (r) { 2755 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); 2756 return r; 2757 } 2758 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); 2759 radeon_ring_write(ring, 0x1); 2760 if (rdev->family >= CHIP_RV770) { 2761 radeon_ring_write(ring, 0x0); 2762 radeon_ring_write(ring, rdev->config.rv770.max_hw_contexts - 1); 2763 } else { 2764 radeon_ring_write(ring, 0x3); 2765 radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1); 2766 } 2767 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); 2768 radeon_ring_write(ring, 0); 2769 radeon_ring_write(ring, 0); 2770 radeon_ring_unlock_commit(rdev, ring, false); 2771 2772 cp_me = 0xff; 2773 WREG32(R_0086D8_CP_ME_CNTL, cp_me); 2774 return 0; 2775 } 2776 2777 int r600_cp_resume(struct radeon_device *rdev) 2778 { 2779 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2780 u32 tmp; 2781 u32 rb_bufsz; 2782 int r; 2783 2784 /* Reset cp */ 2785 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); 2786 RREG32(GRBM_SOFT_RESET); 2787 mdelay(15); 2788 WREG32(GRBM_SOFT_RESET, 0); 2789 2790 /* Set ring buffer size */ 2791 rb_bufsz = order_base_2(ring->ring_size / 8); 2792 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 2793 #ifdef __BIG_ENDIAN 2794 tmp |= BUF_SWAP_32BIT; 2795 #endif 2796 WREG32(CP_RB_CNTL, tmp); 2797 WREG32(CP_SEM_WAIT_TIMER, 0x0); 2798 2799 /* Set the write pointer delay */ 2800 WREG32(CP_RB_WPTR_DELAY, 0); 2801 2802 /* Initialize the ring buffer's read and write pointers */ 2803 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA); 2804 WREG32(CP_RB_RPTR_WR, 0); 2805 ring->wptr = 0; 2806 WREG32(CP_RB_WPTR, ring->wptr); 2807 2808 /* set the wb address whether it's enabled or not */ 2809 WREG32(CP_RB_RPTR_ADDR, 2810 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC)); 2811 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); 2812 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); 2813 2814 if (rdev->wb.enabled) 2815 WREG32(SCRATCH_UMSK, 0xff); 2816 else { 2817 tmp |= RB_NO_UPDATE; 2818 WREG32(SCRATCH_UMSK, 0); 2819 } 2820 2821 mdelay(1); 2822 WREG32(CP_RB_CNTL, tmp); 2823 2824 WREG32(CP_RB_BASE, ring->gpu_addr >> 8); 2825 WREG32(CP_DEBUG, (1 << 27) | (1 << 28)); 2826 2827 r600_cp_start(rdev); 2828 ring->ready = true; 2829 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring); 2830 if (r) { 2831 ring->ready = false; 2832 return r; 2833 } 2834 2835 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX) 2836 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); 2837 2838 return 0; 2839 } 2840 2841 void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size) 2842 { 2843 u32 rb_bufsz; 2844 int r; 2845 2846 /* Align ring size */ 2847 rb_bufsz = order_base_2(ring_size / 8); 2848 ring_size = (1 << (rb_bufsz + 1)) * 4; 2849 ring->ring_size = ring_size; 2850 ring->align_mask = 16 - 1; 2851 2852 if (radeon_ring_supports_scratch_reg(rdev, ring)) { 2853 r = radeon_scratch_get(rdev, &ring->rptr_save_reg); 2854 if (r) { 2855 DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r); 2856 ring->rptr_save_reg = 0; 2857 } 2858 } 2859 } 2860 2861 void r600_cp_fini(struct radeon_device *rdev) 2862 { 2863 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2864 r600_cp_stop(rdev); 2865 radeon_ring_fini(rdev, ring); 2866 radeon_scratch_free(rdev, ring->rptr_save_reg); 2867 } 2868 2869 /* 2870 * GPU scratch registers helpers function. 2871 */ 2872 void r600_scratch_init(struct radeon_device *rdev) 2873 { 2874 int i; 2875 2876 rdev->scratch.num_reg = 7; 2877 rdev->scratch.reg_base = SCRATCH_REG0; 2878 for (i = 0; i < rdev->scratch.num_reg; i++) { 2879 rdev->scratch.free[i] = true; 2880 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4); 2881 } 2882 } 2883 2884 int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *ring) 2885 { 2886 uint32_t scratch; 2887 uint32_t tmp = 0; 2888 unsigned i; 2889 int r; 2890 2891 r = radeon_scratch_get(rdev, &scratch); 2892 if (r) { 2893 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r); 2894 return r; 2895 } 2896 WREG32(scratch, 0xCAFEDEAD); 2897 r = radeon_ring_lock(rdev, ring, 3); 2898 if (r) { 2899 DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", ring->idx, r); 2900 radeon_scratch_free(rdev, scratch); 2901 return r; 2902 } 2903 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2904 radeon_ring_write(ring, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); 2905 radeon_ring_write(ring, 0xDEADBEEF); 2906 radeon_ring_unlock_commit(rdev, ring, false); 2907 for (i = 0; i < rdev->usec_timeout; i++) { 2908 tmp = RREG32(scratch); 2909 if (tmp == 0xDEADBEEF) 2910 break; 2911 DRM_UDELAY(1); 2912 } 2913 if (i < rdev->usec_timeout) { 2914 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); 2915 } else { 2916 DRM_ERROR("radeon: ring %d test failed (scratch(0x%04X)=0x%08X)\n", 2917 ring->idx, scratch, tmp); 2918 r = -EINVAL; 2919 } 2920 radeon_scratch_free(rdev, scratch); 2921 return r; 2922 } 2923 2924 /* 2925 * CP fences/semaphores 2926 */ 2927 2928 void r600_fence_ring_emit(struct radeon_device *rdev, 2929 struct radeon_fence *fence) 2930 { 2931 struct radeon_ring *ring = &rdev->ring[fence->ring]; 2932 u32 cp_coher_cntl = PACKET3_TC_ACTION_ENA | PACKET3_VC_ACTION_ENA | 2933 PACKET3_SH_ACTION_ENA; 2934 2935 if (rdev->family >= CHIP_RV770) 2936 cp_coher_cntl |= PACKET3_FULL_CACHE_ENA; 2937 2938 if (rdev->wb.use_event) { 2939 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; 2940 /* flush read cache over gart */ 2941 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 2942 radeon_ring_write(ring, cp_coher_cntl); 2943 radeon_ring_write(ring, 0xFFFFFFFF); 2944 radeon_ring_write(ring, 0); 2945 radeon_ring_write(ring, 10); /* poll interval */ 2946 /* EVENT_WRITE_EOP - flush caches, send int */ 2947 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); 2948 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5)); 2949 radeon_ring_write(ring, lower_32_bits(addr)); 2950 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); 2951 radeon_ring_write(ring, fence->seq); 2952 radeon_ring_write(ring, 0); 2953 } else { 2954 /* flush read cache over gart */ 2955 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 2956 radeon_ring_write(ring, cp_coher_cntl); 2957 radeon_ring_write(ring, 0xFFFFFFFF); 2958 radeon_ring_write(ring, 0); 2959 radeon_ring_write(ring, 10); /* poll interval */ 2960 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); 2961 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0)); 2962 /* wait for 3D idle clean */ 2963 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2964 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); 2965 radeon_ring_write(ring, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit); 2966 /* Emit fence sequence & fire IRQ */ 2967 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2968 radeon_ring_write(ring, ((rdev->fence_drv[fence->ring].scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); 2969 radeon_ring_write(ring, fence->seq); 2970 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */ 2971 radeon_ring_write(ring, PACKET0(CP_INT_STATUS, 0)); 2972 radeon_ring_write(ring, RB_INT_STAT); 2973 } 2974 } 2975 2976 /** 2977 * r600_semaphore_ring_emit - emit a semaphore on the CP ring 2978 * 2979 * @rdev: radeon_device pointer 2980 * @ring: radeon ring buffer object 2981 * @semaphore: radeon semaphore object 2982 * @emit_wait: Is this a sempahore wait? 2983 * 2984 * Emits a semaphore signal/wait packet to the CP ring and prevents the PFP 2985 * from running ahead of semaphore waits. 2986 */ 2987 bool r600_semaphore_ring_emit(struct radeon_device *rdev, 2988 struct radeon_ring *ring, 2989 struct radeon_semaphore *semaphore, 2990 bool emit_wait) 2991 { 2992 uint64_t addr = semaphore->gpu_addr; 2993 unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL; 2994 2995 if (rdev->family < CHIP_CAYMAN) 2996 sel |= PACKET3_SEM_WAIT_ON_SIGNAL; 2997 2998 radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1)); 2999 radeon_ring_write(ring, lower_32_bits(addr)); 3000 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel); 3001 3002 /* PFP_SYNC_ME packet only exists on 7xx+, only enable it on eg+ */ 3003 if (emit_wait && (rdev->family >= CHIP_CEDAR)) { 3004 /* Prevent the PFP from running ahead of the semaphore wait */ 3005 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 3006 radeon_ring_write(ring, 0x0); 3007 } 3008 3009 return true; 3010 } 3011 3012 /** 3013 * r600_copy_cpdma - copy pages using the CP DMA engine 3014 * 3015 * @rdev: radeon_device pointer 3016 * @src_offset: src GPU address 3017 * @dst_offset: dst GPU address 3018 * @num_gpu_pages: number of GPU pages to xfer 3019 * @fence: radeon fence object 3020 * 3021 * Copy GPU paging using the CP DMA engine (r6xx+). 3022 * Used by the radeon ttm implementation to move pages if 3023 * registered as the asic copy callback. 3024 */ 3025 struct radeon_fence *r600_copy_cpdma(struct radeon_device *rdev, 3026 uint64_t src_offset, uint64_t dst_offset, 3027 unsigned num_gpu_pages, 3028 struct reservation_object *resv) 3029 { 3030 struct radeon_fence *fence; 3031 struct radeon_sync sync; 3032 int ring_index = rdev->asic->copy.blit_ring_index; 3033 struct radeon_ring *ring = &rdev->ring[ring_index]; 3034 u32 size_in_bytes, cur_size_in_bytes, tmp; 3035 int i, num_loops; 3036 int r = 0; 3037 3038 radeon_sync_create(&sync); 3039 3040 size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT); 3041 num_loops = DIV_ROUND_UP(size_in_bytes, 0x1fffff); 3042 r = radeon_ring_lock(rdev, ring, num_loops * 6 + 24); 3043 if (r) { 3044 DRM_ERROR("radeon: moving bo (%d).\n", r); 3045 radeon_sync_free(rdev, &sync, NULL); 3046 return ERR_PTR(r); 3047 } 3048 3049 radeon_sync_resv(rdev, &sync, resv, false); 3050 radeon_sync_rings(rdev, &sync, ring->idx); 3051 3052 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 3053 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); 3054 radeon_ring_write(ring, WAIT_3D_IDLE_bit); 3055 for (i = 0; i < num_loops; i++) { 3056 cur_size_in_bytes = size_in_bytes; 3057 if (cur_size_in_bytes > 0x1fffff) 3058 cur_size_in_bytes = 0x1fffff; 3059 size_in_bytes -= cur_size_in_bytes; 3060 tmp = upper_32_bits(src_offset) & 0xff; 3061 if (size_in_bytes == 0) 3062 tmp |= PACKET3_CP_DMA_CP_SYNC; 3063 radeon_ring_write(ring, PACKET3(PACKET3_CP_DMA, 4)); 3064 radeon_ring_write(ring, lower_32_bits(src_offset)); 3065 radeon_ring_write(ring, tmp); 3066 radeon_ring_write(ring, lower_32_bits(dst_offset)); 3067 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff); 3068 radeon_ring_write(ring, cur_size_in_bytes); 3069 src_offset += cur_size_in_bytes; 3070 dst_offset += cur_size_in_bytes; 3071 } 3072 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 3073 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); 3074 radeon_ring_write(ring, WAIT_CP_DMA_IDLE_bit); 3075 3076 r = radeon_fence_emit(rdev, &fence, ring->idx); 3077 if (r) { 3078 radeon_ring_unlock_undo(rdev, ring); 3079 radeon_sync_free(rdev, &sync, NULL); 3080 return ERR_PTR(r); 3081 } 3082 3083 radeon_ring_unlock_commit(rdev, ring, false); 3084 radeon_sync_free(rdev, &sync, fence); 3085 3086 return fence; 3087 } 3088 3089 int r600_set_surface_reg(struct radeon_device *rdev, int reg, 3090 uint32_t tiling_flags, uint32_t pitch, 3091 uint32_t offset, uint32_t obj_size) 3092 { 3093 /* FIXME: implement */ 3094 return 0; 3095 } 3096 3097 void r600_clear_surface_reg(struct radeon_device *rdev, int reg) 3098 { 3099 /* FIXME: implement */ 3100 } 3101 3102 static int r600_startup(struct radeon_device *rdev) 3103 { 3104 struct radeon_ring *ring; 3105 int r; 3106 3107 /* enable pcie gen2 link */ 3108 r600_pcie_gen2_enable(rdev); 3109 3110 /* scratch needs to be initialized before MC */ 3111 r = r600_vram_scratch_init(rdev); 3112 if (r) 3113 return r; 3114 3115 r600_mc_program(rdev); 3116 3117 if (rdev->flags & RADEON_IS_AGP) { 3118 r600_agp_enable(rdev); 3119 } else { 3120 r = r600_pcie_gart_enable(rdev); 3121 if (r) 3122 return r; 3123 } 3124 r600_gpu_init(rdev); 3125 3126 /* allocate wb buffer */ 3127 r = radeon_wb_init(rdev); 3128 if (r) 3129 return r; 3130 3131 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 3132 if (r) { 3133 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 3134 return r; 3135 } 3136 3137 if (rdev->has_uvd) { 3138 r = uvd_v1_0_resume(rdev); 3139 if (!r) { 3140 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_UVD_INDEX); 3141 if (r) { 3142 dev_err(rdev->dev, "failed initializing UVD fences (%d).\n", r); 3143 } 3144 } 3145 if (r) 3146 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0; 3147 } 3148 3149 /* Enable IRQ */ 3150 if (!rdev->irq.installed) { 3151 r = radeon_irq_kms_init(rdev); 3152 if (r) 3153 return r; 3154 } 3155 3156 r = r600_irq_init(rdev); 3157 if (r) { 3158 DRM_ERROR("radeon: IH init failed (%d).\n", r); 3159 radeon_irq_kms_fini(rdev); 3160 return r; 3161 } 3162 r600_irq_set(rdev); 3163 3164 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 3165 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, 3166 RADEON_CP_PACKET2); 3167 if (r) 3168 return r; 3169 3170 r = r600_cp_load_microcode(rdev); 3171 if (r) 3172 return r; 3173 r = r600_cp_resume(rdev); 3174 if (r) 3175 return r; 3176 3177 if (rdev->has_uvd) { 3178 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; 3179 if (ring->ring_size) { 3180 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, 3181 RADEON_CP_PACKET2); 3182 if (!r) 3183 r = uvd_v1_0_init(rdev); 3184 if (r) 3185 DRM_ERROR("radeon: failed initializing UVD (%d).\n", r); 3186 } 3187 } 3188 3189 r = radeon_ib_pool_init(rdev); 3190 if (r) { 3191 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 3192 return r; 3193 } 3194 3195 r = radeon_audio_init(rdev); 3196 if (r) { 3197 DRM_ERROR("radeon: audio init failed\n"); 3198 return r; 3199 } 3200 3201 return 0; 3202 } 3203 3204 void r600_vga_set_state(struct radeon_device *rdev, bool state) 3205 { 3206 uint32_t temp; 3207 3208 temp = RREG32(CONFIG_CNTL); 3209 if (state == false) { 3210 temp &= ~(1<<0); 3211 temp |= (1<<1); 3212 } else { 3213 temp &= ~(1<<1); 3214 } 3215 WREG32(CONFIG_CNTL, temp); 3216 } 3217 3218 int r600_resume(struct radeon_device *rdev) 3219 { 3220 int r; 3221 3222 /* Do not reset GPU before posting, on r600 hw unlike on r500 hw, 3223 * posting will perform necessary task to bring back GPU into good 3224 * shape. 3225 */ 3226 /* post card */ 3227 atom_asic_init(rdev->mode_info.atom_context); 3228 3229 if (rdev->pm.pm_method == PM_METHOD_DPM) 3230 radeon_pm_resume(rdev); 3231 3232 rdev->accel_working = true; 3233 r = r600_startup(rdev); 3234 if (r) { 3235 DRM_ERROR("r600 startup failed on resume\n"); 3236 rdev->accel_working = false; 3237 return r; 3238 } 3239 3240 return r; 3241 } 3242 3243 int r600_suspend(struct radeon_device *rdev) 3244 { 3245 radeon_pm_suspend(rdev); 3246 radeon_audio_fini(rdev); 3247 r600_cp_stop(rdev); 3248 if (rdev->has_uvd) { 3249 uvd_v1_0_fini(rdev); 3250 radeon_uvd_suspend(rdev); 3251 } 3252 r600_irq_suspend(rdev); 3253 radeon_wb_disable(rdev); 3254 r600_pcie_gart_disable(rdev); 3255 3256 return 0; 3257 } 3258 3259 /* Plan is to move initialization in that function and use 3260 * helper function so that radeon_device_init pretty much 3261 * do nothing more than calling asic specific function. This 3262 * should also allow to remove a bunch of callback function 3263 * like vram_info. 3264 */ 3265 int r600_init(struct radeon_device *rdev) 3266 { 3267 int r; 3268 3269 if (r600_debugfs_mc_info_init(rdev)) { 3270 DRM_ERROR("Failed to register debugfs file for mc !\n"); 3271 } 3272 /* Read BIOS */ 3273 if (!radeon_get_bios(rdev)) { 3274 if (ASIC_IS_AVIVO(rdev)) 3275 return -EINVAL; 3276 } 3277 /* Must be an ATOMBIOS */ 3278 if (!rdev->is_atom_bios) { 3279 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n"); 3280 return -EINVAL; 3281 } 3282 r = radeon_atombios_init(rdev); 3283 if (r) 3284 return r; 3285 /* Post card if necessary */ 3286 if (!radeon_card_posted(rdev)) { 3287 if (!rdev->bios) { 3288 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); 3289 return -EINVAL; 3290 } 3291 DRM_INFO("GPU not posted. posting now...\n"); 3292 atom_asic_init(rdev->mode_info.atom_context); 3293 } 3294 /* Initialize scratch registers */ 3295 r600_scratch_init(rdev); 3296 /* Initialize surface registers */ 3297 radeon_surface_init(rdev); 3298 /* Initialize clocks */ 3299 radeon_get_clock_info(rdev->ddev); 3300 /* Fence driver */ 3301 r = radeon_fence_driver_init(rdev); 3302 if (r) 3303 return r; 3304 if (rdev->flags & RADEON_IS_AGP) { 3305 r = radeon_agp_init(rdev); 3306 if (r) 3307 radeon_agp_disable(rdev); 3308 } 3309 r = r600_mc_init(rdev); 3310 if (r) 3311 return r; 3312 /* Memory manager */ 3313 r = radeon_bo_init(rdev); 3314 if (r) 3315 return r; 3316 3317 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { 3318 r = r600_init_microcode(rdev); 3319 if (r) { 3320 DRM_ERROR("Failed to load firmware!\n"); 3321 return r; 3322 } 3323 } 3324 3325 /* Initialize power management */ 3326 radeon_pm_init(rdev); 3327 3328 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL; 3329 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024); 3330 3331 if (rdev->has_uvd) { 3332 r = radeon_uvd_init(rdev); 3333 if (!r) { 3334 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL; 3335 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX], 4096); 3336 } 3337 } 3338 3339 rdev->ih.ring_obj = NULL; 3340 r600_ih_ring_init(rdev, 64 * 1024); 3341 3342 r = r600_pcie_gart_init(rdev); 3343 if (r) 3344 return r; 3345 3346 rdev->accel_working = true; 3347 r = r600_startup(rdev); 3348 if (r) { 3349 dev_err(rdev->dev, "disabling GPU acceleration\n"); 3350 r600_cp_fini(rdev); 3351 r600_irq_fini(rdev); 3352 radeon_wb_fini(rdev); 3353 radeon_ib_pool_fini(rdev); 3354 radeon_irq_kms_fini(rdev); 3355 r600_pcie_gart_fini(rdev); 3356 rdev->accel_working = false; 3357 } 3358 3359 return 0; 3360 } 3361 3362 void r600_fini(struct radeon_device *rdev) 3363 { 3364 radeon_pm_fini(rdev); 3365 radeon_audio_fini(rdev); 3366 r600_cp_fini(rdev); 3367 r600_irq_fini(rdev); 3368 if (rdev->has_uvd) { 3369 uvd_v1_0_fini(rdev); 3370 radeon_uvd_fini(rdev); 3371 } 3372 radeon_wb_fini(rdev); 3373 radeon_ib_pool_fini(rdev); 3374 radeon_irq_kms_fini(rdev); 3375 r600_pcie_gart_fini(rdev); 3376 r600_vram_scratch_fini(rdev); 3377 radeon_agp_fini(rdev); 3378 radeon_gem_fini(rdev); 3379 radeon_fence_driver_fini(rdev); 3380 radeon_bo_fini(rdev); 3381 radeon_atombios_fini(rdev); 3382 kfree(rdev->bios); 3383 rdev->bios = NULL; 3384 } 3385 3386 3387 /* 3388 * CS stuff 3389 */ 3390 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) 3391 { 3392 struct radeon_ring *ring = &rdev->ring[ib->ring]; 3393 u32 next_rptr; 3394 3395 if (ring->rptr_save_reg) { 3396 next_rptr = ring->wptr + 3 + 4; 3397 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 3398 radeon_ring_write(ring, ((ring->rptr_save_reg - 3399 PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); 3400 radeon_ring_write(ring, next_rptr); 3401 } else if (rdev->wb.enabled) { 3402 next_rptr = ring->wptr + 5 + 4; 3403 radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3)); 3404 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); 3405 radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18)); 3406 radeon_ring_write(ring, next_rptr); 3407 radeon_ring_write(ring, 0); 3408 } 3409 3410 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 3411 radeon_ring_write(ring, 3412 #ifdef __BIG_ENDIAN 3413 (2 << 0) | 3414 #endif 3415 (ib->gpu_addr & 0xFFFFFFFC)); 3416 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF); 3417 radeon_ring_write(ring, ib->length_dw); 3418 } 3419 3420 int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) 3421 { 3422 struct radeon_ib ib; 3423 uint32_t scratch; 3424 uint32_t tmp = 0; 3425 unsigned i; 3426 int r; 3427 3428 r = radeon_scratch_get(rdev, &scratch); 3429 if (r) { 3430 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r); 3431 return r; 3432 } 3433 WREG32(scratch, 0xCAFEDEAD); 3434 r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256); 3435 if (r) { 3436 DRM_ERROR("radeon: failed to get ib (%d).\n", r); 3437 goto free_scratch; 3438 } 3439 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1); 3440 ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); 3441 ib.ptr[2] = 0xDEADBEEF; 3442 ib.length_dw = 3; 3443 r = radeon_ib_schedule(rdev, &ib, NULL, false); 3444 if (r) { 3445 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); 3446 goto free_ib; 3447 } 3448 r = radeon_fence_wait(ib.fence, false); 3449 if (r) { 3450 DRM_ERROR("radeon: fence wait failed (%d).\n", r); 3451 goto free_ib; 3452 } 3453 for (i = 0; i < rdev->usec_timeout; i++) { 3454 tmp = RREG32(scratch); 3455 if (tmp == 0xDEADBEEF) 3456 break; 3457 DRM_UDELAY(1); 3458 } 3459 if (i < rdev->usec_timeout) { 3460 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i); 3461 } else { 3462 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n", 3463 scratch, tmp); 3464 r = -EINVAL; 3465 } 3466 free_ib: 3467 radeon_ib_free(rdev, &ib); 3468 free_scratch: 3469 radeon_scratch_free(rdev, scratch); 3470 return r; 3471 } 3472 3473 /* 3474 * Interrupts 3475 * 3476 * Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty 3477 * the same as the CP ring buffer, but in reverse. Rather than the CPU 3478 * writing to the ring and the GPU consuming, the GPU writes to the ring 3479 * and host consumes. As the host irq handler processes interrupts, it 3480 * increments the rptr. When the rptr catches up with the wptr, all the 3481 * current interrupts have been processed. 3482 */ 3483 3484 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size) 3485 { 3486 u32 rb_bufsz; 3487 3488 /* Align ring size */ 3489 rb_bufsz = order_base_2(ring_size / 4); 3490 ring_size = (1 << rb_bufsz) * 4; 3491 rdev->ih.ring_size = ring_size; 3492 rdev->ih.ptr_mask = rdev->ih.ring_size - 1; 3493 rdev->ih.rptr = 0; 3494 } 3495 3496 int r600_ih_ring_alloc(struct radeon_device *rdev) 3497 { 3498 int r; 3499 3500 /* Allocate ring buffer */ 3501 if (rdev->ih.ring_obj == NULL) { 3502 r = radeon_bo_create(rdev, rdev->ih.ring_size, 3503 PAGE_SIZE, true, 3504 RADEON_GEM_DOMAIN_GTT, 0, 3505 NULL, NULL, &rdev->ih.ring_obj); 3506 if (r) { 3507 DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r); 3508 return r; 3509 } 3510 r = radeon_bo_reserve(rdev->ih.ring_obj, false); 3511 if (unlikely(r != 0)) 3512 return r; 3513 r = radeon_bo_pin(rdev->ih.ring_obj, 3514 RADEON_GEM_DOMAIN_GTT, 3515 &rdev->ih.gpu_addr); 3516 if (r) { 3517 radeon_bo_unreserve(rdev->ih.ring_obj); 3518 DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r); 3519 return r; 3520 } 3521 r = radeon_bo_kmap(rdev->ih.ring_obj, 3522 (void **)__UNVOLATILE(&rdev->ih.ring)); 3523 radeon_bo_unreserve(rdev->ih.ring_obj); 3524 if (r) { 3525 DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r); 3526 return r; 3527 } 3528 } 3529 return 0; 3530 } 3531 3532 void r600_ih_ring_fini(struct radeon_device *rdev) 3533 { 3534 int r; 3535 if (rdev->ih.ring_obj) { 3536 r = radeon_bo_reserve(rdev->ih.ring_obj, false); 3537 if (likely(r == 0)) { 3538 radeon_bo_kunmap(rdev->ih.ring_obj); 3539 radeon_bo_unpin(rdev->ih.ring_obj); 3540 radeon_bo_unreserve(rdev->ih.ring_obj); 3541 } 3542 radeon_bo_unref(&rdev->ih.ring_obj); 3543 rdev->ih.ring = NULL; 3544 rdev->ih.ring_obj = NULL; 3545 } 3546 } 3547 3548 void r600_rlc_stop(struct radeon_device *rdev) 3549 { 3550 3551 if ((rdev->family >= CHIP_RV770) && 3552 (rdev->family <= CHIP_RV740)) { 3553 /* r7xx asics need to soft reset RLC before halting */ 3554 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC); 3555 RREG32(SRBM_SOFT_RESET); 3556 mdelay(15); 3557 WREG32(SRBM_SOFT_RESET, 0); 3558 RREG32(SRBM_SOFT_RESET); 3559 } 3560 3561 WREG32(RLC_CNTL, 0); 3562 } 3563 3564 static void r600_rlc_start(struct radeon_device *rdev) 3565 { 3566 WREG32(RLC_CNTL, RLC_ENABLE); 3567 } 3568 3569 static int r600_rlc_resume(struct radeon_device *rdev) 3570 { 3571 u32 i; 3572 const __be32 *fw_data; 3573 3574 if (!rdev->rlc_fw) 3575 return -EINVAL; 3576 3577 r600_rlc_stop(rdev); 3578 3579 WREG32(RLC_HB_CNTL, 0); 3580 3581 WREG32(RLC_HB_BASE, 0); 3582 WREG32(RLC_HB_RPTR, 0); 3583 WREG32(RLC_HB_WPTR, 0); 3584 WREG32(RLC_HB_WPTR_LSB_ADDR, 0); 3585 WREG32(RLC_HB_WPTR_MSB_ADDR, 0); 3586 WREG32(RLC_MC_CNTL, 0); 3587 WREG32(RLC_UCODE_CNTL, 0); 3588 3589 fw_data = (const __be32 *)rdev->rlc_fw->data; 3590 if (rdev->family >= CHIP_RV770) { 3591 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) { 3592 WREG32(RLC_UCODE_ADDR, i); 3593 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); 3594 } 3595 } else { 3596 for (i = 0; i < R600_RLC_UCODE_SIZE; i++) { 3597 WREG32(RLC_UCODE_ADDR, i); 3598 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); 3599 } 3600 } 3601 WREG32(RLC_UCODE_ADDR, 0); 3602 3603 r600_rlc_start(rdev); 3604 3605 return 0; 3606 } 3607 3608 static void r600_enable_interrupts(struct radeon_device *rdev) 3609 { 3610 u32 ih_cntl = RREG32(IH_CNTL); 3611 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); 3612 3613 ih_cntl |= ENABLE_INTR; 3614 ih_rb_cntl |= IH_RB_ENABLE; 3615 WREG32(IH_CNTL, ih_cntl); 3616 WREG32(IH_RB_CNTL, ih_rb_cntl); 3617 rdev->ih.enabled = true; 3618 } 3619 3620 void r600_disable_interrupts(struct radeon_device *rdev) 3621 { 3622 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); 3623 u32 ih_cntl = RREG32(IH_CNTL); 3624 3625 ih_rb_cntl &= ~IH_RB_ENABLE; 3626 ih_cntl &= ~ENABLE_INTR; 3627 WREG32(IH_RB_CNTL, ih_rb_cntl); 3628 WREG32(IH_CNTL, ih_cntl); 3629 /* set rptr, wptr to 0 */ 3630 WREG32(IH_RB_RPTR, 0); 3631 WREG32(IH_RB_WPTR, 0); 3632 rdev->ih.enabled = false; 3633 rdev->ih.rptr = 0; 3634 } 3635 3636 static void r600_disable_interrupt_state(struct radeon_device *rdev) 3637 { 3638 u32 tmp; 3639 3640 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); 3641 tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE; 3642 WREG32(DMA_CNTL, tmp); 3643 WREG32(GRBM_INT_CNTL, 0); 3644 WREG32(DxMODE_INT_MASK, 0); 3645 WREG32(D1GRPH_INTERRUPT_CONTROL, 0); 3646 WREG32(D2GRPH_INTERRUPT_CONTROL, 0); 3647 if (ASIC_IS_DCE3(rdev)) { 3648 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0); 3649 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0); 3650 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3651 WREG32(DC_HPD1_INT_CONTROL, tmp); 3652 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3653 WREG32(DC_HPD2_INT_CONTROL, tmp); 3654 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3655 WREG32(DC_HPD3_INT_CONTROL, tmp); 3656 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3657 WREG32(DC_HPD4_INT_CONTROL, tmp); 3658 if (ASIC_IS_DCE32(rdev)) { 3659 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3660 WREG32(DC_HPD5_INT_CONTROL, tmp); 3661 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3662 WREG32(DC_HPD6_INT_CONTROL, tmp); 3663 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3664 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp); 3665 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3666 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp); 3667 } else { 3668 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3669 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); 3670 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3671 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp); 3672 } 3673 } else { 3674 WREG32(DACA_AUTODETECT_INT_CONTROL, 0); 3675 WREG32(DACB_AUTODETECT_INT_CONTROL, 0); 3676 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; 3677 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); 3678 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; 3679 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); 3680 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; 3681 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); 3682 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3683 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); 3684 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3685 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp); 3686 } 3687 } 3688 3689 int r600_irq_init(struct radeon_device *rdev) 3690 { 3691 int ret = 0; 3692 int rb_bufsz; 3693 u32 interrupt_cntl, ih_cntl, ih_rb_cntl; 3694 3695 /* allocate ring */ 3696 ret = r600_ih_ring_alloc(rdev); 3697 if (ret) 3698 return ret; 3699 3700 /* disable irqs */ 3701 r600_disable_interrupts(rdev); 3702 3703 /* init rlc */ 3704 if (rdev->family >= CHIP_CEDAR) 3705 ret = evergreen_rlc_resume(rdev); 3706 else 3707 ret = r600_rlc_resume(rdev); 3708 if (ret) { 3709 r600_ih_ring_fini(rdev); 3710 return ret; 3711 } 3712 3713 /* setup interrupt control */ 3714 /* set dummy read address to ring address */ 3715 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8); 3716 interrupt_cntl = RREG32(INTERRUPT_CNTL); 3717 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi 3718 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN 3719 */ 3720 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE; 3721 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */ 3722 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN; 3723 WREG32(INTERRUPT_CNTL, interrupt_cntl); 3724 3725 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8); 3726 rb_bufsz = order_base_2(rdev->ih.ring_size / 4); 3727 3728 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE | 3729 IH_WPTR_OVERFLOW_CLEAR | 3730 (rb_bufsz << 1)); 3731 3732 if (rdev->wb.enabled) 3733 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE; 3734 3735 /* set the writeback address whether it's enabled or not */ 3736 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC); 3737 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF); 3738 3739 WREG32(IH_RB_CNTL, ih_rb_cntl); 3740 3741 /* set rptr, wptr to 0 */ 3742 WREG32(IH_RB_RPTR, 0); 3743 WREG32(IH_RB_WPTR, 0); 3744 3745 /* Default settings for IH_CNTL (disabled at first) */ 3746 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10); 3747 /* RPTR_REARM only works if msi's are enabled */ 3748 if (rdev->msi_enabled) 3749 ih_cntl |= RPTR_REARM; 3750 WREG32(IH_CNTL, ih_cntl); 3751 3752 /* force the active interrupt state to all disabled */ 3753 if (rdev->family >= CHIP_CEDAR) 3754 evergreen_disable_interrupt_state(rdev); 3755 else 3756 r600_disable_interrupt_state(rdev); 3757 3758 /* at this point everything should be setup correctly to enable master */ 3759 pci_set_master(rdev->pdev); 3760 3761 /* enable irqs */ 3762 r600_enable_interrupts(rdev); 3763 3764 return ret; 3765 } 3766 3767 void r600_irq_suspend(struct radeon_device *rdev) 3768 { 3769 r600_irq_disable(rdev); 3770 r600_rlc_stop(rdev); 3771 } 3772 3773 void r600_irq_fini(struct radeon_device *rdev) 3774 { 3775 r600_irq_suspend(rdev); 3776 r600_ih_ring_fini(rdev); 3777 } 3778 3779 int r600_irq_set(struct radeon_device *rdev) 3780 { 3781 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE; 3782 u32 mode_int = 0; 3783 u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0; 3784 u32 grbm_int_cntl = 0; 3785 u32 hdmi0, hdmi1; 3786 u32 dma_cntl; 3787 u32 thermal_int = 0; 3788 3789 if (!rdev->irq.installed) { 3790 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); 3791 return -EINVAL; 3792 } 3793 /* don't enable anything if the ih is disabled */ 3794 if (!rdev->ih.enabled) { 3795 r600_disable_interrupts(rdev); 3796 /* force the active interrupt state to all disabled */ 3797 r600_disable_interrupt_state(rdev); 3798 return 0; 3799 } 3800 3801 if (ASIC_IS_DCE3(rdev)) { 3802 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN; 3803 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN; 3804 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN; 3805 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN; 3806 if (ASIC_IS_DCE32(rdev)) { 3807 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN; 3808 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN; 3809 hdmi0 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~AFMT_AZ_FORMAT_WTRIG_MASK; 3810 hdmi1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~AFMT_AZ_FORMAT_WTRIG_MASK; 3811 } else { 3812 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3813 hdmi1 = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3814 } 3815 } else { 3816 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN; 3817 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN; 3818 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN; 3819 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3820 hdmi1 = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3821 } 3822 3823 dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE; 3824 3825 if ((rdev->family > CHIP_R600) && (rdev->family < CHIP_RV770)) { 3826 thermal_int = RREG32(CG_THERMAL_INT) & 3827 ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW); 3828 } else if (rdev->family >= CHIP_RV770) { 3829 thermal_int = RREG32(RV770_CG_THERMAL_INT) & 3830 ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW); 3831 } 3832 if (rdev->irq.dpm_thermal) { 3833 DRM_DEBUG("dpm thermal\n"); 3834 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW; 3835 } 3836 3837 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { 3838 DRM_DEBUG("r600_irq_set: sw int\n"); 3839 cp_int_cntl |= RB_INT_ENABLE; 3840 cp_int_cntl |= TIME_STAMP_INT_ENABLE; 3841 } 3842 3843 if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) { 3844 DRM_DEBUG("r600_irq_set: sw int dma\n"); 3845 dma_cntl |= TRAP_ENABLE; 3846 } 3847 3848 if (rdev->irq.crtc_vblank_int[0] || 3849 atomic_read(&rdev->irq.pflip[0])) { 3850 DRM_DEBUG("r600_irq_set: vblank 0\n"); 3851 mode_int |= D1MODE_VBLANK_INT_MASK; 3852 } 3853 if (rdev->irq.crtc_vblank_int[1] || 3854 atomic_read(&rdev->irq.pflip[1])) { 3855 DRM_DEBUG("r600_irq_set: vblank 1\n"); 3856 mode_int |= D2MODE_VBLANK_INT_MASK; 3857 } 3858 if (rdev->irq.hpd[0]) { 3859 DRM_DEBUG("r600_irq_set: hpd 1\n"); 3860 hpd1 |= DC_HPDx_INT_EN; 3861 } 3862 if (rdev->irq.hpd[1]) { 3863 DRM_DEBUG("r600_irq_set: hpd 2\n"); 3864 hpd2 |= DC_HPDx_INT_EN; 3865 } 3866 if (rdev->irq.hpd[2]) { 3867 DRM_DEBUG("r600_irq_set: hpd 3\n"); 3868 hpd3 |= DC_HPDx_INT_EN; 3869 } 3870 if (rdev->irq.hpd[3]) { 3871 DRM_DEBUG("r600_irq_set: hpd 4\n"); 3872 hpd4 |= DC_HPDx_INT_EN; 3873 } 3874 if (rdev->irq.hpd[4]) { 3875 DRM_DEBUG("r600_irq_set: hpd 5\n"); 3876 hpd5 |= DC_HPDx_INT_EN; 3877 } 3878 if (rdev->irq.hpd[5]) { 3879 DRM_DEBUG("r600_irq_set: hpd 6\n"); 3880 hpd6 |= DC_HPDx_INT_EN; 3881 } 3882 if (rdev->irq.afmt[0]) { 3883 DRM_DEBUG("r600_irq_set: hdmi 0\n"); 3884 hdmi0 |= HDMI0_AZ_FORMAT_WTRIG_MASK; 3885 } 3886 if (rdev->irq.afmt[1]) { 3887 DRM_DEBUG("r600_irq_set: hdmi 0\n"); 3888 hdmi1 |= HDMI0_AZ_FORMAT_WTRIG_MASK; 3889 } 3890 3891 WREG32(CP_INT_CNTL, cp_int_cntl); 3892 WREG32(DMA_CNTL, dma_cntl); 3893 WREG32(DxMODE_INT_MASK, mode_int); 3894 WREG32(D1GRPH_INTERRUPT_CONTROL, DxGRPH_PFLIP_INT_MASK); 3895 WREG32(D2GRPH_INTERRUPT_CONTROL, DxGRPH_PFLIP_INT_MASK); 3896 WREG32(GRBM_INT_CNTL, grbm_int_cntl); 3897 if (ASIC_IS_DCE3(rdev)) { 3898 WREG32(DC_HPD1_INT_CONTROL, hpd1); 3899 WREG32(DC_HPD2_INT_CONTROL, hpd2); 3900 WREG32(DC_HPD3_INT_CONTROL, hpd3); 3901 WREG32(DC_HPD4_INT_CONTROL, hpd4); 3902 if (ASIC_IS_DCE32(rdev)) { 3903 WREG32(DC_HPD5_INT_CONTROL, hpd5); 3904 WREG32(DC_HPD6_INT_CONTROL, hpd6); 3905 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, hdmi0); 3906 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, hdmi1); 3907 } else { 3908 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0); 3909 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, hdmi1); 3910 } 3911 } else { 3912 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1); 3913 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2); 3914 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3); 3915 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0); 3916 WREG32(HDMI1_AUDIO_PACKET_CONTROL, hdmi1); 3917 } 3918 if ((rdev->family > CHIP_R600) && (rdev->family < CHIP_RV770)) { 3919 WREG32(CG_THERMAL_INT, thermal_int); 3920 } else if (rdev->family >= CHIP_RV770) { 3921 WREG32(RV770_CG_THERMAL_INT, thermal_int); 3922 } 3923 3924 /* posting read */ 3925 RREG32(R_000E50_SRBM_STATUS); 3926 3927 return 0; 3928 } 3929 3930 static void r600_irq_ack(struct radeon_device *rdev) 3931 { 3932 u32 tmp; 3933 3934 if (ASIC_IS_DCE3(rdev)) { 3935 rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS); 3936 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE); 3937 rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2); 3938 if (ASIC_IS_DCE32(rdev)) { 3939 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET0); 3940 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET1); 3941 } else { 3942 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS); 3943 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(DCE3_HDMI1_STATUS); 3944 } 3945 } else { 3946 rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS); 3947 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE); 3948 rdev->irq.stat_regs.r600.disp_int_cont2 = 0; 3949 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS); 3950 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(HDMI1_STATUS); 3951 } 3952 rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS); 3953 rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS); 3954 3955 if (rdev->irq.stat_regs.r600.d1grph_int & DxGRPH_PFLIP_INT_OCCURRED) 3956 WREG32(D1GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR); 3957 if (rdev->irq.stat_regs.r600.d2grph_int & DxGRPH_PFLIP_INT_OCCURRED) 3958 WREG32(D2GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR); 3959 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) 3960 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK); 3961 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) 3962 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK); 3963 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) 3964 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK); 3965 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) 3966 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK); 3967 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) { 3968 if (ASIC_IS_DCE3(rdev)) { 3969 tmp = RREG32(DC_HPD1_INT_CONTROL); 3970 tmp |= DC_HPDx_INT_ACK; 3971 WREG32(DC_HPD1_INT_CONTROL, tmp); 3972 } else { 3973 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL); 3974 tmp |= DC_HPDx_INT_ACK; 3975 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); 3976 } 3977 } 3978 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) { 3979 if (ASIC_IS_DCE3(rdev)) { 3980 tmp = RREG32(DC_HPD2_INT_CONTROL); 3981 tmp |= DC_HPDx_INT_ACK; 3982 WREG32(DC_HPD2_INT_CONTROL, tmp); 3983 } else { 3984 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL); 3985 tmp |= DC_HPDx_INT_ACK; 3986 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); 3987 } 3988 } 3989 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) { 3990 if (ASIC_IS_DCE3(rdev)) { 3991 tmp = RREG32(DC_HPD3_INT_CONTROL); 3992 tmp |= DC_HPDx_INT_ACK; 3993 WREG32(DC_HPD3_INT_CONTROL, tmp); 3994 } else { 3995 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL); 3996 tmp |= DC_HPDx_INT_ACK; 3997 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); 3998 } 3999 } 4000 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) { 4001 tmp = RREG32(DC_HPD4_INT_CONTROL); 4002 tmp |= DC_HPDx_INT_ACK; 4003 WREG32(DC_HPD4_INT_CONTROL, tmp); 4004 } 4005 if (ASIC_IS_DCE32(rdev)) { 4006 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) { 4007 tmp = RREG32(DC_HPD5_INT_CONTROL); 4008 tmp |= DC_HPDx_INT_ACK; 4009 WREG32(DC_HPD5_INT_CONTROL, tmp); 4010 } 4011 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) { 4012 tmp = RREG32(DC_HPD6_INT_CONTROL); 4013 tmp |= DC_HPDx_INT_ACK; 4014 WREG32(DC_HPD6_INT_CONTROL, tmp); 4015 } 4016 if (rdev->irq.stat_regs.r600.hdmi0_status & AFMT_AZ_FORMAT_WTRIG) { 4017 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0); 4018 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; 4019 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp); 4020 } 4021 if (rdev->irq.stat_regs.r600.hdmi1_status & AFMT_AZ_FORMAT_WTRIG) { 4022 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1); 4023 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; 4024 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp); 4025 } 4026 } else { 4027 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) { 4028 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL); 4029 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK; 4030 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); 4031 } 4032 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) { 4033 if (ASIC_IS_DCE3(rdev)) { 4034 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL); 4035 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK; 4036 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp); 4037 } else { 4038 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL); 4039 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK; 4040 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp); 4041 } 4042 } 4043 } 4044 } 4045 4046 void r600_irq_disable(struct radeon_device *rdev) 4047 { 4048 r600_disable_interrupts(rdev); 4049 /* Wait and acknowledge irq */ 4050 mdelay(1); 4051 r600_irq_ack(rdev); 4052 r600_disable_interrupt_state(rdev); 4053 } 4054 4055 static u32 r600_get_ih_wptr(struct radeon_device *rdev) 4056 { 4057 u32 wptr, tmp; 4058 4059 if (rdev->wb.enabled) 4060 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]); 4061 else 4062 wptr = RREG32(IH_RB_WPTR); 4063 4064 if (wptr & RB_OVERFLOW) { 4065 wptr &= ~RB_OVERFLOW; 4066 /* When a ring buffer overflow happen start parsing interrupt 4067 * from the last not overwritten vector (wptr + 16). Hopefully 4068 * this should allow us to catchup. 4069 */ 4070 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n", 4071 wptr, rdev->ih.rptr, (wptr + 16) & rdev->ih.ptr_mask); 4072 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask; 4073 tmp = RREG32(IH_RB_CNTL); 4074 tmp |= IH_WPTR_OVERFLOW_CLEAR; 4075 WREG32(IH_RB_CNTL, tmp); 4076 } 4077 return (wptr & rdev->ih.ptr_mask); 4078 } 4079 4080 /* r600 IV Ring 4081 * Each IV ring entry is 128 bits: 4082 * [7:0] - interrupt source id 4083 * [31:8] - reserved 4084 * [59:32] - interrupt source data 4085 * [127:60] - reserved 4086 * 4087 * The basic interrupt vector entries 4088 * are decoded as follows: 4089 * src_id src_data description 4090 * 1 0 D1 Vblank 4091 * 1 1 D1 Vline 4092 * 5 0 D2 Vblank 4093 * 5 1 D2 Vline 4094 * 19 0 FP Hot plug detection A 4095 * 19 1 FP Hot plug detection B 4096 * 19 2 DAC A auto-detection 4097 * 19 3 DAC B auto-detection 4098 * 21 4 HDMI block A 4099 * 21 5 HDMI block B 4100 * 176 - CP_INT RB 4101 * 177 - CP_INT IB1 4102 * 178 - CP_INT IB2 4103 * 181 - EOP Interrupt 4104 * 233 - GUI Idle 4105 * 4106 * Note, these are based on r600 and may need to be 4107 * adjusted or added to on newer asics 4108 */ 4109 4110 int r600_irq_process(struct radeon_device *rdev) 4111 { 4112 u32 wptr; 4113 u32 rptr; 4114 u32 src_id, src_data; 4115 u32 ring_index; 4116 bool queue_hotplug = false; 4117 bool queue_hdmi = false; 4118 bool queue_thermal = false; 4119 4120 if (!rdev->ih.enabled || rdev->shutdown) 4121 return IRQ_NONE; 4122 4123 /* No MSIs, need a dummy read to flush PCI DMAs */ 4124 if (!rdev->msi_enabled) 4125 RREG32(IH_RB_WPTR); 4126 4127 wptr = r600_get_ih_wptr(rdev); 4128 4129 restart_ih: 4130 /* is somebody else already processing irqs? */ 4131 if (atomic_xchg(&rdev->ih.lock, 1)) 4132 return IRQ_NONE; 4133 4134 rptr = rdev->ih.rptr; 4135 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr); 4136 4137 /* Order reading of wptr vs. reading of IH ring data */ 4138 rmb(); 4139 4140 /* display interrupts */ 4141 r600_irq_ack(rdev); 4142 4143 while (rptr != wptr) { 4144 /* wptr/rptr are in bytes! */ 4145 ring_index = rptr / 4; 4146 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff; 4147 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff; 4148 4149 switch (src_id) { 4150 case 1: /* D1 vblank/vline */ 4151 switch (src_data) { 4152 case 0: /* D1 vblank */ 4153 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT)) 4154 DRM_DEBUG("IH: D1 vblank - IH event w/o asserted irq bit?\n"); 4155 4156 if (rdev->irq.crtc_vblank_int[0]) { 4157 drm_handle_vblank(rdev->ddev, 0); 4158 #ifdef __NetBSD__ 4159 spin_lock(&rdev->irq.vblank_lock); 4160 rdev->pm.vblank_sync = true; 4161 DRM_SPIN_WAKEUP_ONE(&rdev->irq.vblank_queue, &rdev->irq.vblank_lock); 4162 spin_unlock(&rdev->irq.vblank_lock); 4163 #else 4164 rdev->pm.vblank_sync = true; 4165 wake_up(&rdev->irq.vblank_queue); 4166 #endif 4167 } 4168 if (atomic_read(&rdev->irq.pflip[0])) 4169 radeon_crtc_handle_vblank(rdev, 0); 4170 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT; 4171 DRM_DEBUG("IH: D1 vblank\n"); 4172 4173 break; 4174 case 1: /* D1 vline */ 4175 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT)) 4176 DRM_DEBUG("IH: D1 vline - IH event w/o asserted irq bit?\n"); 4177 4178 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT; 4179 DRM_DEBUG("IH: D1 vline\n"); 4180 4181 break; 4182 default: 4183 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 4184 break; 4185 } 4186 break; 4187 case 5: /* D2 vblank/vline */ 4188 switch (src_data) { 4189 case 0: /* D2 vblank */ 4190 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT)) 4191 DRM_DEBUG("IH: D2 vblank - IH event w/o asserted irq bit?\n"); 4192 4193 if (rdev->irq.crtc_vblank_int[1]) { 4194 drm_handle_vblank(rdev->ddev, 1); 4195 #ifdef __NetBSD__ 4196 spin_lock(&rdev->irq.vblank_lock); 4197 rdev->pm.vblank_sync = true; 4198 DRM_SPIN_WAKEUP_ONE(&rdev->irq.vblank_queue, &rdev->irq.vblank_lock); 4199 spin_unlock(&rdev->irq.vblank_lock); 4200 #else 4201 rdev->pm.vblank_sync = true; 4202 wake_up(&rdev->irq.vblank_queue); 4203 #endif 4204 } 4205 if (atomic_read(&rdev->irq.pflip[1])) 4206 radeon_crtc_handle_vblank(rdev, 1); 4207 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT; 4208 DRM_DEBUG("IH: D2 vblank\n"); 4209 4210 break; 4211 case 1: /* D1 vline */ 4212 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT)) 4213 DRM_DEBUG("IH: D2 vline - IH event w/o asserted irq bit?\n"); 4214 4215 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT; 4216 DRM_DEBUG("IH: D2 vline\n"); 4217 4218 break; 4219 default: 4220 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 4221 break; 4222 } 4223 break; 4224 case 9: /* D1 pflip */ 4225 DRM_DEBUG("IH: D1 flip\n"); 4226 if (radeon_use_pflipirq > 0) 4227 radeon_crtc_handle_flip(rdev, 0); 4228 break; 4229 case 11: /* D2 pflip */ 4230 DRM_DEBUG("IH: D2 flip\n"); 4231 if (radeon_use_pflipirq > 0) 4232 radeon_crtc_handle_flip(rdev, 1); 4233 break; 4234 case 19: /* HPD/DAC hotplug */ 4235 switch (src_data) { 4236 case 0: 4237 if (!(rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT)) 4238 DRM_DEBUG("IH: HPD1 - IH event w/o asserted irq bit?\n"); 4239 4240 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT; 4241 queue_hotplug = true; 4242 DRM_DEBUG("IH: HPD1\n"); 4243 break; 4244 case 1: 4245 if (!(rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT)) 4246 DRM_DEBUG("IH: HPD2 - IH event w/o asserted irq bit?\n"); 4247 4248 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT; 4249 queue_hotplug = true; 4250 DRM_DEBUG("IH: HPD2\n"); 4251 break; 4252 case 4: 4253 if (!(rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT)) 4254 DRM_DEBUG("IH: HPD3 - IH event w/o asserted irq bit?\n"); 4255 4256 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT; 4257 queue_hotplug = true; 4258 DRM_DEBUG("IH: HPD3\n"); 4259 break; 4260 case 5: 4261 if (!(rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT)) 4262 DRM_DEBUG("IH: HPD4 - IH event w/o asserted irq bit?\n"); 4263 4264 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT; 4265 queue_hotplug = true; 4266 DRM_DEBUG("IH: HPD4\n"); 4267 break; 4268 case 10: 4269 if (!(rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT)) 4270 DRM_DEBUG("IH: HPD5 - IH event w/o asserted irq bit?\n"); 4271 4272 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT; 4273 queue_hotplug = true; 4274 DRM_DEBUG("IH: HPD5\n"); 4275 break; 4276 case 12: 4277 if (!(rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT)) 4278 DRM_DEBUG("IH: HPD6 - IH event w/o asserted irq bit?\n"); 4279 4280 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT; 4281 queue_hotplug = true; 4282 DRM_DEBUG("IH: HPD6\n"); 4283 4284 break; 4285 default: 4286 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 4287 break; 4288 } 4289 break; 4290 case 21: /* hdmi */ 4291 switch (src_data) { 4292 case 4: 4293 if (!(rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG)) 4294 DRM_DEBUG("IH: HDMI0 - IH event w/o asserted irq bit?\n"); 4295 4296 rdev->irq.stat_regs.r600.hdmi0_status &= ~HDMI0_AZ_FORMAT_WTRIG; 4297 queue_hdmi = true; 4298 DRM_DEBUG("IH: HDMI0\n"); 4299 4300 break; 4301 case 5: 4302 if (!(rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG)) 4303 DRM_DEBUG("IH: HDMI1 - IH event w/o asserted irq bit?\n"); 4304 4305 rdev->irq.stat_regs.r600.hdmi1_status &= ~HDMI0_AZ_FORMAT_WTRIG; 4306 queue_hdmi = true; 4307 DRM_DEBUG("IH: HDMI1\n"); 4308 4309 break; 4310 default: 4311 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data); 4312 break; 4313 } 4314 break; 4315 case 124: /* UVD */ 4316 DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data); 4317 radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX); 4318 break; 4319 case 176: /* CP_INT in ring buffer */ 4320 case 177: /* CP_INT in IB1 */ 4321 case 178: /* CP_INT in IB2 */ 4322 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data); 4323 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); 4324 break; 4325 case 181: /* CP EOP event */ 4326 DRM_DEBUG("IH: CP EOP\n"); 4327 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); 4328 break; 4329 case 224: /* DMA trap event */ 4330 DRM_DEBUG("IH: DMA trap\n"); 4331 radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX); 4332 break; 4333 case 230: /* thermal low to high */ 4334 DRM_DEBUG("IH: thermal low to high\n"); 4335 rdev->pm.dpm.thermal.high_to_low = false; 4336 queue_thermal = true; 4337 break; 4338 case 231: /* thermal high to low */ 4339 DRM_DEBUG("IH: thermal high to low\n"); 4340 rdev->pm.dpm.thermal.high_to_low = true; 4341 queue_thermal = true; 4342 break; 4343 case 233: /* GUI IDLE */ 4344 DRM_DEBUG("IH: GUI idle\n"); 4345 break; 4346 default: 4347 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 4348 break; 4349 } 4350 4351 /* wptr/rptr are in bytes! */ 4352 rptr += 16; 4353 rptr &= rdev->ih.ptr_mask; 4354 WREG32(IH_RB_RPTR, rptr); 4355 } 4356 if (queue_hotplug) 4357 schedule_delayed_work(&rdev->hotplug_work, 0); 4358 if (queue_hdmi) 4359 schedule_work(&rdev->audio_work); 4360 if (queue_thermal && rdev->pm.dpm_enabled) 4361 schedule_work(&rdev->pm.dpm.thermal.work); 4362 rdev->ih.rptr = rptr; 4363 atomic_set(&rdev->ih.lock, 0); 4364 4365 /* make sure wptr hasn't changed while processing */ 4366 wptr = r600_get_ih_wptr(rdev); 4367 if (wptr != rptr) 4368 goto restart_ih; 4369 4370 return IRQ_HANDLED; 4371 } 4372 4373 /* 4374 * Debugfs info 4375 */ 4376 #if defined(CONFIG_DEBUG_FS) 4377 4378 static int r600_debugfs_mc_info(struct seq_file *m, void *data) 4379 { 4380 struct drm_info_node *node = (struct drm_info_node *) m->private; 4381 struct drm_device *dev = node->minor->dev; 4382 struct radeon_device *rdev = dev->dev_private; 4383 4384 DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS); 4385 DREG32_SYS(m, rdev, VM_L2_STATUS); 4386 return 0; 4387 } 4388 4389 static struct drm_info_list r600_mc_info_list[] = { 4390 {"r600_mc_info", r600_debugfs_mc_info, 0, NULL}, 4391 }; 4392 #endif 4393 4394 int r600_debugfs_mc_info_init(struct radeon_device *rdev) 4395 { 4396 #if defined(CONFIG_DEBUG_FS) 4397 return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list)); 4398 #else 4399 return 0; 4400 #endif 4401 } 4402 4403 #ifdef __NetBSD__ 4404 # define __iomem volatile 4405 # define readl fake_readl 4406 #endif 4407 4408 /** 4409 * r600_mmio_hdp_flush - flush Host Data Path cache via MMIO 4410 * rdev: radeon device structure 4411 * 4412 * Some R6XX/R7XX don't seem to take into account HDP flushes performed 4413 * through the ring buffer. This leads to corruption in rendering, see 4414 * http://bugzilla.kernel.org/show_bug.cgi?id=15186 . To avoid this, we 4415 * directly perform the HDP flush by writing the register through MMIO. 4416 */ 4417 void r600_mmio_hdp_flush(struct radeon_device *rdev) 4418 { 4419 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read 4420 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL. 4421 * This seems to cause problems on some AGP cards. Just use the old 4422 * method for them. 4423 */ 4424 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) && 4425 rdev->vram_scratch.ptr && !(rdev->flags & RADEON_IS_AGP)) { 4426 void __iomem *ptr = rdev->vram_scratch.ptr; 4427 4428 WREG32(HDP_DEBUG1, 0); 4429 (void)readl(ptr); 4430 } else 4431 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); 4432 } 4433 4434 #ifdef __NetBSD__ 4435 # undef __iomem 4436 # undef readl 4437 #endif 4438 4439 void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes) 4440 { 4441 u32 link_width_cntl, mask; 4442 4443 if (rdev->flags & RADEON_IS_IGP) 4444 return; 4445 4446 if (!(rdev->flags & RADEON_IS_PCIE)) 4447 return; 4448 4449 /* x2 cards have a special sequence */ 4450 if (ASIC_IS_X2(rdev)) 4451 return; 4452 4453 radeon_gui_idle(rdev); 4454 4455 switch (lanes) { 4456 case 0: 4457 mask = RADEON_PCIE_LC_LINK_WIDTH_X0; 4458 break; 4459 case 1: 4460 mask = RADEON_PCIE_LC_LINK_WIDTH_X1; 4461 break; 4462 case 2: 4463 mask = RADEON_PCIE_LC_LINK_WIDTH_X2; 4464 break; 4465 case 4: 4466 mask = RADEON_PCIE_LC_LINK_WIDTH_X4; 4467 break; 4468 case 8: 4469 mask = RADEON_PCIE_LC_LINK_WIDTH_X8; 4470 break; 4471 case 12: 4472 /* not actually supported */ 4473 mask = RADEON_PCIE_LC_LINK_WIDTH_X12; 4474 break; 4475 case 16: 4476 mask = RADEON_PCIE_LC_LINK_WIDTH_X16; 4477 break; 4478 default: 4479 DRM_ERROR("invalid pcie lane request: %d\n", lanes); 4480 return; 4481 } 4482 4483 link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 4484 link_width_cntl &= ~RADEON_PCIE_LC_LINK_WIDTH_MASK; 4485 link_width_cntl |= mask << RADEON_PCIE_LC_LINK_WIDTH_SHIFT; 4486 link_width_cntl |= (RADEON_PCIE_LC_RECONFIG_NOW | 4487 R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE); 4488 4489 WREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4490 } 4491 4492 int r600_get_pcie_lanes(struct radeon_device *rdev) 4493 { 4494 u32 link_width_cntl; 4495 4496 if (rdev->flags & RADEON_IS_IGP) 4497 return 0; 4498 4499 if (!(rdev->flags & RADEON_IS_PCIE)) 4500 return 0; 4501 4502 /* x2 cards have a special sequence */ 4503 if (ASIC_IS_X2(rdev)) 4504 return 0; 4505 4506 radeon_gui_idle(rdev); 4507 4508 link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 4509 4510 switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) { 4511 case RADEON_PCIE_LC_LINK_WIDTH_X1: 4512 return 1; 4513 case RADEON_PCIE_LC_LINK_WIDTH_X2: 4514 return 2; 4515 case RADEON_PCIE_LC_LINK_WIDTH_X4: 4516 return 4; 4517 case RADEON_PCIE_LC_LINK_WIDTH_X8: 4518 return 8; 4519 case RADEON_PCIE_LC_LINK_WIDTH_X12: 4520 /* not actually supported */ 4521 return 12; 4522 case RADEON_PCIE_LC_LINK_WIDTH_X0: 4523 case RADEON_PCIE_LC_LINK_WIDTH_X16: 4524 default: 4525 return 16; 4526 } 4527 } 4528 4529 static void r600_pcie_gen2_enable(struct radeon_device *rdev) 4530 { 4531 #ifndef __NetBSD__ /* XXX radeon pcie */ 4532 u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp; 4533 u16 link_cntl2; 4534 4535 if (radeon_pcie_gen2 == 0) 4536 return; 4537 4538 if (rdev->flags & RADEON_IS_IGP) 4539 return; 4540 4541 if (!(rdev->flags & RADEON_IS_PCIE)) 4542 return; 4543 4544 /* x2 cards have a special sequence */ 4545 if (ASIC_IS_X2(rdev)) 4546 return; 4547 4548 /* only RV6xx+ chips are supported */ 4549 if (rdev->family <= CHIP_R600) 4550 return; 4551 4552 if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) && 4553 (rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT)) 4554 return; 4555 4556 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 4557 if (speed_cntl & LC_CURRENT_DATA_RATE) { 4558 DRM_INFO("PCIE gen 2 link speeds already enabled\n"); 4559 return; 4560 } 4561 4562 DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n"); 4563 4564 /* 55 nm r6xx asics */ 4565 if ((rdev->family == CHIP_RV670) || 4566 (rdev->family == CHIP_RV620) || 4567 (rdev->family == CHIP_RV635)) { 4568 /* advertise upconfig capability */ 4569 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); 4570 link_width_cntl &= ~LC_UPCONFIGURE_DIS; 4571 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4572 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); 4573 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) { 4574 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT; 4575 link_width_cntl &= ~(LC_LINK_WIDTH_MASK | 4576 LC_RECONFIG_ARC_MISSING_ESCAPE); 4577 link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN; 4578 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4579 } else { 4580 link_width_cntl |= LC_UPCONFIGURE_DIS; 4581 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4582 } 4583 } 4584 4585 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 4586 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) && 4587 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) { 4588 4589 /* 55 nm r6xx asics */ 4590 if ((rdev->family == CHIP_RV670) || 4591 (rdev->family == CHIP_RV620) || 4592 (rdev->family == CHIP_RV635)) { 4593 WREG32(MM_CFGREGS_CNTL, 0x8); 4594 link_cntl2 = RREG32(0x4088); 4595 WREG32(MM_CFGREGS_CNTL, 0); 4596 /* not supported yet */ 4597 if (link_cntl2 & SELECTABLE_DEEMPHASIS) 4598 return; 4599 } 4600 4601 speed_cntl &= ~LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK; 4602 speed_cntl |= (0x3 << LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT); 4603 speed_cntl &= ~LC_VOLTAGE_TIMER_SEL_MASK; 4604 speed_cntl &= ~LC_FORCE_DIS_HW_SPEED_CHANGE; 4605 speed_cntl |= LC_FORCE_EN_HW_SPEED_CHANGE; 4606 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); 4607 4608 tmp = RREG32(0x541c); 4609 WREG32(0x541c, tmp | 0x8); 4610 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN); 4611 link_cntl2 = RREG16(0x4088); 4612 link_cntl2 &= ~TARGET_LINK_SPEED_MASK; 4613 link_cntl2 |= 0x2; 4614 WREG16(0x4088, link_cntl2); 4615 WREG32(MM_CFGREGS_CNTL, 0); 4616 4617 if ((rdev->family == CHIP_RV670) || 4618 (rdev->family == CHIP_RV620) || 4619 (rdev->family == CHIP_RV635)) { 4620 training_cntl = RREG32_PCIE_PORT(PCIE_LC_TRAINING_CNTL); 4621 training_cntl &= ~LC_POINT_7_PLUS_EN; 4622 WREG32_PCIE_PORT(PCIE_LC_TRAINING_CNTL, training_cntl); 4623 } else { 4624 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 4625 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN; 4626 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); 4627 } 4628 4629 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 4630 speed_cntl |= LC_GEN2_EN_STRAP; 4631 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); 4632 4633 } else { 4634 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); 4635 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */ 4636 if (1) 4637 link_width_cntl |= LC_UPCONFIGURE_DIS; 4638 else 4639 link_width_cntl &= ~LC_UPCONFIGURE_DIS; 4640 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4641 } 4642 #endif 4643 } 4644 4645 /** 4646 * r600_get_gpu_clock_counter - return GPU clock counter snapshot 4647 * 4648 * @rdev: radeon_device pointer 4649 * 4650 * Fetches a GPU clock counter snapshot (R6xx-cayman). 4651 * Returns the 64 bit clock counter snapshot. 4652 */ 4653 uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev) 4654 { 4655 uint64_t clock; 4656 4657 mutex_lock(&rdev->gpu_clock_mutex); 4658 WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1); 4659 clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) | 4660 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 4661 mutex_unlock(&rdev->gpu_clock_mutex); 4662 return clock; 4663 } 4664
Indexes created Sat Oct 25 01:09:55 GMT 2025