radeon_r600.c revision 1.1.6.3
1 /* $NetBSD: radeon_r600.c,v 1.1.6.3 2020/04/08 14:08:26 martin Exp $ */ 2 3 /* 4 * Copyright 2008 Advanced Micro Devices, Inc. 5 * Copyright 2008 Red Hat Inc. 6 * Copyright 2009 Jerome Glisse. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: Dave Airlie 27 * Alex Deucher 28 * Jerome Glisse 29 */ 30 #include <sys/cdefs.h> 31 __KERNEL_RCSID(0, "$NetBSD: radeon_r600.c,v 1.1.6.3 2020/04/08 14:08:26 martin Exp $"); 32 33 #include <linux/slab.h> 34 #include <linux/seq_file.h> 35 #include <linux/firmware.h> 36 #include <linux/module.h> 37 #include <drm/drmP.h> 38 #include <drm/radeon_drm.h> 39 #include "radeon.h" 40 #include "radeon_asic.h" 41 #include "radeon_audio.h" 42 #include "radeon_mode.h" 43 #include "r600d.h" 44 #include "atom.h" 45 #include "avivod.h" 46 #include "radeon_ucode.h" 47 48 #include <linux/nbsd-namespace.h> 49 50 /* Firmware Names */ 51 MODULE_FIRMWARE("radeon/R600_pfp.bin"); 52 MODULE_FIRMWARE("radeon/R600_me.bin"); 53 MODULE_FIRMWARE("radeon/RV610_pfp.bin"); 54 MODULE_FIRMWARE("radeon/RV610_me.bin"); 55 MODULE_FIRMWARE("radeon/RV630_pfp.bin"); 56 MODULE_FIRMWARE("radeon/RV630_me.bin"); 57 MODULE_FIRMWARE("radeon/RV620_pfp.bin"); 58 MODULE_FIRMWARE("radeon/RV620_me.bin"); 59 MODULE_FIRMWARE("radeon/RV635_pfp.bin"); 60 MODULE_FIRMWARE("radeon/RV635_me.bin"); 61 MODULE_FIRMWARE("radeon/RV670_pfp.bin"); 62 MODULE_FIRMWARE("radeon/RV670_me.bin"); 63 MODULE_FIRMWARE("radeon/RS780_pfp.bin"); 64 MODULE_FIRMWARE("radeon/RS780_me.bin"); 65 MODULE_FIRMWARE("radeon/RV770_pfp.bin"); 66 MODULE_FIRMWARE("radeon/RV770_me.bin"); 67 MODULE_FIRMWARE("radeon/RV770_smc.bin"); 68 MODULE_FIRMWARE("radeon/RV730_pfp.bin"); 69 MODULE_FIRMWARE("radeon/RV730_me.bin"); 70 MODULE_FIRMWARE("radeon/RV730_smc.bin"); 71 MODULE_FIRMWARE("radeon/RV740_smc.bin"); 72 MODULE_FIRMWARE("radeon/RV710_pfp.bin"); 73 MODULE_FIRMWARE("radeon/RV710_me.bin"); 74 MODULE_FIRMWARE("radeon/RV710_smc.bin"); 75 MODULE_FIRMWARE("radeon/R600_rlc.bin"); 76 MODULE_FIRMWARE("radeon/R700_rlc.bin"); 77 MODULE_FIRMWARE("radeon/CEDAR_pfp.bin"); 78 MODULE_FIRMWARE("radeon/CEDAR_me.bin"); 79 MODULE_FIRMWARE("radeon/CEDAR_rlc.bin"); 80 MODULE_FIRMWARE("radeon/CEDAR_smc.bin"); 81 MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin"); 82 MODULE_FIRMWARE("radeon/REDWOOD_me.bin"); 83 MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin"); 84 MODULE_FIRMWARE("radeon/REDWOOD_smc.bin"); 85 MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin"); 86 MODULE_FIRMWARE("radeon/JUNIPER_me.bin"); 87 MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin"); 88 MODULE_FIRMWARE("radeon/JUNIPER_smc.bin"); 89 MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin"); 90 MODULE_FIRMWARE("radeon/CYPRESS_me.bin"); 91 MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin"); 92 MODULE_FIRMWARE("radeon/CYPRESS_smc.bin"); 93 MODULE_FIRMWARE("radeon/PALM_pfp.bin"); 94 MODULE_FIRMWARE("radeon/PALM_me.bin"); 95 MODULE_FIRMWARE("radeon/SUMO_rlc.bin"); 96 MODULE_FIRMWARE("radeon/SUMO_pfp.bin"); 97 MODULE_FIRMWARE("radeon/SUMO_me.bin"); 98 MODULE_FIRMWARE("radeon/SUMO2_pfp.bin"); 99 MODULE_FIRMWARE("radeon/SUMO2_me.bin"); 100 101 static const u32 crtc_offsets[2] = 102 { 103 0, 104 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL 105 }; 106 107 int r600_debugfs_mc_info_init(struct radeon_device *rdev); 108 109 /* r600,rv610,rv630,rv620,rv635,rv670 */ 110 int r600_mc_wait_for_idle(struct radeon_device *rdev); 111 static void r600_gpu_init(struct radeon_device *rdev); 112 void r600_fini(struct radeon_device *rdev); 113 void r600_irq_disable(struct radeon_device *rdev); 114 static void r600_pcie_gen2_enable(struct radeon_device *rdev); 115 extern int evergreen_rlc_resume(struct radeon_device *rdev); 116 extern void rv770_set_clk_bypass_mode(struct radeon_device *rdev); 117 118 /* 119 * Indirect registers accessor 120 */ 121 u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg) 122 { 123 unsigned long flags; 124 u32 r; 125 126 spin_lock_irqsave(&rdev->rcu_idx_lock, flags); 127 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff)); 128 r = RREG32(R600_RCU_DATA); 129 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags); 130 return r; 131 } 132 133 void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v) 134 { 135 unsigned long flags; 136 137 spin_lock_irqsave(&rdev->rcu_idx_lock, flags); 138 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff)); 139 WREG32(R600_RCU_DATA, (v)); 140 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags); 141 } 142 143 u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg) 144 { 145 unsigned long flags; 146 u32 r; 147 148 spin_lock_irqsave(&rdev->uvd_idx_lock, flags); 149 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff)); 150 r = RREG32(R600_UVD_CTX_DATA); 151 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags); 152 return r; 153 } 154 155 void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v) 156 { 157 unsigned long flags; 158 159 spin_lock_irqsave(&rdev->uvd_idx_lock, flags); 160 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff)); 161 WREG32(R600_UVD_CTX_DATA, (v)); 162 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags); 163 } 164 165 /** 166 * r600_get_allowed_info_register - fetch the register for the info ioctl 167 * 168 * @rdev: radeon_device pointer 169 * @reg: register offset in bytes 170 * @val: register value 171 * 172 * Returns 0 for success or -EINVAL for an invalid register 173 * 174 */ 175 int r600_get_allowed_info_register(struct radeon_device *rdev, 176 u32 reg, u32 *val) 177 { 178 switch (reg) { 179 case GRBM_STATUS: 180 case GRBM_STATUS2: 181 case R_000E50_SRBM_STATUS: 182 case DMA_STATUS_REG: 183 case UVD_STATUS: 184 *val = RREG32(reg); 185 return 0; 186 default: 187 return -EINVAL; 188 } 189 } 190 191 /** 192 * r600_get_xclk - get the xclk 193 * 194 * @rdev: radeon_device pointer 195 * 196 * Returns the reference clock used by the gfx engine 197 * (r6xx, IGPs, APUs). 198 */ 199 u32 r600_get_xclk(struct radeon_device *rdev) 200 { 201 return rdev->clock.spll.reference_freq; 202 } 203 204 int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) 205 { 206 unsigned fb_div = 0, ref_div, vclk_div = 0, dclk_div = 0; 207 int r; 208 209 /* bypass vclk and dclk with bclk */ 210 WREG32_P(CG_UPLL_FUNC_CNTL_2, 211 VCLK_SRC_SEL(1) | DCLK_SRC_SEL(1), 212 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK)); 213 214 /* assert BYPASS_EN, deassert UPLL_RESET, UPLL_SLEEP and UPLL_CTLREQ */ 215 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~( 216 UPLL_RESET_MASK | UPLL_SLEEP_MASK | UPLL_CTLREQ_MASK)); 217 218 if (rdev->family >= CHIP_RS780) 219 WREG32_P(GFX_MACRO_BYPASS_CNTL, UPLL_BYPASS_CNTL, 220 ~UPLL_BYPASS_CNTL); 221 222 if (!vclk || !dclk) { 223 /* keep the Bypass mode, put PLL to sleep */ 224 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK); 225 return 0; 226 } 227 228 if (rdev->clock.spll.reference_freq == 10000) 229 ref_div = 34; 230 else 231 ref_div = 4; 232 233 r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 50000, 160000, 234 ref_div + 1, 0xFFF, 2, 30, ~0, 235 &fb_div, &vclk_div, &dclk_div); 236 if (r) 237 return r; 238 239 if (rdev->family >= CHIP_RV670 && rdev->family < CHIP_RS780) 240 fb_div >>= 1; 241 else 242 fb_div |= 1; 243 244 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL); 245 if (r) 246 return r; 247 248 /* assert PLL_RESET */ 249 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK); 250 251 /* For RS780 we have to choose ref clk */ 252 if (rdev->family >= CHIP_RS780) 253 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_REFCLK_SRC_SEL_MASK, 254 ~UPLL_REFCLK_SRC_SEL_MASK); 255 256 /* set the required fb, ref and post divder values */ 257 WREG32_P(CG_UPLL_FUNC_CNTL, 258 UPLL_FB_DIV(fb_div) | 259 UPLL_REF_DIV(ref_div), 260 ~(UPLL_FB_DIV_MASK | UPLL_REF_DIV_MASK)); 261 WREG32_P(CG_UPLL_FUNC_CNTL_2, 262 UPLL_SW_HILEN(vclk_div >> 1) | 263 UPLL_SW_LOLEN((vclk_div >> 1) + (vclk_div & 1)) | 264 UPLL_SW_HILEN2(dclk_div >> 1) | 265 UPLL_SW_LOLEN2((dclk_div >> 1) + (dclk_div & 1)) | 266 UPLL_DIVEN_MASK | UPLL_DIVEN2_MASK, 267 ~UPLL_SW_MASK); 268 269 /* give the PLL some time to settle */ 270 mdelay(15); 271 272 /* deassert PLL_RESET */ 273 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); 274 275 mdelay(15); 276 277 /* deassert BYPASS EN */ 278 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK); 279 280 if (rdev->family >= CHIP_RS780) 281 WREG32_P(GFX_MACRO_BYPASS_CNTL, 0, ~UPLL_BYPASS_CNTL); 282 283 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL); 284 if (r) 285 return r; 286 287 /* switch VCLK and DCLK selection */ 288 WREG32_P(CG_UPLL_FUNC_CNTL_2, 289 VCLK_SRC_SEL(2) | DCLK_SRC_SEL(2), 290 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK)); 291 292 mdelay(100); 293 294 return 0; 295 } 296 297 void dce3_program_fmt(struct drm_encoder *encoder) 298 { 299 struct drm_device *dev = encoder->dev; 300 struct radeon_device *rdev = dev->dev_private; 301 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 302 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 303 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 304 int bpc = 0; 305 u32 tmp = 0; 306 enum radeon_connector_dither dither = RADEON_FMT_DITHER_DISABLE; 307 308 if (connector) { 309 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 310 bpc = radeon_get_monitor_bpc(connector); 311 dither = radeon_connector->dither; 312 } 313 314 /* LVDS FMT is set up by atom */ 315 if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) 316 return; 317 318 /* not needed for analog */ 319 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) || 320 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2)) 321 return; 322 323 if (bpc == 0) 324 return; 325 326 switch (bpc) { 327 case 6: 328 if (dither == RADEON_FMT_DITHER_ENABLE) 329 /* XXX sort out optimal dither settings */ 330 tmp |= FMT_SPATIAL_DITHER_EN; 331 else 332 tmp |= FMT_TRUNCATE_EN; 333 break; 334 case 8: 335 if (dither == RADEON_FMT_DITHER_ENABLE) 336 /* XXX sort out optimal dither settings */ 337 tmp |= (FMT_SPATIAL_DITHER_EN | FMT_SPATIAL_DITHER_DEPTH); 338 else 339 tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH); 340 break; 341 case 10: 342 default: 343 /* not needed */ 344 break; 345 } 346 347 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp); 348 } 349 350 /* get temperature in millidegrees */ 351 int rv6xx_get_temp(struct radeon_device *rdev) 352 { 353 u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >> 354 ASIC_T_SHIFT; 355 int actual_temp = temp & 0xff; 356 357 if (temp & 0x100) 358 actual_temp -= 256; 359 360 return actual_temp * 1000; 361 } 362 363 void r600_pm_get_dynpm_state(struct radeon_device *rdev) 364 { 365 int i; 366 367 rdev->pm.dynpm_can_upclock = true; 368 rdev->pm.dynpm_can_downclock = true; 369 370 /* power state array is low to high, default is first */ 371 if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) { 372 int min_power_state_index = 0; 373 374 if (rdev->pm.num_power_states > 2) 375 min_power_state_index = 1; 376 377 switch (rdev->pm.dynpm_planned_action) { 378 case DYNPM_ACTION_MINIMUM: 379 rdev->pm.requested_power_state_index = min_power_state_index; 380 rdev->pm.requested_clock_mode_index = 0; 381 rdev->pm.dynpm_can_downclock = false; 382 break; 383 case DYNPM_ACTION_DOWNCLOCK: 384 if (rdev->pm.current_power_state_index == min_power_state_index) { 385 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 386 rdev->pm.dynpm_can_downclock = false; 387 } else { 388 if (rdev->pm.active_crtc_count > 1) { 389 for (i = 0; i < rdev->pm.num_power_states; i++) { 390 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 391 continue; 392 else if (i >= rdev->pm.current_power_state_index) { 393 rdev->pm.requested_power_state_index = 394 rdev->pm.current_power_state_index; 395 break; 396 } else { 397 rdev->pm.requested_power_state_index = i; 398 break; 399 } 400 } 401 } else { 402 if (rdev->pm.current_power_state_index == 0) 403 rdev->pm.requested_power_state_index = 404 rdev->pm.num_power_states - 1; 405 else 406 rdev->pm.requested_power_state_index = 407 rdev->pm.current_power_state_index - 1; 408 } 409 } 410 rdev->pm.requested_clock_mode_index = 0; 411 /* don't use the power state if crtcs are active and no display flag is set */ 412 if ((rdev->pm.active_crtc_count > 0) && 413 (rdev->pm.power_state[rdev->pm.requested_power_state_index]. 414 clock_info[rdev->pm.requested_clock_mode_index].flags & 415 RADEON_PM_MODE_NO_DISPLAY)) { 416 rdev->pm.requested_power_state_index++; 417 } 418 break; 419 case DYNPM_ACTION_UPCLOCK: 420 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) { 421 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 422 rdev->pm.dynpm_can_upclock = false; 423 } else { 424 if (rdev->pm.active_crtc_count > 1) { 425 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) { 426 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 427 continue; 428 else if (i <= rdev->pm.current_power_state_index) { 429 rdev->pm.requested_power_state_index = 430 rdev->pm.current_power_state_index; 431 break; 432 } else { 433 rdev->pm.requested_power_state_index = i; 434 break; 435 } 436 } 437 } else 438 rdev->pm.requested_power_state_index = 439 rdev->pm.current_power_state_index + 1; 440 } 441 rdev->pm.requested_clock_mode_index = 0; 442 break; 443 case DYNPM_ACTION_DEFAULT: 444 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; 445 rdev->pm.requested_clock_mode_index = 0; 446 rdev->pm.dynpm_can_upclock = false; 447 break; 448 case DYNPM_ACTION_NONE: 449 default: 450 DRM_ERROR("Requested mode for not defined action\n"); 451 return; 452 } 453 } else { 454 /* XXX select a power state based on AC/DC, single/dualhead, etc. */ 455 /* for now just select the first power state and switch between clock modes */ 456 /* power state array is low to high, default is first (0) */ 457 if (rdev->pm.active_crtc_count > 1) { 458 rdev->pm.requested_power_state_index = -1; 459 /* start at 1 as we don't want the default mode */ 460 for (i = 1; i < rdev->pm.num_power_states; i++) { 461 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 462 continue; 463 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) || 464 (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) { 465 rdev->pm.requested_power_state_index = i; 466 break; 467 } 468 } 469 /* if nothing selected, grab the default state. */ 470 if (rdev->pm.requested_power_state_index == -1) 471 rdev->pm.requested_power_state_index = 0; 472 } else 473 rdev->pm.requested_power_state_index = 1; 474 475 switch (rdev->pm.dynpm_planned_action) { 476 case DYNPM_ACTION_MINIMUM: 477 rdev->pm.requested_clock_mode_index = 0; 478 rdev->pm.dynpm_can_downclock = false; 479 break; 480 case DYNPM_ACTION_DOWNCLOCK: 481 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) { 482 if (rdev->pm.current_clock_mode_index == 0) { 483 rdev->pm.requested_clock_mode_index = 0; 484 rdev->pm.dynpm_can_downclock = false; 485 } else 486 rdev->pm.requested_clock_mode_index = 487 rdev->pm.current_clock_mode_index - 1; 488 } else { 489 rdev->pm.requested_clock_mode_index = 0; 490 rdev->pm.dynpm_can_downclock = false; 491 } 492 /* don't use the power state if crtcs are active and no display flag is set */ 493 if ((rdev->pm.active_crtc_count > 0) && 494 (rdev->pm.power_state[rdev->pm.requested_power_state_index]. 495 clock_info[rdev->pm.requested_clock_mode_index].flags & 496 RADEON_PM_MODE_NO_DISPLAY)) { 497 rdev->pm.requested_clock_mode_index++; 498 } 499 break; 500 case DYNPM_ACTION_UPCLOCK: 501 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) { 502 if (rdev->pm.current_clock_mode_index == 503 (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) { 504 rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index; 505 rdev->pm.dynpm_can_upclock = false; 506 } else 507 rdev->pm.requested_clock_mode_index = 508 rdev->pm.current_clock_mode_index + 1; 509 } else { 510 rdev->pm.requested_clock_mode_index = 511 rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1; 512 rdev->pm.dynpm_can_upclock = false; 513 } 514 break; 515 case DYNPM_ACTION_DEFAULT: 516 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; 517 rdev->pm.requested_clock_mode_index = 0; 518 rdev->pm.dynpm_can_upclock = false; 519 break; 520 case DYNPM_ACTION_NONE: 521 default: 522 DRM_ERROR("Requested mode for not defined action\n"); 523 return; 524 } 525 } 526 527 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n", 528 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 529 clock_info[rdev->pm.requested_clock_mode_index].sclk, 530 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 531 clock_info[rdev->pm.requested_clock_mode_index].mclk, 532 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 533 pcie_lanes); 534 } 535 536 void rs780_pm_init_profile(struct radeon_device *rdev) 537 { 538 if (rdev->pm.num_power_states == 2) { 539 /* default */ 540 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 541 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 542 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 543 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 544 /* low sh */ 545 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0; 546 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0; 547 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 548 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 549 /* mid sh */ 550 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0; 551 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0; 552 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 553 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 554 /* high sh */ 555 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0; 556 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1; 557 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 558 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 559 /* low mh */ 560 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0; 561 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0; 562 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 563 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 564 /* mid mh */ 565 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0; 566 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0; 567 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 568 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 569 /* high mh */ 570 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0; 571 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1; 572 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 573 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 574 } else if (rdev->pm.num_power_states == 3) { 575 /* default */ 576 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 577 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 578 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 579 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 580 /* low sh */ 581 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1; 582 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1; 583 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 584 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 585 /* mid sh */ 586 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1; 587 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; 588 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 589 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 590 /* high sh */ 591 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1; 592 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2; 593 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 594 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 595 /* low mh */ 596 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1; 597 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1; 598 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 599 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 600 /* mid mh */ 601 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1; 602 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1; 603 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 604 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 605 /* high mh */ 606 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1; 607 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2; 608 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 609 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 610 } else { 611 /* default */ 612 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 613 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 614 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 615 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 616 /* low sh */ 617 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2; 618 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2; 619 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 620 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 621 /* mid sh */ 622 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2; 623 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2; 624 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 625 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 626 /* high sh */ 627 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2; 628 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3; 629 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 630 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 631 /* low mh */ 632 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2; 633 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0; 634 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 635 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 636 /* mid mh */ 637 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2; 638 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0; 639 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 640 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 641 /* high mh */ 642 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2; 643 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3; 644 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 645 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 646 } 647 } 648 649 void r600_pm_init_profile(struct radeon_device *rdev) 650 { 651 int idx; 652 653 if (rdev->family == CHIP_R600) { 654 /* XXX */ 655 /* default */ 656 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 657 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 658 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 659 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 660 /* low sh */ 661 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 662 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 663 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 664 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 665 /* mid sh */ 666 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 667 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 668 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 669 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 670 /* high sh */ 671 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 672 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 673 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 674 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 675 /* low mh */ 676 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 677 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 678 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 679 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 680 /* mid mh */ 681 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 682 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 683 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 684 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 685 /* high mh */ 686 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 687 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 688 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 689 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 690 } else { 691 if (rdev->pm.num_power_states < 4) { 692 /* default */ 693 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 694 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 695 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 696 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2; 697 /* low sh */ 698 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1; 699 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1; 700 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 701 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 702 /* mid sh */ 703 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1; 704 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; 705 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 706 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1; 707 /* high sh */ 708 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1; 709 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1; 710 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 711 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2; 712 /* low mh */ 713 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2; 714 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2; 715 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 716 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 717 /* low mh */ 718 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2; 719 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2; 720 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 721 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1; 722 /* high mh */ 723 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2; 724 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2; 725 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 726 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2; 727 } else { 728 /* default */ 729 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 730 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 731 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 732 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2; 733 /* low sh */ 734 if (rdev->flags & RADEON_IS_MOBILITY) 735 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0); 736 else 737 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); 738 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx; 739 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx; 740 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 741 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 742 /* mid sh */ 743 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx; 744 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx; 745 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 746 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1; 747 /* high sh */ 748 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); 749 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx; 750 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx; 751 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 752 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2; 753 /* low mh */ 754 if (rdev->flags & RADEON_IS_MOBILITY) 755 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1); 756 else 757 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1); 758 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx; 759 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx; 760 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 761 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 762 /* mid mh */ 763 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx; 764 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx; 765 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 766 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1; 767 /* high mh */ 768 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1); 769 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx; 770 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx; 771 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 772 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2; 773 } 774 } 775 } 776 777 void r600_pm_misc(struct radeon_device *rdev) 778 { 779 int req_ps_idx = rdev->pm.requested_power_state_index; 780 int req_cm_idx = rdev->pm.requested_clock_mode_index; 781 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx]; 782 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage; 783 784 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) { 785 /* 0xff01 is a flag rather then an actual voltage */ 786 if (voltage->voltage == 0xff01) 787 return; 788 if (voltage->voltage != rdev->pm.current_vddc) { 789 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC); 790 rdev->pm.current_vddc = voltage->voltage; 791 DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage->voltage); 792 } 793 } 794 } 795 796 bool r600_gui_idle(struct radeon_device *rdev) 797 { 798 if (RREG32(GRBM_STATUS) & GUI_ACTIVE) 799 return false; 800 else 801 return true; 802 } 803 804 /* hpd for digital panel detect/disconnect */ 805 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) 806 { 807 bool connected = false; 808 809 if (ASIC_IS_DCE3(rdev)) { 810 switch (hpd) { 811 case RADEON_HPD_1: 812 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE) 813 connected = true; 814 break; 815 case RADEON_HPD_2: 816 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE) 817 connected = true; 818 break; 819 case RADEON_HPD_3: 820 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE) 821 connected = true; 822 break; 823 case RADEON_HPD_4: 824 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE) 825 connected = true; 826 break; 827 /* DCE 3.2 */ 828 case RADEON_HPD_5: 829 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE) 830 connected = true; 831 break; 832 case RADEON_HPD_6: 833 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE) 834 connected = true; 835 break; 836 default: 837 break; 838 } 839 } else { 840 switch (hpd) { 841 case RADEON_HPD_1: 842 if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) 843 connected = true; 844 break; 845 case RADEON_HPD_2: 846 if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) 847 connected = true; 848 break; 849 case RADEON_HPD_3: 850 if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) 851 connected = true; 852 break; 853 default: 854 break; 855 } 856 } 857 return connected; 858 } 859 860 void r600_hpd_set_polarity(struct radeon_device *rdev, 861 enum radeon_hpd_id hpd) 862 { 863 u32 tmp; 864 bool connected = r600_hpd_sense(rdev, hpd); 865 866 if (ASIC_IS_DCE3(rdev)) { 867 switch (hpd) { 868 case RADEON_HPD_1: 869 tmp = RREG32(DC_HPD1_INT_CONTROL); 870 if (connected) 871 tmp &= ~DC_HPDx_INT_POLARITY; 872 else 873 tmp |= DC_HPDx_INT_POLARITY; 874 WREG32(DC_HPD1_INT_CONTROL, tmp); 875 break; 876 case RADEON_HPD_2: 877 tmp = RREG32(DC_HPD2_INT_CONTROL); 878 if (connected) 879 tmp &= ~DC_HPDx_INT_POLARITY; 880 else 881 tmp |= DC_HPDx_INT_POLARITY; 882 WREG32(DC_HPD2_INT_CONTROL, tmp); 883 break; 884 case RADEON_HPD_3: 885 tmp = RREG32(DC_HPD3_INT_CONTROL); 886 if (connected) 887 tmp &= ~DC_HPDx_INT_POLARITY; 888 else 889 tmp |= DC_HPDx_INT_POLARITY; 890 WREG32(DC_HPD3_INT_CONTROL, tmp); 891 break; 892 case RADEON_HPD_4: 893 tmp = RREG32(DC_HPD4_INT_CONTROL); 894 if (connected) 895 tmp &= ~DC_HPDx_INT_POLARITY; 896 else 897 tmp |= DC_HPDx_INT_POLARITY; 898 WREG32(DC_HPD4_INT_CONTROL, tmp); 899 break; 900 case RADEON_HPD_5: 901 tmp = RREG32(DC_HPD5_INT_CONTROL); 902 if (connected) 903 tmp &= ~DC_HPDx_INT_POLARITY; 904 else 905 tmp |= DC_HPDx_INT_POLARITY; 906 WREG32(DC_HPD5_INT_CONTROL, tmp); 907 break; 908 /* DCE 3.2 */ 909 case RADEON_HPD_6: 910 tmp = RREG32(DC_HPD6_INT_CONTROL); 911 if (connected) 912 tmp &= ~DC_HPDx_INT_POLARITY; 913 else 914 tmp |= DC_HPDx_INT_POLARITY; 915 WREG32(DC_HPD6_INT_CONTROL, tmp); 916 break; 917 default: 918 break; 919 } 920 } else { 921 switch (hpd) { 922 case RADEON_HPD_1: 923 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL); 924 if (connected) 925 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; 926 else 927 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; 928 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); 929 break; 930 case RADEON_HPD_2: 931 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL); 932 if (connected) 933 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; 934 else 935 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; 936 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); 937 break; 938 case RADEON_HPD_3: 939 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL); 940 if (connected) 941 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; 942 else 943 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; 944 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); 945 break; 946 default: 947 break; 948 } 949 } 950 } 951 952 void r600_hpd_init(struct radeon_device *rdev) 953 { 954 struct drm_device *dev = rdev->ddev; 955 struct drm_connector *connector; 956 unsigned enable = 0; 957 958 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 959 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 960 961 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || 962 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { 963 /* don't try to enable hpd on eDP or LVDS avoid breaking the 964 * aux dp channel on imac and help (but not completely fix) 965 * https://bugzilla.redhat.com/show_bug.cgi?id=726143 966 */ 967 continue; 968 } 969 if (ASIC_IS_DCE3(rdev)) { 970 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa); 971 if (ASIC_IS_DCE32(rdev)) 972 tmp |= DC_HPDx_EN; 973 974 switch (radeon_connector->hpd.hpd) { 975 case RADEON_HPD_1: 976 WREG32(DC_HPD1_CONTROL, tmp); 977 break; 978 case RADEON_HPD_2: 979 WREG32(DC_HPD2_CONTROL, tmp); 980 break; 981 case RADEON_HPD_3: 982 WREG32(DC_HPD3_CONTROL, tmp); 983 break; 984 case RADEON_HPD_4: 985 WREG32(DC_HPD4_CONTROL, tmp); 986 break; 987 /* DCE 3.2 */ 988 case RADEON_HPD_5: 989 WREG32(DC_HPD5_CONTROL, tmp); 990 break; 991 case RADEON_HPD_6: 992 WREG32(DC_HPD6_CONTROL, tmp); 993 break; 994 default: 995 break; 996 } 997 } else { 998 switch (radeon_connector->hpd.hpd) { 999 case RADEON_HPD_1: 1000 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN); 1001 break; 1002 case RADEON_HPD_2: 1003 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN); 1004 break; 1005 case RADEON_HPD_3: 1006 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN); 1007 break; 1008 default: 1009 break; 1010 } 1011 } 1012 enable |= 1 << radeon_connector->hpd.hpd; 1013 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); 1014 } 1015 radeon_irq_kms_enable_hpd(rdev, enable); 1016 } 1017 1018 void r600_hpd_fini(struct radeon_device *rdev) 1019 { 1020 struct drm_device *dev = rdev->ddev; 1021 struct drm_connector *connector; 1022 unsigned disable = 0; 1023 1024 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 1025 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1026 if (ASIC_IS_DCE3(rdev)) { 1027 switch (radeon_connector->hpd.hpd) { 1028 case RADEON_HPD_1: 1029 WREG32(DC_HPD1_CONTROL, 0); 1030 break; 1031 case RADEON_HPD_2: 1032 WREG32(DC_HPD2_CONTROL, 0); 1033 break; 1034 case RADEON_HPD_3: 1035 WREG32(DC_HPD3_CONTROL, 0); 1036 break; 1037 case RADEON_HPD_4: 1038 WREG32(DC_HPD4_CONTROL, 0); 1039 break; 1040 /* DCE 3.2 */ 1041 case RADEON_HPD_5: 1042 WREG32(DC_HPD5_CONTROL, 0); 1043 break; 1044 case RADEON_HPD_6: 1045 WREG32(DC_HPD6_CONTROL, 0); 1046 break; 1047 default: 1048 break; 1049 } 1050 } else { 1051 switch (radeon_connector->hpd.hpd) { 1052 case RADEON_HPD_1: 1053 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0); 1054 break; 1055 case RADEON_HPD_2: 1056 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0); 1057 break; 1058 case RADEON_HPD_3: 1059 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0); 1060 break; 1061 default: 1062 break; 1063 } 1064 } 1065 disable |= 1 << radeon_connector->hpd.hpd; 1066 } 1067 radeon_irq_kms_disable_hpd(rdev, disable); 1068 } 1069 1070 #ifdef __NetBSD__ 1071 /* 1072 * XXX Can't use bus_space here because this is all mapped through the 1073 * radeon_bo abstraction. Can't assume we're x86 because this is 1074 * AMD/ATI Radeon, not Intel. 1075 */ 1076 1077 # define __iomem volatile 1078 # define readl fake_readl 1079 1080 static inline uint32_t 1081 fake_readl(const void __iomem *ptr) 1082 { 1083 uint32_t v; 1084 1085 v = *(const uint32_t __iomem *)ptr; 1086 membar_consumer(); 1087 1088 return v; 1089 } 1090 #endif 1091 1092 /* 1093 * R600 PCIE GART 1094 */ 1095 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev) 1096 { 1097 unsigned i; 1098 u32 tmp; 1099 1100 /* flush hdp cache so updates hit vram */ 1101 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) && 1102 !(rdev->flags & RADEON_IS_AGP)) { 1103 void __iomem *ptr = rdev->gart.ptr; 1104 1105 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read 1106 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL 1107 * This seems to cause problems on some AGP cards. Just use the old 1108 * method for them. 1109 */ 1110 WREG32(HDP_DEBUG1, 0); 1111 (void)readl(ptr); 1112 } else 1113 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); 1114 1115 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12); 1116 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12); 1117 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1)); 1118 for (i = 0; i < rdev->usec_timeout; i++) { 1119 /* read MC_STATUS */ 1120 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE); 1121 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT; 1122 if (tmp == 2) { 1123 printk(KERN_WARNING "[drm] r600 flush TLB failed\n"); 1124 return; 1125 } 1126 if (tmp) { 1127 return; 1128 } 1129 udelay(1); 1130 } 1131 } 1132 1133 #ifdef __NetBSD__ 1134 # undef __iomem 1135 # undef readl 1136 #endif 1137 1138 int r600_pcie_gart_init(struct radeon_device *rdev) 1139 { 1140 int r; 1141 1142 if (rdev->gart.robj) { 1143 WARN(1, "R600 PCIE GART already initialized\n"); 1144 return 0; 1145 } 1146 /* Initialize common gart structure */ 1147 r = radeon_gart_init(rdev); 1148 if (r) 1149 return r; 1150 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; 1151 return radeon_gart_table_vram_alloc(rdev); 1152 } 1153 1154 static int r600_pcie_gart_enable(struct radeon_device *rdev) 1155 { 1156 u32 tmp; 1157 int r, i; 1158 1159 if (rdev->gart.robj == NULL) { 1160 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); 1161 return -EINVAL; 1162 } 1163 r = radeon_gart_table_vram_pin(rdev); 1164 if (r) 1165 return r; 1166 1167 /* Setup L2 cache */ 1168 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | 1169 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 1170 EFFECTIVE_L2_QUEUE_SIZE(7)); 1171 WREG32(VM_L2_CNTL2, 0); 1172 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); 1173 /* Setup TLB control */ 1174 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | 1175 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 1176 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | 1177 ENABLE_WAIT_L2_QUERY; 1178 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); 1179 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); 1180 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING); 1181 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); 1182 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); 1183 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); 1184 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); 1185 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); 1186 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); 1187 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); 1188 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); 1189 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); 1190 WREG32(MC_VM_L1_TLB_MCB_RD_UVD_CNTL, tmp); 1191 WREG32(MC_VM_L1_TLB_MCB_WR_UVD_CNTL, tmp); 1192 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); 1193 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); 1194 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); 1195 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); 1196 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); 1197 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | 1198 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); 1199 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 1200 (u32)(rdev->dummy_page.addr >> 12)); 1201 for (i = 1; i < 7; i++) 1202 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 1203 1204 r600_pcie_gart_tlb_flush(rdev); 1205 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 1206 (unsigned)(rdev->mc.gtt_size >> 20), 1207 (unsigned long long)rdev->gart.table_addr); 1208 rdev->gart.ready = true; 1209 return 0; 1210 } 1211 1212 static void r600_pcie_gart_disable(struct radeon_device *rdev) 1213 { 1214 u32 tmp; 1215 int i; 1216 1217 /* Disable all tables */ 1218 for (i = 0; i < 7; i++) 1219 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 1220 1221 /* Disable L2 cache */ 1222 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | 1223 EFFECTIVE_L2_QUEUE_SIZE(7)); 1224 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); 1225 /* Setup L1 TLB control */ 1226 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | 1227 ENABLE_WAIT_L2_QUERY; 1228 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); 1229 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); 1230 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); 1231 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); 1232 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); 1233 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); 1234 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); 1235 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); 1236 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp); 1237 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp); 1238 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); 1239 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); 1240 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp); 1241 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); 1242 WREG32(MC_VM_L1_TLB_MCB_RD_UVD_CNTL, tmp); 1243 WREG32(MC_VM_L1_TLB_MCB_WR_UVD_CNTL, tmp); 1244 radeon_gart_table_vram_unpin(rdev); 1245 } 1246 1247 static void r600_pcie_gart_fini(struct radeon_device *rdev) 1248 { 1249 radeon_gart_fini(rdev); 1250 r600_pcie_gart_disable(rdev); 1251 radeon_gart_table_vram_free(rdev); 1252 } 1253 1254 static void r600_agp_enable(struct radeon_device *rdev) 1255 { 1256 u32 tmp; 1257 int i; 1258 1259 /* Setup L2 cache */ 1260 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | 1261 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 1262 EFFECTIVE_L2_QUEUE_SIZE(7)); 1263 WREG32(VM_L2_CNTL2, 0); 1264 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); 1265 /* Setup TLB control */ 1266 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | 1267 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 1268 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | 1269 ENABLE_WAIT_L2_QUERY; 1270 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); 1271 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); 1272 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING); 1273 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); 1274 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); 1275 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); 1276 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); 1277 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); 1278 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); 1279 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); 1280 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); 1281 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); 1282 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); 1283 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); 1284 for (i = 0; i < 7; i++) 1285 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 1286 } 1287 1288 int r600_mc_wait_for_idle(struct radeon_device *rdev) 1289 { 1290 unsigned i; 1291 u32 tmp; 1292 1293 for (i = 0; i < rdev->usec_timeout; i++) { 1294 /* read MC_STATUS */ 1295 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00; 1296 if (!tmp) 1297 return 0; 1298 udelay(1); 1299 } 1300 return -1; 1301 } 1302 1303 uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg) 1304 { 1305 unsigned long flags; 1306 uint32_t r; 1307 1308 spin_lock_irqsave(&rdev->mc_idx_lock, flags); 1309 WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg)); 1310 r = RREG32(R_0028FC_MC_DATA); 1311 WREG32(R_0028F8_MC_INDEX, ~C_0028F8_MC_IND_ADDR); 1312 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); 1313 return r; 1314 } 1315 1316 void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 1317 { 1318 unsigned long flags; 1319 1320 spin_lock_irqsave(&rdev->mc_idx_lock, flags); 1321 WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg) | 1322 S_0028F8_MC_IND_WR_EN(1)); 1323 WREG32(R_0028FC_MC_DATA, v); 1324 WREG32(R_0028F8_MC_INDEX, 0x7F); 1325 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); 1326 } 1327 1328 static void r600_mc_program(struct radeon_device *rdev) 1329 { 1330 struct rv515_mc_save save; 1331 u32 tmp; 1332 int i, j; 1333 1334 /* Initialize HDP */ 1335 for (i = 0, j = 0; i < 32; i++, j += 0x18) { 1336 WREG32((0x2c14 + j), 0x00000000); 1337 WREG32((0x2c18 + j), 0x00000000); 1338 WREG32((0x2c1c + j), 0x00000000); 1339 WREG32((0x2c20 + j), 0x00000000); 1340 WREG32((0x2c24 + j), 0x00000000); 1341 } 1342 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0); 1343 1344 rv515_mc_stop(rdev, &save); 1345 if (r600_mc_wait_for_idle(rdev)) { 1346 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1347 } 1348 /* Lockout access through VGA aperture (doesn't exist before R600) */ 1349 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); 1350 /* Update configuration */ 1351 if (rdev->flags & RADEON_IS_AGP) { 1352 if (rdev->mc.vram_start < rdev->mc.gtt_start) { 1353 /* VRAM before AGP */ 1354 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 1355 rdev->mc.vram_start >> 12); 1356 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 1357 rdev->mc.gtt_end >> 12); 1358 } else { 1359 /* VRAM after AGP */ 1360 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 1361 rdev->mc.gtt_start >> 12); 1362 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 1363 rdev->mc.vram_end >> 12); 1364 } 1365 } else { 1366 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12); 1367 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12); 1368 } 1369 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12); 1370 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; 1371 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); 1372 WREG32(MC_VM_FB_LOCATION, tmp); 1373 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); 1374 WREG32(HDP_NONSURFACE_INFO, (2 << 7)); 1375 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF); 1376 if (rdev->flags & RADEON_IS_AGP) { 1377 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22); 1378 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22); 1379 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); 1380 } else { 1381 WREG32(MC_VM_AGP_BASE, 0); 1382 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); 1383 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); 1384 } 1385 if (r600_mc_wait_for_idle(rdev)) { 1386 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1387 } 1388 rv515_mc_resume(rdev, &save); 1389 /* we need to own VRAM, so turn off the VGA renderer here 1390 * to stop it overwriting our objects */ 1391 rv515_vga_render_disable(rdev); 1392 } 1393 1394 /** 1395 * r600_vram_gtt_location - try to find VRAM & GTT location 1396 * @rdev: radeon device structure holding all necessary informations 1397 * @mc: memory controller structure holding memory informations 1398 * 1399 * Function will place try to place VRAM at same place as in CPU (PCI) 1400 * address space as some GPU seems to have issue when we reprogram at 1401 * different address space. 1402 * 1403 * If there is not enough space to fit the unvisible VRAM after the 1404 * aperture then we limit the VRAM size to the aperture. 1405 * 1406 * If we are using AGP then place VRAM adjacent to AGP aperture are we need 1407 * them to be in one from GPU point of view so that we can program GPU to 1408 * catch access outside them (weird GPU policy see ??). 1409 * 1410 * This function will never fails, worst case are limiting VRAM or GTT. 1411 * 1412 * Note: GTT start, end, size should be initialized before calling this 1413 * function on AGP platform. 1414 */ 1415 static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) 1416 { 1417 u64 size_bf, size_af; 1418 1419 if (mc->mc_vram_size > 0xE0000000) { 1420 /* leave room for at least 512M GTT */ 1421 dev_warn(rdev->dev, "limiting VRAM\n"); 1422 mc->real_vram_size = 0xE0000000; 1423 mc->mc_vram_size = 0xE0000000; 1424 } 1425 if (rdev->flags & RADEON_IS_AGP) { 1426 size_bf = mc->gtt_start; 1427 size_af = mc->mc_mask - mc->gtt_end; 1428 if (size_bf > size_af) { 1429 if (mc->mc_vram_size > size_bf) { 1430 dev_warn(rdev->dev, "limiting VRAM\n"); 1431 mc->real_vram_size = size_bf; 1432 mc->mc_vram_size = size_bf; 1433 } 1434 mc->vram_start = mc->gtt_start - mc->mc_vram_size; 1435 } else { 1436 if (mc->mc_vram_size > size_af) { 1437 dev_warn(rdev->dev, "limiting VRAM\n"); 1438 mc->real_vram_size = size_af; 1439 mc->mc_vram_size = size_af; 1440 } 1441 mc->vram_start = mc->gtt_end + 1; 1442 } 1443 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; 1444 dev_info(rdev->dev, "VRAM: %"PRIu64"M 0x%08"PRIX64" - 0x%08"PRIX64" (%"PRIu64"M used)\n", 1445 mc->mc_vram_size >> 20, mc->vram_start, 1446 mc->vram_end, mc->real_vram_size >> 20); 1447 } else { 1448 u64 base = 0; 1449 if (rdev->flags & RADEON_IS_IGP) { 1450 base = RREG32(MC_VM_FB_LOCATION) & 0xFFFF; 1451 base <<= 24; 1452 } 1453 radeon_vram_location(rdev, &rdev->mc, base); 1454 rdev->mc.gtt_base_align = 0; 1455 radeon_gtt_location(rdev, mc); 1456 } 1457 } 1458 1459 static int r600_mc_init(struct radeon_device *rdev) 1460 { 1461 u32 tmp; 1462 int chansize, numchan; 1463 uint32_t h_addr, l_addr; 1464 unsigned long long k8_addr; 1465 1466 /* Get VRAM informations */ 1467 rdev->mc.vram_is_ddr = true; 1468 tmp = RREG32(RAMCFG); 1469 if (tmp & CHANSIZE_OVERRIDE) { 1470 chansize = 16; 1471 } else if (tmp & CHANSIZE_MASK) { 1472 chansize = 64; 1473 } else { 1474 chansize = 32; 1475 } 1476 tmp = RREG32(CHMAP); 1477 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { 1478 case 0: 1479 default: 1480 numchan = 1; 1481 break; 1482 case 1: 1483 numchan = 2; 1484 break; 1485 case 2: 1486 numchan = 4; 1487 break; 1488 case 3: 1489 numchan = 8; 1490 break; 1491 } 1492 rdev->mc.vram_width = numchan * chansize; 1493 /* Could aper size report 0 ? */ 1494 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); 1495 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); 1496 /* Setup GPU memory space */ 1497 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); 1498 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); 1499 rdev->mc.visible_vram_size = rdev->mc.aper_size; 1500 r600_vram_gtt_location(rdev, &rdev->mc); 1501 1502 if (rdev->flags & RADEON_IS_IGP) { 1503 rs690_pm_info(rdev); 1504 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); 1505 1506 if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) { 1507 /* Use K8 direct mapping for fast fb access. */ 1508 rdev->fastfb_working = false; 1509 h_addr = G_000012_K8_ADDR_EXT(RREG32_MC(R_000012_MC_MISC_UMA_CNTL)); 1510 l_addr = RREG32_MC(R_000011_K8_FB_LOCATION); 1511 k8_addr = ((unsigned long long)h_addr) << 32 | l_addr; 1512 #if defined(CONFIG_X86_32) && !defined(CONFIG_X86_PAE) 1513 if (k8_addr + rdev->mc.visible_vram_size < 0x100000000ULL) 1514 #endif 1515 { 1516 /* FastFB shall be used with UMA memory. Here it is simply disabled when sideport 1517 * memory is present. 1518 */ 1519 if (rdev->mc.igp_sideport_enabled == false && radeon_fastfb == 1) { 1520 DRM_INFO("Direct mapping: aper base at 0x%llx, replaced by direct mapping base 0x%llx.\n", 1521 (unsigned long long)rdev->mc.aper_base, k8_addr); 1522 rdev->mc.aper_base = (resource_size_t)k8_addr; 1523 rdev->fastfb_working = true; 1524 } 1525 } 1526 } 1527 } 1528 1529 radeon_update_bandwidth_info(rdev); 1530 return 0; 1531 } 1532 1533 int r600_vram_scratch_init(struct radeon_device *rdev) 1534 { 1535 int r; 1536 1537 if (rdev->vram_scratch.robj == NULL) { 1538 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, 1539 PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM, 1540 0, NULL, NULL, &rdev->vram_scratch.robj); 1541 if (r) { 1542 return r; 1543 } 1544 } 1545 1546 r = radeon_bo_reserve(rdev->vram_scratch.robj, false); 1547 if (unlikely(r != 0)) 1548 return r; 1549 r = radeon_bo_pin(rdev->vram_scratch.robj, 1550 RADEON_GEM_DOMAIN_VRAM, &rdev->vram_scratch.gpu_addr); 1551 if (r) { 1552 radeon_bo_unreserve(rdev->vram_scratch.robj); 1553 return r; 1554 } 1555 r = radeon_bo_kmap(rdev->vram_scratch.robj, 1556 (void **)__UNVOLATILE(&rdev->vram_scratch.ptr)); 1557 if (r) 1558 radeon_bo_unpin(rdev->vram_scratch.robj); 1559 radeon_bo_unreserve(rdev->vram_scratch.robj); 1560 1561 return r; 1562 } 1563 1564 void r600_vram_scratch_fini(struct radeon_device *rdev) 1565 { 1566 int r; 1567 1568 if (rdev->vram_scratch.robj == NULL) { 1569 return; 1570 } 1571 r = radeon_bo_reserve(rdev->vram_scratch.robj, false); 1572 if (likely(r == 0)) { 1573 radeon_bo_kunmap(rdev->vram_scratch.robj); 1574 radeon_bo_unpin(rdev->vram_scratch.robj); 1575 radeon_bo_unreserve(rdev->vram_scratch.robj); 1576 } 1577 radeon_bo_unref(&rdev->vram_scratch.robj); 1578 } 1579 1580 void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung) 1581 { 1582 u32 tmp = RREG32(R600_BIOS_3_SCRATCH); 1583 1584 if (hung) 1585 tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG; 1586 else 1587 tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG; 1588 1589 WREG32(R600_BIOS_3_SCRATCH, tmp); 1590 } 1591 1592 static void r600_print_gpu_status_regs(struct radeon_device *rdev) 1593 { 1594 dev_info(rdev->dev, " R_008010_GRBM_STATUS = 0x%08X\n", 1595 RREG32(R_008010_GRBM_STATUS)); 1596 dev_info(rdev->dev, " R_008014_GRBM_STATUS2 = 0x%08X\n", 1597 RREG32(R_008014_GRBM_STATUS2)); 1598 dev_info(rdev->dev, " R_000E50_SRBM_STATUS = 0x%08X\n", 1599 RREG32(R_000E50_SRBM_STATUS)); 1600 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n", 1601 RREG32(CP_STALLED_STAT1)); 1602 dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n", 1603 RREG32(CP_STALLED_STAT2)); 1604 dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n", 1605 RREG32(CP_BUSY_STAT)); 1606 dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n", 1607 RREG32(CP_STAT)); 1608 dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n", 1609 RREG32(DMA_STATUS_REG)); 1610 } 1611 1612 static bool r600_is_display_hung(struct radeon_device *rdev) 1613 { 1614 u32 crtc_hung = 0; 1615 u32 crtc_status[2]; 1616 u32 i, j, tmp; 1617 1618 for (i = 0; i < rdev->num_crtc; i++) { 1619 if (RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN) { 1620 crtc_status[i] = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]); 1621 crtc_hung |= (1 << i); 1622 } 1623 } 1624 1625 for (j = 0; j < 10; j++) { 1626 for (i = 0; i < rdev->num_crtc; i++) { 1627 if (crtc_hung & (1 << i)) { 1628 tmp = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]); 1629 if (tmp != crtc_status[i]) 1630 crtc_hung &= ~(1 << i); 1631 } 1632 } 1633 if (crtc_hung == 0) 1634 return false; 1635 udelay(100); 1636 } 1637 1638 return true; 1639 } 1640 1641 u32 r600_gpu_check_soft_reset(struct radeon_device *rdev) 1642 { 1643 u32 reset_mask = 0; 1644 u32 tmp; 1645 1646 /* GRBM_STATUS */ 1647 tmp = RREG32(R_008010_GRBM_STATUS); 1648 if (rdev->family >= CHIP_RV770) { 1649 if (G_008010_PA_BUSY(tmp) | G_008010_SC_BUSY(tmp) | 1650 G_008010_SH_BUSY(tmp) | G_008010_SX_BUSY(tmp) | 1651 G_008010_TA_BUSY(tmp) | G_008010_VGT_BUSY(tmp) | 1652 G_008010_DB03_BUSY(tmp) | G_008010_CB03_BUSY(tmp) | 1653 G_008010_SPI03_BUSY(tmp) | G_008010_VGT_BUSY_NO_DMA(tmp)) 1654 reset_mask |= RADEON_RESET_GFX; 1655 } else { 1656 if (G_008010_PA_BUSY(tmp) | G_008010_SC_BUSY(tmp) | 1657 G_008010_SH_BUSY(tmp) | G_008010_SX_BUSY(tmp) | 1658 G_008010_TA03_BUSY(tmp) | G_008010_VGT_BUSY(tmp) | 1659 G_008010_DB03_BUSY(tmp) | G_008010_CB03_BUSY(tmp) | 1660 G_008010_SPI03_BUSY(tmp) | G_008010_VGT_BUSY_NO_DMA(tmp)) 1661 reset_mask |= RADEON_RESET_GFX; 1662 } 1663 1664 if (G_008010_CF_RQ_PENDING(tmp) | G_008010_PF_RQ_PENDING(tmp) | 1665 G_008010_CP_BUSY(tmp) | G_008010_CP_COHERENCY_BUSY(tmp)) 1666 reset_mask |= RADEON_RESET_CP; 1667 1668 if (G_008010_GRBM_EE_BUSY(tmp)) 1669 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP; 1670 1671 /* DMA_STATUS_REG */ 1672 tmp = RREG32(DMA_STATUS_REG); 1673 if (!(tmp & DMA_IDLE)) 1674 reset_mask |= RADEON_RESET_DMA; 1675 1676 /* SRBM_STATUS */ 1677 tmp = RREG32(R_000E50_SRBM_STATUS); 1678 if (G_000E50_RLC_RQ_PENDING(tmp) | G_000E50_RLC_BUSY(tmp)) 1679 reset_mask |= RADEON_RESET_RLC; 1680 1681 if (G_000E50_IH_BUSY(tmp)) 1682 reset_mask |= RADEON_RESET_IH; 1683 1684 if (G_000E50_SEM_BUSY(tmp)) 1685 reset_mask |= RADEON_RESET_SEM; 1686 1687 if (G_000E50_GRBM_RQ_PENDING(tmp)) 1688 reset_mask |= RADEON_RESET_GRBM; 1689 1690 if (G_000E50_VMC_BUSY(tmp)) 1691 reset_mask |= RADEON_RESET_VMC; 1692 1693 if (G_000E50_MCB_BUSY(tmp) | G_000E50_MCDZ_BUSY(tmp) | 1694 G_000E50_MCDY_BUSY(tmp) | G_000E50_MCDX_BUSY(tmp) | 1695 G_000E50_MCDW_BUSY(tmp)) 1696 reset_mask |= RADEON_RESET_MC; 1697 1698 if (r600_is_display_hung(rdev)) 1699 reset_mask |= RADEON_RESET_DISPLAY; 1700 1701 /* Skip MC reset as it's mostly likely not hung, just busy */ 1702 if (reset_mask & RADEON_RESET_MC) { 1703 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask); 1704 reset_mask &= ~RADEON_RESET_MC; 1705 } 1706 1707 return reset_mask; 1708 } 1709 1710 static void r600_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask) 1711 { 1712 struct rv515_mc_save save; 1713 u32 grbm_soft_reset = 0, srbm_soft_reset = 0; 1714 u32 tmp; 1715 1716 if (reset_mask == 0) 1717 return; 1718 1719 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask); 1720 1721 r600_print_gpu_status_regs(rdev); 1722 1723 /* Disable CP parsing/prefetching */ 1724 if (rdev->family >= CHIP_RV770) 1725 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1) | S_0086D8_CP_PFP_HALT(1)); 1726 else 1727 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); 1728 1729 /* disable the RLC */ 1730 WREG32(RLC_CNTL, 0); 1731 1732 if (reset_mask & RADEON_RESET_DMA) { 1733 /* Disable DMA */ 1734 tmp = RREG32(DMA_RB_CNTL); 1735 tmp &= ~DMA_RB_ENABLE; 1736 WREG32(DMA_RB_CNTL, tmp); 1737 } 1738 1739 mdelay(50); 1740 1741 rv515_mc_stop(rdev, &save); 1742 if (r600_mc_wait_for_idle(rdev)) { 1743 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1744 } 1745 1746 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) { 1747 if (rdev->family >= CHIP_RV770) 1748 grbm_soft_reset |= S_008020_SOFT_RESET_DB(1) | 1749 S_008020_SOFT_RESET_CB(1) | 1750 S_008020_SOFT_RESET_PA(1) | 1751 S_008020_SOFT_RESET_SC(1) | 1752 S_008020_SOFT_RESET_SPI(1) | 1753 S_008020_SOFT_RESET_SX(1) | 1754 S_008020_SOFT_RESET_SH(1) | 1755 S_008020_SOFT_RESET_TC(1) | 1756 S_008020_SOFT_RESET_TA(1) | 1757 S_008020_SOFT_RESET_VC(1) | 1758 S_008020_SOFT_RESET_VGT(1); 1759 else 1760 grbm_soft_reset |= S_008020_SOFT_RESET_CR(1) | 1761 S_008020_SOFT_RESET_DB(1) | 1762 S_008020_SOFT_RESET_CB(1) | 1763 S_008020_SOFT_RESET_PA(1) | 1764 S_008020_SOFT_RESET_SC(1) | 1765 S_008020_SOFT_RESET_SMX(1) | 1766 S_008020_SOFT_RESET_SPI(1) | 1767 S_008020_SOFT_RESET_SX(1) | 1768 S_008020_SOFT_RESET_SH(1) | 1769 S_008020_SOFT_RESET_TC(1) | 1770 S_008020_SOFT_RESET_TA(1) | 1771 S_008020_SOFT_RESET_VC(1) | 1772 S_008020_SOFT_RESET_VGT(1); 1773 } 1774 1775 if (reset_mask & RADEON_RESET_CP) { 1776 grbm_soft_reset |= S_008020_SOFT_RESET_CP(1) | 1777 S_008020_SOFT_RESET_VGT(1); 1778 1779 srbm_soft_reset |= S_000E60_SOFT_RESET_GRBM(1); 1780 } 1781 1782 if (reset_mask & RADEON_RESET_DMA) { 1783 if (rdev->family >= CHIP_RV770) 1784 srbm_soft_reset |= RV770_SOFT_RESET_DMA; 1785 else 1786 srbm_soft_reset |= SOFT_RESET_DMA; 1787 } 1788 1789 if (reset_mask & RADEON_RESET_RLC) 1790 srbm_soft_reset |= S_000E60_SOFT_RESET_RLC(1); 1791 1792 if (reset_mask & RADEON_RESET_SEM) 1793 srbm_soft_reset |= S_000E60_SOFT_RESET_SEM(1); 1794 1795 if (reset_mask & RADEON_RESET_IH) 1796 srbm_soft_reset |= S_000E60_SOFT_RESET_IH(1); 1797 1798 if (reset_mask & RADEON_RESET_GRBM) 1799 srbm_soft_reset |= S_000E60_SOFT_RESET_GRBM(1); 1800 1801 if (!(rdev->flags & RADEON_IS_IGP)) { 1802 if (reset_mask & RADEON_RESET_MC) 1803 srbm_soft_reset |= S_000E60_SOFT_RESET_MC(1); 1804 } 1805 1806 if (reset_mask & RADEON_RESET_VMC) 1807 srbm_soft_reset |= S_000E60_SOFT_RESET_VMC(1); 1808 1809 if (grbm_soft_reset) { 1810 tmp = RREG32(R_008020_GRBM_SOFT_RESET); 1811 tmp |= grbm_soft_reset; 1812 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp); 1813 WREG32(R_008020_GRBM_SOFT_RESET, tmp); 1814 tmp = RREG32(R_008020_GRBM_SOFT_RESET); 1815 1816 udelay(50); 1817 1818 tmp &= ~grbm_soft_reset; 1819 WREG32(R_008020_GRBM_SOFT_RESET, tmp); 1820 tmp = RREG32(R_008020_GRBM_SOFT_RESET); 1821 } 1822 1823 if (srbm_soft_reset) { 1824 tmp = RREG32(SRBM_SOFT_RESET); 1825 tmp |= srbm_soft_reset; 1826 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1827 WREG32(SRBM_SOFT_RESET, tmp); 1828 tmp = RREG32(SRBM_SOFT_RESET); 1829 1830 udelay(50); 1831 1832 tmp &= ~srbm_soft_reset; 1833 WREG32(SRBM_SOFT_RESET, tmp); 1834 tmp = RREG32(SRBM_SOFT_RESET); 1835 } 1836 1837 /* Wait a little for things to settle down */ 1838 mdelay(1); 1839 1840 rv515_mc_resume(rdev, &save); 1841 udelay(50); 1842 1843 r600_print_gpu_status_regs(rdev); 1844 } 1845 1846 static void r600_gpu_pci_config_reset(struct radeon_device *rdev) 1847 { 1848 struct rv515_mc_save save; 1849 u32 tmp, i; 1850 1851 dev_info(rdev->dev, "GPU pci config reset\n"); 1852 1853 /* disable dpm? */ 1854 1855 /* Disable CP parsing/prefetching */ 1856 if (rdev->family >= CHIP_RV770) 1857 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1) | S_0086D8_CP_PFP_HALT(1)); 1858 else 1859 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); 1860 1861 /* disable the RLC */ 1862 WREG32(RLC_CNTL, 0); 1863 1864 /* Disable DMA */ 1865 tmp = RREG32(DMA_RB_CNTL); 1866 tmp &= ~DMA_RB_ENABLE; 1867 WREG32(DMA_RB_CNTL, tmp); 1868 1869 mdelay(50); 1870 1871 /* set mclk/sclk to bypass */ 1872 if (rdev->family >= CHIP_RV770) 1873 rv770_set_clk_bypass_mode(rdev); 1874 /* disable BM */ 1875 pci_clear_master(rdev->pdev); 1876 /* disable mem access */ 1877 rv515_mc_stop(rdev, &save); 1878 if (r600_mc_wait_for_idle(rdev)) { 1879 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1880 } 1881 1882 /* BIF reset workaround. Not sure if this is needed on 6xx */ 1883 tmp = RREG32(BUS_CNTL); 1884 tmp |= VGA_COHE_SPEC_TIMER_DIS; 1885 WREG32(BUS_CNTL, tmp); 1886 1887 tmp = RREG32(BIF_SCRATCH0); 1888 1889 /* reset */ 1890 radeon_pci_config_reset(rdev); 1891 mdelay(1); 1892 1893 /* BIF reset workaround. Not sure if this is needed on 6xx */ 1894 tmp = SOFT_RESET_BIF; 1895 WREG32(SRBM_SOFT_RESET, tmp); 1896 mdelay(1); 1897 WREG32(SRBM_SOFT_RESET, 0); 1898 1899 /* wait for asic to come out of reset */ 1900 for (i = 0; i < rdev->usec_timeout; i++) { 1901 if (RREG32(CONFIG_MEMSIZE) != 0xffffffff) 1902 break; 1903 udelay(1); 1904 } 1905 } 1906 1907 int r600_asic_reset(struct radeon_device *rdev) 1908 { 1909 u32 reset_mask; 1910 1911 reset_mask = r600_gpu_check_soft_reset(rdev); 1912 1913 if (reset_mask) 1914 r600_set_bios_scratch_engine_hung(rdev, true); 1915 1916 /* try soft reset */ 1917 r600_gpu_soft_reset(rdev, reset_mask); 1918 1919 reset_mask = r600_gpu_check_soft_reset(rdev); 1920 1921 /* try pci config reset */ 1922 if (reset_mask && radeon_hard_reset) 1923 r600_gpu_pci_config_reset(rdev); 1924 1925 reset_mask = r600_gpu_check_soft_reset(rdev); 1926 1927 if (!reset_mask) 1928 r600_set_bios_scratch_engine_hung(rdev, false); 1929 1930 return 0; 1931 } 1932 1933 /** 1934 * r600_gfx_is_lockup - Check if the GFX engine is locked up 1935 * 1936 * @rdev: radeon_device pointer 1937 * @ring: radeon_ring structure holding ring information 1938 * 1939 * Check if the GFX engine is locked up. 1940 * Returns true if the engine appears to be locked up, false if not. 1941 */ 1942 bool r600_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) 1943 { 1944 u32 reset_mask = r600_gpu_check_soft_reset(rdev); 1945 1946 if (!(reset_mask & (RADEON_RESET_GFX | 1947 RADEON_RESET_COMPUTE | 1948 RADEON_RESET_CP))) { 1949 radeon_ring_lockup_update(rdev, ring); 1950 return false; 1951 } 1952 return radeon_ring_test_lockup(rdev, ring); 1953 } 1954 1955 u32 r6xx_remap_render_backend(struct radeon_device *rdev, 1956 u32 tiling_pipe_num, 1957 u32 max_rb_num, 1958 u32 total_max_rb_num, 1959 u32 disabled_rb_mask) 1960 { 1961 u32 rendering_pipe_num, rb_num_width, req_rb_num; 1962 u32 pipe_rb_ratio, pipe_rb_remain, tmp; 1963 u32 data = 0, mask = 1 << (max_rb_num - 1); 1964 unsigned i, j; 1965 1966 /* mask out the RBs that don't exist on that asic */ 1967 tmp = disabled_rb_mask | ((0xff << max_rb_num) & 0xff); 1968 /* make sure at least one RB is available */ 1969 if ((tmp & 0xff) != 0xff) 1970 disabled_rb_mask = tmp; 1971 1972 rendering_pipe_num = 1 << tiling_pipe_num; 1973 req_rb_num = total_max_rb_num - r600_count_pipe_bits(disabled_rb_mask); 1974 BUG_ON(rendering_pipe_num < req_rb_num); 1975 1976 pipe_rb_ratio = rendering_pipe_num / req_rb_num; 1977 pipe_rb_remain = rendering_pipe_num - pipe_rb_ratio * req_rb_num; 1978 1979 if (rdev->family <= CHIP_RV740) { 1980 /* r6xx/r7xx */ 1981 rb_num_width = 2; 1982 } else { 1983 /* eg+ */ 1984 rb_num_width = 4; 1985 } 1986 1987 for (i = 0; i < max_rb_num; i++) { 1988 if (!(mask & disabled_rb_mask)) { 1989 for (j = 0; j < pipe_rb_ratio; j++) { 1990 data <<= rb_num_width; 1991 data |= max_rb_num - i - 1; 1992 } 1993 if (pipe_rb_remain) { 1994 data <<= rb_num_width; 1995 data |= max_rb_num - i - 1; 1996 pipe_rb_remain--; 1997 } 1998 } 1999 mask >>= 1; 2000 } 2001 2002 return data; 2003 } 2004 2005 int r600_count_pipe_bits(uint32_t val) 2006 { 2007 return hweight32(val); 2008 } 2009 2010 static void r600_gpu_init(struct radeon_device *rdev) 2011 { 2012 u32 tiling_config; 2013 u32 ramcfg; 2014 u32 cc_gc_shader_pipe_config; 2015 u32 tmp; 2016 int i, j; 2017 u32 sq_config; 2018 u32 sq_gpr_resource_mgmt_1 = 0; 2019 u32 sq_gpr_resource_mgmt_2 = 0; 2020 u32 sq_thread_resource_mgmt = 0; 2021 u32 sq_stack_resource_mgmt_1 = 0; 2022 u32 sq_stack_resource_mgmt_2 = 0; 2023 u32 disabled_rb_mask; 2024 2025 rdev->config.r600.tiling_group_size = 256; 2026 switch (rdev->family) { 2027 case CHIP_R600: 2028 rdev->config.r600.max_pipes = 4; 2029 rdev->config.r600.max_tile_pipes = 8; 2030 rdev->config.r600.max_simds = 4; 2031 rdev->config.r600.max_backends = 4; 2032 rdev->config.r600.max_gprs = 256; 2033 rdev->config.r600.max_threads = 192; 2034 rdev->config.r600.max_stack_entries = 256; 2035 rdev->config.r600.max_hw_contexts = 8; 2036 rdev->config.r600.max_gs_threads = 16; 2037 rdev->config.r600.sx_max_export_size = 128; 2038 rdev->config.r600.sx_max_export_pos_size = 16; 2039 rdev->config.r600.sx_max_export_smx_size = 128; 2040 rdev->config.r600.sq_num_cf_insts = 2; 2041 break; 2042 case CHIP_RV630: 2043 case CHIP_RV635: 2044 rdev->config.r600.max_pipes = 2; 2045 rdev->config.r600.max_tile_pipes = 2; 2046 rdev->config.r600.max_simds = 3; 2047 rdev->config.r600.max_backends = 1; 2048 rdev->config.r600.max_gprs = 128; 2049 rdev->config.r600.max_threads = 192; 2050 rdev->config.r600.max_stack_entries = 128; 2051 rdev->config.r600.max_hw_contexts = 8; 2052 rdev->config.r600.max_gs_threads = 4; 2053 rdev->config.r600.sx_max_export_size = 128; 2054 rdev->config.r600.sx_max_export_pos_size = 16; 2055 rdev->config.r600.sx_max_export_smx_size = 128; 2056 rdev->config.r600.sq_num_cf_insts = 2; 2057 break; 2058 case CHIP_RV610: 2059 case CHIP_RV620: 2060 case CHIP_RS780: 2061 case CHIP_RS880: 2062 rdev->config.r600.max_pipes = 1; 2063 rdev->config.r600.max_tile_pipes = 1; 2064 rdev->config.r600.max_simds = 2; 2065 rdev->config.r600.max_backends = 1; 2066 rdev->config.r600.max_gprs = 128; 2067 rdev->config.r600.max_threads = 192; 2068 rdev->config.r600.max_stack_entries = 128; 2069 rdev->config.r600.max_hw_contexts = 4; 2070 rdev->config.r600.max_gs_threads = 4; 2071 rdev->config.r600.sx_max_export_size = 128; 2072 rdev->config.r600.sx_max_export_pos_size = 16; 2073 rdev->config.r600.sx_max_export_smx_size = 128; 2074 rdev->config.r600.sq_num_cf_insts = 1; 2075 break; 2076 case CHIP_RV670: 2077 rdev->config.r600.max_pipes = 4; 2078 rdev->config.r600.max_tile_pipes = 4; 2079 rdev->config.r600.max_simds = 4; 2080 rdev->config.r600.max_backends = 4; 2081 rdev->config.r600.max_gprs = 192; 2082 rdev->config.r600.max_threads = 192; 2083 rdev->config.r600.max_stack_entries = 256; 2084 rdev->config.r600.max_hw_contexts = 8; 2085 rdev->config.r600.max_gs_threads = 16; 2086 rdev->config.r600.sx_max_export_size = 128; 2087 rdev->config.r600.sx_max_export_pos_size = 16; 2088 rdev->config.r600.sx_max_export_smx_size = 128; 2089 rdev->config.r600.sq_num_cf_insts = 2; 2090 break; 2091 default: 2092 break; 2093 } 2094 2095 /* Initialize HDP */ 2096 for (i = 0, j = 0; i < 32; i++, j += 0x18) { 2097 WREG32((0x2c14 + j), 0x00000000); 2098 WREG32((0x2c18 + j), 0x00000000); 2099 WREG32((0x2c1c + j), 0x00000000); 2100 WREG32((0x2c20 + j), 0x00000000); 2101 WREG32((0x2c24 + j), 0x00000000); 2102 } 2103 2104 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); 2105 2106 /* Setup tiling */ 2107 tiling_config = 0; 2108 ramcfg = RREG32(RAMCFG); 2109 switch (rdev->config.r600.max_tile_pipes) { 2110 case 1: 2111 tiling_config |= PIPE_TILING(0); 2112 break; 2113 case 2: 2114 tiling_config |= PIPE_TILING(1); 2115 break; 2116 case 4: 2117 tiling_config |= PIPE_TILING(2); 2118 break; 2119 case 8: 2120 tiling_config |= PIPE_TILING(3); 2121 break; 2122 default: 2123 break; 2124 } 2125 rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes; 2126 rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); 2127 tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); 2128 tiling_config |= GROUP_SIZE((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT); 2129 2130 tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT; 2131 if (tmp > 3) { 2132 tiling_config |= ROW_TILING(3); 2133 tiling_config |= SAMPLE_SPLIT(3); 2134 } else { 2135 tiling_config |= ROW_TILING(tmp); 2136 tiling_config |= SAMPLE_SPLIT(tmp); 2137 } 2138 tiling_config |= BANK_SWAPS(1); 2139 2140 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0x00ffff00; 2141 tmp = rdev->config.r600.max_simds - 2142 r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R6XX_MAX_SIMDS_MASK); 2143 rdev->config.r600.active_simds = tmp; 2144 2145 disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R6XX_MAX_BACKENDS_MASK; 2146 tmp = 0; 2147 for (i = 0; i < rdev->config.r600.max_backends; i++) 2148 tmp |= (1 << i); 2149 /* if all the backends are disabled, fix it up here */ 2150 if ((disabled_rb_mask & tmp) == tmp) { 2151 for (i = 0; i < rdev->config.r600.max_backends; i++) 2152 disabled_rb_mask &= ~(1 << i); 2153 } 2154 tmp = (tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT; 2155 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.r600.max_backends, 2156 R6XX_MAX_BACKENDS, disabled_rb_mask); 2157 tiling_config |= tmp << 16; 2158 rdev->config.r600.backend_map = tmp; 2159 2160 rdev->config.r600.tile_config = tiling_config; 2161 WREG32(GB_TILING_CONFIG, tiling_config); 2162 WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff); 2163 WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff); 2164 WREG32(DMA_TILING_CONFIG, tiling_config & 0xffff); 2165 2166 tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8); 2167 WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK); 2168 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK); 2169 2170 /* Setup some CP states */ 2171 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b))); 2172 WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40))); 2173 2174 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT | 2175 SYNC_WALKER | SYNC_ALIGNER)); 2176 /* Setup various GPU states */ 2177 if (rdev->family == CHIP_RV670) 2178 WREG32(ARB_GDEC_RD_CNTL, 0x00000021); 2179 2180 tmp = RREG32(SX_DEBUG_1); 2181 tmp |= SMX_EVENT_RELEASE; 2182 if ((rdev->family > CHIP_R600)) 2183 tmp |= ENABLE_NEW_SMX_ADDRESS; 2184 WREG32(SX_DEBUG_1, tmp); 2185 2186 if (((rdev->family) == CHIP_R600) || 2187 ((rdev->family) == CHIP_RV630) || 2188 ((rdev->family) == CHIP_RV610) || 2189 ((rdev->family) == CHIP_RV620) || 2190 ((rdev->family) == CHIP_RS780) || 2191 ((rdev->family) == CHIP_RS880)) { 2192 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE); 2193 } else { 2194 WREG32(DB_DEBUG, 0); 2195 } 2196 WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) | 2197 DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4))); 2198 2199 WREG32(PA_SC_MULTI_CHIP_CNTL, 0); 2200 WREG32(VGT_NUM_INSTANCES, 0); 2201 2202 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0)); 2203 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0)); 2204 2205 tmp = RREG32(SQ_MS_FIFO_SIZES); 2206 if (((rdev->family) == CHIP_RV610) || 2207 ((rdev->family) == CHIP_RV620) || 2208 ((rdev->family) == CHIP_RS780) || 2209 ((rdev->family) == CHIP_RS880)) { 2210 tmp = (CACHE_FIFO_SIZE(0xa) | 2211 FETCH_FIFO_HIWATER(0xa) | 2212 DONE_FIFO_HIWATER(0xe0) | 2213 ALU_UPDATE_FIFO_HIWATER(0x8)); 2214 } else if (((rdev->family) == CHIP_R600) || 2215 ((rdev->family) == CHIP_RV630)) { 2216 tmp &= ~DONE_FIFO_HIWATER(0xff); 2217 tmp |= DONE_FIFO_HIWATER(0x4); 2218 } 2219 WREG32(SQ_MS_FIFO_SIZES, tmp); 2220 2221 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT 2222 * should be adjusted as needed by the 2D/3D drivers. This just sets default values 2223 */ 2224 sq_config = RREG32(SQ_CONFIG); 2225 sq_config &= ~(PS_PRIO(3) | 2226 VS_PRIO(3) | 2227 GS_PRIO(3) | 2228 ES_PRIO(3)); 2229 sq_config |= (DX9_CONSTS | 2230 VC_ENABLE | 2231 PS_PRIO(0) | 2232 VS_PRIO(1) | 2233 GS_PRIO(2) | 2234 ES_PRIO(3)); 2235 2236 if ((rdev->family) == CHIP_R600) { 2237 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) | 2238 NUM_VS_GPRS(124) | 2239 NUM_CLAUSE_TEMP_GPRS(4)); 2240 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) | 2241 NUM_ES_GPRS(0)); 2242 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) | 2243 NUM_VS_THREADS(48) | 2244 NUM_GS_THREADS(4) | 2245 NUM_ES_THREADS(4)); 2246 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) | 2247 NUM_VS_STACK_ENTRIES(128)); 2248 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) | 2249 NUM_ES_STACK_ENTRIES(0)); 2250 } else if (((rdev->family) == CHIP_RV610) || 2251 ((rdev->family) == CHIP_RV620) || 2252 ((rdev->family) == CHIP_RS780) || 2253 ((rdev->family) == CHIP_RS880)) { 2254 /* no vertex cache */ 2255 sq_config &= ~VC_ENABLE; 2256 2257 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | 2258 NUM_VS_GPRS(44) | 2259 NUM_CLAUSE_TEMP_GPRS(2)); 2260 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) | 2261 NUM_ES_GPRS(17)); 2262 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | 2263 NUM_VS_THREADS(78) | 2264 NUM_GS_THREADS(4) | 2265 NUM_ES_THREADS(31)); 2266 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) | 2267 NUM_VS_STACK_ENTRIES(40)); 2268 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) | 2269 NUM_ES_STACK_ENTRIES(16)); 2270 } else if (((rdev->family) == CHIP_RV630) || 2271 ((rdev->family) == CHIP_RV635)) { 2272 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | 2273 NUM_VS_GPRS(44) | 2274 NUM_CLAUSE_TEMP_GPRS(2)); 2275 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) | 2276 NUM_ES_GPRS(18)); 2277 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | 2278 NUM_VS_THREADS(78) | 2279 NUM_GS_THREADS(4) | 2280 NUM_ES_THREADS(31)); 2281 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) | 2282 NUM_VS_STACK_ENTRIES(40)); 2283 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) | 2284 NUM_ES_STACK_ENTRIES(16)); 2285 } else if ((rdev->family) == CHIP_RV670) { 2286 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | 2287 NUM_VS_GPRS(44) | 2288 NUM_CLAUSE_TEMP_GPRS(2)); 2289 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) | 2290 NUM_ES_GPRS(17)); 2291 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | 2292 NUM_VS_THREADS(78) | 2293 NUM_GS_THREADS(4) | 2294 NUM_ES_THREADS(31)); 2295 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) | 2296 NUM_VS_STACK_ENTRIES(64)); 2297 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) | 2298 NUM_ES_STACK_ENTRIES(64)); 2299 } 2300 2301 WREG32(SQ_CONFIG, sq_config); 2302 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1); 2303 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2); 2304 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); 2305 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1); 2306 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2); 2307 2308 if (((rdev->family) == CHIP_RV610) || 2309 ((rdev->family) == CHIP_RV620) || 2310 ((rdev->family) == CHIP_RS780) || 2311 ((rdev->family) == CHIP_RS880)) { 2312 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY)); 2313 } else { 2314 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC)); 2315 } 2316 2317 /* More default values. 2D/3D driver should adjust as needed */ 2318 WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) | 2319 S1_X(0x4) | S1_Y(0xc))); 2320 WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) | 2321 S1_X(0x2) | S1_Y(0x2) | 2322 S2_X(0xa) | S2_Y(0x6) | 2323 S3_X(0x6) | S3_Y(0xa))); 2324 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) | 2325 S1_X(0x4) | S1_Y(0xc) | 2326 S2_X(0x1) | S2_Y(0x6) | 2327 S3_X(0xa) | S3_Y(0xe))); 2328 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) | 2329 S5_X(0x0) | S5_Y(0x0) | 2330 S6_X(0xb) | S6_Y(0x4) | 2331 S7_X(0x7) | S7_Y(0x8))); 2332 2333 WREG32(VGT_STRMOUT_EN, 0); 2334 tmp = rdev->config.r600.max_pipes * 16; 2335 switch (rdev->family) { 2336 case CHIP_RV610: 2337 case CHIP_RV620: 2338 case CHIP_RS780: 2339 case CHIP_RS880: 2340 tmp += 32; 2341 break; 2342 case CHIP_RV670: 2343 tmp += 128; 2344 break; 2345 default: 2346 break; 2347 } 2348 if (tmp > 256) { 2349 tmp = 256; 2350 } 2351 WREG32(VGT_ES_PER_GS, 128); 2352 WREG32(VGT_GS_PER_ES, tmp); 2353 WREG32(VGT_GS_PER_VS, 2); 2354 WREG32(VGT_GS_VERTEX_REUSE, 16); 2355 2356 /* more default values. 2D/3D driver should adjust as needed */ 2357 WREG32(PA_SC_LINE_STIPPLE_STATE, 0); 2358 WREG32(VGT_STRMOUT_EN, 0); 2359 WREG32(SX_MISC, 0); 2360 WREG32(PA_SC_MODE_CNTL, 0); 2361 WREG32(PA_SC_AA_CONFIG, 0); 2362 WREG32(PA_SC_LINE_STIPPLE, 0); 2363 WREG32(SPI_INPUT_Z, 0); 2364 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2)); 2365 WREG32(CB_COLOR7_FRAG, 0); 2366 2367 /* Clear render buffer base addresses */ 2368 WREG32(CB_COLOR0_BASE, 0); 2369 WREG32(CB_COLOR1_BASE, 0); 2370 WREG32(CB_COLOR2_BASE, 0); 2371 WREG32(CB_COLOR3_BASE, 0); 2372 WREG32(CB_COLOR4_BASE, 0); 2373 WREG32(CB_COLOR5_BASE, 0); 2374 WREG32(CB_COLOR6_BASE, 0); 2375 WREG32(CB_COLOR7_BASE, 0); 2376 WREG32(CB_COLOR7_FRAG, 0); 2377 2378 switch (rdev->family) { 2379 case CHIP_RV610: 2380 case CHIP_RV620: 2381 case CHIP_RS780: 2382 case CHIP_RS880: 2383 tmp = TC_L2_SIZE(8); 2384 break; 2385 case CHIP_RV630: 2386 case CHIP_RV635: 2387 tmp = TC_L2_SIZE(4); 2388 break; 2389 case CHIP_R600: 2390 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT; 2391 break; 2392 default: 2393 tmp = TC_L2_SIZE(0); 2394 break; 2395 } 2396 WREG32(TC_CNTL, tmp); 2397 2398 tmp = RREG32(HDP_HOST_PATH_CNTL); 2399 WREG32(HDP_HOST_PATH_CNTL, tmp); 2400 2401 tmp = RREG32(ARB_POP); 2402 tmp |= ENABLE_TC128; 2403 WREG32(ARB_POP, tmp); 2404 2405 WREG32(PA_SC_MULTI_CHIP_CNTL, 0); 2406 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA | 2407 NUM_CLIP_SEQ(3))); 2408 WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095)); 2409 WREG32(VC_ENHANCE, 0); 2410 } 2411 2412 2413 /* 2414 * Indirect registers accessor 2415 */ 2416 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg) 2417 { 2418 unsigned long flags; 2419 u32 r; 2420 2421 spin_lock_irqsave(&rdev->pciep_idx_lock, flags); 2422 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); 2423 (void)RREG32(PCIE_PORT_INDEX); 2424 r = RREG32(PCIE_PORT_DATA); 2425 spin_unlock_irqrestore(&rdev->pciep_idx_lock, flags); 2426 return r; 2427 } 2428 2429 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2430 { 2431 unsigned long flags; 2432 2433 spin_lock_irqsave(&rdev->pciep_idx_lock, flags); 2434 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); 2435 (void)RREG32(PCIE_PORT_INDEX); 2436 WREG32(PCIE_PORT_DATA, (v)); 2437 (void)RREG32(PCIE_PORT_DATA); 2438 spin_unlock_irqrestore(&rdev->pciep_idx_lock, flags); 2439 } 2440 2441 /* 2442 * CP & Ring 2443 */ 2444 void r600_cp_stop(struct radeon_device *rdev) 2445 { 2446 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX) 2447 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 2448 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); 2449 WREG32(SCRATCH_UMSK, 0); 2450 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; 2451 } 2452 2453 int r600_init_microcode(struct radeon_device *rdev) 2454 { 2455 const char *chip_name; 2456 const char *rlc_chip_name; 2457 const char *smc_chip_name = "RV770"; 2458 size_t pfp_req_size, me_req_size, rlc_req_size, smc_req_size = 0; 2459 char fw_name[30]; 2460 int err; 2461 2462 DRM_DEBUG("\n"); 2463 2464 switch (rdev->family) { 2465 case CHIP_R600: 2466 chip_name = "R600"; 2467 rlc_chip_name = "R600"; 2468 break; 2469 case CHIP_RV610: 2470 chip_name = "RV610"; 2471 rlc_chip_name = "R600"; 2472 break; 2473 case CHIP_RV630: 2474 chip_name = "RV630"; 2475 rlc_chip_name = "R600"; 2476 break; 2477 case CHIP_RV620: 2478 chip_name = "RV620"; 2479 rlc_chip_name = "R600"; 2480 break; 2481 case CHIP_RV635: 2482 chip_name = "RV635"; 2483 rlc_chip_name = "R600"; 2484 break; 2485 case CHIP_RV670: 2486 chip_name = "RV670"; 2487 rlc_chip_name = "R600"; 2488 break; 2489 case CHIP_RS780: 2490 case CHIP_RS880: 2491 chip_name = "RS780"; 2492 rlc_chip_name = "R600"; 2493 break; 2494 case CHIP_RV770: 2495 chip_name = "RV770"; 2496 rlc_chip_name = "R700"; 2497 smc_chip_name = "RV770"; 2498 smc_req_size = ALIGN(RV770_SMC_UCODE_SIZE, 4); 2499 break; 2500 case CHIP_RV730: 2501 chip_name = "RV730"; 2502 rlc_chip_name = "R700"; 2503 smc_chip_name = "RV730"; 2504 smc_req_size = ALIGN(RV730_SMC_UCODE_SIZE, 4); 2505 break; 2506 case CHIP_RV710: 2507 chip_name = "RV710"; 2508 rlc_chip_name = "R700"; 2509 smc_chip_name = "RV710"; 2510 smc_req_size = ALIGN(RV710_SMC_UCODE_SIZE, 4); 2511 break; 2512 case CHIP_RV740: 2513 chip_name = "RV730"; 2514 rlc_chip_name = "R700"; 2515 smc_chip_name = "RV740"; 2516 smc_req_size = ALIGN(RV740_SMC_UCODE_SIZE, 4); 2517 break; 2518 case CHIP_CEDAR: 2519 chip_name = "CEDAR"; 2520 rlc_chip_name = "CEDAR"; 2521 smc_chip_name = "CEDAR"; 2522 smc_req_size = ALIGN(CEDAR_SMC_UCODE_SIZE, 4); 2523 break; 2524 case CHIP_REDWOOD: 2525 chip_name = "REDWOOD"; 2526 rlc_chip_name = "REDWOOD"; 2527 smc_chip_name = "REDWOOD"; 2528 smc_req_size = ALIGN(REDWOOD_SMC_UCODE_SIZE, 4); 2529 break; 2530 case CHIP_JUNIPER: 2531 chip_name = "JUNIPER"; 2532 rlc_chip_name = "JUNIPER"; 2533 smc_chip_name = "JUNIPER"; 2534 smc_req_size = ALIGN(JUNIPER_SMC_UCODE_SIZE, 4); 2535 break; 2536 case CHIP_CYPRESS: 2537 case CHIP_HEMLOCK: 2538 chip_name = "CYPRESS"; 2539 rlc_chip_name = "CYPRESS"; 2540 smc_chip_name = "CYPRESS"; 2541 smc_req_size = ALIGN(CYPRESS_SMC_UCODE_SIZE, 4); 2542 break; 2543 case CHIP_PALM: 2544 chip_name = "PALM"; 2545 rlc_chip_name = "SUMO"; 2546 break; 2547 case CHIP_SUMO: 2548 chip_name = "SUMO"; 2549 rlc_chip_name = "SUMO"; 2550 break; 2551 case CHIP_SUMO2: 2552 chip_name = "SUMO2"; 2553 rlc_chip_name = "SUMO"; 2554 break; 2555 default: BUG(); 2556 } 2557 2558 if (rdev->family >= CHIP_CEDAR) { 2559 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4; 2560 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4; 2561 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4; 2562 } else if (rdev->family >= CHIP_RV770) { 2563 pfp_req_size = R700_PFP_UCODE_SIZE * 4; 2564 me_req_size = R700_PM4_UCODE_SIZE * 4; 2565 rlc_req_size = R700_RLC_UCODE_SIZE * 4; 2566 } else { 2567 pfp_req_size = R600_PFP_UCODE_SIZE * 4; 2568 me_req_size = R600_PM4_UCODE_SIZE * 12; 2569 rlc_req_size = R600_RLC_UCODE_SIZE * 4; 2570 } 2571 2572 DRM_INFO("Loading %s Microcode\n", chip_name); 2573 2574 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name); 2575 err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev); 2576 if (err) 2577 goto out; 2578 if (rdev->pfp_fw->size != pfp_req_size) { 2579 printk(KERN_ERR 2580 "r600_cp: Bogus length %zu in firmware \"%s\"\n", 2581 rdev->pfp_fw->size, fw_name); 2582 err = -EINVAL; 2583 goto out; 2584 } 2585 2586 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name); 2587 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev); 2588 if (err) 2589 goto out; 2590 if (rdev->me_fw->size != me_req_size) { 2591 printk(KERN_ERR 2592 "r600_cp: Bogus length %zu in firmware \"%s\"\n", 2593 rdev->me_fw->size, fw_name); 2594 err = -EINVAL; 2595 } 2596 2597 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name); 2598 err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev); 2599 if (err) 2600 goto out; 2601 if (rdev->rlc_fw->size != rlc_req_size) { 2602 printk(KERN_ERR 2603 "r600_rlc: Bogus length %zu in firmware \"%s\"\n", 2604 rdev->rlc_fw->size, fw_name); 2605 err = -EINVAL; 2606 } 2607 2608 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_HEMLOCK)) { 2609 snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", smc_chip_name); 2610 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev); 2611 if (err) { 2612 printk(KERN_ERR 2613 "smc: error loading firmware \"%s\"\n", 2614 fw_name); 2615 release_firmware(rdev->smc_fw); 2616 rdev->smc_fw = NULL; 2617 err = 0; 2618 } else if (rdev->smc_fw->size != smc_req_size) { 2619 printk(KERN_ERR 2620 "smc: Bogus length %zu in firmware \"%s\"\n", 2621 rdev->smc_fw->size, fw_name); 2622 err = -EINVAL; 2623 } 2624 } 2625 2626 out: 2627 if (err) { 2628 if (err != -EINVAL) 2629 printk(KERN_ERR 2630 "r600_cp: Failed to load firmware \"%s\"\n", 2631 fw_name); 2632 release_firmware(rdev->pfp_fw); 2633 rdev->pfp_fw = NULL; 2634 release_firmware(rdev->me_fw); 2635 rdev->me_fw = NULL; 2636 release_firmware(rdev->rlc_fw); 2637 rdev->rlc_fw = NULL; 2638 release_firmware(rdev->smc_fw); 2639 rdev->smc_fw = NULL; 2640 } 2641 return err; 2642 } 2643 2644 u32 r600_gfx_get_rptr(struct radeon_device *rdev, 2645 struct radeon_ring *ring) 2646 { 2647 u32 rptr; 2648 2649 if (rdev->wb.enabled) 2650 rptr = rdev->wb.wb[ring->rptr_offs/4]; 2651 else 2652 rptr = RREG32(R600_CP_RB_RPTR); 2653 2654 return rptr; 2655 } 2656 2657 u32 r600_gfx_get_wptr(struct radeon_device *rdev, 2658 struct radeon_ring *ring) 2659 { 2660 u32 wptr; 2661 2662 wptr = RREG32(R600_CP_RB_WPTR); 2663 2664 return wptr; 2665 } 2666 2667 void r600_gfx_set_wptr(struct radeon_device *rdev, 2668 struct radeon_ring *ring) 2669 { 2670 WREG32(R600_CP_RB_WPTR, ring->wptr); 2671 (void)RREG32(R600_CP_RB_WPTR); 2672 } 2673 2674 static int r600_cp_load_microcode(struct radeon_device *rdev) 2675 { 2676 const __be32 *fw_data; 2677 int i; 2678 2679 if (!rdev->me_fw || !rdev->pfp_fw) 2680 return -EINVAL; 2681 2682 r600_cp_stop(rdev); 2683 2684 WREG32(CP_RB_CNTL, 2685 #ifdef __BIG_ENDIAN 2686 BUF_SWAP_32BIT | 2687 #endif 2688 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); 2689 2690 /* Reset cp */ 2691 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); 2692 RREG32(GRBM_SOFT_RESET); 2693 mdelay(15); 2694 WREG32(GRBM_SOFT_RESET, 0); 2695 2696 WREG32(CP_ME_RAM_WADDR, 0); 2697 2698 fw_data = (const __be32 *)rdev->me_fw->data; 2699 WREG32(CP_ME_RAM_WADDR, 0); 2700 for (i = 0; i < R600_PM4_UCODE_SIZE * 3; i++) 2701 WREG32(CP_ME_RAM_DATA, 2702 be32_to_cpup(fw_data++)); 2703 2704 fw_data = (const __be32 *)rdev->pfp_fw->data; 2705 WREG32(CP_PFP_UCODE_ADDR, 0); 2706 for (i = 0; i < R600_PFP_UCODE_SIZE; i++) 2707 WREG32(CP_PFP_UCODE_DATA, 2708 be32_to_cpup(fw_data++)); 2709 2710 WREG32(CP_PFP_UCODE_ADDR, 0); 2711 WREG32(CP_ME_RAM_WADDR, 0); 2712 WREG32(CP_ME_RAM_RADDR, 0); 2713 return 0; 2714 } 2715 2716 int r600_cp_start(struct radeon_device *rdev) 2717 { 2718 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2719 int r; 2720 uint32_t cp_me; 2721 2722 r = radeon_ring_lock(rdev, ring, 7); 2723 if (r) { 2724 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); 2725 return r; 2726 } 2727 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); 2728 radeon_ring_write(ring, 0x1); 2729 if (rdev->family >= CHIP_RV770) { 2730 radeon_ring_write(ring, 0x0); 2731 radeon_ring_write(ring, rdev->config.rv770.max_hw_contexts - 1); 2732 } else { 2733 radeon_ring_write(ring, 0x3); 2734 radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1); 2735 } 2736 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); 2737 radeon_ring_write(ring, 0); 2738 radeon_ring_write(ring, 0); 2739 radeon_ring_unlock_commit(rdev, ring, false); 2740 2741 cp_me = 0xff; 2742 WREG32(R_0086D8_CP_ME_CNTL, cp_me); 2743 return 0; 2744 } 2745 2746 int r600_cp_resume(struct radeon_device *rdev) 2747 { 2748 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2749 u32 tmp; 2750 u32 rb_bufsz; 2751 int r; 2752 2753 /* Reset cp */ 2754 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); 2755 RREG32(GRBM_SOFT_RESET); 2756 mdelay(15); 2757 WREG32(GRBM_SOFT_RESET, 0); 2758 2759 /* Set ring buffer size */ 2760 rb_bufsz = order_base_2(ring->ring_size / 8); 2761 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 2762 #ifdef __BIG_ENDIAN 2763 tmp |= BUF_SWAP_32BIT; 2764 #endif 2765 WREG32(CP_RB_CNTL, tmp); 2766 WREG32(CP_SEM_WAIT_TIMER, 0x0); 2767 2768 /* Set the write pointer delay */ 2769 WREG32(CP_RB_WPTR_DELAY, 0); 2770 2771 /* Initialize the ring buffer's read and write pointers */ 2772 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA); 2773 WREG32(CP_RB_RPTR_WR, 0); 2774 ring->wptr = 0; 2775 WREG32(CP_RB_WPTR, ring->wptr); 2776 2777 /* set the wb address whether it's enabled or not */ 2778 WREG32(CP_RB_RPTR_ADDR, 2779 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC)); 2780 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); 2781 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); 2782 2783 if (rdev->wb.enabled) 2784 WREG32(SCRATCH_UMSK, 0xff); 2785 else { 2786 tmp |= RB_NO_UPDATE; 2787 WREG32(SCRATCH_UMSK, 0); 2788 } 2789 2790 mdelay(1); 2791 WREG32(CP_RB_CNTL, tmp); 2792 2793 WREG32(CP_RB_BASE, ring->gpu_addr >> 8); 2794 WREG32(CP_DEBUG, (1 << 27) | (1 << 28)); 2795 2796 r600_cp_start(rdev); 2797 ring->ready = true; 2798 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring); 2799 if (r) { 2800 ring->ready = false; 2801 return r; 2802 } 2803 2804 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX) 2805 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); 2806 2807 return 0; 2808 } 2809 2810 void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size) 2811 { 2812 u32 rb_bufsz; 2813 int r; 2814 2815 /* Align ring size */ 2816 rb_bufsz = order_base_2(ring_size / 8); 2817 ring_size = (1 << (rb_bufsz + 1)) * 4; 2818 ring->ring_size = ring_size; 2819 ring->align_mask = 16 - 1; 2820 2821 if (radeon_ring_supports_scratch_reg(rdev, ring)) { 2822 r = radeon_scratch_get(rdev, &ring->rptr_save_reg); 2823 if (r) { 2824 DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r); 2825 ring->rptr_save_reg = 0; 2826 } 2827 } 2828 } 2829 2830 void r600_cp_fini(struct radeon_device *rdev) 2831 { 2832 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2833 r600_cp_stop(rdev); 2834 radeon_ring_fini(rdev, ring); 2835 radeon_scratch_free(rdev, ring->rptr_save_reg); 2836 } 2837 2838 /* 2839 * GPU scratch registers helpers function. 2840 */ 2841 void r600_scratch_init(struct radeon_device *rdev) 2842 { 2843 int i; 2844 2845 rdev->scratch.num_reg = 7; 2846 rdev->scratch.reg_base = SCRATCH_REG0; 2847 for (i = 0; i < rdev->scratch.num_reg; i++) { 2848 rdev->scratch.free[i] = true; 2849 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4); 2850 } 2851 } 2852 2853 int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *ring) 2854 { 2855 uint32_t scratch; 2856 uint32_t tmp = 0; 2857 unsigned i; 2858 int r; 2859 2860 r = radeon_scratch_get(rdev, &scratch); 2861 if (r) { 2862 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r); 2863 return r; 2864 } 2865 WREG32(scratch, 0xCAFEDEAD); 2866 r = radeon_ring_lock(rdev, ring, 3); 2867 if (r) { 2868 DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", ring->idx, r); 2869 radeon_scratch_free(rdev, scratch); 2870 return r; 2871 } 2872 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2873 radeon_ring_write(ring, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); 2874 radeon_ring_write(ring, 0xDEADBEEF); 2875 radeon_ring_unlock_commit(rdev, ring, false); 2876 for (i = 0; i < rdev->usec_timeout; i++) { 2877 tmp = RREG32(scratch); 2878 if (tmp == 0xDEADBEEF) 2879 break; 2880 DRM_UDELAY(1); 2881 } 2882 if (i < rdev->usec_timeout) { 2883 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); 2884 } else { 2885 DRM_ERROR("radeon: ring %d test failed (scratch(0x%04X)=0x%08X)\n", 2886 ring->idx, scratch, tmp); 2887 r = -EINVAL; 2888 } 2889 radeon_scratch_free(rdev, scratch); 2890 return r; 2891 } 2892 2893 /* 2894 * CP fences/semaphores 2895 */ 2896 2897 void r600_fence_ring_emit(struct radeon_device *rdev, 2898 struct radeon_fence *fence) 2899 { 2900 struct radeon_ring *ring = &rdev->ring[fence->ring]; 2901 u32 cp_coher_cntl = PACKET3_TC_ACTION_ENA | PACKET3_VC_ACTION_ENA | 2902 PACKET3_SH_ACTION_ENA; 2903 2904 if (rdev->family >= CHIP_RV770) 2905 cp_coher_cntl |= PACKET3_FULL_CACHE_ENA; 2906 2907 if (rdev->wb.use_event) { 2908 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; 2909 /* flush read cache over gart */ 2910 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 2911 radeon_ring_write(ring, cp_coher_cntl); 2912 radeon_ring_write(ring, 0xFFFFFFFF); 2913 radeon_ring_write(ring, 0); 2914 radeon_ring_write(ring, 10); /* poll interval */ 2915 /* EVENT_WRITE_EOP - flush caches, send int */ 2916 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); 2917 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5)); 2918 radeon_ring_write(ring, lower_32_bits(addr)); 2919 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); 2920 radeon_ring_write(ring, fence->seq); 2921 radeon_ring_write(ring, 0); 2922 } else { 2923 /* flush read cache over gart */ 2924 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 2925 radeon_ring_write(ring, cp_coher_cntl); 2926 radeon_ring_write(ring, 0xFFFFFFFF); 2927 radeon_ring_write(ring, 0); 2928 radeon_ring_write(ring, 10); /* poll interval */ 2929 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); 2930 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0)); 2931 /* wait for 3D idle clean */ 2932 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2933 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); 2934 radeon_ring_write(ring, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit); 2935 /* Emit fence sequence & fire IRQ */ 2936 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2937 radeon_ring_write(ring, ((rdev->fence_drv[fence->ring].scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); 2938 radeon_ring_write(ring, fence->seq); 2939 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */ 2940 radeon_ring_write(ring, PACKET0(CP_INT_STATUS, 0)); 2941 radeon_ring_write(ring, RB_INT_STAT); 2942 } 2943 } 2944 2945 /** 2946 * r600_semaphore_ring_emit - emit a semaphore on the CP ring 2947 * 2948 * @rdev: radeon_device pointer 2949 * @ring: radeon ring buffer object 2950 * @semaphore: radeon semaphore object 2951 * @emit_wait: Is this a sempahore wait? 2952 * 2953 * Emits a semaphore signal/wait packet to the CP ring and prevents the PFP 2954 * from running ahead of semaphore waits. 2955 */ 2956 bool r600_semaphore_ring_emit(struct radeon_device *rdev, 2957 struct radeon_ring *ring, 2958 struct radeon_semaphore *semaphore, 2959 bool emit_wait) 2960 { 2961 uint64_t addr = semaphore->gpu_addr; 2962 unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL; 2963 2964 if (rdev->family < CHIP_CAYMAN) 2965 sel |= PACKET3_SEM_WAIT_ON_SIGNAL; 2966 2967 radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1)); 2968 radeon_ring_write(ring, lower_32_bits(addr)); 2969 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel); 2970 2971 /* PFP_SYNC_ME packet only exists on 7xx+, only enable it on eg+ */ 2972 if (emit_wait && (rdev->family >= CHIP_CEDAR)) { 2973 /* Prevent the PFP from running ahead of the semaphore wait */ 2974 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 2975 radeon_ring_write(ring, 0x0); 2976 } 2977 2978 return true; 2979 } 2980 2981 /** 2982 * r600_copy_cpdma - copy pages using the CP DMA engine 2983 * 2984 * @rdev: radeon_device pointer 2985 * @src_offset: src GPU address 2986 * @dst_offset: dst GPU address 2987 * @num_gpu_pages: number of GPU pages to xfer 2988 * @fence: radeon fence object 2989 * 2990 * Copy GPU paging using the CP DMA engine (r6xx+). 2991 * Used by the radeon ttm implementation to move pages if 2992 * registered as the asic copy callback. 2993 */ 2994 struct radeon_fence *r600_copy_cpdma(struct radeon_device *rdev, 2995 uint64_t src_offset, uint64_t dst_offset, 2996 unsigned num_gpu_pages, 2997 struct reservation_object *resv) 2998 { 2999 struct radeon_fence *fence; 3000 struct radeon_sync sync; 3001 int ring_index = rdev->asic->copy.blit_ring_index; 3002 struct radeon_ring *ring = &rdev->ring[ring_index]; 3003 u32 size_in_bytes, cur_size_in_bytes, tmp; 3004 int i, num_loops; 3005 int r = 0; 3006 3007 radeon_sync_create(&sync); 3008 3009 size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT); 3010 num_loops = DIV_ROUND_UP(size_in_bytes, 0x1fffff); 3011 r = radeon_ring_lock(rdev, ring, num_loops * 6 + 24); 3012 if (r) { 3013 DRM_ERROR("radeon: moving bo (%d).\n", r); 3014 radeon_sync_free(rdev, &sync, NULL); 3015 return ERR_PTR(r); 3016 } 3017 3018 radeon_sync_resv(rdev, &sync, resv, false); 3019 radeon_sync_rings(rdev, &sync, ring->idx); 3020 3021 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 3022 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); 3023 radeon_ring_write(ring, WAIT_3D_IDLE_bit); 3024 for (i = 0; i < num_loops; i++) { 3025 cur_size_in_bytes = size_in_bytes; 3026 if (cur_size_in_bytes > 0x1fffff) 3027 cur_size_in_bytes = 0x1fffff; 3028 size_in_bytes -= cur_size_in_bytes; 3029 tmp = upper_32_bits(src_offset) & 0xff; 3030 if (size_in_bytes == 0) 3031 tmp |= PACKET3_CP_DMA_CP_SYNC; 3032 radeon_ring_write(ring, PACKET3(PACKET3_CP_DMA, 4)); 3033 radeon_ring_write(ring, lower_32_bits(src_offset)); 3034 radeon_ring_write(ring, tmp); 3035 radeon_ring_write(ring, lower_32_bits(dst_offset)); 3036 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff); 3037 radeon_ring_write(ring, cur_size_in_bytes); 3038 src_offset += cur_size_in_bytes; 3039 dst_offset += cur_size_in_bytes; 3040 } 3041 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 3042 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); 3043 radeon_ring_write(ring, WAIT_CP_DMA_IDLE_bit); 3044 3045 r = radeon_fence_emit(rdev, &fence, ring->idx); 3046 if (r) { 3047 radeon_ring_unlock_undo(rdev, ring); 3048 radeon_sync_free(rdev, &sync, NULL); 3049 return ERR_PTR(r); 3050 } 3051 3052 radeon_ring_unlock_commit(rdev, ring, false); 3053 radeon_sync_free(rdev, &sync, fence); 3054 3055 return fence; 3056 } 3057 3058 int r600_set_surface_reg(struct radeon_device *rdev, int reg, 3059 uint32_t tiling_flags, uint32_t pitch, 3060 uint32_t offset, uint32_t obj_size) 3061 { 3062 /* FIXME: implement */ 3063 return 0; 3064 } 3065 3066 void r600_clear_surface_reg(struct radeon_device *rdev, int reg) 3067 { 3068 /* FIXME: implement */ 3069 } 3070 3071 static int r600_startup(struct radeon_device *rdev) 3072 { 3073 struct radeon_ring *ring; 3074 int r; 3075 3076 /* enable pcie gen2 link */ 3077 r600_pcie_gen2_enable(rdev); 3078 3079 /* scratch needs to be initialized before MC */ 3080 r = r600_vram_scratch_init(rdev); 3081 if (r) 3082 return r; 3083 3084 r600_mc_program(rdev); 3085 3086 if (rdev->flags & RADEON_IS_AGP) { 3087 r600_agp_enable(rdev); 3088 } else { 3089 r = r600_pcie_gart_enable(rdev); 3090 if (r) 3091 return r; 3092 } 3093 r600_gpu_init(rdev); 3094 3095 /* allocate wb buffer */ 3096 r = radeon_wb_init(rdev); 3097 if (r) 3098 return r; 3099 3100 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 3101 if (r) { 3102 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 3103 return r; 3104 } 3105 3106 if (rdev->has_uvd) { 3107 r = uvd_v1_0_resume(rdev); 3108 if (!r) { 3109 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_UVD_INDEX); 3110 if (r) { 3111 dev_err(rdev->dev, "failed initializing UVD fences (%d).\n", r); 3112 } 3113 } 3114 if (r) 3115 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0; 3116 } 3117 3118 /* Enable IRQ */ 3119 if (!rdev->irq.installed) { 3120 r = radeon_irq_kms_init(rdev); 3121 if (r) 3122 return r; 3123 } 3124 3125 r = r600_irq_init(rdev); 3126 if (r) { 3127 DRM_ERROR("radeon: IH init failed (%d).\n", r); 3128 radeon_irq_kms_fini(rdev); 3129 return r; 3130 } 3131 r600_irq_set(rdev); 3132 3133 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 3134 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, 3135 RADEON_CP_PACKET2); 3136 if (r) 3137 return r; 3138 3139 r = r600_cp_load_microcode(rdev); 3140 if (r) 3141 return r; 3142 r = r600_cp_resume(rdev); 3143 if (r) 3144 return r; 3145 3146 if (rdev->has_uvd) { 3147 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; 3148 if (ring->ring_size) { 3149 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, 3150 RADEON_CP_PACKET2); 3151 if (!r) 3152 r = uvd_v1_0_init(rdev); 3153 if (r) 3154 DRM_ERROR("radeon: failed initializing UVD (%d).\n", r); 3155 } 3156 } 3157 3158 r = radeon_ib_pool_init(rdev); 3159 if (r) { 3160 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 3161 return r; 3162 } 3163 3164 r = radeon_audio_init(rdev); 3165 if (r) { 3166 DRM_ERROR("radeon: audio init failed\n"); 3167 return r; 3168 } 3169 3170 return 0; 3171 } 3172 3173 void r600_vga_set_state(struct radeon_device *rdev, bool state) 3174 { 3175 uint32_t temp; 3176 3177 temp = RREG32(CONFIG_CNTL); 3178 if (state == false) { 3179 temp &= ~(1<<0); 3180 temp |= (1<<1); 3181 } else { 3182 temp &= ~(1<<1); 3183 } 3184 WREG32(CONFIG_CNTL, temp); 3185 } 3186 3187 int r600_resume(struct radeon_device *rdev) 3188 { 3189 int r; 3190 3191 /* Do not reset GPU before posting, on r600 hw unlike on r500 hw, 3192 * posting will perform necessary task to bring back GPU into good 3193 * shape. 3194 */ 3195 /* post card */ 3196 atom_asic_init(rdev->mode_info.atom_context); 3197 3198 if (rdev->pm.pm_method == PM_METHOD_DPM) 3199 radeon_pm_resume(rdev); 3200 3201 rdev->accel_working = true; 3202 r = r600_startup(rdev); 3203 if (r) { 3204 DRM_ERROR("r600 startup failed on resume\n"); 3205 rdev->accel_working = false; 3206 return r; 3207 } 3208 3209 return r; 3210 } 3211 3212 int r600_suspend(struct radeon_device *rdev) 3213 { 3214 radeon_pm_suspend(rdev); 3215 radeon_audio_fini(rdev); 3216 r600_cp_stop(rdev); 3217 if (rdev->has_uvd) { 3218 uvd_v1_0_fini(rdev); 3219 radeon_uvd_suspend(rdev); 3220 } 3221 r600_irq_suspend(rdev); 3222 radeon_wb_disable(rdev); 3223 r600_pcie_gart_disable(rdev); 3224 3225 return 0; 3226 } 3227 3228 /* Plan is to move initialization in that function and use 3229 * helper function so that radeon_device_init pretty much 3230 * do nothing more than calling asic specific function. This 3231 * should also allow to remove a bunch of callback function 3232 * like vram_info. 3233 */ 3234 int r600_init(struct radeon_device *rdev) 3235 { 3236 int r; 3237 3238 if (r600_debugfs_mc_info_init(rdev)) { 3239 DRM_ERROR("Failed to register debugfs file for mc !\n"); 3240 } 3241 /* Read BIOS */ 3242 if (!radeon_get_bios(rdev)) { 3243 if (ASIC_IS_AVIVO(rdev)) 3244 return -EINVAL; 3245 } 3246 /* Must be an ATOMBIOS */ 3247 if (!rdev->is_atom_bios) { 3248 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n"); 3249 return -EINVAL; 3250 } 3251 r = radeon_atombios_init(rdev); 3252 if (r) 3253 return r; 3254 /* Post card if necessary */ 3255 if (!radeon_card_posted(rdev)) { 3256 if (!rdev->bios) { 3257 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); 3258 return -EINVAL; 3259 } 3260 DRM_INFO("GPU not posted. posting now...\n"); 3261 atom_asic_init(rdev->mode_info.atom_context); 3262 } 3263 /* Initialize scratch registers */ 3264 r600_scratch_init(rdev); 3265 /* Initialize surface registers */ 3266 radeon_surface_init(rdev); 3267 /* Initialize clocks */ 3268 radeon_get_clock_info(rdev->ddev); 3269 /* Fence driver */ 3270 r = radeon_fence_driver_init(rdev); 3271 if (r) 3272 return r; 3273 if (rdev->flags & RADEON_IS_AGP) { 3274 r = radeon_agp_init(rdev); 3275 if (r) 3276 radeon_agp_disable(rdev); 3277 } 3278 r = r600_mc_init(rdev); 3279 if (r) 3280 return r; 3281 /* Memory manager */ 3282 r = radeon_bo_init(rdev); 3283 if (r) 3284 return r; 3285 3286 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { 3287 r = r600_init_microcode(rdev); 3288 if (r) { 3289 DRM_ERROR("Failed to load firmware!\n"); 3290 return r; 3291 } 3292 } 3293 3294 /* Initialize power management */ 3295 radeon_pm_init(rdev); 3296 3297 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL; 3298 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024); 3299 3300 if (rdev->has_uvd) { 3301 r = radeon_uvd_init(rdev); 3302 if (!r) { 3303 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL; 3304 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX], 4096); 3305 } 3306 } 3307 3308 rdev->ih.ring_obj = NULL; 3309 r600_ih_ring_init(rdev, 64 * 1024); 3310 3311 r = r600_pcie_gart_init(rdev); 3312 if (r) 3313 return r; 3314 3315 rdev->accel_working = true; 3316 r = r600_startup(rdev); 3317 if (r) { 3318 dev_err(rdev->dev, "disabling GPU acceleration\n"); 3319 r600_cp_fini(rdev); 3320 r600_irq_fini(rdev); 3321 radeon_wb_fini(rdev); 3322 radeon_ib_pool_fini(rdev); 3323 radeon_irq_kms_fini(rdev); 3324 r600_pcie_gart_fini(rdev); 3325 rdev->accel_working = false; 3326 } 3327 3328 return 0; 3329 } 3330 3331 void r600_fini(struct radeon_device *rdev) 3332 { 3333 radeon_pm_fini(rdev); 3334 radeon_audio_fini(rdev); 3335 r600_cp_fini(rdev); 3336 r600_irq_fini(rdev); 3337 if (rdev->has_uvd) { 3338 uvd_v1_0_fini(rdev); 3339 radeon_uvd_fini(rdev); 3340 } 3341 radeon_wb_fini(rdev); 3342 radeon_ib_pool_fini(rdev); 3343 radeon_irq_kms_fini(rdev); 3344 r600_pcie_gart_fini(rdev); 3345 r600_vram_scratch_fini(rdev); 3346 radeon_agp_fini(rdev); 3347 radeon_gem_fini(rdev); 3348 radeon_fence_driver_fini(rdev); 3349 radeon_bo_fini(rdev); 3350 radeon_atombios_fini(rdev); 3351 kfree(rdev->bios); 3352 rdev->bios = NULL; 3353 } 3354 3355 3356 /* 3357 * CS stuff 3358 */ 3359 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) 3360 { 3361 struct radeon_ring *ring = &rdev->ring[ib->ring]; 3362 u32 next_rptr; 3363 3364 if (ring->rptr_save_reg) { 3365 next_rptr = ring->wptr + 3 + 4; 3366 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 3367 radeon_ring_write(ring, ((ring->rptr_save_reg - 3368 PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); 3369 radeon_ring_write(ring, next_rptr); 3370 } else if (rdev->wb.enabled) { 3371 next_rptr = ring->wptr + 5 + 4; 3372 radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3)); 3373 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); 3374 radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18)); 3375 radeon_ring_write(ring, next_rptr); 3376 radeon_ring_write(ring, 0); 3377 } 3378 3379 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 3380 radeon_ring_write(ring, 3381 #ifdef __BIG_ENDIAN 3382 (2 << 0) | 3383 #endif 3384 (ib->gpu_addr & 0xFFFFFFFC)); 3385 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF); 3386 radeon_ring_write(ring, ib->length_dw); 3387 } 3388 3389 int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) 3390 { 3391 struct radeon_ib ib; 3392 uint32_t scratch; 3393 uint32_t tmp = 0; 3394 unsigned i; 3395 int r; 3396 3397 r = radeon_scratch_get(rdev, &scratch); 3398 if (r) { 3399 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r); 3400 return r; 3401 } 3402 WREG32(scratch, 0xCAFEDEAD); 3403 r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256); 3404 if (r) { 3405 DRM_ERROR("radeon: failed to get ib (%d).\n", r); 3406 goto free_scratch; 3407 } 3408 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1); 3409 ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); 3410 ib.ptr[2] = 0xDEADBEEF; 3411 ib.length_dw = 3; 3412 r = radeon_ib_schedule(rdev, &ib, NULL, false); 3413 if (r) { 3414 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); 3415 goto free_ib; 3416 } 3417 r = radeon_fence_wait(ib.fence, false); 3418 if (r) { 3419 DRM_ERROR("radeon: fence wait failed (%d).\n", r); 3420 goto free_ib; 3421 } 3422 for (i = 0; i < rdev->usec_timeout; i++) { 3423 tmp = RREG32(scratch); 3424 if (tmp == 0xDEADBEEF) 3425 break; 3426 DRM_UDELAY(1); 3427 } 3428 if (i < rdev->usec_timeout) { 3429 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i); 3430 } else { 3431 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n", 3432 scratch, tmp); 3433 r = -EINVAL; 3434 } 3435 free_ib: 3436 radeon_ib_free(rdev, &ib); 3437 free_scratch: 3438 radeon_scratch_free(rdev, scratch); 3439 return r; 3440 } 3441 3442 /* 3443 * Interrupts 3444 * 3445 * Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty 3446 * the same as the CP ring buffer, but in reverse. Rather than the CPU 3447 * writing to the ring and the GPU consuming, the GPU writes to the ring 3448 * and host consumes. As the host irq handler processes interrupts, it 3449 * increments the rptr. When the rptr catches up with the wptr, all the 3450 * current interrupts have been processed. 3451 */ 3452 3453 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size) 3454 { 3455 u32 rb_bufsz; 3456 3457 /* Align ring size */ 3458 rb_bufsz = order_base_2(ring_size / 4); 3459 ring_size = (1 << rb_bufsz) * 4; 3460 rdev->ih.ring_size = ring_size; 3461 rdev->ih.ptr_mask = rdev->ih.ring_size - 1; 3462 rdev->ih.rptr = 0; 3463 } 3464 3465 int r600_ih_ring_alloc(struct radeon_device *rdev) 3466 { 3467 int r; 3468 3469 /* Allocate ring buffer */ 3470 if (rdev->ih.ring_obj == NULL) { 3471 r = radeon_bo_create(rdev, rdev->ih.ring_size, 3472 PAGE_SIZE, true, 3473 RADEON_GEM_DOMAIN_GTT, 0, 3474 NULL, NULL, &rdev->ih.ring_obj); 3475 if (r) { 3476 DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r); 3477 return r; 3478 } 3479 r = radeon_bo_reserve(rdev->ih.ring_obj, false); 3480 if (unlikely(r != 0)) 3481 return r; 3482 r = radeon_bo_pin(rdev->ih.ring_obj, 3483 RADEON_GEM_DOMAIN_GTT, 3484 &rdev->ih.gpu_addr); 3485 if (r) { 3486 radeon_bo_unreserve(rdev->ih.ring_obj); 3487 DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r); 3488 return r; 3489 } 3490 r = radeon_bo_kmap(rdev->ih.ring_obj, 3491 (void **)__UNVOLATILE(&rdev->ih.ring)); 3492 radeon_bo_unreserve(rdev->ih.ring_obj); 3493 if (r) { 3494 DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r); 3495 return r; 3496 } 3497 } 3498 return 0; 3499 } 3500 3501 void r600_ih_ring_fini(struct radeon_device *rdev) 3502 { 3503 int r; 3504 if (rdev->ih.ring_obj) { 3505 r = radeon_bo_reserve(rdev->ih.ring_obj, false); 3506 if (likely(r == 0)) { 3507 radeon_bo_kunmap(rdev->ih.ring_obj); 3508 radeon_bo_unpin(rdev->ih.ring_obj); 3509 radeon_bo_unreserve(rdev->ih.ring_obj); 3510 } 3511 radeon_bo_unref(&rdev->ih.ring_obj); 3512 rdev->ih.ring = NULL; 3513 rdev->ih.ring_obj = NULL; 3514 } 3515 } 3516 3517 void r600_rlc_stop(struct radeon_device *rdev) 3518 { 3519 3520 if ((rdev->family >= CHIP_RV770) && 3521 (rdev->family <= CHIP_RV740)) { 3522 /* r7xx asics need to soft reset RLC before halting */ 3523 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC); 3524 RREG32(SRBM_SOFT_RESET); 3525 mdelay(15); 3526 WREG32(SRBM_SOFT_RESET, 0); 3527 RREG32(SRBM_SOFT_RESET); 3528 } 3529 3530 WREG32(RLC_CNTL, 0); 3531 } 3532 3533 static void r600_rlc_start(struct radeon_device *rdev) 3534 { 3535 WREG32(RLC_CNTL, RLC_ENABLE); 3536 } 3537 3538 static int r600_rlc_resume(struct radeon_device *rdev) 3539 { 3540 u32 i; 3541 const __be32 *fw_data; 3542 3543 if (!rdev->rlc_fw) 3544 return -EINVAL; 3545 3546 r600_rlc_stop(rdev); 3547 3548 WREG32(RLC_HB_CNTL, 0); 3549 3550 WREG32(RLC_HB_BASE, 0); 3551 WREG32(RLC_HB_RPTR, 0); 3552 WREG32(RLC_HB_WPTR, 0); 3553 WREG32(RLC_HB_WPTR_LSB_ADDR, 0); 3554 WREG32(RLC_HB_WPTR_MSB_ADDR, 0); 3555 WREG32(RLC_MC_CNTL, 0); 3556 WREG32(RLC_UCODE_CNTL, 0); 3557 3558 fw_data = (const __be32 *)rdev->rlc_fw->data; 3559 if (rdev->family >= CHIP_RV770) { 3560 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) { 3561 WREG32(RLC_UCODE_ADDR, i); 3562 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); 3563 } 3564 } else { 3565 for (i = 0; i < R600_RLC_UCODE_SIZE; i++) { 3566 WREG32(RLC_UCODE_ADDR, i); 3567 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); 3568 } 3569 } 3570 WREG32(RLC_UCODE_ADDR, 0); 3571 3572 r600_rlc_start(rdev); 3573 3574 return 0; 3575 } 3576 3577 static void r600_enable_interrupts(struct radeon_device *rdev) 3578 { 3579 u32 ih_cntl = RREG32(IH_CNTL); 3580 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); 3581 3582 ih_cntl |= ENABLE_INTR; 3583 ih_rb_cntl |= IH_RB_ENABLE; 3584 WREG32(IH_CNTL, ih_cntl); 3585 WREG32(IH_RB_CNTL, ih_rb_cntl); 3586 rdev->ih.enabled = true; 3587 } 3588 3589 void r600_disable_interrupts(struct radeon_device *rdev) 3590 { 3591 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); 3592 u32 ih_cntl = RREG32(IH_CNTL); 3593 3594 ih_rb_cntl &= ~IH_RB_ENABLE; 3595 ih_cntl &= ~ENABLE_INTR; 3596 WREG32(IH_RB_CNTL, ih_rb_cntl); 3597 WREG32(IH_CNTL, ih_cntl); 3598 /* set rptr, wptr to 0 */ 3599 WREG32(IH_RB_RPTR, 0); 3600 WREG32(IH_RB_WPTR, 0); 3601 rdev->ih.enabled = false; 3602 rdev->ih.rptr = 0; 3603 } 3604 3605 static void r600_disable_interrupt_state(struct radeon_device *rdev) 3606 { 3607 u32 tmp; 3608 3609 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); 3610 tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE; 3611 WREG32(DMA_CNTL, tmp); 3612 WREG32(GRBM_INT_CNTL, 0); 3613 WREG32(DxMODE_INT_MASK, 0); 3614 WREG32(D1GRPH_INTERRUPT_CONTROL, 0); 3615 WREG32(D2GRPH_INTERRUPT_CONTROL, 0); 3616 if (ASIC_IS_DCE3(rdev)) { 3617 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0); 3618 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0); 3619 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3620 WREG32(DC_HPD1_INT_CONTROL, tmp); 3621 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3622 WREG32(DC_HPD2_INT_CONTROL, tmp); 3623 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3624 WREG32(DC_HPD3_INT_CONTROL, tmp); 3625 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3626 WREG32(DC_HPD4_INT_CONTROL, tmp); 3627 if (ASIC_IS_DCE32(rdev)) { 3628 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3629 WREG32(DC_HPD5_INT_CONTROL, tmp); 3630 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3631 WREG32(DC_HPD6_INT_CONTROL, tmp); 3632 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3633 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp); 3634 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3635 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp); 3636 } else { 3637 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3638 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); 3639 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3640 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp); 3641 } 3642 } else { 3643 WREG32(DACA_AUTODETECT_INT_CONTROL, 0); 3644 WREG32(DACB_AUTODETECT_INT_CONTROL, 0); 3645 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; 3646 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); 3647 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; 3648 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); 3649 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; 3650 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); 3651 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3652 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); 3653 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3654 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp); 3655 } 3656 } 3657 3658 int r600_irq_init(struct radeon_device *rdev) 3659 { 3660 int ret = 0; 3661 int rb_bufsz; 3662 u32 interrupt_cntl, ih_cntl, ih_rb_cntl; 3663 3664 /* allocate ring */ 3665 ret = r600_ih_ring_alloc(rdev); 3666 if (ret) 3667 return ret; 3668 3669 /* disable irqs */ 3670 r600_disable_interrupts(rdev); 3671 3672 /* init rlc */ 3673 if (rdev->family >= CHIP_CEDAR) 3674 ret = evergreen_rlc_resume(rdev); 3675 else 3676 ret = r600_rlc_resume(rdev); 3677 if (ret) { 3678 r600_ih_ring_fini(rdev); 3679 return ret; 3680 } 3681 3682 /* setup interrupt control */ 3683 /* set dummy read address to ring address */ 3684 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8); 3685 interrupt_cntl = RREG32(INTERRUPT_CNTL); 3686 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi 3687 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN 3688 */ 3689 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE; 3690 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */ 3691 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN; 3692 WREG32(INTERRUPT_CNTL, interrupt_cntl); 3693 3694 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8); 3695 rb_bufsz = order_base_2(rdev->ih.ring_size / 4); 3696 3697 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE | 3698 IH_WPTR_OVERFLOW_CLEAR | 3699 (rb_bufsz << 1)); 3700 3701 if (rdev->wb.enabled) 3702 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE; 3703 3704 /* set the writeback address whether it's enabled or not */ 3705 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC); 3706 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF); 3707 3708 WREG32(IH_RB_CNTL, ih_rb_cntl); 3709 3710 /* set rptr, wptr to 0 */ 3711 WREG32(IH_RB_RPTR, 0); 3712 WREG32(IH_RB_WPTR, 0); 3713 3714 /* Default settings for IH_CNTL (disabled at first) */ 3715 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10); 3716 /* RPTR_REARM only works if msi's are enabled */ 3717 if (rdev->msi_enabled) 3718 ih_cntl |= RPTR_REARM; 3719 WREG32(IH_CNTL, ih_cntl); 3720 3721 /* force the active interrupt state to all disabled */ 3722 if (rdev->family >= CHIP_CEDAR) 3723 evergreen_disable_interrupt_state(rdev); 3724 else 3725 r600_disable_interrupt_state(rdev); 3726 3727 /* at this point everything should be setup correctly to enable master */ 3728 pci_set_master(rdev->pdev); 3729 3730 /* enable irqs */ 3731 r600_enable_interrupts(rdev); 3732 3733 return ret; 3734 } 3735 3736 void r600_irq_suspend(struct radeon_device *rdev) 3737 { 3738 r600_irq_disable(rdev); 3739 r600_rlc_stop(rdev); 3740 } 3741 3742 void r600_irq_fini(struct radeon_device *rdev) 3743 { 3744 r600_irq_suspend(rdev); 3745 r600_ih_ring_fini(rdev); 3746 } 3747 3748 int r600_irq_set(struct radeon_device *rdev) 3749 { 3750 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE; 3751 u32 mode_int = 0; 3752 u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0; 3753 u32 grbm_int_cntl = 0; 3754 u32 hdmi0, hdmi1; 3755 u32 dma_cntl; 3756 u32 thermal_int = 0; 3757 3758 if (!rdev->irq.installed) { 3759 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); 3760 return -EINVAL; 3761 } 3762 /* don't enable anything if the ih is disabled */ 3763 if (!rdev->ih.enabled) { 3764 r600_disable_interrupts(rdev); 3765 /* force the active interrupt state to all disabled */ 3766 r600_disable_interrupt_state(rdev); 3767 return 0; 3768 } 3769 3770 if (ASIC_IS_DCE3(rdev)) { 3771 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN; 3772 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN; 3773 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN; 3774 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN; 3775 if (ASIC_IS_DCE32(rdev)) { 3776 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN; 3777 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN; 3778 hdmi0 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~AFMT_AZ_FORMAT_WTRIG_MASK; 3779 hdmi1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~AFMT_AZ_FORMAT_WTRIG_MASK; 3780 } else { 3781 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3782 hdmi1 = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3783 } 3784 } else { 3785 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN; 3786 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN; 3787 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN; 3788 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3789 hdmi1 = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3790 } 3791 3792 dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE; 3793 3794 if ((rdev->family > CHIP_R600) && (rdev->family < CHIP_RV770)) { 3795 thermal_int = RREG32(CG_THERMAL_INT) & 3796 ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW); 3797 } else if (rdev->family >= CHIP_RV770) { 3798 thermal_int = RREG32(RV770_CG_THERMAL_INT) & 3799 ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW); 3800 } 3801 if (rdev->irq.dpm_thermal) { 3802 DRM_DEBUG("dpm thermal\n"); 3803 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW; 3804 } 3805 3806 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { 3807 DRM_DEBUG("r600_irq_set: sw int\n"); 3808 cp_int_cntl |= RB_INT_ENABLE; 3809 cp_int_cntl |= TIME_STAMP_INT_ENABLE; 3810 } 3811 3812 if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) { 3813 DRM_DEBUG("r600_irq_set: sw int dma\n"); 3814 dma_cntl |= TRAP_ENABLE; 3815 } 3816 3817 if (rdev->irq.crtc_vblank_int[0] || 3818 atomic_read(&rdev->irq.pflip[0])) { 3819 DRM_DEBUG("r600_irq_set: vblank 0\n"); 3820 mode_int |= D1MODE_VBLANK_INT_MASK; 3821 } 3822 if (rdev->irq.crtc_vblank_int[1] || 3823 atomic_read(&rdev->irq.pflip[1])) { 3824 DRM_DEBUG("r600_irq_set: vblank 1\n"); 3825 mode_int |= D2MODE_VBLANK_INT_MASK; 3826 } 3827 if (rdev->irq.hpd[0]) { 3828 DRM_DEBUG("r600_irq_set: hpd 1\n"); 3829 hpd1 |= DC_HPDx_INT_EN; 3830 } 3831 if (rdev->irq.hpd[1]) { 3832 DRM_DEBUG("r600_irq_set: hpd 2\n"); 3833 hpd2 |= DC_HPDx_INT_EN; 3834 } 3835 if (rdev->irq.hpd[2]) { 3836 DRM_DEBUG("r600_irq_set: hpd 3\n"); 3837 hpd3 |= DC_HPDx_INT_EN; 3838 } 3839 if (rdev->irq.hpd[3]) { 3840 DRM_DEBUG("r600_irq_set: hpd 4\n"); 3841 hpd4 |= DC_HPDx_INT_EN; 3842 } 3843 if (rdev->irq.hpd[4]) { 3844 DRM_DEBUG("r600_irq_set: hpd 5\n"); 3845 hpd5 |= DC_HPDx_INT_EN; 3846 } 3847 if (rdev->irq.hpd[5]) { 3848 DRM_DEBUG("r600_irq_set: hpd 6\n"); 3849 hpd6 |= DC_HPDx_INT_EN; 3850 } 3851 if (rdev->irq.afmt[0]) { 3852 DRM_DEBUG("r600_irq_set: hdmi 0\n"); 3853 hdmi0 |= HDMI0_AZ_FORMAT_WTRIG_MASK; 3854 } 3855 if (rdev->irq.afmt[1]) { 3856 DRM_DEBUG("r600_irq_set: hdmi 0\n"); 3857 hdmi1 |= HDMI0_AZ_FORMAT_WTRIG_MASK; 3858 } 3859 3860 WREG32(CP_INT_CNTL, cp_int_cntl); 3861 WREG32(DMA_CNTL, dma_cntl); 3862 WREG32(DxMODE_INT_MASK, mode_int); 3863 WREG32(D1GRPH_INTERRUPT_CONTROL, DxGRPH_PFLIP_INT_MASK); 3864 WREG32(D2GRPH_INTERRUPT_CONTROL, DxGRPH_PFLIP_INT_MASK); 3865 WREG32(GRBM_INT_CNTL, grbm_int_cntl); 3866 if (ASIC_IS_DCE3(rdev)) { 3867 WREG32(DC_HPD1_INT_CONTROL, hpd1); 3868 WREG32(DC_HPD2_INT_CONTROL, hpd2); 3869 WREG32(DC_HPD3_INT_CONTROL, hpd3); 3870 WREG32(DC_HPD4_INT_CONTROL, hpd4); 3871 if (ASIC_IS_DCE32(rdev)) { 3872 WREG32(DC_HPD5_INT_CONTROL, hpd5); 3873 WREG32(DC_HPD6_INT_CONTROL, hpd6); 3874 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, hdmi0); 3875 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, hdmi1); 3876 } else { 3877 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0); 3878 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, hdmi1); 3879 } 3880 } else { 3881 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1); 3882 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2); 3883 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3); 3884 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0); 3885 WREG32(HDMI1_AUDIO_PACKET_CONTROL, hdmi1); 3886 } 3887 if ((rdev->family > CHIP_R600) && (rdev->family < CHIP_RV770)) { 3888 WREG32(CG_THERMAL_INT, thermal_int); 3889 } else if (rdev->family >= CHIP_RV770) { 3890 WREG32(RV770_CG_THERMAL_INT, thermal_int); 3891 } 3892 3893 /* posting read */ 3894 RREG32(R_000E50_SRBM_STATUS); 3895 3896 return 0; 3897 } 3898 3899 static void r600_irq_ack(struct radeon_device *rdev) 3900 { 3901 u32 tmp; 3902 3903 if (ASIC_IS_DCE3(rdev)) { 3904 rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS); 3905 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE); 3906 rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2); 3907 if (ASIC_IS_DCE32(rdev)) { 3908 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET0); 3909 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET1); 3910 } else { 3911 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS); 3912 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(DCE3_HDMI1_STATUS); 3913 } 3914 } else { 3915 rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS); 3916 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE); 3917 rdev->irq.stat_regs.r600.disp_int_cont2 = 0; 3918 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS); 3919 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(HDMI1_STATUS); 3920 } 3921 rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS); 3922 rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS); 3923 3924 if (rdev->irq.stat_regs.r600.d1grph_int & DxGRPH_PFLIP_INT_OCCURRED) 3925 WREG32(D1GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR); 3926 if (rdev->irq.stat_regs.r600.d2grph_int & DxGRPH_PFLIP_INT_OCCURRED) 3927 WREG32(D2GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR); 3928 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) 3929 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK); 3930 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) 3931 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK); 3932 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) 3933 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK); 3934 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) 3935 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK); 3936 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) { 3937 if (ASIC_IS_DCE3(rdev)) { 3938 tmp = RREG32(DC_HPD1_INT_CONTROL); 3939 tmp |= DC_HPDx_INT_ACK; 3940 WREG32(DC_HPD1_INT_CONTROL, tmp); 3941 } else { 3942 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL); 3943 tmp |= DC_HPDx_INT_ACK; 3944 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); 3945 } 3946 } 3947 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) { 3948 if (ASIC_IS_DCE3(rdev)) { 3949 tmp = RREG32(DC_HPD2_INT_CONTROL); 3950 tmp |= DC_HPDx_INT_ACK; 3951 WREG32(DC_HPD2_INT_CONTROL, tmp); 3952 } else { 3953 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL); 3954 tmp |= DC_HPDx_INT_ACK; 3955 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); 3956 } 3957 } 3958 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) { 3959 if (ASIC_IS_DCE3(rdev)) { 3960 tmp = RREG32(DC_HPD3_INT_CONTROL); 3961 tmp |= DC_HPDx_INT_ACK; 3962 WREG32(DC_HPD3_INT_CONTROL, tmp); 3963 } else { 3964 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL); 3965 tmp |= DC_HPDx_INT_ACK; 3966 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); 3967 } 3968 } 3969 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) { 3970 tmp = RREG32(DC_HPD4_INT_CONTROL); 3971 tmp |= DC_HPDx_INT_ACK; 3972 WREG32(DC_HPD4_INT_CONTROL, tmp); 3973 } 3974 if (ASIC_IS_DCE32(rdev)) { 3975 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) { 3976 tmp = RREG32(DC_HPD5_INT_CONTROL); 3977 tmp |= DC_HPDx_INT_ACK; 3978 WREG32(DC_HPD5_INT_CONTROL, tmp); 3979 } 3980 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) { 3981 tmp = RREG32(DC_HPD6_INT_CONTROL); 3982 tmp |= DC_HPDx_INT_ACK; 3983 WREG32(DC_HPD6_INT_CONTROL, tmp); 3984 } 3985 if (rdev->irq.stat_regs.r600.hdmi0_status & AFMT_AZ_FORMAT_WTRIG) { 3986 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0); 3987 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; 3988 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp); 3989 } 3990 if (rdev->irq.stat_regs.r600.hdmi1_status & AFMT_AZ_FORMAT_WTRIG) { 3991 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1); 3992 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; 3993 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp); 3994 } 3995 } else { 3996 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) { 3997 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL); 3998 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK; 3999 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); 4000 } 4001 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) { 4002 if (ASIC_IS_DCE3(rdev)) { 4003 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL); 4004 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK; 4005 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp); 4006 } else { 4007 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL); 4008 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK; 4009 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp); 4010 } 4011 } 4012 } 4013 } 4014 4015 void r600_irq_disable(struct radeon_device *rdev) 4016 { 4017 r600_disable_interrupts(rdev); 4018 /* Wait and acknowledge irq */ 4019 mdelay(1); 4020 r600_irq_ack(rdev); 4021 r600_disable_interrupt_state(rdev); 4022 } 4023 4024 static u32 r600_get_ih_wptr(struct radeon_device *rdev) 4025 { 4026 u32 wptr, tmp; 4027 4028 if (rdev->wb.enabled) 4029 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]); 4030 else 4031 wptr = RREG32(IH_RB_WPTR); 4032 4033 if (wptr & RB_OVERFLOW) { 4034 wptr &= ~RB_OVERFLOW; 4035 /* When a ring buffer overflow happen start parsing interrupt 4036 * from the last not overwritten vector (wptr + 16). Hopefully 4037 * this should allow us to catchup. 4038 */ 4039 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n", 4040 wptr, rdev->ih.rptr, (wptr + 16) & rdev->ih.ptr_mask); 4041 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask; 4042 tmp = RREG32(IH_RB_CNTL); 4043 tmp |= IH_WPTR_OVERFLOW_CLEAR; 4044 WREG32(IH_RB_CNTL, tmp); 4045 } 4046 return (wptr & rdev->ih.ptr_mask); 4047 } 4048 4049 /* r600 IV Ring 4050 * Each IV ring entry is 128 bits: 4051 * [7:0] - interrupt source id 4052 * [31:8] - reserved 4053 * [59:32] - interrupt source data 4054 * [127:60] - reserved 4055 * 4056 * The basic interrupt vector entries 4057 * are decoded as follows: 4058 * src_id src_data description 4059 * 1 0 D1 Vblank 4060 * 1 1 D1 Vline 4061 * 5 0 D2 Vblank 4062 * 5 1 D2 Vline 4063 * 19 0 FP Hot plug detection A 4064 * 19 1 FP Hot plug detection B 4065 * 19 2 DAC A auto-detection 4066 * 19 3 DAC B auto-detection 4067 * 21 4 HDMI block A 4068 * 21 5 HDMI block B 4069 * 176 - CP_INT RB 4070 * 177 - CP_INT IB1 4071 * 178 - CP_INT IB2 4072 * 181 - EOP Interrupt 4073 * 233 - GUI Idle 4074 * 4075 * Note, these are based on r600 and may need to be 4076 * adjusted or added to on newer asics 4077 */ 4078 4079 int r600_irq_process(struct radeon_device *rdev) 4080 { 4081 u32 wptr; 4082 u32 rptr; 4083 u32 src_id, src_data; 4084 u32 ring_index; 4085 bool queue_hotplug = false; 4086 bool queue_hdmi = false; 4087 bool queue_thermal = false; 4088 4089 if (!rdev->ih.enabled || rdev->shutdown) 4090 return IRQ_NONE; 4091 4092 /* No MSIs, need a dummy read to flush PCI DMAs */ 4093 if (!rdev->msi_enabled) 4094 RREG32(IH_RB_WPTR); 4095 4096 wptr = r600_get_ih_wptr(rdev); 4097 4098 restart_ih: 4099 /* is somebody else already processing irqs? */ 4100 if (atomic_xchg(&rdev->ih.lock, 1)) 4101 return IRQ_NONE; 4102 4103 rptr = rdev->ih.rptr; 4104 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr); 4105 4106 /* Order reading of wptr vs. reading of IH ring data */ 4107 rmb(); 4108 4109 /* display interrupts */ 4110 r600_irq_ack(rdev); 4111 4112 while (rptr != wptr) { 4113 /* wptr/rptr are in bytes! */ 4114 ring_index = rptr / 4; 4115 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff; 4116 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff; 4117 4118 switch (src_id) { 4119 case 1: /* D1 vblank/vline */ 4120 switch (src_data) { 4121 case 0: /* D1 vblank */ 4122 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT)) 4123 DRM_DEBUG("IH: D1 vblank - IH event w/o asserted irq bit?\n"); 4124 4125 if (rdev->irq.crtc_vblank_int[0]) { 4126 drm_handle_vblank(rdev->ddev, 0); 4127 #ifdef __NetBSD__ 4128 spin_lock(&rdev->irq.vblank_lock); 4129 rdev->pm.vblank_sync = true; 4130 DRM_SPIN_WAKEUP_ONE(&rdev->irq.vblank_queue, &rdev->irq.vblank_lock); 4131 spin_unlock(&rdev->irq.vblank_lock); 4132 #else 4133 rdev->pm.vblank_sync = true; 4134 wake_up(&rdev->irq.vblank_queue); 4135 #endif 4136 } 4137 if (atomic_read(&rdev->irq.pflip[0])) 4138 radeon_crtc_handle_vblank(rdev, 0); 4139 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT; 4140 DRM_DEBUG("IH: D1 vblank\n"); 4141 4142 break; 4143 case 1: /* D1 vline */ 4144 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT)) 4145 DRM_DEBUG("IH: D1 vline - IH event w/o asserted irq bit?\n"); 4146 4147 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT; 4148 DRM_DEBUG("IH: D1 vline\n"); 4149 4150 break; 4151 default: 4152 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 4153 break; 4154 } 4155 break; 4156 case 5: /* D2 vblank/vline */ 4157 switch (src_data) { 4158 case 0: /* D2 vblank */ 4159 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT)) 4160 DRM_DEBUG("IH: D2 vblank - IH event w/o asserted irq bit?\n"); 4161 4162 if (rdev->irq.crtc_vblank_int[1]) { 4163 drm_handle_vblank(rdev->ddev, 1); 4164 #ifdef __NetBSD__ 4165 spin_lock(&rdev->irq.vblank_lock); 4166 rdev->pm.vblank_sync = true; 4167 DRM_SPIN_WAKEUP_ONE(&rdev->irq.vblank_queue, &rdev->irq.vblank_lock); 4168 spin_unlock(&rdev->irq.vblank_lock); 4169 #else 4170 rdev->pm.vblank_sync = true; 4171 wake_up(&rdev->irq.vblank_queue); 4172 #endif 4173 } 4174 if (atomic_read(&rdev->irq.pflip[1])) 4175 radeon_crtc_handle_vblank(rdev, 1); 4176 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT; 4177 DRM_DEBUG("IH: D2 vblank\n"); 4178 4179 break; 4180 case 1: /* D1 vline */ 4181 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT)) 4182 DRM_DEBUG("IH: D2 vline - IH event w/o asserted irq bit?\n"); 4183 4184 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT; 4185 DRM_DEBUG("IH: D2 vline\n"); 4186 4187 break; 4188 default: 4189 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 4190 break; 4191 } 4192 break; 4193 case 9: /* D1 pflip */ 4194 DRM_DEBUG("IH: D1 flip\n"); 4195 if (radeon_use_pflipirq > 0) 4196 radeon_crtc_handle_flip(rdev, 0); 4197 break; 4198 case 11: /* D2 pflip */ 4199 DRM_DEBUG("IH: D2 flip\n"); 4200 if (radeon_use_pflipirq > 0) 4201 radeon_crtc_handle_flip(rdev, 1); 4202 break; 4203 case 19: /* HPD/DAC hotplug */ 4204 switch (src_data) { 4205 case 0: 4206 if (!(rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT)) 4207 DRM_DEBUG("IH: HPD1 - IH event w/o asserted irq bit?\n"); 4208 4209 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT; 4210 queue_hotplug = true; 4211 DRM_DEBUG("IH: HPD1\n"); 4212 break; 4213 case 1: 4214 if (!(rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT)) 4215 DRM_DEBUG("IH: HPD2 - IH event w/o asserted irq bit?\n"); 4216 4217 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT; 4218 queue_hotplug = true; 4219 DRM_DEBUG("IH: HPD2\n"); 4220 break; 4221 case 4: 4222 if (!(rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT)) 4223 DRM_DEBUG("IH: HPD3 - IH event w/o asserted irq bit?\n"); 4224 4225 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT; 4226 queue_hotplug = true; 4227 DRM_DEBUG("IH: HPD3\n"); 4228 break; 4229 case 5: 4230 if (!(rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT)) 4231 DRM_DEBUG("IH: HPD4 - IH event w/o asserted irq bit?\n"); 4232 4233 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT; 4234 queue_hotplug = true; 4235 DRM_DEBUG("IH: HPD4\n"); 4236 break; 4237 case 10: 4238 if (!(rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT)) 4239 DRM_DEBUG("IH: HPD5 - IH event w/o asserted irq bit?\n"); 4240 4241 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT; 4242 queue_hotplug = true; 4243 DRM_DEBUG("IH: HPD5\n"); 4244 break; 4245 case 12: 4246 if (!(rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT)) 4247 DRM_DEBUG("IH: HPD6 - IH event w/o asserted irq bit?\n"); 4248 4249 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT; 4250 queue_hotplug = true; 4251 DRM_DEBUG("IH: HPD6\n"); 4252 4253 break; 4254 default: 4255 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 4256 break; 4257 } 4258 break; 4259 case 21: /* hdmi */ 4260 switch (src_data) { 4261 case 4: 4262 if (!(rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG)) 4263 DRM_DEBUG("IH: HDMI0 - IH event w/o asserted irq bit?\n"); 4264 4265 rdev->irq.stat_regs.r600.hdmi0_status &= ~HDMI0_AZ_FORMAT_WTRIG; 4266 queue_hdmi = true; 4267 DRM_DEBUG("IH: HDMI0\n"); 4268 4269 break; 4270 case 5: 4271 if (!(rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG)) 4272 DRM_DEBUG("IH: HDMI1 - IH event w/o asserted irq bit?\n"); 4273 4274 rdev->irq.stat_regs.r600.hdmi1_status &= ~HDMI0_AZ_FORMAT_WTRIG; 4275 queue_hdmi = true; 4276 DRM_DEBUG("IH: HDMI1\n"); 4277 4278 break; 4279 default: 4280 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data); 4281 break; 4282 } 4283 break; 4284 case 124: /* UVD */ 4285 DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data); 4286 radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX); 4287 break; 4288 case 176: /* CP_INT in ring buffer */ 4289 case 177: /* CP_INT in IB1 */ 4290 case 178: /* CP_INT in IB2 */ 4291 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data); 4292 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); 4293 break; 4294 case 181: /* CP EOP event */ 4295 DRM_DEBUG("IH: CP EOP\n"); 4296 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); 4297 break; 4298 case 224: /* DMA trap event */ 4299 DRM_DEBUG("IH: DMA trap\n"); 4300 radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX); 4301 break; 4302 case 230: /* thermal low to high */ 4303 DRM_DEBUG("IH: thermal low to high\n"); 4304 rdev->pm.dpm.thermal.high_to_low = false; 4305 queue_thermal = true; 4306 break; 4307 case 231: /* thermal high to low */ 4308 DRM_DEBUG("IH: thermal high to low\n"); 4309 rdev->pm.dpm.thermal.high_to_low = true; 4310 queue_thermal = true; 4311 break; 4312 case 233: /* GUI IDLE */ 4313 DRM_DEBUG("IH: GUI idle\n"); 4314 break; 4315 default: 4316 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 4317 break; 4318 } 4319 4320 /* wptr/rptr are in bytes! */ 4321 rptr += 16; 4322 rptr &= rdev->ih.ptr_mask; 4323 WREG32(IH_RB_RPTR, rptr); 4324 } 4325 if (queue_hotplug) 4326 schedule_delayed_work(&rdev->hotplug_work, 0); 4327 if (queue_hdmi) 4328 schedule_work(&rdev->audio_work); 4329 if (queue_thermal && rdev->pm.dpm_enabled) 4330 schedule_work(&rdev->pm.dpm.thermal.work); 4331 rdev->ih.rptr = rptr; 4332 atomic_set(&rdev->ih.lock, 0); 4333 4334 /* make sure wptr hasn't changed while processing */ 4335 wptr = r600_get_ih_wptr(rdev); 4336 if (wptr != rptr) 4337 goto restart_ih; 4338 4339 return IRQ_HANDLED; 4340 } 4341 4342 /* 4343 * Debugfs info 4344 */ 4345 #if defined(CONFIG_DEBUG_FS) 4346 4347 static int r600_debugfs_mc_info(struct seq_file *m, void *data) 4348 { 4349 struct drm_info_node *node = (struct drm_info_node *) m->private; 4350 struct drm_device *dev = node->minor->dev; 4351 struct radeon_device *rdev = dev->dev_private; 4352 4353 DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS); 4354 DREG32_SYS(m, rdev, VM_L2_STATUS); 4355 return 0; 4356 } 4357 4358 static struct drm_info_list r600_mc_info_list[] = { 4359 {"r600_mc_info", r600_debugfs_mc_info, 0, NULL}, 4360 }; 4361 #endif 4362 4363 int r600_debugfs_mc_info_init(struct radeon_device *rdev) 4364 { 4365 #if defined(CONFIG_DEBUG_FS) 4366 return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list)); 4367 #else 4368 return 0; 4369 #endif 4370 } 4371 4372 #ifdef __NetBSD__ 4373 # define __iomem volatile 4374 # define readl fake_readl 4375 #endif 4376 4377 /** 4378 * r600_mmio_hdp_flush - flush Host Data Path cache via MMIO 4379 * rdev: radeon device structure 4380 * 4381 * Some R6XX/R7XX don't seem to take into account HDP flushes performed 4382 * through the ring buffer. This leads to corruption in rendering, see 4383 * http://bugzilla.kernel.org/show_bug.cgi?id=15186 . To avoid this, we 4384 * directly perform the HDP flush by writing the register through MMIO. 4385 */ 4386 void r600_mmio_hdp_flush(struct radeon_device *rdev) 4387 { 4388 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read 4389 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL. 4390 * This seems to cause problems on some AGP cards. Just use the old 4391 * method for them. 4392 */ 4393 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) && 4394 rdev->vram_scratch.ptr && !(rdev->flags & RADEON_IS_AGP)) { 4395 void __iomem *ptr = rdev->vram_scratch.ptr; 4396 4397 WREG32(HDP_DEBUG1, 0); 4398 (void)readl(ptr); 4399 } else 4400 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); 4401 } 4402 4403 #ifdef __NetBSD__ 4404 # undef __iomem 4405 # undef readl 4406 #endif 4407 4408 void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes) 4409 { 4410 u32 link_width_cntl, mask; 4411 4412 if (rdev->flags & RADEON_IS_IGP) 4413 return; 4414 4415 if (!(rdev->flags & RADEON_IS_PCIE)) 4416 return; 4417 4418 /* x2 cards have a special sequence */ 4419 if (ASIC_IS_X2(rdev)) 4420 return; 4421 4422 radeon_gui_idle(rdev); 4423 4424 switch (lanes) { 4425 case 0: 4426 mask = RADEON_PCIE_LC_LINK_WIDTH_X0; 4427 break; 4428 case 1: 4429 mask = RADEON_PCIE_LC_LINK_WIDTH_X1; 4430 break; 4431 case 2: 4432 mask = RADEON_PCIE_LC_LINK_WIDTH_X2; 4433 break; 4434 case 4: 4435 mask = RADEON_PCIE_LC_LINK_WIDTH_X4; 4436 break; 4437 case 8: 4438 mask = RADEON_PCIE_LC_LINK_WIDTH_X8; 4439 break; 4440 case 12: 4441 /* not actually supported */ 4442 mask = RADEON_PCIE_LC_LINK_WIDTH_X12; 4443 break; 4444 case 16: 4445 mask = RADEON_PCIE_LC_LINK_WIDTH_X16; 4446 break; 4447 default: 4448 DRM_ERROR("invalid pcie lane request: %d\n", lanes); 4449 return; 4450 } 4451 4452 link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 4453 link_width_cntl &= ~RADEON_PCIE_LC_LINK_WIDTH_MASK; 4454 link_width_cntl |= mask << RADEON_PCIE_LC_LINK_WIDTH_SHIFT; 4455 link_width_cntl |= (RADEON_PCIE_LC_RECONFIG_NOW | 4456 R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE); 4457 4458 WREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4459 } 4460 4461 int r600_get_pcie_lanes(struct radeon_device *rdev) 4462 { 4463 u32 link_width_cntl; 4464 4465 if (rdev->flags & RADEON_IS_IGP) 4466 return 0; 4467 4468 if (!(rdev->flags & RADEON_IS_PCIE)) 4469 return 0; 4470 4471 /* x2 cards have a special sequence */ 4472 if (ASIC_IS_X2(rdev)) 4473 return 0; 4474 4475 radeon_gui_idle(rdev); 4476 4477 link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 4478 4479 switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) { 4480 case RADEON_PCIE_LC_LINK_WIDTH_X1: 4481 return 1; 4482 case RADEON_PCIE_LC_LINK_WIDTH_X2: 4483 return 2; 4484 case RADEON_PCIE_LC_LINK_WIDTH_X4: 4485 return 4; 4486 case RADEON_PCIE_LC_LINK_WIDTH_X8: 4487 return 8; 4488 case RADEON_PCIE_LC_LINK_WIDTH_X12: 4489 /* not actually supported */ 4490 return 12; 4491 case RADEON_PCIE_LC_LINK_WIDTH_X0: 4492 case RADEON_PCIE_LC_LINK_WIDTH_X16: 4493 default: 4494 return 16; 4495 } 4496 } 4497 4498 static void r600_pcie_gen2_enable(struct radeon_device *rdev) 4499 { 4500 #ifndef __NetBSD__ /* XXX radeon pcie */ 4501 u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp; 4502 u16 link_cntl2; 4503 4504 if (radeon_pcie_gen2 == 0) 4505 return; 4506 4507 if (rdev->flags & RADEON_IS_IGP) 4508 return; 4509 4510 if (!(rdev->flags & RADEON_IS_PCIE)) 4511 return; 4512 4513 /* x2 cards have a special sequence */ 4514 if (ASIC_IS_X2(rdev)) 4515 return; 4516 4517 /* only RV6xx+ chips are supported */ 4518 if (rdev->family <= CHIP_R600) 4519 return; 4520 4521 if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) && 4522 (rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT)) 4523 return; 4524 4525 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 4526 if (speed_cntl & LC_CURRENT_DATA_RATE) { 4527 DRM_INFO("PCIE gen 2 link speeds already enabled\n"); 4528 return; 4529 } 4530 4531 DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n"); 4532 4533 /* 55 nm r6xx asics */ 4534 if ((rdev->family == CHIP_RV670) || 4535 (rdev->family == CHIP_RV620) || 4536 (rdev->family == CHIP_RV635)) { 4537 /* advertise upconfig capability */ 4538 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); 4539 link_width_cntl &= ~LC_UPCONFIGURE_DIS; 4540 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4541 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); 4542 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) { 4543 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT; 4544 link_width_cntl &= ~(LC_LINK_WIDTH_MASK | 4545 LC_RECONFIG_ARC_MISSING_ESCAPE); 4546 link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN; 4547 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4548 } else { 4549 link_width_cntl |= LC_UPCONFIGURE_DIS; 4550 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4551 } 4552 } 4553 4554 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 4555 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) && 4556 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) { 4557 4558 /* 55 nm r6xx asics */ 4559 if ((rdev->family == CHIP_RV670) || 4560 (rdev->family == CHIP_RV620) || 4561 (rdev->family == CHIP_RV635)) { 4562 WREG32(MM_CFGREGS_CNTL, 0x8); 4563 link_cntl2 = RREG32(0x4088); 4564 WREG32(MM_CFGREGS_CNTL, 0); 4565 /* not supported yet */ 4566 if (link_cntl2 & SELECTABLE_DEEMPHASIS) 4567 return; 4568 } 4569 4570 speed_cntl &= ~LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK; 4571 speed_cntl |= (0x3 << LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT); 4572 speed_cntl &= ~LC_VOLTAGE_TIMER_SEL_MASK; 4573 speed_cntl &= ~LC_FORCE_DIS_HW_SPEED_CHANGE; 4574 speed_cntl |= LC_FORCE_EN_HW_SPEED_CHANGE; 4575 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); 4576 4577 tmp = RREG32(0x541c); 4578 WREG32(0x541c, tmp | 0x8); 4579 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN); 4580 link_cntl2 = RREG16(0x4088); 4581 link_cntl2 &= ~TARGET_LINK_SPEED_MASK; 4582 link_cntl2 |= 0x2; 4583 WREG16(0x4088, link_cntl2); 4584 WREG32(MM_CFGREGS_CNTL, 0); 4585 4586 if ((rdev->family == CHIP_RV670) || 4587 (rdev->family == CHIP_RV620) || 4588 (rdev->family == CHIP_RV635)) { 4589 training_cntl = RREG32_PCIE_PORT(PCIE_LC_TRAINING_CNTL); 4590 training_cntl &= ~LC_POINT_7_PLUS_EN; 4591 WREG32_PCIE_PORT(PCIE_LC_TRAINING_CNTL, training_cntl); 4592 } else { 4593 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 4594 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN; 4595 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); 4596 } 4597 4598 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 4599 speed_cntl |= LC_GEN2_EN_STRAP; 4600 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); 4601 4602 } else { 4603 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); 4604 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */ 4605 if (1) 4606 link_width_cntl |= LC_UPCONFIGURE_DIS; 4607 else 4608 link_width_cntl &= ~LC_UPCONFIGURE_DIS; 4609 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4610 } 4611 #endif 4612 } 4613 4614 /** 4615 * r600_get_gpu_clock_counter - return GPU clock counter snapshot 4616 * 4617 * @rdev: radeon_device pointer 4618 * 4619 * Fetches a GPU clock counter snapshot (R6xx-cayman). 4620 * Returns the 64 bit clock counter snapshot. 4621 */ 4622 uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev) 4623 { 4624 uint64_t clock; 4625 4626 mutex_lock(&rdev->gpu_clock_mutex); 4627 WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1); 4628 clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) | 4629 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 4630 mutex_unlock(&rdev->gpu_clock_mutex); 4631 return clock; 4632 } 4633
Indexes created Sat Oct 25 01:09:55 GMT 2025