radeon_r600.c revision 1.1.6.4
1 /* $NetBSD: radeon_r600.c,v 1.1.6.4 2020/04/13 08:04:58 martin Exp $ */ 2 3 /* 4 * Copyright 2008 Advanced Micro Devices, Inc. 5 * Copyright 2008 Red Hat Inc. 6 * Copyright 2009 Jerome Glisse. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: Dave Airlie 27 * Alex Deucher 28 * Jerome Glisse 29 */ 30 #include <sys/cdefs.h> 31 __KERNEL_RCSID(0, "$NetBSD: radeon_r600.c,v 1.1.6.4 2020/04/13 08:04:58 martin Exp $"); 32 33 #include <linux/slab.h> 34 #include <linux/seq_file.h> 35 #include <linux/firmware.h> 36 #include <linux/module.h> 37 #include <drm/drmP.h> 38 #include <drm/radeon_drm.h> 39 #include "radeon.h" 40 #include "radeon_asic.h" 41 #include "radeon_audio.h" 42 #include "radeon_mode.h" 43 #include "r600d.h" 44 #include "atom.h" 45 #include "avivod.h" 46 #include "radeon_ucode.h" 47 48 #include <linux/nbsd-namespace.h> 49 50 /* Firmware Names */ 51 MODULE_FIRMWARE("radeon/R600_pfp.bin"); 52 MODULE_FIRMWARE("radeon/R600_me.bin"); 53 MODULE_FIRMWARE("radeon/RV610_pfp.bin"); 54 MODULE_FIRMWARE("radeon/RV610_me.bin"); 55 MODULE_FIRMWARE("radeon/RV630_pfp.bin"); 56 MODULE_FIRMWARE("radeon/RV630_me.bin"); 57 MODULE_FIRMWARE("radeon/RV620_pfp.bin"); 58 MODULE_FIRMWARE("radeon/RV620_me.bin"); 59 MODULE_FIRMWARE("radeon/RV635_pfp.bin"); 60 MODULE_FIRMWARE("radeon/RV635_me.bin"); 61 MODULE_FIRMWARE("radeon/RV670_pfp.bin"); 62 MODULE_FIRMWARE("radeon/RV670_me.bin"); 63 MODULE_FIRMWARE("radeon/RS780_pfp.bin"); 64 MODULE_FIRMWARE("radeon/RS780_me.bin"); 65 MODULE_FIRMWARE("radeon/RV770_pfp.bin"); 66 MODULE_FIRMWARE("radeon/RV770_me.bin"); 67 MODULE_FIRMWARE("radeon/RV770_smc.bin"); 68 MODULE_FIRMWARE("radeon/RV730_pfp.bin"); 69 MODULE_FIRMWARE("radeon/RV730_me.bin"); 70 MODULE_FIRMWARE("radeon/RV730_smc.bin"); 71 MODULE_FIRMWARE("radeon/RV740_smc.bin"); 72 MODULE_FIRMWARE("radeon/RV710_pfp.bin"); 73 MODULE_FIRMWARE("radeon/RV710_me.bin"); 74 MODULE_FIRMWARE("radeon/RV710_smc.bin"); 75 MODULE_FIRMWARE("radeon/R600_rlc.bin"); 76 MODULE_FIRMWARE("radeon/R700_rlc.bin"); 77 MODULE_FIRMWARE("radeon/CEDAR_pfp.bin"); 78 MODULE_FIRMWARE("radeon/CEDAR_me.bin"); 79 MODULE_FIRMWARE("radeon/CEDAR_rlc.bin"); 80 MODULE_FIRMWARE("radeon/CEDAR_smc.bin"); 81 MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin"); 82 MODULE_FIRMWARE("radeon/REDWOOD_me.bin"); 83 MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin"); 84 MODULE_FIRMWARE("radeon/REDWOOD_smc.bin"); 85 MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin"); 86 MODULE_FIRMWARE("radeon/JUNIPER_me.bin"); 87 MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin"); 88 MODULE_FIRMWARE("radeon/JUNIPER_smc.bin"); 89 MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin"); 90 MODULE_FIRMWARE("radeon/CYPRESS_me.bin"); 91 MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin"); 92 MODULE_FIRMWARE("radeon/CYPRESS_smc.bin"); 93 MODULE_FIRMWARE("radeon/PALM_pfp.bin"); 94 MODULE_FIRMWARE("radeon/PALM_me.bin"); 95 MODULE_FIRMWARE("radeon/SUMO_rlc.bin"); 96 MODULE_FIRMWARE("radeon/SUMO_pfp.bin"); 97 MODULE_FIRMWARE("radeon/SUMO_me.bin"); 98 MODULE_FIRMWARE("radeon/SUMO2_pfp.bin"); 99 MODULE_FIRMWARE("radeon/SUMO2_me.bin"); 100 101 static const u32 crtc_offsets[2] = 102 { 103 0, 104 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL 105 }; 106 107 int r600_debugfs_mc_info_init(struct radeon_device *rdev); 108 109 /* r600,rv610,rv630,rv620,rv635,rv670 */ 110 int r600_mc_wait_for_idle(struct radeon_device *rdev); 111 static void r600_gpu_init(struct radeon_device *rdev); 112 void r600_fini(struct radeon_device *rdev); 113 void r600_irq_disable(struct radeon_device *rdev); 114 static void r600_pcie_gen2_enable(struct radeon_device *rdev); 115 extern int evergreen_rlc_resume(struct radeon_device *rdev); 116 extern void rv770_set_clk_bypass_mode(struct radeon_device *rdev); 117 118 /* 119 * Indirect registers accessor 120 */ 121 u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg) 122 { 123 unsigned long flags; 124 u32 r; 125 126 spin_lock_irqsave(&rdev->rcu_idx_lock, flags); 127 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff)); 128 r = RREG32(R600_RCU_DATA); 129 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags); 130 return r; 131 } 132 133 void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v) 134 { 135 unsigned long flags; 136 137 spin_lock_irqsave(&rdev->rcu_idx_lock, flags); 138 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff)); 139 WREG32(R600_RCU_DATA, (v)); 140 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags); 141 } 142 143 u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg) 144 { 145 unsigned long flags; 146 u32 r; 147 148 spin_lock_irqsave(&rdev->uvd_idx_lock, flags); 149 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff)); 150 r = RREG32(R600_UVD_CTX_DATA); 151 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags); 152 return r; 153 } 154 155 void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v) 156 { 157 unsigned long flags; 158 159 spin_lock_irqsave(&rdev->uvd_idx_lock, flags); 160 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff)); 161 WREG32(R600_UVD_CTX_DATA, (v)); 162 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags); 163 } 164 165 /** 166 * r600_get_allowed_info_register - fetch the register for the info ioctl 167 * 168 * @rdev: radeon_device pointer 169 * @reg: register offset in bytes 170 * @val: register value 171 * 172 * Returns 0 for success or -EINVAL for an invalid register 173 * 174 */ 175 int r600_get_allowed_info_register(struct radeon_device *rdev, 176 u32 reg, u32 *val) 177 { 178 switch (reg) { 179 case GRBM_STATUS: 180 case GRBM_STATUS2: 181 case R_000E50_SRBM_STATUS: 182 case DMA_STATUS_REG: 183 case UVD_STATUS: 184 *val = RREG32(reg); 185 return 0; 186 default: 187 return -EINVAL; 188 } 189 } 190 191 /** 192 * r600_get_xclk - get the xclk 193 * 194 * @rdev: radeon_device pointer 195 * 196 * Returns the reference clock used by the gfx engine 197 * (r6xx, IGPs, APUs). 198 */ 199 u32 r600_get_xclk(struct radeon_device *rdev) 200 { 201 return rdev->clock.spll.reference_freq; 202 } 203 204 int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) 205 { 206 unsigned fb_div = 0, ref_div, vclk_div = 0, dclk_div = 0; 207 int r; 208 209 /* bypass vclk and dclk with bclk */ 210 WREG32_P(CG_UPLL_FUNC_CNTL_2, 211 VCLK_SRC_SEL(1) | DCLK_SRC_SEL(1), 212 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK)); 213 214 /* assert BYPASS_EN, deassert UPLL_RESET, UPLL_SLEEP and UPLL_CTLREQ */ 215 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~( 216 UPLL_RESET_MASK | UPLL_SLEEP_MASK | UPLL_CTLREQ_MASK)); 217 218 if (rdev->family >= CHIP_RS780) 219 WREG32_P(GFX_MACRO_BYPASS_CNTL, UPLL_BYPASS_CNTL, 220 ~UPLL_BYPASS_CNTL); 221 222 if (!vclk || !dclk) { 223 /* keep the Bypass mode, put PLL to sleep */ 224 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK); 225 return 0; 226 } 227 228 if (rdev->clock.spll.reference_freq == 10000) 229 ref_div = 34; 230 else 231 ref_div = 4; 232 233 r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 50000, 160000, 234 ref_div + 1, 0xFFF, 2, 30, ~0, 235 &fb_div, &vclk_div, &dclk_div); 236 if (r) 237 return r; 238 239 if (rdev->family >= CHIP_RV670 && rdev->family < CHIP_RS780) 240 fb_div >>= 1; 241 else 242 fb_div |= 1; 243 244 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL); 245 if (r) 246 return r; 247 248 /* assert PLL_RESET */ 249 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK); 250 251 /* For RS780 we have to choose ref clk */ 252 if (rdev->family >= CHIP_RS780) 253 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_REFCLK_SRC_SEL_MASK, 254 ~UPLL_REFCLK_SRC_SEL_MASK); 255 256 /* set the required fb, ref and post divder values */ 257 WREG32_P(CG_UPLL_FUNC_CNTL, 258 UPLL_FB_DIV(fb_div) | 259 UPLL_REF_DIV(ref_div), 260 ~(UPLL_FB_DIV_MASK | UPLL_REF_DIV_MASK)); 261 WREG32_P(CG_UPLL_FUNC_CNTL_2, 262 UPLL_SW_HILEN(vclk_div >> 1) | 263 UPLL_SW_LOLEN((vclk_div >> 1) + (vclk_div & 1)) | 264 UPLL_SW_HILEN2(dclk_div >> 1) | 265 UPLL_SW_LOLEN2((dclk_div >> 1) + (dclk_div & 1)) | 266 UPLL_DIVEN_MASK | UPLL_DIVEN2_MASK, 267 ~UPLL_SW_MASK); 268 269 /* give the PLL some time to settle */ 270 mdelay(15); 271 272 /* deassert PLL_RESET */ 273 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); 274 275 mdelay(15); 276 277 /* deassert BYPASS EN */ 278 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK); 279 280 if (rdev->family >= CHIP_RS780) 281 WREG32_P(GFX_MACRO_BYPASS_CNTL, 0, ~UPLL_BYPASS_CNTL); 282 283 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL); 284 if (r) 285 return r; 286 287 /* switch VCLK and DCLK selection */ 288 WREG32_P(CG_UPLL_FUNC_CNTL_2, 289 VCLK_SRC_SEL(2) | DCLK_SRC_SEL(2), 290 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK)); 291 292 mdelay(100); 293 294 return 0; 295 } 296 297 void dce3_program_fmt(struct drm_encoder *encoder) 298 { 299 struct drm_device *dev = encoder->dev; 300 struct radeon_device *rdev = dev->dev_private; 301 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 302 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 303 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 304 int bpc = 0; 305 u32 tmp = 0; 306 enum radeon_connector_dither dither = RADEON_FMT_DITHER_DISABLE; 307 308 if (connector) { 309 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 310 bpc = radeon_get_monitor_bpc(connector); 311 dither = radeon_connector->dither; 312 } 313 314 /* LVDS FMT is set up by atom */ 315 if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) 316 return; 317 318 /* not needed for analog */ 319 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) || 320 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2)) 321 return; 322 323 if (bpc == 0) 324 return; 325 326 switch (bpc) { 327 case 6: 328 if (dither == RADEON_FMT_DITHER_ENABLE) 329 /* XXX sort out optimal dither settings */ 330 tmp |= FMT_SPATIAL_DITHER_EN; 331 else 332 tmp |= FMT_TRUNCATE_EN; 333 break; 334 case 8: 335 if (dither == RADEON_FMT_DITHER_ENABLE) 336 /* XXX sort out optimal dither settings */ 337 tmp |= (FMT_SPATIAL_DITHER_EN | FMT_SPATIAL_DITHER_DEPTH); 338 else 339 tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH); 340 break; 341 case 10: 342 default: 343 /* not needed */ 344 break; 345 } 346 347 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp); 348 } 349 350 /* get temperature in millidegrees */ 351 int rv6xx_get_temp(struct radeon_device *rdev) 352 { 353 u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >> 354 ASIC_T_SHIFT; 355 int actual_temp = temp & 0xff; 356 357 if (temp & 0x100) 358 actual_temp -= 256; 359 360 return actual_temp * 1000; 361 } 362 363 void r600_pm_get_dynpm_state(struct radeon_device *rdev) 364 { 365 int i; 366 367 rdev->pm.dynpm_can_upclock = true; 368 rdev->pm.dynpm_can_downclock = true; 369 370 /* power state array is low to high, default is first */ 371 if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) { 372 int min_power_state_index = 0; 373 374 if (rdev->pm.num_power_states > 2) 375 min_power_state_index = 1; 376 377 switch (rdev->pm.dynpm_planned_action) { 378 case DYNPM_ACTION_MINIMUM: 379 rdev->pm.requested_power_state_index = min_power_state_index; 380 rdev->pm.requested_clock_mode_index = 0; 381 rdev->pm.dynpm_can_downclock = false; 382 break; 383 case DYNPM_ACTION_DOWNCLOCK: 384 if (rdev->pm.current_power_state_index == min_power_state_index) { 385 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 386 rdev->pm.dynpm_can_downclock = false; 387 } else { 388 if (rdev->pm.active_crtc_count > 1) { 389 for (i = 0; i < rdev->pm.num_power_states; i++) { 390 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 391 continue; 392 else if (i >= rdev->pm.current_power_state_index) { 393 rdev->pm.requested_power_state_index = 394 rdev->pm.current_power_state_index; 395 break; 396 } else { 397 rdev->pm.requested_power_state_index = i; 398 break; 399 } 400 } 401 } else { 402 if (rdev->pm.current_power_state_index == 0) 403 rdev->pm.requested_power_state_index = 404 rdev->pm.num_power_states - 1; 405 else 406 rdev->pm.requested_power_state_index = 407 rdev->pm.current_power_state_index - 1; 408 } 409 } 410 rdev->pm.requested_clock_mode_index = 0; 411 /* don't use the power state if crtcs are active and no display flag is set */ 412 if ((rdev->pm.active_crtc_count > 0) && 413 (rdev->pm.power_state[rdev->pm.requested_power_state_index]. 414 clock_info[rdev->pm.requested_clock_mode_index].flags & 415 RADEON_PM_MODE_NO_DISPLAY)) { 416 rdev->pm.requested_power_state_index++; 417 } 418 break; 419 case DYNPM_ACTION_UPCLOCK: 420 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) { 421 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 422 rdev->pm.dynpm_can_upclock = false; 423 } else { 424 if (rdev->pm.active_crtc_count > 1) { 425 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) { 426 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 427 continue; 428 else if (i <= rdev->pm.current_power_state_index) { 429 rdev->pm.requested_power_state_index = 430 rdev->pm.current_power_state_index; 431 break; 432 } else { 433 rdev->pm.requested_power_state_index = i; 434 break; 435 } 436 } 437 } else 438 rdev->pm.requested_power_state_index = 439 rdev->pm.current_power_state_index + 1; 440 } 441 rdev->pm.requested_clock_mode_index = 0; 442 break; 443 case DYNPM_ACTION_DEFAULT: 444 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; 445 rdev->pm.requested_clock_mode_index = 0; 446 rdev->pm.dynpm_can_upclock = false; 447 break; 448 case DYNPM_ACTION_NONE: 449 default: 450 DRM_ERROR("Requested mode for not defined action\n"); 451 return; 452 } 453 } else { 454 /* XXX select a power state based on AC/DC, single/dualhead, etc. */ 455 /* for now just select the first power state and switch between clock modes */ 456 /* power state array is low to high, default is first (0) */ 457 if (rdev->pm.active_crtc_count > 1) { 458 rdev->pm.requested_power_state_index = -1; 459 /* start at 1 as we don't want the default mode */ 460 for (i = 1; i < rdev->pm.num_power_states; i++) { 461 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 462 continue; 463 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) || 464 (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) { 465 rdev->pm.requested_power_state_index = i; 466 break; 467 } 468 } 469 /* if nothing selected, grab the default state. */ 470 if (rdev->pm.requested_power_state_index == -1) 471 rdev->pm.requested_power_state_index = 0; 472 } else 473 rdev->pm.requested_power_state_index = 1; 474 475 switch (rdev->pm.dynpm_planned_action) { 476 case DYNPM_ACTION_MINIMUM: 477 rdev->pm.requested_clock_mode_index = 0; 478 rdev->pm.dynpm_can_downclock = false; 479 break; 480 case DYNPM_ACTION_DOWNCLOCK: 481 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) { 482 if (rdev->pm.current_clock_mode_index == 0) { 483 rdev->pm.requested_clock_mode_index = 0; 484 rdev->pm.dynpm_can_downclock = false; 485 } else 486 rdev->pm.requested_clock_mode_index = 487 rdev->pm.current_clock_mode_index - 1; 488 } else { 489 rdev->pm.requested_clock_mode_index = 0; 490 rdev->pm.dynpm_can_downclock = false; 491 } 492 /* don't use the power state if crtcs are active and no display flag is set */ 493 if ((rdev->pm.active_crtc_count > 0) && 494 (rdev->pm.power_state[rdev->pm.requested_power_state_index]. 495 clock_info[rdev->pm.requested_clock_mode_index].flags & 496 RADEON_PM_MODE_NO_DISPLAY)) { 497 rdev->pm.requested_clock_mode_index++; 498 } 499 break; 500 case DYNPM_ACTION_UPCLOCK: 501 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) { 502 if (rdev->pm.current_clock_mode_index == 503 (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) { 504 rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index; 505 rdev->pm.dynpm_can_upclock = false; 506 } else 507 rdev->pm.requested_clock_mode_index = 508 rdev->pm.current_clock_mode_index + 1; 509 } else { 510 rdev->pm.requested_clock_mode_index = 511 rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1; 512 rdev->pm.dynpm_can_upclock = false; 513 } 514 break; 515 case DYNPM_ACTION_DEFAULT: 516 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; 517 rdev->pm.requested_clock_mode_index = 0; 518 rdev->pm.dynpm_can_upclock = false; 519 break; 520 case DYNPM_ACTION_NONE: 521 default: 522 DRM_ERROR("Requested mode for not defined action\n"); 523 return; 524 } 525 } 526 527 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n", 528 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 529 clock_info[rdev->pm.requested_clock_mode_index].sclk, 530 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 531 clock_info[rdev->pm.requested_clock_mode_index].mclk, 532 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 533 pcie_lanes); 534 } 535 536 void rs780_pm_init_profile(struct radeon_device *rdev) 537 { 538 if (rdev->pm.num_power_states == 2) { 539 /* default */ 540 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 541 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 542 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 543 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 544 /* low sh */ 545 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0; 546 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0; 547 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 548 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 549 /* mid sh */ 550 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0; 551 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0; 552 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 553 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 554 /* high sh */ 555 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0; 556 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1; 557 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 558 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 559 /* low mh */ 560 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0; 561 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0; 562 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 563 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 564 /* mid mh */ 565 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0; 566 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0; 567 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 568 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 569 /* high mh */ 570 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0; 571 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1; 572 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 573 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 574 } else if (rdev->pm.num_power_states == 3) { 575 /* default */ 576 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 577 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 578 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 579 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 580 /* low sh */ 581 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1; 582 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1; 583 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 584 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 585 /* mid sh */ 586 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1; 587 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; 588 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 589 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 590 /* high sh */ 591 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1; 592 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2; 593 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 594 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 595 /* low mh */ 596 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1; 597 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1; 598 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 599 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 600 /* mid mh */ 601 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1; 602 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1; 603 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 604 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 605 /* high mh */ 606 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1; 607 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2; 608 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 609 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 610 } else { 611 /* default */ 612 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 613 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 614 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 615 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 616 /* low sh */ 617 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2; 618 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2; 619 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 620 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 621 /* mid sh */ 622 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2; 623 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2; 624 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 625 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 626 /* high sh */ 627 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2; 628 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3; 629 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 630 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 631 /* low mh */ 632 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2; 633 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0; 634 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 635 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 636 /* mid mh */ 637 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2; 638 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0; 639 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 640 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 641 /* high mh */ 642 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2; 643 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3; 644 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 645 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 646 } 647 } 648 649 void r600_pm_init_profile(struct radeon_device *rdev) 650 { 651 int idx; 652 653 if (rdev->family == CHIP_R600) { 654 /* XXX */ 655 /* default */ 656 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 657 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 658 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 659 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 660 /* low sh */ 661 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 662 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 663 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 664 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 665 /* mid sh */ 666 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 667 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 668 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 669 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 670 /* high sh */ 671 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 672 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 673 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 674 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 675 /* low mh */ 676 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 677 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 678 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 679 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 680 /* mid mh */ 681 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 682 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 683 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 684 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 685 /* high mh */ 686 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 687 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 688 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 689 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 690 } else { 691 if (rdev->pm.num_power_states < 4) { 692 /* default */ 693 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 694 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 695 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 696 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2; 697 /* low sh */ 698 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1; 699 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1; 700 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 701 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 702 /* mid sh */ 703 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1; 704 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; 705 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 706 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1; 707 /* high sh */ 708 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1; 709 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1; 710 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 711 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2; 712 /* low mh */ 713 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2; 714 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2; 715 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 716 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 717 /* low mh */ 718 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2; 719 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2; 720 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 721 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1; 722 /* high mh */ 723 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2; 724 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2; 725 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 726 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2; 727 } else { 728 /* default */ 729 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 730 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 731 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 732 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2; 733 /* low sh */ 734 if (rdev->flags & RADEON_IS_MOBILITY) 735 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0); 736 else 737 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); 738 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx; 739 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx; 740 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 741 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 742 /* mid sh */ 743 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx; 744 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx; 745 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 746 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1; 747 /* high sh */ 748 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); 749 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx; 750 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx; 751 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 752 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2; 753 /* low mh */ 754 if (rdev->flags & RADEON_IS_MOBILITY) 755 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1); 756 else 757 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1); 758 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx; 759 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx; 760 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 761 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 762 /* mid mh */ 763 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx; 764 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx; 765 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 766 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1; 767 /* high mh */ 768 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1); 769 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx; 770 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx; 771 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 772 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2; 773 } 774 } 775 } 776 777 void r600_pm_misc(struct radeon_device *rdev) 778 { 779 int req_ps_idx = rdev->pm.requested_power_state_index; 780 int req_cm_idx = rdev->pm.requested_clock_mode_index; 781 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx]; 782 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage; 783 784 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) { 785 /* 0xff01 is a flag rather then an actual voltage */ 786 if (voltage->voltage == 0xff01) 787 return; 788 if (voltage->voltage != rdev->pm.current_vddc) { 789 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC); 790 rdev->pm.current_vddc = voltage->voltage; 791 DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage->voltage); 792 } 793 } 794 } 795 796 bool r600_gui_idle(struct radeon_device *rdev) 797 { 798 if (RREG32(GRBM_STATUS) & GUI_ACTIVE) 799 return false; 800 else 801 return true; 802 } 803 804 /* hpd for digital panel detect/disconnect */ 805 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) 806 { 807 bool connected = false; 808 809 if (ASIC_IS_DCE3(rdev)) { 810 switch (hpd) { 811 case RADEON_HPD_1: 812 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE) 813 connected = true; 814 break; 815 case RADEON_HPD_2: 816 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE) 817 connected = true; 818 break; 819 case RADEON_HPD_3: 820 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE) 821 connected = true; 822 break; 823 case RADEON_HPD_4: 824 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE) 825 connected = true; 826 break; 827 /* DCE 3.2 */ 828 case RADEON_HPD_5: 829 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE) 830 connected = true; 831 break; 832 case RADEON_HPD_6: 833 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE) 834 connected = true; 835 break; 836 default: 837 break; 838 } 839 } else { 840 switch (hpd) { 841 case RADEON_HPD_1: 842 if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) 843 connected = true; 844 break; 845 case RADEON_HPD_2: 846 if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) 847 connected = true; 848 break; 849 case RADEON_HPD_3: 850 if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) 851 connected = true; 852 break; 853 default: 854 break; 855 } 856 } 857 return connected; 858 } 859 860 void r600_hpd_set_polarity(struct radeon_device *rdev, 861 enum radeon_hpd_id hpd) 862 { 863 u32 tmp; 864 bool connected = r600_hpd_sense(rdev, hpd); 865 866 if (ASIC_IS_DCE3(rdev)) { 867 switch (hpd) { 868 case RADEON_HPD_1: 869 tmp = RREG32(DC_HPD1_INT_CONTROL); 870 if (connected) 871 tmp &= ~DC_HPDx_INT_POLARITY; 872 else 873 tmp |= DC_HPDx_INT_POLARITY; 874 WREG32(DC_HPD1_INT_CONTROL, tmp); 875 break; 876 case RADEON_HPD_2: 877 tmp = RREG32(DC_HPD2_INT_CONTROL); 878 if (connected) 879 tmp &= ~DC_HPDx_INT_POLARITY; 880 else 881 tmp |= DC_HPDx_INT_POLARITY; 882 WREG32(DC_HPD2_INT_CONTROL, tmp); 883 break; 884 case RADEON_HPD_3: 885 tmp = RREG32(DC_HPD3_INT_CONTROL); 886 if (connected) 887 tmp &= ~DC_HPDx_INT_POLARITY; 888 else 889 tmp |= DC_HPDx_INT_POLARITY; 890 WREG32(DC_HPD3_INT_CONTROL, tmp); 891 break; 892 case RADEON_HPD_4: 893 tmp = RREG32(DC_HPD4_INT_CONTROL); 894 if (connected) 895 tmp &= ~DC_HPDx_INT_POLARITY; 896 else 897 tmp |= DC_HPDx_INT_POLARITY; 898 WREG32(DC_HPD4_INT_CONTROL, tmp); 899 break; 900 case RADEON_HPD_5: 901 tmp = RREG32(DC_HPD5_INT_CONTROL); 902 if (connected) 903 tmp &= ~DC_HPDx_INT_POLARITY; 904 else 905 tmp |= DC_HPDx_INT_POLARITY; 906 WREG32(DC_HPD5_INT_CONTROL, tmp); 907 break; 908 /* DCE 3.2 */ 909 case RADEON_HPD_6: 910 tmp = RREG32(DC_HPD6_INT_CONTROL); 911 if (connected) 912 tmp &= ~DC_HPDx_INT_POLARITY; 913 else 914 tmp |= DC_HPDx_INT_POLARITY; 915 WREG32(DC_HPD6_INT_CONTROL, tmp); 916 break; 917 default: 918 break; 919 } 920 } else { 921 switch (hpd) { 922 case RADEON_HPD_1: 923 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL); 924 if (connected) 925 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; 926 else 927 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; 928 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); 929 break; 930 case RADEON_HPD_2: 931 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL); 932 if (connected) 933 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; 934 else 935 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; 936 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); 937 break; 938 case RADEON_HPD_3: 939 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL); 940 if (connected) 941 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; 942 else 943 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; 944 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); 945 break; 946 default: 947 break; 948 } 949 } 950 } 951 952 void r600_hpd_init(struct radeon_device *rdev) 953 { 954 struct drm_device *dev = rdev->ddev; 955 struct drm_connector *connector; 956 unsigned enable = 0; 957 958 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 959 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 960 961 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || 962 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { 963 /* don't try to enable hpd on eDP or LVDS avoid breaking the 964 * aux dp channel on imac and help (but not completely fix) 965 * https://bugzilla.redhat.com/show_bug.cgi?id=726143 966 */ 967 continue; 968 } 969 if (ASIC_IS_DCE3(rdev)) { 970 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa); 971 if (ASIC_IS_DCE32(rdev)) 972 tmp |= DC_HPDx_EN; 973 974 switch (radeon_connector->hpd.hpd) { 975 case RADEON_HPD_1: 976 WREG32(DC_HPD1_CONTROL, tmp); 977 break; 978 case RADEON_HPD_2: 979 WREG32(DC_HPD2_CONTROL, tmp); 980 break; 981 case RADEON_HPD_3: 982 WREG32(DC_HPD3_CONTROL, tmp); 983 break; 984 case RADEON_HPD_4: 985 WREG32(DC_HPD4_CONTROL, tmp); 986 break; 987 /* DCE 3.2 */ 988 case RADEON_HPD_5: 989 WREG32(DC_HPD5_CONTROL, tmp); 990 break; 991 case RADEON_HPD_6: 992 WREG32(DC_HPD6_CONTROL, tmp); 993 break; 994 default: 995 break; 996 } 997 } else { 998 switch (radeon_connector->hpd.hpd) { 999 case RADEON_HPD_1: 1000 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN); 1001 break; 1002 case RADEON_HPD_2: 1003 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN); 1004 break; 1005 case RADEON_HPD_3: 1006 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN); 1007 break; 1008 default: 1009 break; 1010 } 1011 } 1012 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) 1013 enable |= 1 << radeon_connector->hpd.hpd; 1014 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); 1015 } 1016 radeon_irq_kms_enable_hpd(rdev, enable); 1017 } 1018 1019 void r600_hpd_fini(struct radeon_device *rdev) 1020 { 1021 struct drm_device *dev = rdev->ddev; 1022 struct drm_connector *connector; 1023 unsigned disable = 0; 1024 1025 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 1026 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1027 if (ASIC_IS_DCE3(rdev)) { 1028 switch (radeon_connector->hpd.hpd) { 1029 case RADEON_HPD_1: 1030 WREG32(DC_HPD1_CONTROL, 0); 1031 break; 1032 case RADEON_HPD_2: 1033 WREG32(DC_HPD2_CONTROL, 0); 1034 break; 1035 case RADEON_HPD_3: 1036 WREG32(DC_HPD3_CONTROL, 0); 1037 break; 1038 case RADEON_HPD_4: 1039 WREG32(DC_HPD4_CONTROL, 0); 1040 break; 1041 /* DCE 3.2 */ 1042 case RADEON_HPD_5: 1043 WREG32(DC_HPD5_CONTROL, 0); 1044 break; 1045 case RADEON_HPD_6: 1046 WREG32(DC_HPD6_CONTROL, 0); 1047 break; 1048 default: 1049 break; 1050 } 1051 } else { 1052 switch (radeon_connector->hpd.hpd) { 1053 case RADEON_HPD_1: 1054 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0); 1055 break; 1056 case RADEON_HPD_2: 1057 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0); 1058 break; 1059 case RADEON_HPD_3: 1060 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0); 1061 break; 1062 default: 1063 break; 1064 } 1065 } 1066 disable |= 1 << radeon_connector->hpd.hpd; 1067 } 1068 radeon_irq_kms_disable_hpd(rdev, disable); 1069 } 1070 1071 #ifdef __NetBSD__ 1072 /* 1073 * XXX Can't use bus_space here because this is all mapped through the 1074 * radeon_bo abstraction. Can't assume we're x86 because this is 1075 * AMD/ATI Radeon, not Intel. 1076 */ 1077 1078 # define __iomem volatile 1079 # define readl fake_readl 1080 1081 static inline uint32_t 1082 fake_readl(const void __iomem *ptr) 1083 { 1084 uint32_t v; 1085 1086 v = *(const uint32_t __iomem *)ptr; 1087 membar_consumer(); 1088 1089 return v; 1090 } 1091 #endif 1092 1093 /* 1094 * R600 PCIE GART 1095 */ 1096 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev) 1097 { 1098 unsigned i; 1099 u32 tmp; 1100 1101 /* flush hdp cache so updates hit vram */ 1102 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) && 1103 !(rdev->flags & RADEON_IS_AGP)) { 1104 void __iomem *ptr = rdev->gart.ptr; 1105 1106 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read 1107 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL 1108 * This seems to cause problems on some AGP cards. Just use the old 1109 * method for them. 1110 */ 1111 WREG32(HDP_DEBUG1, 0); 1112 (void)readl(ptr); 1113 } else 1114 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); 1115 1116 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12); 1117 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12); 1118 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1)); 1119 for (i = 0; i < rdev->usec_timeout; i++) { 1120 /* read MC_STATUS */ 1121 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE); 1122 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT; 1123 if (tmp == 2) { 1124 printk(KERN_WARNING "[drm] r600 flush TLB failed\n"); 1125 return; 1126 } 1127 if (tmp) { 1128 return; 1129 } 1130 udelay(1); 1131 } 1132 } 1133 1134 #ifdef __NetBSD__ 1135 # undef __iomem 1136 # undef readl 1137 #endif 1138 1139 int r600_pcie_gart_init(struct radeon_device *rdev) 1140 { 1141 int r; 1142 1143 if (rdev->gart.robj) { 1144 WARN(1, "R600 PCIE GART already initialized\n"); 1145 return 0; 1146 } 1147 /* Initialize common gart structure */ 1148 r = radeon_gart_init(rdev); 1149 if (r) 1150 return r; 1151 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; 1152 return radeon_gart_table_vram_alloc(rdev); 1153 } 1154 1155 static int r600_pcie_gart_enable(struct radeon_device *rdev) 1156 { 1157 u32 tmp; 1158 int r, i; 1159 1160 if (rdev->gart.robj == NULL) { 1161 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); 1162 return -EINVAL; 1163 } 1164 r = radeon_gart_table_vram_pin(rdev); 1165 if (r) 1166 return r; 1167 1168 /* Setup L2 cache */ 1169 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | 1170 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 1171 EFFECTIVE_L2_QUEUE_SIZE(7)); 1172 WREG32(VM_L2_CNTL2, 0); 1173 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); 1174 /* Setup TLB control */ 1175 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | 1176 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 1177 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | 1178 ENABLE_WAIT_L2_QUERY; 1179 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); 1180 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); 1181 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING); 1182 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); 1183 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); 1184 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); 1185 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); 1186 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); 1187 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); 1188 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); 1189 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); 1190 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); 1191 WREG32(MC_VM_L1_TLB_MCB_RD_UVD_CNTL, tmp); 1192 WREG32(MC_VM_L1_TLB_MCB_WR_UVD_CNTL, tmp); 1193 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); 1194 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); 1195 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); 1196 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); 1197 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); 1198 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | 1199 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); 1200 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 1201 (u32)(rdev->dummy_page.addr >> 12)); 1202 for (i = 1; i < 7; i++) 1203 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 1204 1205 r600_pcie_gart_tlb_flush(rdev); 1206 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 1207 (unsigned)(rdev->mc.gtt_size >> 20), 1208 (unsigned long long)rdev->gart.table_addr); 1209 rdev->gart.ready = true; 1210 return 0; 1211 } 1212 1213 static void r600_pcie_gart_disable(struct radeon_device *rdev) 1214 { 1215 u32 tmp; 1216 int i; 1217 1218 /* Disable all tables */ 1219 for (i = 0; i < 7; i++) 1220 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 1221 1222 /* Disable L2 cache */ 1223 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | 1224 EFFECTIVE_L2_QUEUE_SIZE(7)); 1225 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); 1226 /* Setup L1 TLB control */ 1227 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | 1228 ENABLE_WAIT_L2_QUERY; 1229 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); 1230 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); 1231 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); 1232 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); 1233 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); 1234 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); 1235 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); 1236 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); 1237 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp); 1238 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp); 1239 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); 1240 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); 1241 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp); 1242 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); 1243 WREG32(MC_VM_L1_TLB_MCB_RD_UVD_CNTL, tmp); 1244 WREG32(MC_VM_L1_TLB_MCB_WR_UVD_CNTL, tmp); 1245 radeon_gart_table_vram_unpin(rdev); 1246 } 1247 1248 static void r600_pcie_gart_fini(struct radeon_device *rdev) 1249 { 1250 radeon_gart_fini(rdev); 1251 r600_pcie_gart_disable(rdev); 1252 radeon_gart_table_vram_free(rdev); 1253 } 1254 1255 static void r600_agp_enable(struct radeon_device *rdev) 1256 { 1257 u32 tmp; 1258 int i; 1259 1260 /* Setup L2 cache */ 1261 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | 1262 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 1263 EFFECTIVE_L2_QUEUE_SIZE(7)); 1264 WREG32(VM_L2_CNTL2, 0); 1265 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); 1266 /* Setup TLB control */ 1267 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | 1268 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 1269 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | 1270 ENABLE_WAIT_L2_QUERY; 1271 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); 1272 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); 1273 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING); 1274 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); 1275 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); 1276 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); 1277 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); 1278 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); 1279 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); 1280 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); 1281 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); 1282 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); 1283 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); 1284 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); 1285 for (i = 0; i < 7; i++) 1286 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 1287 } 1288 1289 int r600_mc_wait_for_idle(struct radeon_device *rdev) 1290 { 1291 unsigned i; 1292 u32 tmp; 1293 1294 for (i = 0; i < rdev->usec_timeout; i++) { 1295 /* read MC_STATUS */ 1296 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00; 1297 if (!tmp) 1298 return 0; 1299 udelay(1); 1300 } 1301 return -1; 1302 } 1303 1304 uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg) 1305 { 1306 unsigned long flags; 1307 uint32_t r; 1308 1309 spin_lock_irqsave(&rdev->mc_idx_lock, flags); 1310 WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg)); 1311 r = RREG32(R_0028FC_MC_DATA); 1312 WREG32(R_0028F8_MC_INDEX, ~C_0028F8_MC_IND_ADDR); 1313 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); 1314 return r; 1315 } 1316 1317 void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 1318 { 1319 unsigned long flags; 1320 1321 spin_lock_irqsave(&rdev->mc_idx_lock, flags); 1322 WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg) | 1323 S_0028F8_MC_IND_WR_EN(1)); 1324 WREG32(R_0028FC_MC_DATA, v); 1325 WREG32(R_0028F8_MC_INDEX, 0x7F); 1326 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); 1327 } 1328 1329 static void r600_mc_program(struct radeon_device *rdev) 1330 { 1331 struct rv515_mc_save save; 1332 u32 tmp; 1333 int i, j; 1334 1335 /* Initialize HDP */ 1336 for (i = 0, j = 0; i < 32; i++, j += 0x18) { 1337 WREG32((0x2c14 + j), 0x00000000); 1338 WREG32((0x2c18 + j), 0x00000000); 1339 WREG32((0x2c1c + j), 0x00000000); 1340 WREG32((0x2c20 + j), 0x00000000); 1341 WREG32((0x2c24 + j), 0x00000000); 1342 } 1343 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0); 1344 1345 rv515_mc_stop(rdev, &save); 1346 if (r600_mc_wait_for_idle(rdev)) { 1347 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1348 } 1349 /* Lockout access through VGA aperture (doesn't exist before R600) */ 1350 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); 1351 /* Update configuration */ 1352 if (rdev->flags & RADEON_IS_AGP) { 1353 if (rdev->mc.vram_start < rdev->mc.gtt_start) { 1354 /* VRAM before AGP */ 1355 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 1356 rdev->mc.vram_start >> 12); 1357 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 1358 rdev->mc.gtt_end >> 12); 1359 } else { 1360 /* VRAM after AGP */ 1361 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 1362 rdev->mc.gtt_start >> 12); 1363 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 1364 rdev->mc.vram_end >> 12); 1365 } 1366 } else { 1367 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12); 1368 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12); 1369 } 1370 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12); 1371 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; 1372 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); 1373 WREG32(MC_VM_FB_LOCATION, tmp); 1374 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); 1375 WREG32(HDP_NONSURFACE_INFO, (2 << 7)); 1376 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF); 1377 if (rdev->flags & RADEON_IS_AGP) { 1378 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22); 1379 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22); 1380 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); 1381 } else { 1382 WREG32(MC_VM_AGP_BASE, 0); 1383 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); 1384 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); 1385 } 1386 if (r600_mc_wait_for_idle(rdev)) { 1387 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1388 } 1389 rv515_mc_resume(rdev, &save); 1390 /* we need to own VRAM, so turn off the VGA renderer here 1391 * to stop it overwriting our objects */ 1392 rv515_vga_render_disable(rdev); 1393 } 1394 1395 /** 1396 * r600_vram_gtt_location - try to find VRAM & GTT location 1397 * @rdev: radeon device structure holding all necessary informations 1398 * @mc: memory controller structure holding memory informations 1399 * 1400 * Function will place try to place VRAM at same place as in CPU (PCI) 1401 * address space as some GPU seems to have issue when we reprogram at 1402 * different address space. 1403 * 1404 * If there is not enough space to fit the unvisible VRAM after the 1405 * aperture then we limit the VRAM size to the aperture. 1406 * 1407 * If we are using AGP then place VRAM adjacent to AGP aperture are we need 1408 * them to be in one from GPU point of view so that we can program GPU to 1409 * catch access outside them (weird GPU policy see ??). 1410 * 1411 * This function will never fails, worst case are limiting VRAM or GTT. 1412 * 1413 * Note: GTT start, end, size should be initialized before calling this 1414 * function on AGP platform. 1415 */ 1416 static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) 1417 { 1418 u64 size_bf, size_af; 1419 1420 if (mc->mc_vram_size > 0xE0000000) { 1421 /* leave room for at least 512M GTT */ 1422 dev_warn(rdev->dev, "limiting VRAM\n"); 1423 mc->real_vram_size = 0xE0000000; 1424 mc->mc_vram_size = 0xE0000000; 1425 } 1426 if (rdev->flags & RADEON_IS_AGP) { 1427 size_bf = mc->gtt_start; 1428 size_af = mc->mc_mask - mc->gtt_end; 1429 if (size_bf > size_af) { 1430 if (mc->mc_vram_size > size_bf) { 1431 dev_warn(rdev->dev, "limiting VRAM\n"); 1432 mc->real_vram_size = size_bf; 1433 mc->mc_vram_size = size_bf; 1434 } 1435 mc->vram_start = mc->gtt_start - mc->mc_vram_size; 1436 } else { 1437 if (mc->mc_vram_size > size_af) { 1438 dev_warn(rdev->dev, "limiting VRAM\n"); 1439 mc->real_vram_size = size_af; 1440 mc->mc_vram_size = size_af; 1441 } 1442 mc->vram_start = mc->gtt_end + 1; 1443 } 1444 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; 1445 dev_info(rdev->dev, "VRAM: %"PRIu64"M 0x%08"PRIX64" - 0x%08"PRIX64" (%"PRIu64"M used)\n", 1446 mc->mc_vram_size >> 20, mc->vram_start, 1447 mc->vram_end, mc->real_vram_size >> 20); 1448 } else { 1449 u64 base = 0; 1450 if (rdev->flags & RADEON_IS_IGP) { 1451 base = RREG32(MC_VM_FB_LOCATION) & 0xFFFF; 1452 base <<= 24; 1453 } 1454 radeon_vram_location(rdev, &rdev->mc, base); 1455 rdev->mc.gtt_base_align = 0; 1456 radeon_gtt_location(rdev, mc); 1457 } 1458 } 1459 1460 static int r600_mc_init(struct radeon_device *rdev) 1461 { 1462 u32 tmp; 1463 int chansize, numchan; 1464 uint32_t h_addr, l_addr; 1465 unsigned long long k8_addr; 1466 1467 /* Get VRAM informations */ 1468 rdev->mc.vram_is_ddr = true; 1469 tmp = RREG32(RAMCFG); 1470 if (tmp & CHANSIZE_OVERRIDE) { 1471 chansize = 16; 1472 } else if (tmp & CHANSIZE_MASK) { 1473 chansize = 64; 1474 } else { 1475 chansize = 32; 1476 } 1477 tmp = RREG32(CHMAP); 1478 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { 1479 case 0: 1480 default: 1481 numchan = 1; 1482 break; 1483 case 1: 1484 numchan = 2; 1485 break; 1486 case 2: 1487 numchan = 4; 1488 break; 1489 case 3: 1490 numchan = 8; 1491 break; 1492 } 1493 rdev->mc.vram_width = numchan * chansize; 1494 /* Could aper size report 0 ? */ 1495 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); 1496 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); 1497 /* Setup GPU memory space */ 1498 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); 1499 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); 1500 rdev->mc.visible_vram_size = rdev->mc.aper_size; 1501 r600_vram_gtt_location(rdev, &rdev->mc); 1502 1503 if (rdev->flags & RADEON_IS_IGP) { 1504 rs690_pm_info(rdev); 1505 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); 1506 1507 if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) { 1508 /* Use K8 direct mapping for fast fb access. */ 1509 rdev->fastfb_working = false; 1510 h_addr = G_000012_K8_ADDR_EXT(RREG32_MC(R_000012_MC_MISC_UMA_CNTL)); 1511 l_addr = RREG32_MC(R_000011_K8_FB_LOCATION); 1512 k8_addr = ((unsigned long long)h_addr) << 32 | l_addr; 1513 #if defined(CONFIG_X86_32) && !defined(CONFIG_X86_PAE) 1514 if (k8_addr + rdev->mc.visible_vram_size < 0x100000000ULL) 1515 #endif 1516 { 1517 /* FastFB shall be used with UMA memory. Here it is simply disabled when sideport 1518 * memory is present. 1519 */ 1520 if (rdev->mc.igp_sideport_enabled == false && radeon_fastfb == 1) { 1521 DRM_INFO("Direct mapping: aper base at 0x%llx, replaced by direct mapping base 0x%llx.\n", 1522 (unsigned long long)rdev->mc.aper_base, k8_addr); 1523 rdev->mc.aper_base = (resource_size_t)k8_addr; 1524 rdev->fastfb_working = true; 1525 } 1526 } 1527 } 1528 } 1529 1530 radeon_update_bandwidth_info(rdev); 1531 return 0; 1532 } 1533 1534 int r600_vram_scratch_init(struct radeon_device *rdev) 1535 { 1536 int r; 1537 1538 if (rdev->vram_scratch.robj == NULL) { 1539 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, 1540 PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM, 1541 0, NULL, NULL, &rdev->vram_scratch.robj); 1542 if (r) { 1543 return r; 1544 } 1545 } 1546 1547 r = radeon_bo_reserve(rdev->vram_scratch.robj, false); 1548 if (unlikely(r != 0)) 1549 return r; 1550 r = radeon_bo_pin(rdev->vram_scratch.robj, 1551 RADEON_GEM_DOMAIN_VRAM, &rdev->vram_scratch.gpu_addr); 1552 if (r) { 1553 radeon_bo_unreserve(rdev->vram_scratch.robj); 1554 return r; 1555 } 1556 r = radeon_bo_kmap(rdev->vram_scratch.robj, 1557 (void **)__UNVOLATILE(&rdev->vram_scratch.ptr)); 1558 if (r) 1559 radeon_bo_unpin(rdev->vram_scratch.robj); 1560 radeon_bo_unreserve(rdev->vram_scratch.robj); 1561 1562 return r; 1563 } 1564 1565 void r600_vram_scratch_fini(struct radeon_device *rdev) 1566 { 1567 int r; 1568 1569 if (rdev->vram_scratch.robj == NULL) { 1570 return; 1571 } 1572 r = radeon_bo_reserve(rdev->vram_scratch.robj, false); 1573 if (likely(r == 0)) { 1574 radeon_bo_kunmap(rdev->vram_scratch.robj); 1575 radeon_bo_unpin(rdev->vram_scratch.robj); 1576 radeon_bo_unreserve(rdev->vram_scratch.robj); 1577 } 1578 radeon_bo_unref(&rdev->vram_scratch.robj); 1579 } 1580 1581 void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung) 1582 { 1583 u32 tmp = RREG32(R600_BIOS_3_SCRATCH); 1584 1585 if (hung) 1586 tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG; 1587 else 1588 tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG; 1589 1590 WREG32(R600_BIOS_3_SCRATCH, tmp); 1591 } 1592 1593 static void r600_print_gpu_status_regs(struct radeon_device *rdev) 1594 { 1595 dev_info(rdev->dev, " R_008010_GRBM_STATUS = 0x%08X\n", 1596 RREG32(R_008010_GRBM_STATUS)); 1597 dev_info(rdev->dev, " R_008014_GRBM_STATUS2 = 0x%08X\n", 1598 RREG32(R_008014_GRBM_STATUS2)); 1599 dev_info(rdev->dev, " R_000E50_SRBM_STATUS = 0x%08X\n", 1600 RREG32(R_000E50_SRBM_STATUS)); 1601 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n", 1602 RREG32(CP_STALLED_STAT1)); 1603 dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n", 1604 RREG32(CP_STALLED_STAT2)); 1605 dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n", 1606 RREG32(CP_BUSY_STAT)); 1607 dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n", 1608 RREG32(CP_STAT)); 1609 dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n", 1610 RREG32(DMA_STATUS_REG)); 1611 } 1612 1613 static bool r600_is_display_hung(struct radeon_device *rdev) 1614 { 1615 u32 crtc_hung = 0; 1616 u32 crtc_status[2]; 1617 u32 i, j, tmp; 1618 1619 for (i = 0; i < rdev->num_crtc; i++) { 1620 if (RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN) { 1621 crtc_status[i] = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]); 1622 crtc_hung |= (1 << i); 1623 } 1624 } 1625 1626 for (j = 0; j < 10; j++) { 1627 for (i = 0; i < rdev->num_crtc; i++) { 1628 if (crtc_hung & (1 << i)) { 1629 tmp = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]); 1630 if (tmp != crtc_status[i]) 1631 crtc_hung &= ~(1 << i); 1632 } 1633 } 1634 if (crtc_hung == 0) 1635 return false; 1636 udelay(100); 1637 } 1638 1639 return true; 1640 } 1641 1642 u32 r600_gpu_check_soft_reset(struct radeon_device *rdev) 1643 { 1644 u32 reset_mask = 0; 1645 u32 tmp; 1646 1647 /* GRBM_STATUS */ 1648 tmp = RREG32(R_008010_GRBM_STATUS); 1649 if (rdev->family >= CHIP_RV770) { 1650 if (G_008010_PA_BUSY(tmp) | G_008010_SC_BUSY(tmp) | 1651 G_008010_SH_BUSY(tmp) | G_008010_SX_BUSY(tmp) | 1652 G_008010_TA_BUSY(tmp) | G_008010_VGT_BUSY(tmp) | 1653 G_008010_DB03_BUSY(tmp) | G_008010_CB03_BUSY(tmp) | 1654 G_008010_SPI03_BUSY(tmp) | G_008010_VGT_BUSY_NO_DMA(tmp)) 1655 reset_mask |= RADEON_RESET_GFX; 1656 } else { 1657 if (G_008010_PA_BUSY(tmp) | G_008010_SC_BUSY(tmp) | 1658 G_008010_SH_BUSY(tmp) | G_008010_SX_BUSY(tmp) | 1659 G_008010_TA03_BUSY(tmp) | G_008010_VGT_BUSY(tmp) | 1660 G_008010_DB03_BUSY(tmp) | G_008010_CB03_BUSY(tmp) | 1661 G_008010_SPI03_BUSY(tmp) | G_008010_VGT_BUSY_NO_DMA(tmp)) 1662 reset_mask |= RADEON_RESET_GFX; 1663 } 1664 1665 if (G_008010_CF_RQ_PENDING(tmp) | G_008010_PF_RQ_PENDING(tmp) | 1666 G_008010_CP_BUSY(tmp) | G_008010_CP_COHERENCY_BUSY(tmp)) 1667 reset_mask |= RADEON_RESET_CP; 1668 1669 if (G_008010_GRBM_EE_BUSY(tmp)) 1670 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP; 1671 1672 /* DMA_STATUS_REG */ 1673 tmp = RREG32(DMA_STATUS_REG); 1674 if (!(tmp & DMA_IDLE)) 1675 reset_mask |= RADEON_RESET_DMA; 1676 1677 /* SRBM_STATUS */ 1678 tmp = RREG32(R_000E50_SRBM_STATUS); 1679 if (G_000E50_RLC_RQ_PENDING(tmp) | G_000E50_RLC_BUSY(tmp)) 1680 reset_mask |= RADEON_RESET_RLC; 1681 1682 if (G_000E50_IH_BUSY(tmp)) 1683 reset_mask |= RADEON_RESET_IH; 1684 1685 if (G_000E50_SEM_BUSY(tmp)) 1686 reset_mask |= RADEON_RESET_SEM; 1687 1688 if (G_000E50_GRBM_RQ_PENDING(tmp)) 1689 reset_mask |= RADEON_RESET_GRBM; 1690 1691 if (G_000E50_VMC_BUSY(tmp)) 1692 reset_mask |= RADEON_RESET_VMC; 1693 1694 if (G_000E50_MCB_BUSY(tmp) | G_000E50_MCDZ_BUSY(tmp) | 1695 G_000E50_MCDY_BUSY(tmp) | G_000E50_MCDX_BUSY(tmp) | 1696 G_000E50_MCDW_BUSY(tmp)) 1697 reset_mask |= RADEON_RESET_MC; 1698 1699 if (r600_is_display_hung(rdev)) 1700 reset_mask |= RADEON_RESET_DISPLAY; 1701 1702 /* Skip MC reset as it's mostly likely not hung, just busy */ 1703 if (reset_mask & RADEON_RESET_MC) { 1704 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask); 1705 reset_mask &= ~RADEON_RESET_MC; 1706 } 1707 1708 return reset_mask; 1709 } 1710 1711 static void r600_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask) 1712 { 1713 struct rv515_mc_save save; 1714 u32 grbm_soft_reset = 0, srbm_soft_reset = 0; 1715 u32 tmp; 1716 1717 if (reset_mask == 0) 1718 return; 1719 1720 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask); 1721 1722 r600_print_gpu_status_regs(rdev); 1723 1724 /* Disable CP parsing/prefetching */ 1725 if (rdev->family >= CHIP_RV770) 1726 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1) | S_0086D8_CP_PFP_HALT(1)); 1727 else 1728 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); 1729 1730 /* disable the RLC */ 1731 WREG32(RLC_CNTL, 0); 1732 1733 if (reset_mask & RADEON_RESET_DMA) { 1734 /* Disable DMA */ 1735 tmp = RREG32(DMA_RB_CNTL); 1736 tmp &= ~DMA_RB_ENABLE; 1737 WREG32(DMA_RB_CNTL, tmp); 1738 } 1739 1740 mdelay(50); 1741 1742 rv515_mc_stop(rdev, &save); 1743 if (r600_mc_wait_for_idle(rdev)) { 1744 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1745 } 1746 1747 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) { 1748 if (rdev->family >= CHIP_RV770) 1749 grbm_soft_reset |= S_008020_SOFT_RESET_DB(1) | 1750 S_008020_SOFT_RESET_CB(1) | 1751 S_008020_SOFT_RESET_PA(1) | 1752 S_008020_SOFT_RESET_SC(1) | 1753 S_008020_SOFT_RESET_SPI(1) | 1754 S_008020_SOFT_RESET_SX(1) | 1755 S_008020_SOFT_RESET_SH(1) | 1756 S_008020_SOFT_RESET_TC(1) | 1757 S_008020_SOFT_RESET_TA(1) | 1758 S_008020_SOFT_RESET_VC(1) | 1759 S_008020_SOFT_RESET_VGT(1); 1760 else 1761 grbm_soft_reset |= S_008020_SOFT_RESET_CR(1) | 1762 S_008020_SOFT_RESET_DB(1) | 1763 S_008020_SOFT_RESET_CB(1) | 1764 S_008020_SOFT_RESET_PA(1) | 1765 S_008020_SOFT_RESET_SC(1) | 1766 S_008020_SOFT_RESET_SMX(1) | 1767 S_008020_SOFT_RESET_SPI(1) | 1768 S_008020_SOFT_RESET_SX(1) | 1769 S_008020_SOFT_RESET_SH(1) | 1770 S_008020_SOFT_RESET_TC(1) | 1771 S_008020_SOFT_RESET_TA(1) | 1772 S_008020_SOFT_RESET_VC(1) | 1773 S_008020_SOFT_RESET_VGT(1); 1774 } 1775 1776 if (reset_mask & RADEON_RESET_CP) { 1777 grbm_soft_reset |= S_008020_SOFT_RESET_CP(1) | 1778 S_008020_SOFT_RESET_VGT(1); 1779 1780 srbm_soft_reset |= S_000E60_SOFT_RESET_GRBM(1); 1781 } 1782 1783 if (reset_mask & RADEON_RESET_DMA) { 1784 if (rdev->family >= CHIP_RV770) 1785 srbm_soft_reset |= RV770_SOFT_RESET_DMA; 1786 else 1787 srbm_soft_reset |= SOFT_RESET_DMA; 1788 } 1789 1790 if (reset_mask & RADEON_RESET_RLC) 1791 srbm_soft_reset |= S_000E60_SOFT_RESET_RLC(1); 1792 1793 if (reset_mask & RADEON_RESET_SEM) 1794 srbm_soft_reset |= S_000E60_SOFT_RESET_SEM(1); 1795 1796 if (reset_mask & RADEON_RESET_IH) 1797 srbm_soft_reset |= S_000E60_SOFT_RESET_IH(1); 1798 1799 if (reset_mask & RADEON_RESET_GRBM) 1800 srbm_soft_reset |= S_000E60_SOFT_RESET_GRBM(1); 1801 1802 if (!(rdev->flags & RADEON_IS_IGP)) { 1803 if (reset_mask & RADEON_RESET_MC) 1804 srbm_soft_reset |= S_000E60_SOFT_RESET_MC(1); 1805 } 1806 1807 if (reset_mask & RADEON_RESET_VMC) 1808 srbm_soft_reset |= S_000E60_SOFT_RESET_VMC(1); 1809 1810 if (grbm_soft_reset) { 1811 tmp = RREG32(R_008020_GRBM_SOFT_RESET); 1812 tmp |= grbm_soft_reset; 1813 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp); 1814 WREG32(R_008020_GRBM_SOFT_RESET, tmp); 1815 tmp = RREG32(R_008020_GRBM_SOFT_RESET); 1816 1817 udelay(50); 1818 1819 tmp &= ~grbm_soft_reset; 1820 WREG32(R_008020_GRBM_SOFT_RESET, tmp); 1821 tmp = RREG32(R_008020_GRBM_SOFT_RESET); 1822 } 1823 1824 if (srbm_soft_reset) { 1825 tmp = RREG32(SRBM_SOFT_RESET); 1826 tmp |= srbm_soft_reset; 1827 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1828 WREG32(SRBM_SOFT_RESET, tmp); 1829 tmp = RREG32(SRBM_SOFT_RESET); 1830 1831 udelay(50); 1832 1833 tmp &= ~srbm_soft_reset; 1834 WREG32(SRBM_SOFT_RESET, tmp); 1835 tmp = RREG32(SRBM_SOFT_RESET); 1836 } 1837 1838 /* Wait a little for things to settle down */ 1839 mdelay(1); 1840 1841 rv515_mc_resume(rdev, &save); 1842 udelay(50); 1843 1844 r600_print_gpu_status_regs(rdev); 1845 } 1846 1847 static void r600_gpu_pci_config_reset(struct radeon_device *rdev) 1848 { 1849 struct rv515_mc_save save; 1850 u32 tmp, i; 1851 1852 dev_info(rdev->dev, "GPU pci config reset\n"); 1853 1854 /* disable dpm? */ 1855 1856 /* Disable CP parsing/prefetching */ 1857 if (rdev->family >= CHIP_RV770) 1858 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1) | S_0086D8_CP_PFP_HALT(1)); 1859 else 1860 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); 1861 1862 /* disable the RLC */ 1863 WREG32(RLC_CNTL, 0); 1864 1865 /* Disable DMA */ 1866 tmp = RREG32(DMA_RB_CNTL); 1867 tmp &= ~DMA_RB_ENABLE; 1868 WREG32(DMA_RB_CNTL, tmp); 1869 1870 mdelay(50); 1871 1872 /* set mclk/sclk to bypass */ 1873 if (rdev->family >= CHIP_RV770) 1874 rv770_set_clk_bypass_mode(rdev); 1875 /* disable BM */ 1876 pci_clear_master(rdev->pdev); 1877 /* disable mem access */ 1878 rv515_mc_stop(rdev, &save); 1879 if (r600_mc_wait_for_idle(rdev)) { 1880 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1881 } 1882 1883 /* BIF reset workaround. Not sure if this is needed on 6xx */ 1884 tmp = RREG32(BUS_CNTL); 1885 tmp |= VGA_COHE_SPEC_TIMER_DIS; 1886 WREG32(BUS_CNTL, tmp); 1887 1888 tmp = RREG32(BIF_SCRATCH0); 1889 1890 /* reset */ 1891 radeon_pci_config_reset(rdev); 1892 mdelay(1); 1893 1894 /* BIF reset workaround. Not sure if this is needed on 6xx */ 1895 tmp = SOFT_RESET_BIF; 1896 WREG32(SRBM_SOFT_RESET, tmp); 1897 mdelay(1); 1898 WREG32(SRBM_SOFT_RESET, 0); 1899 1900 /* wait for asic to come out of reset */ 1901 for (i = 0; i < rdev->usec_timeout; i++) { 1902 if (RREG32(CONFIG_MEMSIZE) != 0xffffffff) 1903 break; 1904 udelay(1); 1905 } 1906 } 1907 1908 int r600_asic_reset(struct radeon_device *rdev) 1909 { 1910 u32 reset_mask; 1911 1912 reset_mask = r600_gpu_check_soft_reset(rdev); 1913 1914 if (reset_mask) 1915 r600_set_bios_scratch_engine_hung(rdev, true); 1916 1917 /* try soft reset */ 1918 r600_gpu_soft_reset(rdev, reset_mask); 1919 1920 reset_mask = r600_gpu_check_soft_reset(rdev); 1921 1922 /* try pci config reset */ 1923 if (reset_mask && radeon_hard_reset) 1924 r600_gpu_pci_config_reset(rdev); 1925 1926 reset_mask = r600_gpu_check_soft_reset(rdev); 1927 1928 if (!reset_mask) 1929 r600_set_bios_scratch_engine_hung(rdev, false); 1930 1931 return 0; 1932 } 1933 1934 /** 1935 * r600_gfx_is_lockup - Check if the GFX engine is locked up 1936 * 1937 * @rdev: radeon_device pointer 1938 * @ring: radeon_ring structure holding ring information 1939 * 1940 * Check if the GFX engine is locked up. 1941 * Returns true if the engine appears to be locked up, false if not. 1942 */ 1943 bool r600_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) 1944 { 1945 u32 reset_mask = r600_gpu_check_soft_reset(rdev); 1946 1947 if (!(reset_mask & (RADEON_RESET_GFX | 1948 RADEON_RESET_COMPUTE | 1949 RADEON_RESET_CP))) { 1950 radeon_ring_lockup_update(rdev, ring); 1951 return false; 1952 } 1953 return radeon_ring_test_lockup(rdev, ring); 1954 } 1955 1956 u32 r6xx_remap_render_backend(struct radeon_device *rdev, 1957 u32 tiling_pipe_num, 1958 u32 max_rb_num, 1959 u32 total_max_rb_num, 1960 u32 disabled_rb_mask) 1961 { 1962 u32 rendering_pipe_num, rb_num_width, req_rb_num; 1963 u32 pipe_rb_ratio, pipe_rb_remain, tmp; 1964 u32 data = 0, mask = 1 << (max_rb_num - 1); 1965 unsigned i, j; 1966 1967 /* mask out the RBs that don't exist on that asic */ 1968 tmp = disabled_rb_mask | ((0xff << max_rb_num) & 0xff); 1969 /* make sure at least one RB is available */ 1970 if ((tmp & 0xff) != 0xff) 1971 disabled_rb_mask = tmp; 1972 1973 rendering_pipe_num = 1 << tiling_pipe_num; 1974 req_rb_num = total_max_rb_num - r600_count_pipe_bits(disabled_rb_mask); 1975 BUG_ON(rendering_pipe_num < req_rb_num); 1976 1977 pipe_rb_ratio = rendering_pipe_num / req_rb_num; 1978 pipe_rb_remain = rendering_pipe_num - pipe_rb_ratio * req_rb_num; 1979 1980 if (rdev->family <= CHIP_RV740) { 1981 /* r6xx/r7xx */ 1982 rb_num_width = 2; 1983 } else { 1984 /* eg+ */ 1985 rb_num_width = 4; 1986 } 1987 1988 for (i = 0; i < max_rb_num; i++) { 1989 if (!(mask & disabled_rb_mask)) { 1990 for (j = 0; j < pipe_rb_ratio; j++) { 1991 data <<= rb_num_width; 1992 data |= max_rb_num - i - 1; 1993 } 1994 if (pipe_rb_remain) { 1995 data <<= rb_num_width; 1996 data |= max_rb_num - i - 1; 1997 pipe_rb_remain--; 1998 } 1999 } 2000 mask >>= 1; 2001 } 2002 2003 return data; 2004 } 2005 2006 int r600_count_pipe_bits(uint32_t val) 2007 { 2008 return hweight32(val); 2009 } 2010 2011 static void r600_gpu_init(struct radeon_device *rdev) 2012 { 2013 u32 tiling_config; 2014 u32 ramcfg; 2015 u32 cc_gc_shader_pipe_config; 2016 u32 tmp; 2017 int i, j; 2018 u32 sq_config; 2019 u32 sq_gpr_resource_mgmt_1 = 0; 2020 u32 sq_gpr_resource_mgmt_2 = 0; 2021 u32 sq_thread_resource_mgmt = 0; 2022 u32 sq_stack_resource_mgmt_1 = 0; 2023 u32 sq_stack_resource_mgmt_2 = 0; 2024 u32 disabled_rb_mask; 2025 2026 rdev->config.r600.tiling_group_size = 256; 2027 switch (rdev->family) { 2028 case CHIP_R600: 2029 rdev->config.r600.max_pipes = 4; 2030 rdev->config.r600.max_tile_pipes = 8; 2031 rdev->config.r600.max_simds = 4; 2032 rdev->config.r600.max_backends = 4; 2033 rdev->config.r600.max_gprs = 256; 2034 rdev->config.r600.max_threads = 192; 2035 rdev->config.r600.max_stack_entries = 256; 2036 rdev->config.r600.max_hw_contexts = 8; 2037 rdev->config.r600.max_gs_threads = 16; 2038 rdev->config.r600.sx_max_export_size = 128; 2039 rdev->config.r600.sx_max_export_pos_size = 16; 2040 rdev->config.r600.sx_max_export_smx_size = 128; 2041 rdev->config.r600.sq_num_cf_insts = 2; 2042 break; 2043 case CHIP_RV630: 2044 case CHIP_RV635: 2045 rdev->config.r600.max_pipes = 2; 2046 rdev->config.r600.max_tile_pipes = 2; 2047 rdev->config.r600.max_simds = 3; 2048 rdev->config.r600.max_backends = 1; 2049 rdev->config.r600.max_gprs = 128; 2050 rdev->config.r600.max_threads = 192; 2051 rdev->config.r600.max_stack_entries = 128; 2052 rdev->config.r600.max_hw_contexts = 8; 2053 rdev->config.r600.max_gs_threads = 4; 2054 rdev->config.r600.sx_max_export_size = 128; 2055 rdev->config.r600.sx_max_export_pos_size = 16; 2056 rdev->config.r600.sx_max_export_smx_size = 128; 2057 rdev->config.r600.sq_num_cf_insts = 2; 2058 break; 2059 case CHIP_RV610: 2060 case CHIP_RV620: 2061 case CHIP_RS780: 2062 case CHIP_RS880: 2063 rdev->config.r600.max_pipes = 1; 2064 rdev->config.r600.max_tile_pipes = 1; 2065 rdev->config.r600.max_simds = 2; 2066 rdev->config.r600.max_backends = 1; 2067 rdev->config.r600.max_gprs = 128; 2068 rdev->config.r600.max_threads = 192; 2069 rdev->config.r600.max_stack_entries = 128; 2070 rdev->config.r600.max_hw_contexts = 4; 2071 rdev->config.r600.max_gs_threads = 4; 2072 rdev->config.r600.sx_max_export_size = 128; 2073 rdev->config.r600.sx_max_export_pos_size = 16; 2074 rdev->config.r600.sx_max_export_smx_size = 128; 2075 rdev->config.r600.sq_num_cf_insts = 1; 2076 break; 2077 case CHIP_RV670: 2078 rdev->config.r600.max_pipes = 4; 2079 rdev->config.r600.max_tile_pipes = 4; 2080 rdev->config.r600.max_simds = 4; 2081 rdev->config.r600.max_backends = 4; 2082 rdev->config.r600.max_gprs = 192; 2083 rdev->config.r600.max_threads = 192; 2084 rdev->config.r600.max_stack_entries = 256; 2085 rdev->config.r600.max_hw_contexts = 8; 2086 rdev->config.r600.max_gs_threads = 16; 2087 rdev->config.r600.sx_max_export_size = 128; 2088 rdev->config.r600.sx_max_export_pos_size = 16; 2089 rdev->config.r600.sx_max_export_smx_size = 128; 2090 rdev->config.r600.sq_num_cf_insts = 2; 2091 break; 2092 default: 2093 break; 2094 } 2095 2096 /* Initialize HDP */ 2097 for (i = 0, j = 0; i < 32; i++, j += 0x18) { 2098 WREG32((0x2c14 + j), 0x00000000); 2099 WREG32((0x2c18 + j), 0x00000000); 2100 WREG32((0x2c1c + j), 0x00000000); 2101 WREG32((0x2c20 + j), 0x00000000); 2102 WREG32((0x2c24 + j), 0x00000000); 2103 } 2104 2105 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); 2106 2107 /* Setup tiling */ 2108 tiling_config = 0; 2109 ramcfg = RREG32(RAMCFG); 2110 switch (rdev->config.r600.max_tile_pipes) { 2111 case 1: 2112 tiling_config |= PIPE_TILING(0); 2113 break; 2114 case 2: 2115 tiling_config |= PIPE_TILING(1); 2116 break; 2117 case 4: 2118 tiling_config |= PIPE_TILING(2); 2119 break; 2120 case 8: 2121 tiling_config |= PIPE_TILING(3); 2122 break; 2123 default: 2124 break; 2125 } 2126 rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes; 2127 rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); 2128 tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); 2129 tiling_config |= GROUP_SIZE((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT); 2130 2131 tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT; 2132 if (tmp > 3) { 2133 tiling_config |= ROW_TILING(3); 2134 tiling_config |= SAMPLE_SPLIT(3); 2135 } else { 2136 tiling_config |= ROW_TILING(tmp); 2137 tiling_config |= SAMPLE_SPLIT(tmp); 2138 } 2139 tiling_config |= BANK_SWAPS(1); 2140 2141 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0x00ffff00; 2142 tmp = rdev->config.r600.max_simds - 2143 r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R6XX_MAX_SIMDS_MASK); 2144 rdev->config.r600.active_simds = tmp; 2145 2146 disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R6XX_MAX_BACKENDS_MASK; 2147 tmp = 0; 2148 for (i = 0; i < rdev->config.r600.max_backends; i++) 2149 tmp |= (1 << i); 2150 /* if all the backends are disabled, fix it up here */ 2151 if ((disabled_rb_mask & tmp) == tmp) { 2152 for (i = 0; i < rdev->config.r600.max_backends; i++) 2153 disabled_rb_mask &= ~(1 << i); 2154 } 2155 tmp = (tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT; 2156 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.r600.max_backends, 2157 R6XX_MAX_BACKENDS, disabled_rb_mask); 2158 tiling_config |= tmp << 16; 2159 rdev->config.r600.backend_map = tmp; 2160 2161 rdev->config.r600.tile_config = tiling_config; 2162 WREG32(GB_TILING_CONFIG, tiling_config); 2163 WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff); 2164 WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff); 2165 WREG32(DMA_TILING_CONFIG, tiling_config & 0xffff); 2166 2167 tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8); 2168 WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK); 2169 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK); 2170 2171 /* Setup some CP states */ 2172 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b))); 2173 WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40))); 2174 2175 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT | 2176 SYNC_WALKER | SYNC_ALIGNER)); 2177 /* Setup various GPU states */ 2178 if (rdev->family == CHIP_RV670) 2179 WREG32(ARB_GDEC_RD_CNTL, 0x00000021); 2180 2181 tmp = RREG32(SX_DEBUG_1); 2182 tmp |= SMX_EVENT_RELEASE; 2183 if ((rdev->family > CHIP_R600)) 2184 tmp |= ENABLE_NEW_SMX_ADDRESS; 2185 WREG32(SX_DEBUG_1, tmp); 2186 2187 if (((rdev->family) == CHIP_R600) || 2188 ((rdev->family) == CHIP_RV630) || 2189 ((rdev->family) == CHIP_RV610) || 2190 ((rdev->family) == CHIP_RV620) || 2191 ((rdev->family) == CHIP_RS780) || 2192 ((rdev->family) == CHIP_RS880)) { 2193 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE); 2194 } else { 2195 WREG32(DB_DEBUG, 0); 2196 } 2197 WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) | 2198 DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4))); 2199 2200 WREG32(PA_SC_MULTI_CHIP_CNTL, 0); 2201 WREG32(VGT_NUM_INSTANCES, 0); 2202 2203 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0)); 2204 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0)); 2205 2206 tmp = RREG32(SQ_MS_FIFO_SIZES); 2207 if (((rdev->family) == CHIP_RV610) || 2208 ((rdev->family) == CHIP_RV620) || 2209 ((rdev->family) == CHIP_RS780) || 2210 ((rdev->family) == CHIP_RS880)) { 2211 tmp = (CACHE_FIFO_SIZE(0xa) | 2212 FETCH_FIFO_HIWATER(0xa) | 2213 DONE_FIFO_HIWATER(0xe0) | 2214 ALU_UPDATE_FIFO_HIWATER(0x8)); 2215 } else if (((rdev->family) == CHIP_R600) || 2216 ((rdev->family) == CHIP_RV630)) { 2217 tmp &= ~DONE_FIFO_HIWATER(0xff); 2218 tmp |= DONE_FIFO_HIWATER(0x4); 2219 } 2220 WREG32(SQ_MS_FIFO_SIZES, tmp); 2221 2222 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT 2223 * should be adjusted as needed by the 2D/3D drivers. This just sets default values 2224 */ 2225 sq_config = RREG32(SQ_CONFIG); 2226 sq_config &= ~(PS_PRIO(3) | 2227 VS_PRIO(3) | 2228 GS_PRIO(3) | 2229 ES_PRIO(3U)); 2230 sq_config |= (DX9_CONSTS | 2231 VC_ENABLE | 2232 PS_PRIO(0) | 2233 VS_PRIO(1) | 2234 GS_PRIO(2) | 2235 ES_PRIO(3U)); 2236 2237 if ((rdev->family) == CHIP_R600) { 2238 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) | 2239 NUM_VS_GPRS(124) | 2240 NUM_CLAUSE_TEMP_GPRS(4)); 2241 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) | 2242 NUM_ES_GPRS(0)); 2243 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) | 2244 NUM_VS_THREADS(48) | 2245 NUM_GS_THREADS(4) | 2246 NUM_ES_THREADS(4)); 2247 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) | 2248 NUM_VS_STACK_ENTRIES(128)); 2249 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) | 2250 NUM_ES_STACK_ENTRIES(0)); 2251 } else if (((rdev->family) == CHIP_RV610) || 2252 ((rdev->family) == CHIP_RV620) || 2253 ((rdev->family) == CHIP_RS780) || 2254 ((rdev->family) == CHIP_RS880)) { 2255 /* no vertex cache */ 2256 sq_config &= ~VC_ENABLE; 2257 2258 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | 2259 NUM_VS_GPRS(44) | 2260 NUM_CLAUSE_TEMP_GPRS(2)); 2261 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) | 2262 NUM_ES_GPRS(17)); 2263 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | 2264 NUM_VS_THREADS(78) | 2265 NUM_GS_THREADS(4) | 2266 NUM_ES_THREADS(31)); 2267 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) | 2268 NUM_VS_STACK_ENTRIES(40)); 2269 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) | 2270 NUM_ES_STACK_ENTRIES(16)); 2271 } else if (((rdev->family) == CHIP_RV630) || 2272 ((rdev->family) == CHIP_RV635)) { 2273 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | 2274 NUM_VS_GPRS(44) | 2275 NUM_CLAUSE_TEMP_GPRS(2)); 2276 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) | 2277 NUM_ES_GPRS(18)); 2278 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | 2279 NUM_VS_THREADS(78) | 2280 NUM_GS_THREADS(4) | 2281 NUM_ES_THREADS(31)); 2282 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) | 2283 NUM_VS_STACK_ENTRIES(40)); 2284 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) | 2285 NUM_ES_STACK_ENTRIES(16)); 2286 } else if ((rdev->family) == CHIP_RV670) { 2287 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | 2288 NUM_VS_GPRS(44) | 2289 NUM_CLAUSE_TEMP_GPRS(2)); 2290 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) | 2291 NUM_ES_GPRS(17)); 2292 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | 2293 NUM_VS_THREADS(78) | 2294 NUM_GS_THREADS(4) | 2295 NUM_ES_THREADS(31)); 2296 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) | 2297 NUM_VS_STACK_ENTRIES(64)); 2298 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) | 2299 NUM_ES_STACK_ENTRIES(64)); 2300 } 2301 2302 WREG32(SQ_CONFIG, sq_config); 2303 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1); 2304 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2); 2305 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); 2306 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1); 2307 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2); 2308 2309 if (((rdev->family) == CHIP_RV610) || 2310 ((rdev->family) == CHIP_RV620) || 2311 ((rdev->family) == CHIP_RS780) || 2312 ((rdev->family) == CHIP_RS880)) { 2313 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY)); 2314 } else { 2315 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC)); 2316 } 2317 2318 /* More default values. 2D/3D driver should adjust as needed */ 2319 WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) | 2320 S1_X(0x4) | S1_Y(0xc))); 2321 WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) | 2322 S1_X(0x2) | S1_Y(0x2) | 2323 S2_X(0xa) | S2_Y(0x6) | 2324 S3_X(0x6) | S3_Y(0xaU))); 2325 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) | 2326 S1_X(0x4) | S1_Y(0xc) | 2327 S2_X(0x1) | S2_Y(0x6) | 2328 S3_X(0xa) | S3_Y(0xeU))); 2329 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) | 2330 S5_X(0x0) | S5_Y(0x0) | 2331 S6_X(0xb) | S6_Y(0x4) | 2332 S7_X(0x7) | S7_Y(0x8U))); 2333 2334 WREG32(VGT_STRMOUT_EN, 0); 2335 tmp = rdev->config.r600.max_pipes * 16; 2336 switch (rdev->family) { 2337 case CHIP_RV610: 2338 case CHIP_RV620: 2339 case CHIP_RS780: 2340 case CHIP_RS880: 2341 tmp += 32; 2342 break; 2343 case CHIP_RV670: 2344 tmp += 128; 2345 break; 2346 default: 2347 break; 2348 } 2349 if (tmp > 256) { 2350 tmp = 256; 2351 } 2352 WREG32(VGT_ES_PER_GS, 128); 2353 WREG32(VGT_GS_PER_ES, tmp); 2354 WREG32(VGT_GS_PER_VS, 2); 2355 WREG32(VGT_GS_VERTEX_REUSE, 16); 2356 2357 /* more default values. 2D/3D driver should adjust as needed */ 2358 WREG32(PA_SC_LINE_STIPPLE_STATE, 0); 2359 WREG32(VGT_STRMOUT_EN, 0); 2360 WREG32(SX_MISC, 0); 2361 WREG32(PA_SC_MODE_CNTL, 0); 2362 WREG32(PA_SC_AA_CONFIG, 0); 2363 WREG32(PA_SC_LINE_STIPPLE, 0); 2364 WREG32(SPI_INPUT_Z, 0); 2365 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2)); 2366 WREG32(CB_COLOR7_FRAG, 0); 2367 2368 /* Clear render buffer base addresses */ 2369 WREG32(CB_COLOR0_BASE, 0); 2370 WREG32(CB_COLOR1_BASE, 0); 2371 WREG32(CB_COLOR2_BASE, 0); 2372 WREG32(CB_COLOR3_BASE, 0); 2373 WREG32(CB_COLOR4_BASE, 0); 2374 WREG32(CB_COLOR5_BASE, 0); 2375 WREG32(CB_COLOR6_BASE, 0); 2376 WREG32(CB_COLOR7_BASE, 0); 2377 WREG32(CB_COLOR7_FRAG, 0); 2378 2379 switch (rdev->family) { 2380 case CHIP_RV610: 2381 case CHIP_RV620: 2382 case CHIP_RS780: 2383 case CHIP_RS880: 2384 tmp = TC_L2_SIZE(8); 2385 break; 2386 case CHIP_RV630: 2387 case CHIP_RV635: 2388 tmp = TC_L2_SIZE(4); 2389 break; 2390 case CHIP_R600: 2391 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT; 2392 break; 2393 default: 2394 tmp = TC_L2_SIZE(0); 2395 break; 2396 } 2397 WREG32(TC_CNTL, tmp); 2398 2399 tmp = RREG32(HDP_HOST_PATH_CNTL); 2400 WREG32(HDP_HOST_PATH_CNTL, tmp); 2401 2402 tmp = RREG32(ARB_POP); 2403 tmp |= ENABLE_TC128; 2404 WREG32(ARB_POP, tmp); 2405 2406 WREG32(PA_SC_MULTI_CHIP_CNTL, 0); 2407 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA | 2408 NUM_CLIP_SEQ(3))); 2409 WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095)); 2410 WREG32(VC_ENHANCE, 0); 2411 } 2412 2413 2414 /* 2415 * Indirect registers accessor 2416 */ 2417 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg) 2418 { 2419 unsigned long flags; 2420 u32 r; 2421 2422 spin_lock_irqsave(&rdev->pciep_idx_lock, flags); 2423 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); 2424 (void)RREG32(PCIE_PORT_INDEX); 2425 r = RREG32(PCIE_PORT_DATA); 2426 spin_unlock_irqrestore(&rdev->pciep_idx_lock, flags); 2427 return r; 2428 } 2429 2430 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2431 { 2432 unsigned long flags; 2433 2434 spin_lock_irqsave(&rdev->pciep_idx_lock, flags); 2435 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); 2436 (void)RREG32(PCIE_PORT_INDEX); 2437 WREG32(PCIE_PORT_DATA, (v)); 2438 (void)RREG32(PCIE_PORT_DATA); 2439 spin_unlock_irqrestore(&rdev->pciep_idx_lock, flags); 2440 } 2441 2442 /* 2443 * CP & Ring 2444 */ 2445 void r600_cp_stop(struct radeon_device *rdev) 2446 { 2447 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX) 2448 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 2449 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); 2450 WREG32(SCRATCH_UMSK, 0); 2451 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; 2452 } 2453 2454 int r600_init_microcode(struct radeon_device *rdev) 2455 { 2456 const char *chip_name; 2457 const char *rlc_chip_name; 2458 const char *smc_chip_name = "RV770"; 2459 size_t pfp_req_size, me_req_size, rlc_req_size, smc_req_size = 0; 2460 char fw_name[30]; 2461 int err; 2462 2463 DRM_DEBUG("\n"); 2464 2465 switch (rdev->family) { 2466 case CHIP_R600: 2467 chip_name = "R600"; 2468 rlc_chip_name = "R600"; 2469 break; 2470 case CHIP_RV610: 2471 chip_name = "RV610"; 2472 rlc_chip_name = "R600"; 2473 break; 2474 case CHIP_RV630: 2475 chip_name = "RV630"; 2476 rlc_chip_name = "R600"; 2477 break; 2478 case CHIP_RV620: 2479 chip_name = "RV620"; 2480 rlc_chip_name = "R600"; 2481 break; 2482 case CHIP_RV635: 2483 chip_name = "RV635"; 2484 rlc_chip_name = "R600"; 2485 break; 2486 case CHIP_RV670: 2487 chip_name = "RV670"; 2488 rlc_chip_name = "R600"; 2489 break; 2490 case CHIP_RS780: 2491 case CHIP_RS880: 2492 chip_name = "RS780"; 2493 rlc_chip_name = "R600"; 2494 break; 2495 case CHIP_RV770: 2496 chip_name = "RV770"; 2497 rlc_chip_name = "R700"; 2498 smc_chip_name = "RV770"; 2499 smc_req_size = ALIGN(RV770_SMC_UCODE_SIZE, 4); 2500 break; 2501 case CHIP_RV730: 2502 chip_name = "RV730"; 2503 rlc_chip_name = "R700"; 2504 smc_chip_name = "RV730"; 2505 smc_req_size = ALIGN(RV730_SMC_UCODE_SIZE, 4); 2506 break; 2507 case CHIP_RV710: 2508 chip_name = "RV710"; 2509 rlc_chip_name = "R700"; 2510 smc_chip_name = "RV710"; 2511 smc_req_size = ALIGN(RV710_SMC_UCODE_SIZE, 4); 2512 break; 2513 case CHIP_RV740: 2514 chip_name = "RV730"; 2515 rlc_chip_name = "R700"; 2516 smc_chip_name = "RV740"; 2517 smc_req_size = ALIGN(RV740_SMC_UCODE_SIZE, 4); 2518 break; 2519 case CHIP_CEDAR: 2520 chip_name = "CEDAR"; 2521 rlc_chip_name = "CEDAR"; 2522 smc_chip_name = "CEDAR"; 2523 smc_req_size = ALIGN(CEDAR_SMC_UCODE_SIZE, 4); 2524 break; 2525 case CHIP_REDWOOD: 2526 chip_name = "REDWOOD"; 2527 rlc_chip_name = "REDWOOD"; 2528 smc_chip_name = "REDWOOD"; 2529 smc_req_size = ALIGN(REDWOOD_SMC_UCODE_SIZE, 4); 2530 break; 2531 case CHIP_JUNIPER: 2532 chip_name = "JUNIPER"; 2533 rlc_chip_name = "JUNIPER"; 2534 smc_chip_name = "JUNIPER"; 2535 smc_req_size = ALIGN(JUNIPER_SMC_UCODE_SIZE, 4); 2536 break; 2537 case CHIP_CYPRESS: 2538 case CHIP_HEMLOCK: 2539 chip_name = "CYPRESS"; 2540 rlc_chip_name = "CYPRESS"; 2541 smc_chip_name = "CYPRESS"; 2542 smc_req_size = ALIGN(CYPRESS_SMC_UCODE_SIZE, 4); 2543 break; 2544 case CHIP_PALM: 2545 chip_name = "PALM"; 2546 rlc_chip_name = "SUMO"; 2547 break; 2548 case CHIP_SUMO: 2549 chip_name = "SUMO"; 2550 rlc_chip_name = "SUMO"; 2551 break; 2552 case CHIP_SUMO2: 2553 chip_name = "SUMO2"; 2554 rlc_chip_name = "SUMO"; 2555 break; 2556 default: BUG(); 2557 } 2558 2559 if (rdev->family >= CHIP_CEDAR) { 2560 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4; 2561 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4; 2562 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4; 2563 } else if (rdev->family >= CHIP_RV770) { 2564 pfp_req_size = R700_PFP_UCODE_SIZE * 4; 2565 me_req_size = R700_PM4_UCODE_SIZE * 4; 2566 rlc_req_size = R700_RLC_UCODE_SIZE * 4; 2567 } else { 2568 pfp_req_size = R600_PFP_UCODE_SIZE * 4; 2569 me_req_size = R600_PM4_UCODE_SIZE * 12; 2570 rlc_req_size = R600_RLC_UCODE_SIZE * 4; 2571 } 2572 2573 DRM_INFO("Loading %s Microcode\n", chip_name); 2574 2575 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name); 2576 err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev); 2577 if (err) 2578 goto out; 2579 if (rdev->pfp_fw->size != pfp_req_size) { 2580 printk(KERN_ERR 2581 "r600_cp: Bogus length %zu in firmware \"%s\"\n", 2582 rdev->pfp_fw->size, fw_name); 2583 err = -EINVAL; 2584 goto out; 2585 } 2586 2587 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name); 2588 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev); 2589 if (err) 2590 goto out; 2591 if (rdev->me_fw->size != me_req_size) { 2592 printk(KERN_ERR 2593 "r600_cp: Bogus length %zu in firmware \"%s\"\n", 2594 rdev->me_fw->size, fw_name); 2595 err = -EINVAL; 2596 } 2597 2598 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name); 2599 err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev); 2600 if (err) 2601 goto out; 2602 if (rdev->rlc_fw->size != rlc_req_size) { 2603 printk(KERN_ERR 2604 "r600_rlc: Bogus length %zu in firmware \"%s\"\n", 2605 rdev->rlc_fw->size, fw_name); 2606 err = -EINVAL; 2607 } 2608 2609 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_HEMLOCK)) { 2610 snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", smc_chip_name); 2611 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev); 2612 if (err) { 2613 printk(KERN_ERR 2614 "smc: error loading firmware \"%s\"\n", 2615 fw_name); 2616 release_firmware(rdev->smc_fw); 2617 rdev->smc_fw = NULL; 2618 err = 0; 2619 } else if (rdev->smc_fw->size != smc_req_size) { 2620 printk(KERN_ERR 2621 "smc: Bogus length %zu in firmware \"%s\"\n", 2622 rdev->smc_fw->size, fw_name); 2623 err = -EINVAL; 2624 } 2625 } 2626 2627 out: 2628 if (err) { 2629 if (err != -EINVAL) 2630 printk(KERN_ERR 2631 "r600_cp: Failed to load firmware \"%s\"\n", 2632 fw_name); 2633 release_firmware(rdev->pfp_fw); 2634 rdev->pfp_fw = NULL; 2635 release_firmware(rdev->me_fw); 2636 rdev->me_fw = NULL; 2637 release_firmware(rdev->rlc_fw); 2638 rdev->rlc_fw = NULL; 2639 release_firmware(rdev->smc_fw); 2640 rdev->smc_fw = NULL; 2641 } 2642 return err; 2643 } 2644 2645 u32 r600_gfx_get_rptr(struct radeon_device *rdev, 2646 struct radeon_ring *ring) 2647 { 2648 u32 rptr; 2649 2650 if (rdev->wb.enabled) 2651 rptr = rdev->wb.wb[ring->rptr_offs/4]; 2652 else 2653 rptr = RREG32(R600_CP_RB_RPTR); 2654 2655 return rptr; 2656 } 2657 2658 u32 r600_gfx_get_wptr(struct radeon_device *rdev, 2659 struct radeon_ring *ring) 2660 { 2661 u32 wptr; 2662 2663 wptr = RREG32(R600_CP_RB_WPTR); 2664 2665 return wptr; 2666 } 2667 2668 void r600_gfx_set_wptr(struct radeon_device *rdev, 2669 struct radeon_ring *ring) 2670 { 2671 WREG32(R600_CP_RB_WPTR, ring->wptr); 2672 (void)RREG32(R600_CP_RB_WPTR); 2673 } 2674 2675 static int r600_cp_load_microcode(struct radeon_device *rdev) 2676 { 2677 const __be32 *fw_data; 2678 int i; 2679 2680 if (!rdev->me_fw || !rdev->pfp_fw) 2681 return -EINVAL; 2682 2683 r600_cp_stop(rdev); 2684 2685 WREG32(CP_RB_CNTL, 2686 #ifdef __BIG_ENDIAN 2687 BUF_SWAP_32BIT | 2688 #endif 2689 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); 2690 2691 /* Reset cp */ 2692 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); 2693 RREG32(GRBM_SOFT_RESET); 2694 mdelay(15); 2695 WREG32(GRBM_SOFT_RESET, 0); 2696 2697 WREG32(CP_ME_RAM_WADDR, 0); 2698 2699 fw_data = (const __be32 *)rdev->me_fw->data; 2700 WREG32(CP_ME_RAM_WADDR, 0); 2701 for (i = 0; i < R600_PM4_UCODE_SIZE * 3; i++) 2702 WREG32(CP_ME_RAM_DATA, 2703 be32_to_cpup(fw_data++)); 2704 2705 fw_data = (const __be32 *)rdev->pfp_fw->data; 2706 WREG32(CP_PFP_UCODE_ADDR, 0); 2707 for (i = 0; i < R600_PFP_UCODE_SIZE; i++) 2708 WREG32(CP_PFP_UCODE_DATA, 2709 be32_to_cpup(fw_data++)); 2710 2711 WREG32(CP_PFP_UCODE_ADDR, 0); 2712 WREG32(CP_ME_RAM_WADDR, 0); 2713 WREG32(CP_ME_RAM_RADDR, 0); 2714 return 0; 2715 } 2716 2717 int r600_cp_start(struct radeon_device *rdev) 2718 { 2719 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2720 int r; 2721 uint32_t cp_me; 2722 2723 r = radeon_ring_lock(rdev, ring, 7); 2724 if (r) { 2725 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); 2726 return r; 2727 } 2728 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); 2729 radeon_ring_write(ring, 0x1); 2730 if (rdev->family >= CHIP_RV770) { 2731 radeon_ring_write(ring, 0x0); 2732 radeon_ring_write(ring, rdev->config.rv770.max_hw_contexts - 1); 2733 } else { 2734 radeon_ring_write(ring, 0x3); 2735 radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1); 2736 } 2737 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); 2738 radeon_ring_write(ring, 0); 2739 radeon_ring_write(ring, 0); 2740 radeon_ring_unlock_commit(rdev, ring, false); 2741 2742 cp_me = 0xff; 2743 WREG32(R_0086D8_CP_ME_CNTL, cp_me); 2744 return 0; 2745 } 2746 2747 int r600_cp_resume(struct radeon_device *rdev) 2748 { 2749 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2750 u32 tmp; 2751 u32 rb_bufsz; 2752 int r; 2753 2754 /* Reset cp */ 2755 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); 2756 RREG32(GRBM_SOFT_RESET); 2757 mdelay(15); 2758 WREG32(GRBM_SOFT_RESET, 0); 2759 2760 /* Set ring buffer size */ 2761 rb_bufsz = order_base_2(ring->ring_size / 8); 2762 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 2763 #ifdef __BIG_ENDIAN 2764 tmp |= BUF_SWAP_32BIT; 2765 #endif 2766 WREG32(CP_RB_CNTL, tmp); 2767 WREG32(CP_SEM_WAIT_TIMER, 0x0); 2768 2769 /* Set the write pointer delay */ 2770 WREG32(CP_RB_WPTR_DELAY, 0); 2771 2772 /* Initialize the ring buffer's read and write pointers */ 2773 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA); 2774 WREG32(CP_RB_RPTR_WR, 0); 2775 ring->wptr = 0; 2776 WREG32(CP_RB_WPTR, ring->wptr); 2777 2778 /* set the wb address whether it's enabled or not */ 2779 WREG32(CP_RB_RPTR_ADDR, 2780 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC)); 2781 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); 2782 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); 2783 2784 if (rdev->wb.enabled) 2785 WREG32(SCRATCH_UMSK, 0xff); 2786 else { 2787 tmp |= RB_NO_UPDATE; 2788 WREG32(SCRATCH_UMSK, 0); 2789 } 2790 2791 mdelay(1); 2792 WREG32(CP_RB_CNTL, tmp); 2793 2794 WREG32(CP_RB_BASE, ring->gpu_addr >> 8); 2795 WREG32(CP_DEBUG, (1 << 27) | (1 << 28)); 2796 2797 r600_cp_start(rdev); 2798 ring->ready = true; 2799 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring); 2800 if (r) { 2801 ring->ready = false; 2802 return r; 2803 } 2804 2805 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX) 2806 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); 2807 2808 return 0; 2809 } 2810 2811 void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size) 2812 { 2813 u32 rb_bufsz; 2814 int r; 2815 2816 /* Align ring size */ 2817 rb_bufsz = order_base_2(ring_size / 8); 2818 ring_size = (1 << (rb_bufsz + 1)) * 4; 2819 ring->ring_size = ring_size; 2820 ring->align_mask = 16 - 1; 2821 2822 if (radeon_ring_supports_scratch_reg(rdev, ring)) { 2823 r = radeon_scratch_get(rdev, &ring->rptr_save_reg); 2824 if (r) { 2825 DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r); 2826 ring->rptr_save_reg = 0; 2827 } 2828 } 2829 } 2830 2831 void r600_cp_fini(struct radeon_device *rdev) 2832 { 2833 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2834 r600_cp_stop(rdev); 2835 radeon_ring_fini(rdev, ring); 2836 radeon_scratch_free(rdev, ring->rptr_save_reg); 2837 } 2838 2839 /* 2840 * GPU scratch registers helpers function. 2841 */ 2842 void r600_scratch_init(struct radeon_device *rdev) 2843 { 2844 int i; 2845 2846 rdev->scratch.num_reg = 7; 2847 rdev->scratch.reg_base = SCRATCH_REG0; 2848 for (i = 0; i < rdev->scratch.num_reg; i++) { 2849 rdev->scratch.free[i] = true; 2850 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4); 2851 } 2852 } 2853 2854 int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *ring) 2855 { 2856 uint32_t scratch; 2857 uint32_t tmp = 0; 2858 unsigned i; 2859 int r; 2860 2861 r = radeon_scratch_get(rdev, &scratch); 2862 if (r) { 2863 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r); 2864 return r; 2865 } 2866 WREG32(scratch, 0xCAFEDEAD); 2867 r = radeon_ring_lock(rdev, ring, 3); 2868 if (r) { 2869 DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", ring->idx, r); 2870 radeon_scratch_free(rdev, scratch); 2871 return r; 2872 } 2873 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2874 radeon_ring_write(ring, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); 2875 radeon_ring_write(ring, 0xDEADBEEF); 2876 radeon_ring_unlock_commit(rdev, ring, false); 2877 for (i = 0; i < rdev->usec_timeout; i++) { 2878 tmp = RREG32(scratch); 2879 if (tmp == 0xDEADBEEF) 2880 break; 2881 DRM_UDELAY(1); 2882 } 2883 if (i < rdev->usec_timeout) { 2884 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); 2885 } else { 2886 DRM_ERROR("radeon: ring %d test failed (scratch(0x%04X)=0x%08X)\n", 2887 ring->idx, scratch, tmp); 2888 r = -EINVAL; 2889 } 2890 radeon_scratch_free(rdev, scratch); 2891 return r; 2892 } 2893 2894 /* 2895 * CP fences/semaphores 2896 */ 2897 2898 void r600_fence_ring_emit(struct radeon_device *rdev, 2899 struct radeon_fence *fence) 2900 { 2901 struct radeon_ring *ring = &rdev->ring[fence->ring]; 2902 u32 cp_coher_cntl = PACKET3_TC_ACTION_ENA | PACKET3_VC_ACTION_ENA | 2903 PACKET3_SH_ACTION_ENA; 2904 2905 if (rdev->family >= CHIP_RV770) 2906 cp_coher_cntl |= PACKET3_FULL_CACHE_ENA; 2907 2908 if (rdev->wb.use_event) { 2909 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; 2910 /* flush read cache over gart */ 2911 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 2912 radeon_ring_write(ring, cp_coher_cntl); 2913 radeon_ring_write(ring, 0xFFFFFFFF); 2914 radeon_ring_write(ring, 0); 2915 radeon_ring_write(ring, 10); /* poll interval */ 2916 /* EVENT_WRITE_EOP - flush caches, send int */ 2917 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); 2918 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5)); 2919 radeon_ring_write(ring, lower_32_bits(addr)); 2920 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); 2921 radeon_ring_write(ring, fence->seq); 2922 radeon_ring_write(ring, 0); 2923 } else { 2924 /* flush read cache over gart */ 2925 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 2926 radeon_ring_write(ring, cp_coher_cntl); 2927 radeon_ring_write(ring, 0xFFFFFFFF); 2928 radeon_ring_write(ring, 0); 2929 radeon_ring_write(ring, 10); /* poll interval */ 2930 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); 2931 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0)); 2932 /* wait for 3D idle clean */ 2933 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2934 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); 2935 radeon_ring_write(ring, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit); 2936 /* Emit fence sequence & fire IRQ */ 2937 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2938 radeon_ring_write(ring, ((rdev->fence_drv[fence->ring].scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); 2939 radeon_ring_write(ring, fence->seq); 2940 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */ 2941 radeon_ring_write(ring, PACKET0(CP_INT_STATUS, 0)); 2942 radeon_ring_write(ring, RB_INT_STAT); 2943 } 2944 } 2945 2946 /** 2947 * r600_semaphore_ring_emit - emit a semaphore on the CP ring 2948 * 2949 * @rdev: radeon_device pointer 2950 * @ring: radeon ring buffer object 2951 * @semaphore: radeon semaphore object 2952 * @emit_wait: Is this a sempahore wait? 2953 * 2954 * Emits a semaphore signal/wait packet to the CP ring and prevents the PFP 2955 * from running ahead of semaphore waits. 2956 */ 2957 bool r600_semaphore_ring_emit(struct radeon_device *rdev, 2958 struct radeon_ring *ring, 2959 struct radeon_semaphore *semaphore, 2960 bool emit_wait) 2961 { 2962 uint64_t addr = semaphore->gpu_addr; 2963 unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL; 2964 2965 if (rdev->family < CHIP_CAYMAN) 2966 sel |= PACKET3_SEM_WAIT_ON_SIGNAL; 2967 2968 radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1)); 2969 radeon_ring_write(ring, lower_32_bits(addr)); 2970 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel); 2971 2972 /* PFP_SYNC_ME packet only exists on 7xx+, only enable it on eg+ */ 2973 if (emit_wait && (rdev->family >= CHIP_CEDAR)) { 2974 /* Prevent the PFP from running ahead of the semaphore wait */ 2975 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 2976 radeon_ring_write(ring, 0x0); 2977 } 2978 2979 return true; 2980 } 2981 2982 /** 2983 * r600_copy_cpdma - copy pages using the CP DMA engine 2984 * 2985 * @rdev: radeon_device pointer 2986 * @src_offset: src GPU address 2987 * @dst_offset: dst GPU address 2988 * @num_gpu_pages: number of GPU pages to xfer 2989 * @fence: radeon fence object 2990 * 2991 * Copy GPU paging using the CP DMA engine (r6xx+). 2992 * Used by the radeon ttm implementation to move pages if 2993 * registered as the asic copy callback. 2994 */ 2995 struct radeon_fence *r600_copy_cpdma(struct radeon_device *rdev, 2996 uint64_t src_offset, uint64_t dst_offset, 2997 unsigned num_gpu_pages, 2998 struct reservation_object *resv) 2999 { 3000 struct radeon_fence *fence; 3001 struct radeon_sync sync; 3002 int ring_index = rdev->asic->copy.blit_ring_index; 3003 struct radeon_ring *ring = &rdev->ring[ring_index]; 3004 u32 size_in_bytes, cur_size_in_bytes, tmp; 3005 int i, num_loops; 3006 int r = 0; 3007 3008 radeon_sync_create(&sync); 3009 3010 size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT); 3011 num_loops = DIV_ROUND_UP(size_in_bytes, 0x1fffff); 3012 r = radeon_ring_lock(rdev, ring, num_loops * 6 + 24); 3013 if (r) { 3014 DRM_ERROR("radeon: moving bo (%d).\n", r); 3015 radeon_sync_free(rdev, &sync, NULL); 3016 return ERR_PTR(r); 3017 } 3018 3019 radeon_sync_resv(rdev, &sync, resv, false); 3020 radeon_sync_rings(rdev, &sync, ring->idx); 3021 3022 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 3023 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); 3024 radeon_ring_write(ring, WAIT_3D_IDLE_bit); 3025 for (i = 0; i < num_loops; i++) { 3026 cur_size_in_bytes = size_in_bytes; 3027 if (cur_size_in_bytes > 0x1fffff) 3028 cur_size_in_bytes = 0x1fffff; 3029 size_in_bytes -= cur_size_in_bytes; 3030 tmp = upper_32_bits(src_offset) & 0xff; 3031 if (size_in_bytes == 0) 3032 tmp |= PACKET3_CP_DMA_CP_SYNC; 3033 radeon_ring_write(ring, PACKET3(PACKET3_CP_DMA, 4)); 3034 radeon_ring_write(ring, lower_32_bits(src_offset)); 3035 radeon_ring_write(ring, tmp); 3036 radeon_ring_write(ring, lower_32_bits(dst_offset)); 3037 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff); 3038 radeon_ring_write(ring, cur_size_in_bytes); 3039 src_offset += cur_size_in_bytes; 3040 dst_offset += cur_size_in_bytes; 3041 } 3042 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 3043 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); 3044 radeon_ring_write(ring, WAIT_CP_DMA_IDLE_bit); 3045 3046 r = radeon_fence_emit(rdev, &fence, ring->idx); 3047 if (r) { 3048 radeon_ring_unlock_undo(rdev, ring); 3049 radeon_sync_free(rdev, &sync, NULL); 3050 return ERR_PTR(r); 3051 } 3052 3053 radeon_ring_unlock_commit(rdev, ring, false); 3054 radeon_sync_free(rdev, &sync, fence); 3055 3056 return fence; 3057 } 3058 3059 int r600_set_surface_reg(struct radeon_device *rdev, int reg, 3060 uint32_t tiling_flags, uint32_t pitch, 3061 uint32_t offset, uint32_t obj_size) 3062 { 3063 /* FIXME: implement */ 3064 return 0; 3065 } 3066 3067 void r600_clear_surface_reg(struct radeon_device *rdev, int reg) 3068 { 3069 /* FIXME: implement */ 3070 } 3071 3072 static int r600_startup(struct radeon_device *rdev) 3073 { 3074 struct radeon_ring *ring; 3075 int r; 3076 3077 /* enable pcie gen2 link */ 3078 r600_pcie_gen2_enable(rdev); 3079 3080 /* scratch needs to be initialized before MC */ 3081 r = r600_vram_scratch_init(rdev); 3082 if (r) 3083 return r; 3084 3085 r600_mc_program(rdev); 3086 3087 if (rdev->flags & RADEON_IS_AGP) { 3088 r600_agp_enable(rdev); 3089 } else { 3090 r = r600_pcie_gart_enable(rdev); 3091 if (r) 3092 return r; 3093 } 3094 r600_gpu_init(rdev); 3095 3096 /* allocate wb buffer */ 3097 r = radeon_wb_init(rdev); 3098 if (r) 3099 return r; 3100 3101 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 3102 if (r) { 3103 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 3104 return r; 3105 } 3106 3107 if (rdev->has_uvd) { 3108 r = uvd_v1_0_resume(rdev); 3109 if (!r) { 3110 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_UVD_INDEX); 3111 if (r) { 3112 dev_err(rdev->dev, "failed initializing UVD fences (%d).\n", r); 3113 } 3114 } 3115 if (r) 3116 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0; 3117 } 3118 3119 /* Enable IRQ */ 3120 if (!rdev->irq.installed) { 3121 r = radeon_irq_kms_init(rdev); 3122 if (r) 3123 return r; 3124 } 3125 3126 r = r600_irq_init(rdev); 3127 if (r) { 3128 DRM_ERROR("radeon: IH init failed (%d).\n", r); 3129 radeon_irq_kms_fini(rdev); 3130 return r; 3131 } 3132 r600_irq_set(rdev); 3133 3134 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 3135 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, 3136 RADEON_CP_PACKET2); 3137 if (r) 3138 return r; 3139 3140 r = r600_cp_load_microcode(rdev); 3141 if (r) 3142 return r; 3143 r = r600_cp_resume(rdev); 3144 if (r) 3145 return r; 3146 3147 if (rdev->has_uvd) { 3148 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; 3149 if (ring->ring_size) { 3150 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, 3151 RADEON_CP_PACKET2); 3152 if (!r) 3153 r = uvd_v1_0_init(rdev); 3154 if (r) 3155 DRM_ERROR("radeon: failed initializing UVD (%d).\n", r); 3156 } 3157 } 3158 3159 r = radeon_ib_pool_init(rdev); 3160 if (r) { 3161 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 3162 return r; 3163 } 3164 3165 r = radeon_audio_init(rdev); 3166 if (r) { 3167 DRM_ERROR("radeon: audio init failed\n"); 3168 return r; 3169 } 3170 3171 return 0; 3172 } 3173 3174 void r600_vga_set_state(struct radeon_device *rdev, bool state) 3175 { 3176 uint32_t temp; 3177 3178 temp = RREG32(CONFIG_CNTL); 3179 if (state == false) { 3180 temp &= ~(1<<0); 3181 temp |= (1<<1); 3182 } else { 3183 temp &= ~(1<<1); 3184 } 3185 WREG32(CONFIG_CNTL, temp); 3186 } 3187 3188 int r600_resume(struct radeon_device *rdev) 3189 { 3190 int r; 3191 3192 /* Do not reset GPU before posting, on r600 hw unlike on r500 hw, 3193 * posting will perform necessary task to bring back GPU into good 3194 * shape. 3195 */ 3196 /* post card */ 3197 atom_asic_init(rdev->mode_info.atom_context); 3198 3199 if (rdev->pm.pm_method == PM_METHOD_DPM) 3200 radeon_pm_resume(rdev); 3201 3202 rdev->accel_working = true; 3203 r = r600_startup(rdev); 3204 if (r) { 3205 DRM_ERROR("r600 startup failed on resume\n"); 3206 rdev->accel_working = false; 3207 return r; 3208 } 3209 3210 return r; 3211 } 3212 3213 int r600_suspend(struct radeon_device *rdev) 3214 { 3215 radeon_pm_suspend(rdev); 3216 radeon_audio_fini(rdev); 3217 r600_cp_stop(rdev); 3218 if (rdev->has_uvd) { 3219 uvd_v1_0_fini(rdev); 3220 radeon_uvd_suspend(rdev); 3221 } 3222 r600_irq_suspend(rdev); 3223 radeon_wb_disable(rdev); 3224 r600_pcie_gart_disable(rdev); 3225 3226 return 0; 3227 } 3228 3229 /* Plan is to move initialization in that function and use 3230 * helper function so that radeon_device_init pretty much 3231 * do nothing more than calling asic specific function. This 3232 * should also allow to remove a bunch of callback function 3233 * like vram_info. 3234 */ 3235 int r600_init(struct radeon_device *rdev) 3236 { 3237 int r; 3238 3239 if (r600_debugfs_mc_info_init(rdev)) { 3240 DRM_ERROR("Failed to register debugfs file for mc !\n"); 3241 } 3242 /* Read BIOS */ 3243 if (!radeon_get_bios(rdev)) { 3244 if (ASIC_IS_AVIVO(rdev)) 3245 return -EINVAL; 3246 } 3247 /* Must be an ATOMBIOS */ 3248 if (!rdev->is_atom_bios) { 3249 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n"); 3250 return -EINVAL; 3251 } 3252 r = radeon_atombios_init(rdev); 3253 if (r) 3254 return r; 3255 /* Post card if necessary */ 3256 if (!radeon_card_posted(rdev)) { 3257 if (!rdev->bios) { 3258 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); 3259 return -EINVAL; 3260 } 3261 DRM_INFO("GPU not posted. posting now...\n"); 3262 atom_asic_init(rdev->mode_info.atom_context); 3263 } 3264 /* Initialize scratch registers */ 3265 r600_scratch_init(rdev); 3266 /* Initialize surface registers */ 3267 radeon_surface_init(rdev); 3268 /* Initialize clocks */ 3269 radeon_get_clock_info(rdev->ddev); 3270 /* Fence driver */ 3271 r = radeon_fence_driver_init(rdev); 3272 if (r) 3273 return r; 3274 if (rdev->flags & RADEON_IS_AGP) { 3275 r = radeon_agp_init(rdev); 3276 if (r) 3277 radeon_agp_disable(rdev); 3278 } 3279 r = r600_mc_init(rdev); 3280 if (r) 3281 return r; 3282 /* Memory manager */ 3283 r = radeon_bo_init(rdev); 3284 if (r) 3285 return r; 3286 3287 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { 3288 r = r600_init_microcode(rdev); 3289 if (r) { 3290 DRM_ERROR("Failed to load firmware!\n"); 3291 return r; 3292 } 3293 } 3294 3295 /* Initialize power management */ 3296 radeon_pm_init(rdev); 3297 3298 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL; 3299 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024); 3300 3301 if (rdev->has_uvd) { 3302 r = radeon_uvd_init(rdev); 3303 if (!r) { 3304 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL; 3305 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX], 4096); 3306 } 3307 } 3308 3309 rdev->ih.ring_obj = NULL; 3310 r600_ih_ring_init(rdev, 64 * 1024); 3311 3312 r = r600_pcie_gart_init(rdev); 3313 if (r) 3314 return r; 3315 3316 rdev->accel_working = true; 3317 r = r600_startup(rdev); 3318 if (r) { 3319 dev_err(rdev->dev, "disabling GPU acceleration\n"); 3320 r600_cp_fini(rdev); 3321 r600_irq_fini(rdev); 3322 radeon_wb_fini(rdev); 3323 radeon_ib_pool_fini(rdev); 3324 radeon_irq_kms_fini(rdev); 3325 r600_pcie_gart_fini(rdev); 3326 rdev->accel_working = false; 3327 } 3328 3329 return 0; 3330 } 3331 3332 void r600_fini(struct radeon_device *rdev) 3333 { 3334 radeon_pm_fini(rdev); 3335 radeon_audio_fini(rdev); 3336 r600_cp_fini(rdev); 3337 r600_irq_fini(rdev); 3338 if (rdev->has_uvd) { 3339 uvd_v1_0_fini(rdev); 3340 radeon_uvd_fini(rdev); 3341 } 3342 radeon_wb_fini(rdev); 3343 radeon_ib_pool_fini(rdev); 3344 radeon_irq_kms_fini(rdev); 3345 r600_pcie_gart_fini(rdev); 3346 r600_vram_scratch_fini(rdev); 3347 radeon_agp_fini(rdev); 3348 radeon_gem_fini(rdev); 3349 radeon_fence_driver_fini(rdev); 3350 radeon_bo_fini(rdev); 3351 radeon_atombios_fini(rdev); 3352 kfree(rdev->bios); 3353 rdev->bios = NULL; 3354 } 3355 3356 3357 /* 3358 * CS stuff 3359 */ 3360 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) 3361 { 3362 struct radeon_ring *ring = &rdev->ring[ib->ring]; 3363 u32 next_rptr; 3364 3365 if (ring->rptr_save_reg) { 3366 next_rptr = ring->wptr + 3 + 4; 3367 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 3368 radeon_ring_write(ring, ((ring->rptr_save_reg - 3369 PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); 3370 radeon_ring_write(ring, next_rptr); 3371 } else if (rdev->wb.enabled) { 3372 next_rptr = ring->wptr + 5 + 4; 3373 radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3)); 3374 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); 3375 radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18)); 3376 radeon_ring_write(ring, next_rptr); 3377 radeon_ring_write(ring, 0); 3378 } 3379 3380 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 3381 radeon_ring_write(ring, 3382 #ifdef __BIG_ENDIAN 3383 (2 << 0) | 3384 #endif 3385 (ib->gpu_addr & 0xFFFFFFFC)); 3386 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF); 3387 radeon_ring_write(ring, ib->length_dw); 3388 } 3389 3390 int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) 3391 { 3392 struct radeon_ib ib; 3393 uint32_t scratch; 3394 uint32_t tmp = 0; 3395 unsigned i; 3396 int r; 3397 3398 r = radeon_scratch_get(rdev, &scratch); 3399 if (r) { 3400 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r); 3401 return r; 3402 } 3403 WREG32(scratch, 0xCAFEDEAD); 3404 r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256); 3405 if (r) { 3406 DRM_ERROR("radeon: failed to get ib (%d).\n", r); 3407 goto free_scratch; 3408 } 3409 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1); 3410 ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); 3411 ib.ptr[2] = 0xDEADBEEF; 3412 ib.length_dw = 3; 3413 r = radeon_ib_schedule(rdev, &ib, NULL, false); 3414 if (r) { 3415 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); 3416 goto free_ib; 3417 } 3418 r = radeon_fence_wait(ib.fence, false); 3419 if (r) { 3420 DRM_ERROR("radeon: fence wait failed (%d).\n", r); 3421 goto free_ib; 3422 } 3423 for (i = 0; i < rdev->usec_timeout; i++) { 3424 tmp = RREG32(scratch); 3425 if (tmp == 0xDEADBEEF) 3426 break; 3427 DRM_UDELAY(1); 3428 } 3429 if (i < rdev->usec_timeout) { 3430 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i); 3431 } else { 3432 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n", 3433 scratch, tmp); 3434 r = -EINVAL; 3435 } 3436 free_ib: 3437 radeon_ib_free(rdev, &ib); 3438 free_scratch: 3439 radeon_scratch_free(rdev, scratch); 3440 return r; 3441 } 3442 3443 /* 3444 * Interrupts 3445 * 3446 * Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty 3447 * the same as the CP ring buffer, but in reverse. Rather than the CPU 3448 * writing to the ring and the GPU consuming, the GPU writes to the ring 3449 * and host consumes. As the host irq handler processes interrupts, it 3450 * increments the rptr. When the rptr catches up with the wptr, all the 3451 * current interrupts have been processed. 3452 */ 3453 3454 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size) 3455 { 3456 u32 rb_bufsz; 3457 3458 /* Align ring size */ 3459 rb_bufsz = order_base_2(ring_size / 4); 3460 ring_size = (1 << rb_bufsz) * 4; 3461 rdev->ih.ring_size = ring_size; 3462 rdev->ih.ptr_mask = rdev->ih.ring_size - 1; 3463 rdev->ih.rptr = 0; 3464 } 3465 3466 int r600_ih_ring_alloc(struct radeon_device *rdev) 3467 { 3468 int r; 3469 3470 /* Allocate ring buffer */ 3471 if (rdev->ih.ring_obj == NULL) { 3472 r = radeon_bo_create(rdev, rdev->ih.ring_size, 3473 PAGE_SIZE, true, 3474 RADEON_GEM_DOMAIN_GTT, 0, 3475 NULL, NULL, &rdev->ih.ring_obj); 3476 if (r) { 3477 DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r); 3478 return r; 3479 } 3480 r = radeon_bo_reserve(rdev->ih.ring_obj, false); 3481 if (unlikely(r != 0)) 3482 return r; 3483 r = radeon_bo_pin(rdev->ih.ring_obj, 3484 RADEON_GEM_DOMAIN_GTT, 3485 &rdev->ih.gpu_addr); 3486 if (r) { 3487 radeon_bo_unreserve(rdev->ih.ring_obj); 3488 DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r); 3489 return r; 3490 } 3491 r = radeon_bo_kmap(rdev->ih.ring_obj, 3492 (void **)__UNVOLATILE(&rdev->ih.ring)); 3493 radeon_bo_unreserve(rdev->ih.ring_obj); 3494 if (r) { 3495 DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r); 3496 return r; 3497 } 3498 } 3499 return 0; 3500 } 3501 3502 void r600_ih_ring_fini(struct radeon_device *rdev) 3503 { 3504 int r; 3505 if (rdev->ih.ring_obj) { 3506 r = radeon_bo_reserve(rdev->ih.ring_obj, false); 3507 if (likely(r == 0)) { 3508 radeon_bo_kunmap(rdev->ih.ring_obj); 3509 radeon_bo_unpin(rdev->ih.ring_obj); 3510 radeon_bo_unreserve(rdev->ih.ring_obj); 3511 } 3512 radeon_bo_unref(&rdev->ih.ring_obj); 3513 rdev->ih.ring = NULL; 3514 rdev->ih.ring_obj = NULL; 3515 } 3516 } 3517 3518 void r600_rlc_stop(struct radeon_device *rdev) 3519 { 3520 3521 if ((rdev->family >= CHIP_RV770) && 3522 (rdev->family <= CHIP_RV740)) { 3523 /* r7xx asics need to soft reset RLC before halting */ 3524 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC); 3525 RREG32(SRBM_SOFT_RESET); 3526 mdelay(15); 3527 WREG32(SRBM_SOFT_RESET, 0); 3528 RREG32(SRBM_SOFT_RESET); 3529 } 3530 3531 WREG32(RLC_CNTL, 0); 3532 } 3533 3534 static void r600_rlc_start(struct radeon_device *rdev) 3535 { 3536 WREG32(RLC_CNTL, RLC_ENABLE); 3537 } 3538 3539 static int r600_rlc_resume(struct radeon_device *rdev) 3540 { 3541 u32 i; 3542 const __be32 *fw_data; 3543 3544 if (!rdev->rlc_fw) 3545 return -EINVAL; 3546 3547 r600_rlc_stop(rdev); 3548 3549 WREG32(RLC_HB_CNTL, 0); 3550 3551 WREG32(RLC_HB_BASE, 0); 3552 WREG32(RLC_HB_RPTR, 0); 3553 WREG32(RLC_HB_WPTR, 0); 3554 WREG32(RLC_HB_WPTR_LSB_ADDR, 0); 3555 WREG32(RLC_HB_WPTR_MSB_ADDR, 0); 3556 WREG32(RLC_MC_CNTL, 0); 3557 WREG32(RLC_UCODE_CNTL, 0); 3558 3559 fw_data = (const __be32 *)rdev->rlc_fw->data; 3560 if (rdev->family >= CHIP_RV770) { 3561 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) { 3562 WREG32(RLC_UCODE_ADDR, i); 3563 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); 3564 } 3565 } else { 3566 for (i = 0; i < R600_RLC_UCODE_SIZE; i++) { 3567 WREG32(RLC_UCODE_ADDR, i); 3568 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); 3569 } 3570 } 3571 WREG32(RLC_UCODE_ADDR, 0); 3572 3573 r600_rlc_start(rdev); 3574 3575 return 0; 3576 } 3577 3578 static void r600_enable_interrupts(struct radeon_device *rdev) 3579 { 3580 u32 ih_cntl = RREG32(IH_CNTL); 3581 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); 3582 3583 ih_cntl |= ENABLE_INTR; 3584 ih_rb_cntl |= IH_RB_ENABLE; 3585 WREG32(IH_CNTL, ih_cntl); 3586 WREG32(IH_RB_CNTL, ih_rb_cntl); 3587 rdev->ih.enabled = true; 3588 } 3589 3590 void r600_disable_interrupts(struct radeon_device *rdev) 3591 { 3592 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); 3593 u32 ih_cntl = RREG32(IH_CNTL); 3594 3595 ih_rb_cntl &= ~IH_RB_ENABLE; 3596 ih_cntl &= ~ENABLE_INTR; 3597 WREG32(IH_RB_CNTL, ih_rb_cntl); 3598 WREG32(IH_CNTL, ih_cntl); 3599 /* set rptr, wptr to 0 */ 3600 WREG32(IH_RB_RPTR, 0); 3601 WREG32(IH_RB_WPTR, 0); 3602 rdev->ih.enabled = false; 3603 rdev->ih.rptr = 0; 3604 } 3605 3606 static void r600_disable_interrupt_state(struct radeon_device *rdev) 3607 { 3608 u32 tmp; 3609 3610 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); 3611 tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE; 3612 WREG32(DMA_CNTL, tmp); 3613 WREG32(GRBM_INT_CNTL, 0); 3614 WREG32(DxMODE_INT_MASK, 0); 3615 WREG32(D1GRPH_INTERRUPT_CONTROL, 0); 3616 WREG32(D2GRPH_INTERRUPT_CONTROL, 0); 3617 if (ASIC_IS_DCE3(rdev)) { 3618 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0); 3619 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0); 3620 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3621 WREG32(DC_HPD1_INT_CONTROL, tmp); 3622 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3623 WREG32(DC_HPD2_INT_CONTROL, tmp); 3624 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3625 WREG32(DC_HPD3_INT_CONTROL, tmp); 3626 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3627 WREG32(DC_HPD4_INT_CONTROL, tmp); 3628 if (ASIC_IS_DCE32(rdev)) { 3629 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3630 WREG32(DC_HPD5_INT_CONTROL, tmp); 3631 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3632 WREG32(DC_HPD6_INT_CONTROL, tmp); 3633 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3634 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp); 3635 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3636 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp); 3637 } else { 3638 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3639 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); 3640 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3641 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp); 3642 } 3643 } else { 3644 WREG32(DACA_AUTODETECT_INT_CONTROL, 0); 3645 WREG32(DACB_AUTODETECT_INT_CONTROL, 0); 3646 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; 3647 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); 3648 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; 3649 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); 3650 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; 3651 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); 3652 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3653 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); 3654 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3655 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp); 3656 } 3657 } 3658 3659 int r600_irq_init(struct radeon_device *rdev) 3660 { 3661 int ret = 0; 3662 int rb_bufsz; 3663 u32 interrupt_cntl, ih_cntl, ih_rb_cntl; 3664 3665 /* allocate ring */ 3666 ret = r600_ih_ring_alloc(rdev); 3667 if (ret) 3668 return ret; 3669 3670 /* disable irqs */ 3671 r600_disable_interrupts(rdev); 3672 3673 /* init rlc */ 3674 if (rdev->family >= CHIP_CEDAR) 3675 ret = evergreen_rlc_resume(rdev); 3676 else 3677 ret = r600_rlc_resume(rdev); 3678 if (ret) { 3679 r600_ih_ring_fini(rdev); 3680 return ret; 3681 } 3682 3683 /* setup interrupt control */ 3684 /* set dummy read address to ring address */ 3685 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8); 3686 interrupt_cntl = RREG32(INTERRUPT_CNTL); 3687 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi 3688 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN 3689 */ 3690 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE; 3691 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */ 3692 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN; 3693 WREG32(INTERRUPT_CNTL, interrupt_cntl); 3694 3695 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8); 3696 rb_bufsz = order_base_2(rdev->ih.ring_size / 4); 3697 3698 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE | 3699 IH_WPTR_OVERFLOW_CLEAR | 3700 (rb_bufsz << 1)); 3701 3702 if (rdev->wb.enabled) 3703 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE; 3704 3705 /* set the writeback address whether it's enabled or not */ 3706 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC); 3707 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF); 3708 3709 WREG32(IH_RB_CNTL, ih_rb_cntl); 3710 3711 /* set rptr, wptr to 0 */ 3712 WREG32(IH_RB_RPTR, 0); 3713 WREG32(IH_RB_WPTR, 0); 3714 3715 /* Default settings for IH_CNTL (disabled at first) */ 3716 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10); 3717 /* RPTR_REARM only works if msi's are enabled */ 3718 if (rdev->msi_enabled) 3719 ih_cntl |= RPTR_REARM; 3720 WREG32(IH_CNTL, ih_cntl); 3721 3722 /* force the active interrupt state to all disabled */ 3723 if (rdev->family >= CHIP_CEDAR) 3724 evergreen_disable_interrupt_state(rdev); 3725 else 3726 r600_disable_interrupt_state(rdev); 3727 3728 /* at this point everything should be setup correctly to enable master */ 3729 pci_set_master(rdev->pdev); 3730 3731 /* enable irqs */ 3732 r600_enable_interrupts(rdev); 3733 3734 return ret; 3735 } 3736 3737 void r600_irq_suspend(struct radeon_device *rdev) 3738 { 3739 r600_irq_disable(rdev); 3740 r600_rlc_stop(rdev); 3741 } 3742 3743 void r600_irq_fini(struct radeon_device *rdev) 3744 { 3745 r600_irq_suspend(rdev); 3746 r600_ih_ring_fini(rdev); 3747 } 3748 3749 int r600_irq_set(struct radeon_device *rdev) 3750 { 3751 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE; 3752 u32 mode_int = 0; 3753 u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0; 3754 u32 grbm_int_cntl = 0; 3755 u32 hdmi0, hdmi1; 3756 u32 dma_cntl; 3757 u32 thermal_int = 0; 3758 3759 if (!rdev->irq.installed) { 3760 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); 3761 return -EINVAL; 3762 } 3763 /* don't enable anything if the ih is disabled */ 3764 if (!rdev->ih.enabled) { 3765 r600_disable_interrupts(rdev); 3766 /* force the active interrupt state to all disabled */ 3767 r600_disable_interrupt_state(rdev); 3768 return 0; 3769 } 3770 3771 if (ASIC_IS_DCE3(rdev)) { 3772 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN; 3773 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN; 3774 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN; 3775 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN; 3776 if (ASIC_IS_DCE32(rdev)) { 3777 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN; 3778 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN; 3779 hdmi0 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~AFMT_AZ_FORMAT_WTRIG_MASK; 3780 hdmi1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~AFMT_AZ_FORMAT_WTRIG_MASK; 3781 } else { 3782 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3783 hdmi1 = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3784 } 3785 } else { 3786 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN; 3787 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN; 3788 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN; 3789 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3790 hdmi1 = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3791 } 3792 3793 dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE; 3794 3795 if ((rdev->family > CHIP_R600) && (rdev->family < CHIP_RV770)) { 3796 thermal_int = RREG32(CG_THERMAL_INT) & 3797 ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW); 3798 } else if (rdev->family >= CHIP_RV770) { 3799 thermal_int = RREG32(RV770_CG_THERMAL_INT) & 3800 ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW); 3801 } 3802 if (rdev->irq.dpm_thermal) { 3803 DRM_DEBUG("dpm thermal\n"); 3804 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW; 3805 } 3806 3807 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { 3808 DRM_DEBUG("r600_irq_set: sw int\n"); 3809 cp_int_cntl |= RB_INT_ENABLE; 3810 cp_int_cntl |= TIME_STAMP_INT_ENABLE; 3811 } 3812 3813 if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) { 3814 DRM_DEBUG("r600_irq_set: sw int dma\n"); 3815 dma_cntl |= TRAP_ENABLE; 3816 } 3817 3818 if (rdev->irq.crtc_vblank_int[0] || 3819 atomic_read(&rdev->irq.pflip[0])) { 3820 DRM_DEBUG("r600_irq_set: vblank 0\n"); 3821 mode_int |= D1MODE_VBLANK_INT_MASK; 3822 } 3823 if (rdev->irq.crtc_vblank_int[1] || 3824 atomic_read(&rdev->irq.pflip[1])) { 3825 DRM_DEBUG("r600_irq_set: vblank 1\n"); 3826 mode_int |= D2MODE_VBLANK_INT_MASK; 3827 } 3828 if (rdev->irq.hpd[0]) { 3829 DRM_DEBUG("r600_irq_set: hpd 1\n"); 3830 hpd1 |= DC_HPDx_INT_EN; 3831 } 3832 if (rdev->irq.hpd[1]) { 3833 DRM_DEBUG("r600_irq_set: hpd 2\n"); 3834 hpd2 |= DC_HPDx_INT_EN; 3835 } 3836 if (rdev->irq.hpd[2]) { 3837 DRM_DEBUG("r600_irq_set: hpd 3\n"); 3838 hpd3 |= DC_HPDx_INT_EN; 3839 } 3840 if (rdev->irq.hpd[3]) { 3841 DRM_DEBUG("r600_irq_set: hpd 4\n"); 3842 hpd4 |= DC_HPDx_INT_EN; 3843 } 3844 if (rdev->irq.hpd[4]) { 3845 DRM_DEBUG("r600_irq_set: hpd 5\n"); 3846 hpd5 |= DC_HPDx_INT_EN; 3847 } 3848 if (rdev->irq.hpd[5]) { 3849 DRM_DEBUG("r600_irq_set: hpd 6\n"); 3850 hpd6 |= DC_HPDx_INT_EN; 3851 } 3852 if (rdev->irq.afmt[0]) { 3853 DRM_DEBUG("r600_irq_set: hdmi 0\n"); 3854 hdmi0 |= HDMI0_AZ_FORMAT_WTRIG_MASK; 3855 } 3856 if (rdev->irq.afmt[1]) { 3857 DRM_DEBUG("r600_irq_set: hdmi 0\n"); 3858 hdmi1 |= HDMI0_AZ_FORMAT_WTRIG_MASK; 3859 } 3860 3861 WREG32(CP_INT_CNTL, cp_int_cntl); 3862 WREG32(DMA_CNTL, dma_cntl); 3863 WREG32(DxMODE_INT_MASK, mode_int); 3864 WREG32(D1GRPH_INTERRUPT_CONTROL, DxGRPH_PFLIP_INT_MASK); 3865 WREG32(D2GRPH_INTERRUPT_CONTROL, DxGRPH_PFLIP_INT_MASK); 3866 WREG32(GRBM_INT_CNTL, grbm_int_cntl); 3867 if (ASIC_IS_DCE3(rdev)) { 3868 WREG32(DC_HPD1_INT_CONTROL, hpd1); 3869 WREG32(DC_HPD2_INT_CONTROL, hpd2); 3870 WREG32(DC_HPD3_INT_CONTROL, hpd3); 3871 WREG32(DC_HPD4_INT_CONTROL, hpd4); 3872 if (ASIC_IS_DCE32(rdev)) { 3873 WREG32(DC_HPD5_INT_CONTROL, hpd5); 3874 WREG32(DC_HPD6_INT_CONTROL, hpd6); 3875 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, hdmi0); 3876 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, hdmi1); 3877 } else { 3878 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0); 3879 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, hdmi1); 3880 } 3881 } else { 3882 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1); 3883 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2); 3884 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3); 3885 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0); 3886 WREG32(HDMI1_AUDIO_PACKET_CONTROL, hdmi1); 3887 } 3888 if ((rdev->family > CHIP_R600) && (rdev->family < CHIP_RV770)) { 3889 WREG32(CG_THERMAL_INT, thermal_int); 3890 } else if (rdev->family >= CHIP_RV770) { 3891 WREG32(RV770_CG_THERMAL_INT, thermal_int); 3892 } 3893 3894 /* posting read */ 3895 RREG32(R_000E50_SRBM_STATUS); 3896 3897 return 0; 3898 } 3899 3900 static void r600_irq_ack(struct radeon_device *rdev) 3901 { 3902 u32 tmp; 3903 3904 if (ASIC_IS_DCE3(rdev)) { 3905 rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS); 3906 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE); 3907 rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2); 3908 if (ASIC_IS_DCE32(rdev)) { 3909 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET0); 3910 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET1); 3911 } else { 3912 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS); 3913 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(DCE3_HDMI1_STATUS); 3914 } 3915 } else { 3916 rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS); 3917 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE); 3918 rdev->irq.stat_regs.r600.disp_int_cont2 = 0; 3919 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS); 3920 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(HDMI1_STATUS); 3921 } 3922 rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS); 3923 rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS); 3924 3925 if (rdev->irq.stat_regs.r600.d1grph_int & DxGRPH_PFLIP_INT_OCCURRED) 3926 WREG32(D1GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR); 3927 if (rdev->irq.stat_regs.r600.d2grph_int & DxGRPH_PFLIP_INT_OCCURRED) 3928 WREG32(D2GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR); 3929 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) 3930 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK); 3931 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) 3932 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK); 3933 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) 3934 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK); 3935 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) 3936 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK); 3937 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) { 3938 if (ASIC_IS_DCE3(rdev)) { 3939 tmp = RREG32(DC_HPD1_INT_CONTROL); 3940 tmp |= DC_HPDx_INT_ACK; 3941 WREG32(DC_HPD1_INT_CONTROL, tmp); 3942 } else { 3943 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL); 3944 tmp |= DC_HPDx_INT_ACK; 3945 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); 3946 } 3947 } 3948 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) { 3949 if (ASIC_IS_DCE3(rdev)) { 3950 tmp = RREG32(DC_HPD2_INT_CONTROL); 3951 tmp |= DC_HPDx_INT_ACK; 3952 WREG32(DC_HPD2_INT_CONTROL, tmp); 3953 } else { 3954 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL); 3955 tmp |= DC_HPDx_INT_ACK; 3956 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); 3957 } 3958 } 3959 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) { 3960 if (ASIC_IS_DCE3(rdev)) { 3961 tmp = RREG32(DC_HPD3_INT_CONTROL); 3962 tmp |= DC_HPDx_INT_ACK; 3963 WREG32(DC_HPD3_INT_CONTROL, tmp); 3964 } else { 3965 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL); 3966 tmp |= DC_HPDx_INT_ACK; 3967 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); 3968 } 3969 } 3970 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) { 3971 tmp = RREG32(DC_HPD4_INT_CONTROL); 3972 tmp |= DC_HPDx_INT_ACK; 3973 WREG32(DC_HPD4_INT_CONTROL, tmp); 3974 } 3975 if (ASIC_IS_DCE32(rdev)) { 3976 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) { 3977 tmp = RREG32(DC_HPD5_INT_CONTROL); 3978 tmp |= DC_HPDx_INT_ACK; 3979 WREG32(DC_HPD5_INT_CONTROL, tmp); 3980 } 3981 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) { 3982 tmp = RREG32(DC_HPD6_INT_CONTROL); 3983 tmp |= DC_HPDx_INT_ACK; 3984 WREG32(DC_HPD6_INT_CONTROL, tmp); 3985 } 3986 if (rdev->irq.stat_regs.r600.hdmi0_status & AFMT_AZ_FORMAT_WTRIG) { 3987 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0); 3988 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; 3989 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp); 3990 } 3991 if (rdev->irq.stat_regs.r600.hdmi1_status & AFMT_AZ_FORMAT_WTRIG) { 3992 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1); 3993 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; 3994 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp); 3995 } 3996 } else { 3997 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) { 3998 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL); 3999 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK; 4000 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); 4001 } 4002 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) { 4003 if (ASIC_IS_DCE3(rdev)) { 4004 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL); 4005 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK; 4006 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp); 4007 } else { 4008 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL); 4009 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK; 4010 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp); 4011 } 4012 } 4013 } 4014 } 4015 4016 void r600_irq_disable(struct radeon_device *rdev) 4017 { 4018 r600_disable_interrupts(rdev); 4019 /* Wait and acknowledge irq */ 4020 mdelay(1); 4021 r600_irq_ack(rdev); 4022 r600_disable_interrupt_state(rdev); 4023 } 4024 4025 static u32 r600_get_ih_wptr(struct radeon_device *rdev) 4026 { 4027 u32 wptr, tmp; 4028 4029 if (rdev->wb.enabled) 4030 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]); 4031 else 4032 wptr = RREG32(IH_RB_WPTR); 4033 4034 if (wptr & RB_OVERFLOW) { 4035 wptr &= ~RB_OVERFLOW; 4036 /* When a ring buffer overflow happen start parsing interrupt 4037 * from the last not overwritten vector (wptr + 16). Hopefully 4038 * this should allow us to catchup. 4039 */ 4040 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n", 4041 wptr, rdev->ih.rptr, (wptr + 16) & rdev->ih.ptr_mask); 4042 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask; 4043 tmp = RREG32(IH_RB_CNTL); 4044 tmp |= IH_WPTR_OVERFLOW_CLEAR; 4045 WREG32(IH_RB_CNTL, tmp); 4046 } 4047 return (wptr & rdev->ih.ptr_mask); 4048 } 4049 4050 /* r600 IV Ring 4051 * Each IV ring entry is 128 bits: 4052 * [7:0] - interrupt source id 4053 * [31:8] - reserved 4054 * [59:32] - interrupt source data 4055 * [127:60] - reserved 4056 * 4057 * The basic interrupt vector entries 4058 * are decoded as follows: 4059 * src_id src_data description 4060 * 1 0 D1 Vblank 4061 * 1 1 D1 Vline 4062 * 5 0 D2 Vblank 4063 * 5 1 D2 Vline 4064 * 19 0 FP Hot plug detection A 4065 * 19 1 FP Hot plug detection B 4066 * 19 2 DAC A auto-detection 4067 * 19 3 DAC B auto-detection 4068 * 21 4 HDMI block A 4069 * 21 5 HDMI block B 4070 * 176 - CP_INT RB 4071 * 177 - CP_INT IB1 4072 * 178 - CP_INT IB2 4073 * 181 - EOP Interrupt 4074 * 233 - GUI Idle 4075 * 4076 * Note, these are based on r600 and may need to be 4077 * adjusted or added to on newer asics 4078 */ 4079 4080 int r600_irq_process(struct radeon_device *rdev) 4081 { 4082 u32 wptr; 4083 u32 rptr; 4084 u32 src_id, src_data; 4085 u32 ring_index; 4086 bool queue_hotplug = false; 4087 bool queue_hdmi = false; 4088 bool queue_thermal = false; 4089 4090 if (!rdev->ih.enabled || rdev->shutdown) 4091 return IRQ_NONE; 4092 4093 /* No MSIs, need a dummy read to flush PCI DMAs */ 4094 if (!rdev->msi_enabled) 4095 RREG32(IH_RB_WPTR); 4096 4097 wptr = r600_get_ih_wptr(rdev); 4098 4099 restart_ih: 4100 /* is somebody else already processing irqs? */ 4101 if (atomic_xchg(&rdev->ih.lock, 1)) 4102 return IRQ_NONE; 4103 4104 rptr = rdev->ih.rptr; 4105 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr); 4106 4107 /* Order reading of wptr vs. reading of IH ring data */ 4108 rmb(); 4109 4110 /* display interrupts */ 4111 r600_irq_ack(rdev); 4112 4113 while (rptr != wptr) { 4114 /* wptr/rptr are in bytes! */ 4115 ring_index = rptr / 4; 4116 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff; 4117 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff; 4118 4119 switch (src_id) { 4120 case 1: /* D1 vblank/vline */ 4121 switch (src_data) { 4122 case 0: /* D1 vblank */ 4123 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT)) 4124 DRM_DEBUG("IH: D1 vblank - IH event w/o asserted irq bit?\n"); 4125 4126 if (rdev->irq.crtc_vblank_int[0]) { 4127 drm_handle_vblank(rdev->ddev, 0); 4128 #ifdef __NetBSD__ 4129 spin_lock(&rdev->irq.vblank_lock); 4130 rdev->pm.vblank_sync = true; 4131 DRM_SPIN_WAKEUP_ONE(&rdev->irq.vblank_queue, &rdev->irq.vblank_lock); 4132 spin_unlock(&rdev->irq.vblank_lock); 4133 #else 4134 rdev->pm.vblank_sync = true; 4135 wake_up(&rdev->irq.vblank_queue); 4136 #endif 4137 } 4138 if (atomic_read(&rdev->irq.pflip[0])) 4139 radeon_crtc_handle_vblank(rdev, 0); 4140 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT; 4141 DRM_DEBUG("IH: D1 vblank\n"); 4142 4143 break; 4144 case 1: /* D1 vline */ 4145 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT)) 4146 DRM_DEBUG("IH: D1 vline - IH event w/o asserted irq bit?\n"); 4147 4148 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT; 4149 DRM_DEBUG("IH: D1 vline\n"); 4150 4151 break; 4152 default: 4153 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 4154 break; 4155 } 4156 break; 4157 case 5: /* D2 vblank/vline */ 4158 switch (src_data) { 4159 case 0: /* D2 vblank */ 4160 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT)) 4161 DRM_DEBUG("IH: D2 vblank - IH event w/o asserted irq bit?\n"); 4162 4163 if (rdev->irq.crtc_vblank_int[1]) { 4164 drm_handle_vblank(rdev->ddev, 1); 4165 #ifdef __NetBSD__ 4166 spin_lock(&rdev->irq.vblank_lock); 4167 rdev->pm.vblank_sync = true; 4168 DRM_SPIN_WAKEUP_ONE(&rdev->irq.vblank_queue, &rdev->irq.vblank_lock); 4169 spin_unlock(&rdev->irq.vblank_lock); 4170 #else 4171 rdev->pm.vblank_sync = true; 4172 wake_up(&rdev->irq.vblank_queue); 4173 #endif 4174 } 4175 if (atomic_read(&rdev->irq.pflip[1])) 4176 radeon_crtc_handle_vblank(rdev, 1); 4177 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT; 4178 DRM_DEBUG("IH: D2 vblank\n"); 4179 4180 break; 4181 case 1: /* D1 vline */ 4182 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT)) 4183 DRM_DEBUG("IH: D2 vline - IH event w/o asserted irq bit?\n"); 4184 4185 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT; 4186 DRM_DEBUG("IH: D2 vline\n"); 4187 4188 break; 4189 default: 4190 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 4191 break; 4192 } 4193 break; 4194 case 9: /* D1 pflip */ 4195 DRM_DEBUG("IH: D1 flip\n"); 4196 if (radeon_use_pflipirq > 0) 4197 radeon_crtc_handle_flip(rdev, 0); 4198 break; 4199 case 11: /* D2 pflip */ 4200 DRM_DEBUG("IH: D2 flip\n"); 4201 if (radeon_use_pflipirq > 0) 4202 radeon_crtc_handle_flip(rdev, 1); 4203 break; 4204 case 19: /* HPD/DAC hotplug */ 4205 switch (src_data) { 4206 case 0: 4207 if (!(rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT)) 4208 DRM_DEBUG("IH: HPD1 - IH event w/o asserted irq bit?\n"); 4209 4210 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT; 4211 queue_hotplug = true; 4212 DRM_DEBUG("IH: HPD1\n"); 4213 break; 4214 case 1: 4215 if (!(rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT)) 4216 DRM_DEBUG("IH: HPD2 - IH event w/o asserted irq bit?\n"); 4217 4218 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT; 4219 queue_hotplug = true; 4220 DRM_DEBUG("IH: HPD2\n"); 4221 break; 4222 case 4: 4223 if (!(rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT)) 4224 DRM_DEBUG("IH: HPD3 - IH event w/o asserted irq bit?\n"); 4225 4226 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT; 4227 queue_hotplug = true; 4228 DRM_DEBUG("IH: HPD3\n"); 4229 break; 4230 case 5: 4231 if (!(rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT)) 4232 DRM_DEBUG("IH: HPD4 - IH event w/o asserted irq bit?\n"); 4233 4234 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT; 4235 queue_hotplug = true; 4236 DRM_DEBUG("IH: HPD4\n"); 4237 break; 4238 case 10: 4239 if (!(rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT)) 4240 DRM_DEBUG("IH: HPD5 - IH event w/o asserted irq bit?\n"); 4241 4242 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT; 4243 queue_hotplug = true; 4244 DRM_DEBUG("IH: HPD5\n"); 4245 break; 4246 case 12: 4247 if (!(rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT)) 4248 DRM_DEBUG("IH: HPD6 - IH event w/o asserted irq bit?\n"); 4249 4250 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT; 4251 queue_hotplug = true; 4252 DRM_DEBUG("IH: HPD6\n"); 4253 4254 break; 4255 default: 4256 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 4257 break; 4258 } 4259 break; 4260 case 21: /* hdmi */ 4261 switch (src_data) { 4262 case 4: 4263 if (!(rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG)) 4264 DRM_DEBUG("IH: HDMI0 - IH event w/o asserted irq bit?\n"); 4265 4266 rdev->irq.stat_regs.r600.hdmi0_status &= ~HDMI0_AZ_FORMAT_WTRIG; 4267 queue_hdmi = true; 4268 DRM_DEBUG("IH: HDMI0\n"); 4269 4270 break; 4271 case 5: 4272 if (!(rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG)) 4273 DRM_DEBUG("IH: HDMI1 - IH event w/o asserted irq bit?\n"); 4274 4275 rdev->irq.stat_regs.r600.hdmi1_status &= ~HDMI0_AZ_FORMAT_WTRIG; 4276 queue_hdmi = true; 4277 DRM_DEBUG("IH: HDMI1\n"); 4278 4279 break; 4280 default: 4281 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data); 4282 break; 4283 } 4284 break; 4285 case 124: /* UVD */ 4286 DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data); 4287 radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX); 4288 break; 4289 case 176: /* CP_INT in ring buffer */ 4290 case 177: /* CP_INT in IB1 */ 4291 case 178: /* CP_INT in IB2 */ 4292 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data); 4293 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); 4294 break; 4295 case 181: /* CP EOP event */ 4296 DRM_DEBUG("IH: CP EOP\n"); 4297 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); 4298 break; 4299 case 224: /* DMA trap event */ 4300 DRM_DEBUG("IH: DMA trap\n"); 4301 radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX); 4302 break; 4303 case 230: /* thermal low to high */ 4304 DRM_DEBUG("IH: thermal low to high\n"); 4305 rdev->pm.dpm.thermal.high_to_low = false; 4306 queue_thermal = true; 4307 break; 4308 case 231: /* thermal high to low */ 4309 DRM_DEBUG("IH: thermal high to low\n"); 4310 rdev->pm.dpm.thermal.high_to_low = true; 4311 queue_thermal = true; 4312 break; 4313 case 233: /* GUI IDLE */ 4314 DRM_DEBUG("IH: GUI idle\n"); 4315 break; 4316 default: 4317 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 4318 break; 4319 } 4320 4321 /* wptr/rptr are in bytes! */ 4322 rptr += 16; 4323 rptr &= rdev->ih.ptr_mask; 4324 WREG32(IH_RB_RPTR, rptr); 4325 } 4326 if (queue_hotplug) 4327 schedule_delayed_work(&rdev->hotplug_work, 0); 4328 if (queue_hdmi) 4329 schedule_work(&rdev->audio_work); 4330 if (queue_thermal && rdev->pm.dpm_enabled) 4331 schedule_work(&rdev->pm.dpm.thermal.work); 4332 rdev->ih.rptr = rptr; 4333 atomic_set(&rdev->ih.lock, 0); 4334 4335 /* make sure wptr hasn't changed while processing */ 4336 wptr = r600_get_ih_wptr(rdev); 4337 if (wptr != rptr) 4338 goto restart_ih; 4339 4340 return IRQ_HANDLED; 4341 } 4342 4343 /* 4344 * Debugfs info 4345 */ 4346 #if defined(CONFIG_DEBUG_FS) 4347 4348 static int r600_debugfs_mc_info(struct seq_file *m, void *data) 4349 { 4350 struct drm_info_node *node = (struct drm_info_node *) m->private; 4351 struct drm_device *dev = node->minor->dev; 4352 struct radeon_device *rdev = dev->dev_private; 4353 4354 DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS); 4355 DREG32_SYS(m, rdev, VM_L2_STATUS); 4356 return 0; 4357 } 4358 4359 static struct drm_info_list r600_mc_info_list[] = { 4360 {"r600_mc_info", r600_debugfs_mc_info, 0, NULL}, 4361 }; 4362 #endif 4363 4364 int r600_debugfs_mc_info_init(struct radeon_device *rdev) 4365 { 4366 #if defined(CONFIG_DEBUG_FS) 4367 return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list)); 4368 #else 4369 return 0; 4370 #endif 4371 } 4372 4373 #ifdef __NetBSD__ 4374 # define __iomem volatile 4375 # define readl fake_readl 4376 #endif 4377 4378 /** 4379 * r600_mmio_hdp_flush - flush Host Data Path cache via MMIO 4380 * rdev: radeon device structure 4381 * 4382 * Some R6XX/R7XX don't seem to take into account HDP flushes performed 4383 * through the ring buffer. This leads to corruption in rendering, see 4384 * http://bugzilla.kernel.org/show_bug.cgi?id=15186 . To avoid this, we 4385 * directly perform the HDP flush by writing the register through MMIO. 4386 */ 4387 void r600_mmio_hdp_flush(struct radeon_device *rdev) 4388 { 4389 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read 4390 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL. 4391 * This seems to cause problems on some AGP cards. Just use the old 4392 * method for them. 4393 */ 4394 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) && 4395 rdev->vram_scratch.ptr && !(rdev->flags & RADEON_IS_AGP)) { 4396 void __iomem *ptr = rdev->vram_scratch.ptr; 4397 4398 WREG32(HDP_DEBUG1, 0); 4399 (void)readl(ptr); 4400 } else 4401 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); 4402 } 4403 4404 #ifdef __NetBSD__ 4405 # undef __iomem 4406 # undef readl 4407 #endif 4408 4409 void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes) 4410 { 4411 u32 link_width_cntl, mask; 4412 4413 if (rdev->flags & RADEON_IS_IGP) 4414 return; 4415 4416 if (!(rdev->flags & RADEON_IS_PCIE)) 4417 return; 4418 4419 /* x2 cards have a special sequence */ 4420 if (ASIC_IS_X2(rdev)) 4421 return; 4422 4423 radeon_gui_idle(rdev); 4424 4425 switch (lanes) { 4426 case 0: 4427 mask = RADEON_PCIE_LC_LINK_WIDTH_X0; 4428 break; 4429 case 1: 4430 mask = RADEON_PCIE_LC_LINK_WIDTH_X1; 4431 break; 4432 case 2: 4433 mask = RADEON_PCIE_LC_LINK_WIDTH_X2; 4434 break; 4435 case 4: 4436 mask = RADEON_PCIE_LC_LINK_WIDTH_X4; 4437 break; 4438 case 8: 4439 mask = RADEON_PCIE_LC_LINK_WIDTH_X8; 4440 break; 4441 case 12: 4442 /* not actually supported */ 4443 mask = RADEON_PCIE_LC_LINK_WIDTH_X12; 4444 break; 4445 case 16: 4446 mask = RADEON_PCIE_LC_LINK_WIDTH_X16; 4447 break; 4448 default: 4449 DRM_ERROR("invalid pcie lane request: %d\n", lanes); 4450 return; 4451 } 4452 4453 link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 4454 link_width_cntl &= ~RADEON_PCIE_LC_LINK_WIDTH_MASK; 4455 link_width_cntl |= mask << RADEON_PCIE_LC_LINK_WIDTH_SHIFT; 4456 link_width_cntl |= (RADEON_PCIE_LC_RECONFIG_NOW | 4457 R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE); 4458 4459 WREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4460 } 4461 4462 int r600_get_pcie_lanes(struct radeon_device *rdev) 4463 { 4464 u32 link_width_cntl; 4465 4466 if (rdev->flags & RADEON_IS_IGP) 4467 return 0; 4468 4469 if (!(rdev->flags & RADEON_IS_PCIE)) 4470 return 0; 4471 4472 /* x2 cards have a special sequence */ 4473 if (ASIC_IS_X2(rdev)) 4474 return 0; 4475 4476 radeon_gui_idle(rdev); 4477 4478 link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 4479 4480 switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) { 4481 case RADEON_PCIE_LC_LINK_WIDTH_X1: 4482 return 1; 4483 case RADEON_PCIE_LC_LINK_WIDTH_X2: 4484 return 2; 4485 case RADEON_PCIE_LC_LINK_WIDTH_X4: 4486 return 4; 4487 case RADEON_PCIE_LC_LINK_WIDTH_X8: 4488 return 8; 4489 case RADEON_PCIE_LC_LINK_WIDTH_X12: 4490 /* not actually supported */ 4491 return 12; 4492 case RADEON_PCIE_LC_LINK_WIDTH_X0: 4493 case RADEON_PCIE_LC_LINK_WIDTH_X16: 4494 default: 4495 return 16; 4496 } 4497 } 4498 4499 static void r600_pcie_gen2_enable(struct radeon_device *rdev) 4500 { 4501 #ifndef __NetBSD__ /* XXX radeon pcie */ 4502 u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp; 4503 u16 link_cntl2; 4504 4505 if (radeon_pcie_gen2 == 0) 4506 return; 4507 4508 if (rdev->flags & RADEON_IS_IGP) 4509 return; 4510 4511 if (!(rdev->flags & RADEON_IS_PCIE)) 4512 return; 4513 4514 /* x2 cards have a special sequence */ 4515 if (ASIC_IS_X2(rdev)) 4516 return; 4517 4518 /* only RV6xx+ chips are supported */ 4519 if (rdev->family <= CHIP_R600) 4520 return; 4521 4522 if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) && 4523 (rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT)) 4524 return; 4525 4526 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 4527 if (speed_cntl & LC_CURRENT_DATA_RATE) { 4528 DRM_INFO("PCIE gen 2 link speeds already enabled\n"); 4529 return; 4530 } 4531 4532 DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n"); 4533 4534 /* 55 nm r6xx asics */ 4535 if ((rdev->family == CHIP_RV670) || 4536 (rdev->family == CHIP_RV620) || 4537 (rdev->family == CHIP_RV635)) { 4538 /* advertise upconfig capability */ 4539 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); 4540 link_width_cntl &= ~LC_UPCONFIGURE_DIS; 4541 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4542 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); 4543 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) { 4544 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT; 4545 link_width_cntl &= ~(LC_LINK_WIDTH_MASK | 4546 LC_RECONFIG_ARC_MISSING_ESCAPE); 4547 link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN; 4548 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4549 } else { 4550 link_width_cntl |= LC_UPCONFIGURE_DIS; 4551 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4552 } 4553 } 4554 4555 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 4556 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) && 4557 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) { 4558 4559 /* 55 nm r6xx asics */ 4560 if ((rdev->family == CHIP_RV670) || 4561 (rdev->family == CHIP_RV620) || 4562 (rdev->family == CHIP_RV635)) { 4563 WREG32(MM_CFGREGS_CNTL, 0x8); 4564 link_cntl2 = RREG32(0x4088); 4565 WREG32(MM_CFGREGS_CNTL, 0); 4566 /* not supported yet */ 4567 if (link_cntl2 & SELECTABLE_DEEMPHASIS) 4568 return; 4569 } 4570 4571 speed_cntl &= ~LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK; 4572 speed_cntl |= (0x3 << LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT); 4573 speed_cntl &= ~LC_VOLTAGE_TIMER_SEL_MASK; 4574 speed_cntl &= ~LC_FORCE_DIS_HW_SPEED_CHANGE; 4575 speed_cntl |= LC_FORCE_EN_HW_SPEED_CHANGE; 4576 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); 4577 4578 tmp = RREG32(0x541c); 4579 WREG32(0x541c, tmp | 0x8); 4580 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN); 4581 link_cntl2 = RREG16(0x4088); 4582 link_cntl2 &= ~TARGET_LINK_SPEED_MASK; 4583 link_cntl2 |= 0x2; 4584 WREG16(0x4088, link_cntl2); 4585 WREG32(MM_CFGREGS_CNTL, 0); 4586 4587 if ((rdev->family == CHIP_RV670) || 4588 (rdev->family == CHIP_RV620) || 4589 (rdev->family == CHIP_RV635)) { 4590 training_cntl = RREG32_PCIE_PORT(PCIE_LC_TRAINING_CNTL); 4591 training_cntl &= ~LC_POINT_7_PLUS_EN; 4592 WREG32_PCIE_PORT(PCIE_LC_TRAINING_CNTL, training_cntl); 4593 } else { 4594 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 4595 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN; 4596 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); 4597 } 4598 4599 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 4600 speed_cntl |= LC_GEN2_EN_STRAP; 4601 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); 4602 4603 } else { 4604 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); 4605 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */ 4606 if (1) 4607 link_width_cntl |= LC_UPCONFIGURE_DIS; 4608 else 4609 link_width_cntl &= ~LC_UPCONFIGURE_DIS; 4610 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4611 } 4612 #endif 4613 } 4614 4615 /** 4616 * r600_get_gpu_clock_counter - return GPU clock counter snapshot 4617 * 4618 * @rdev: radeon_device pointer 4619 * 4620 * Fetches a GPU clock counter snapshot (R6xx-cayman). 4621 * Returns the 64 bit clock counter snapshot. 4622 */ 4623 uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev) 4624 { 4625 uint64_t clock; 4626 4627 mutex_lock(&rdev->gpu_clock_mutex); 4628 WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1); 4629 clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) | 4630 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 4631 mutex_unlock(&rdev->gpu_clock_mutex); 4632 return clock; 4633 } 4634
Indexes created Sat Oct 25 16:10:12 GMT 2025