radeon_r600.c revision 1.4
1 /* $NetBSD: radeon_r600.c,v 1.4 2020/02/14 04:35:20 riastradh Exp $ */ 2 3 /* 4 * Copyright 2008 Advanced Micro Devices, Inc. 5 * Copyright 2008 Red Hat Inc. 6 * Copyright 2009 Jerome Glisse. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: Dave Airlie 27 * Alex Deucher 28 * Jerome Glisse 29 */ 30 #include <sys/cdefs.h> 31 __KERNEL_RCSID(0, "$NetBSD: radeon_r600.c,v 1.4 2020/02/14 04:35:20 riastradh Exp $"); 32 33 #include <linux/bitops.h> 34 #include <linux/slab.h> 35 #include <linux/seq_file.h> 36 #include <linux/firmware.h> 37 #include <linux/module.h> 38 #include <drm/drmP.h> 39 #include <drm/radeon_drm.h> 40 #include "radeon.h" 41 #include "radeon_asic.h" 42 #include "radeon_audio.h" 43 #include "radeon_mode.h" 44 #include "r600d.h" 45 #include "atom.h" 46 #include "avivod.h" 47 #include "radeon_ucode.h" 48 49 #include <linux/nbsd-namespace.h> 50 51 /* Firmware Names */ 52 MODULE_FIRMWARE("radeon/R600_pfp.bin"); 53 MODULE_FIRMWARE("radeon/R600_me.bin"); 54 MODULE_FIRMWARE("radeon/RV610_pfp.bin"); 55 MODULE_FIRMWARE("radeon/RV610_me.bin"); 56 MODULE_FIRMWARE("radeon/RV630_pfp.bin"); 57 MODULE_FIRMWARE("radeon/RV630_me.bin"); 58 MODULE_FIRMWARE("radeon/RV620_pfp.bin"); 59 MODULE_FIRMWARE("radeon/RV620_me.bin"); 60 MODULE_FIRMWARE("radeon/RV635_pfp.bin"); 61 MODULE_FIRMWARE("radeon/RV635_me.bin"); 62 MODULE_FIRMWARE("radeon/RV670_pfp.bin"); 63 MODULE_FIRMWARE("radeon/RV670_me.bin"); 64 MODULE_FIRMWARE("radeon/RS780_pfp.bin"); 65 MODULE_FIRMWARE("radeon/RS780_me.bin"); 66 MODULE_FIRMWARE("radeon/RV770_pfp.bin"); 67 MODULE_FIRMWARE("radeon/RV770_me.bin"); 68 MODULE_FIRMWARE("radeon/RV770_smc.bin"); 69 MODULE_FIRMWARE("radeon/RV730_pfp.bin"); 70 MODULE_FIRMWARE("radeon/RV730_me.bin"); 71 MODULE_FIRMWARE("radeon/RV730_smc.bin"); 72 MODULE_FIRMWARE("radeon/RV740_smc.bin"); 73 MODULE_FIRMWARE("radeon/RV710_pfp.bin"); 74 MODULE_FIRMWARE("radeon/RV710_me.bin"); 75 MODULE_FIRMWARE("radeon/RV710_smc.bin"); 76 MODULE_FIRMWARE("radeon/R600_rlc.bin"); 77 MODULE_FIRMWARE("radeon/R700_rlc.bin"); 78 MODULE_FIRMWARE("radeon/CEDAR_pfp.bin"); 79 MODULE_FIRMWARE("radeon/CEDAR_me.bin"); 80 MODULE_FIRMWARE("radeon/CEDAR_rlc.bin"); 81 MODULE_FIRMWARE("radeon/CEDAR_smc.bin"); 82 MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin"); 83 MODULE_FIRMWARE("radeon/REDWOOD_me.bin"); 84 MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin"); 85 MODULE_FIRMWARE("radeon/REDWOOD_smc.bin"); 86 MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin"); 87 MODULE_FIRMWARE("radeon/JUNIPER_me.bin"); 88 MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin"); 89 MODULE_FIRMWARE("radeon/JUNIPER_smc.bin"); 90 MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin"); 91 MODULE_FIRMWARE("radeon/CYPRESS_me.bin"); 92 MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin"); 93 MODULE_FIRMWARE("radeon/CYPRESS_smc.bin"); 94 MODULE_FIRMWARE("radeon/PALM_pfp.bin"); 95 MODULE_FIRMWARE("radeon/PALM_me.bin"); 96 MODULE_FIRMWARE("radeon/SUMO_rlc.bin"); 97 MODULE_FIRMWARE("radeon/SUMO_pfp.bin"); 98 MODULE_FIRMWARE("radeon/SUMO_me.bin"); 99 MODULE_FIRMWARE("radeon/SUMO2_pfp.bin"); 100 MODULE_FIRMWARE("radeon/SUMO2_me.bin"); 101 102 static const u32 crtc_offsets[2] = 103 { 104 0, 105 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL 106 }; 107 108 int r600_debugfs_mc_info_init(struct radeon_device *rdev); 109 110 /* r600,rv610,rv630,rv620,rv635,rv670 */ 111 int r600_mc_wait_for_idle(struct radeon_device *rdev); 112 static void r600_gpu_init(struct radeon_device *rdev); 113 void r600_fini(struct radeon_device *rdev); 114 void r600_irq_disable(struct radeon_device *rdev); 115 static void r600_pcie_gen2_enable(struct radeon_device *rdev); 116 extern int evergreen_rlc_resume(struct radeon_device *rdev); 117 extern void rv770_set_clk_bypass_mode(struct radeon_device *rdev); 118 119 /* 120 * Indirect registers accessor 121 */ 122 u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg) 123 { 124 unsigned long flags; 125 u32 r; 126 127 spin_lock_irqsave(&rdev->rcu_idx_lock, flags); 128 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff)); 129 r = RREG32(R600_RCU_DATA); 130 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags); 131 return r; 132 } 133 134 void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v) 135 { 136 unsigned long flags; 137 138 spin_lock_irqsave(&rdev->rcu_idx_lock, flags); 139 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff)); 140 WREG32(R600_RCU_DATA, (v)); 141 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags); 142 } 143 144 u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg) 145 { 146 unsigned long flags; 147 u32 r; 148 149 spin_lock_irqsave(&rdev->uvd_idx_lock, flags); 150 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff)); 151 r = RREG32(R600_UVD_CTX_DATA); 152 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags); 153 return r; 154 } 155 156 void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v) 157 { 158 unsigned long flags; 159 160 spin_lock_irqsave(&rdev->uvd_idx_lock, flags); 161 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff)); 162 WREG32(R600_UVD_CTX_DATA, (v)); 163 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags); 164 } 165 166 /** 167 * r600_get_allowed_info_register - fetch the register for the info ioctl 168 * 169 * @rdev: radeon_device pointer 170 * @reg: register offset in bytes 171 * @val: register value 172 * 173 * Returns 0 for success or -EINVAL for an invalid register 174 * 175 */ 176 int r600_get_allowed_info_register(struct radeon_device *rdev, 177 u32 reg, u32 *val) 178 { 179 switch (reg) { 180 case GRBM_STATUS: 181 case GRBM_STATUS2: 182 case R_000E50_SRBM_STATUS: 183 case DMA_STATUS_REG: 184 case UVD_STATUS: 185 *val = RREG32(reg); 186 return 0; 187 default: 188 return -EINVAL; 189 } 190 } 191 192 /** 193 * r600_get_xclk - get the xclk 194 * 195 * @rdev: radeon_device pointer 196 * 197 * Returns the reference clock used by the gfx engine 198 * (r6xx, IGPs, APUs). 199 */ 200 u32 r600_get_xclk(struct radeon_device *rdev) 201 { 202 return rdev->clock.spll.reference_freq; 203 } 204 205 int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) 206 { 207 unsigned fb_div = 0, ref_div, vclk_div = 0, dclk_div = 0; 208 int r; 209 210 /* bypass vclk and dclk with bclk */ 211 WREG32_P(CG_UPLL_FUNC_CNTL_2, 212 VCLK_SRC_SEL(1) | DCLK_SRC_SEL(1), 213 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK)); 214 215 /* assert BYPASS_EN, deassert UPLL_RESET, UPLL_SLEEP and UPLL_CTLREQ */ 216 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~( 217 UPLL_RESET_MASK | UPLL_SLEEP_MASK | UPLL_CTLREQ_MASK)); 218 219 if (rdev->family >= CHIP_RS780) 220 WREG32_P(GFX_MACRO_BYPASS_CNTL, UPLL_BYPASS_CNTL, 221 ~UPLL_BYPASS_CNTL); 222 223 if (!vclk || !dclk) { 224 /* keep the Bypass mode, put PLL to sleep */ 225 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK); 226 return 0; 227 } 228 229 if (rdev->clock.spll.reference_freq == 10000) 230 ref_div = 34; 231 else 232 ref_div = 4; 233 234 r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 50000, 160000, 235 ref_div + 1, 0xFFF, 2, 30, ~0, 236 &fb_div, &vclk_div, &dclk_div); 237 if (r) 238 return r; 239 240 if (rdev->family >= CHIP_RV670 && rdev->family < CHIP_RS780) 241 fb_div >>= 1; 242 else 243 fb_div |= 1; 244 245 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL); 246 if (r) 247 return r; 248 249 /* assert PLL_RESET */ 250 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK); 251 252 /* For RS780 we have to choose ref clk */ 253 if (rdev->family >= CHIP_RS780) 254 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_REFCLK_SRC_SEL_MASK, 255 ~UPLL_REFCLK_SRC_SEL_MASK); 256 257 /* set the required fb, ref and post divder values */ 258 WREG32_P(CG_UPLL_FUNC_CNTL, 259 UPLL_FB_DIV(fb_div) | 260 UPLL_REF_DIV(ref_div), 261 ~(UPLL_FB_DIV_MASK | UPLL_REF_DIV_MASK)); 262 WREG32_P(CG_UPLL_FUNC_CNTL_2, 263 UPLL_SW_HILEN(vclk_div >> 1) | 264 UPLL_SW_LOLEN((vclk_div >> 1) + (vclk_div & 1)) | 265 UPLL_SW_HILEN2(dclk_div >> 1) | 266 UPLL_SW_LOLEN2((dclk_div >> 1) + (dclk_div & 1)) | 267 UPLL_DIVEN_MASK | UPLL_DIVEN2_MASK, 268 ~UPLL_SW_MASK); 269 270 /* give the PLL some time to settle */ 271 mdelay(15); 272 273 /* deassert PLL_RESET */ 274 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); 275 276 mdelay(15); 277 278 /* deassert BYPASS EN */ 279 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK); 280 281 if (rdev->family >= CHIP_RS780) 282 WREG32_P(GFX_MACRO_BYPASS_CNTL, 0, ~UPLL_BYPASS_CNTL); 283 284 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL); 285 if (r) 286 return r; 287 288 /* switch VCLK and DCLK selection */ 289 WREG32_P(CG_UPLL_FUNC_CNTL_2, 290 VCLK_SRC_SEL(2) | DCLK_SRC_SEL(2), 291 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK)); 292 293 mdelay(100); 294 295 return 0; 296 } 297 298 void dce3_program_fmt(struct drm_encoder *encoder) 299 { 300 struct drm_device *dev = encoder->dev; 301 struct radeon_device *rdev = dev->dev_private; 302 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 303 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 304 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 305 int bpc = 0; 306 u32 tmp = 0; 307 enum radeon_connector_dither dither = RADEON_FMT_DITHER_DISABLE; 308 309 if (connector) { 310 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 311 bpc = radeon_get_monitor_bpc(connector); 312 dither = radeon_connector->dither; 313 } 314 315 /* LVDS FMT is set up by atom */ 316 if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) 317 return; 318 319 /* not needed for analog */ 320 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) || 321 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2)) 322 return; 323 324 if (bpc == 0) 325 return; 326 327 switch (bpc) { 328 case 6: 329 if (dither == RADEON_FMT_DITHER_ENABLE) 330 /* XXX sort out optimal dither settings */ 331 tmp |= FMT_SPATIAL_DITHER_EN; 332 else 333 tmp |= FMT_TRUNCATE_EN; 334 break; 335 case 8: 336 if (dither == RADEON_FMT_DITHER_ENABLE) 337 /* XXX sort out optimal dither settings */ 338 tmp |= (FMT_SPATIAL_DITHER_EN | FMT_SPATIAL_DITHER_DEPTH); 339 else 340 tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH); 341 break; 342 case 10: 343 default: 344 /* not needed */ 345 break; 346 } 347 348 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp); 349 } 350 351 /* get temperature in millidegrees */ 352 int rv6xx_get_temp(struct radeon_device *rdev) 353 { 354 u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >> 355 ASIC_T_SHIFT; 356 int actual_temp = temp & 0xff; 357 358 if (temp & 0x100) 359 actual_temp -= 256; 360 361 return actual_temp * 1000; 362 } 363 364 void r600_pm_get_dynpm_state(struct radeon_device *rdev) 365 { 366 int i; 367 368 rdev->pm.dynpm_can_upclock = true; 369 rdev->pm.dynpm_can_downclock = true; 370 371 /* power state array is low to high, default is first */ 372 if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) { 373 int min_power_state_index = 0; 374 375 if (rdev->pm.num_power_states > 2) 376 min_power_state_index = 1; 377 378 switch (rdev->pm.dynpm_planned_action) { 379 case DYNPM_ACTION_MINIMUM: 380 rdev->pm.requested_power_state_index = min_power_state_index; 381 rdev->pm.requested_clock_mode_index = 0; 382 rdev->pm.dynpm_can_downclock = false; 383 break; 384 case DYNPM_ACTION_DOWNCLOCK: 385 if (rdev->pm.current_power_state_index == min_power_state_index) { 386 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 387 rdev->pm.dynpm_can_downclock = false; 388 } else { 389 if (rdev->pm.active_crtc_count > 1) { 390 for (i = 0; i < rdev->pm.num_power_states; i++) { 391 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 392 continue; 393 else if (i >= rdev->pm.current_power_state_index) { 394 rdev->pm.requested_power_state_index = 395 rdev->pm.current_power_state_index; 396 break; 397 } else { 398 rdev->pm.requested_power_state_index = i; 399 break; 400 } 401 } 402 } else { 403 if (rdev->pm.current_power_state_index == 0) 404 rdev->pm.requested_power_state_index = 405 rdev->pm.num_power_states - 1; 406 else 407 rdev->pm.requested_power_state_index = 408 rdev->pm.current_power_state_index - 1; 409 } 410 } 411 rdev->pm.requested_clock_mode_index = 0; 412 /* don't use the power state if crtcs are active and no display flag is set */ 413 if ((rdev->pm.active_crtc_count > 0) && 414 (rdev->pm.power_state[rdev->pm.requested_power_state_index]. 415 clock_info[rdev->pm.requested_clock_mode_index].flags & 416 RADEON_PM_MODE_NO_DISPLAY)) { 417 rdev->pm.requested_power_state_index++; 418 } 419 break; 420 case DYNPM_ACTION_UPCLOCK: 421 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) { 422 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 423 rdev->pm.dynpm_can_upclock = false; 424 } else { 425 if (rdev->pm.active_crtc_count > 1) { 426 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) { 427 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 428 continue; 429 else if (i <= rdev->pm.current_power_state_index) { 430 rdev->pm.requested_power_state_index = 431 rdev->pm.current_power_state_index; 432 break; 433 } else { 434 rdev->pm.requested_power_state_index = i; 435 break; 436 } 437 } 438 } else 439 rdev->pm.requested_power_state_index = 440 rdev->pm.current_power_state_index + 1; 441 } 442 rdev->pm.requested_clock_mode_index = 0; 443 break; 444 case DYNPM_ACTION_DEFAULT: 445 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; 446 rdev->pm.requested_clock_mode_index = 0; 447 rdev->pm.dynpm_can_upclock = false; 448 break; 449 case DYNPM_ACTION_NONE: 450 default: 451 DRM_ERROR("Requested mode for not defined action\n"); 452 return; 453 } 454 } else { 455 /* XXX select a power state based on AC/DC, single/dualhead, etc. */ 456 /* for now just select the first power state and switch between clock modes */ 457 /* power state array is low to high, default is first (0) */ 458 if (rdev->pm.active_crtc_count > 1) { 459 rdev->pm.requested_power_state_index = -1; 460 /* start at 1 as we don't want the default mode */ 461 for (i = 1; i < rdev->pm.num_power_states; i++) { 462 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 463 continue; 464 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) || 465 (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) { 466 rdev->pm.requested_power_state_index = i; 467 break; 468 } 469 } 470 /* if nothing selected, grab the default state. */ 471 if (rdev->pm.requested_power_state_index == -1) 472 rdev->pm.requested_power_state_index = 0; 473 } else 474 rdev->pm.requested_power_state_index = 1; 475 476 switch (rdev->pm.dynpm_planned_action) { 477 case DYNPM_ACTION_MINIMUM: 478 rdev->pm.requested_clock_mode_index = 0; 479 rdev->pm.dynpm_can_downclock = false; 480 break; 481 case DYNPM_ACTION_DOWNCLOCK: 482 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) { 483 if (rdev->pm.current_clock_mode_index == 0) { 484 rdev->pm.requested_clock_mode_index = 0; 485 rdev->pm.dynpm_can_downclock = false; 486 } else 487 rdev->pm.requested_clock_mode_index = 488 rdev->pm.current_clock_mode_index - 1; 489 } else { 490 rdev->pm.requested_clock_mode_index = 0; 491 rdev->pm.dynpm_can_downclock = false; 492 } 493 /* don't use the power state if crtcs are active and no display flag is set */ 494 if ((rdev->pm.active_crtc_count > 0) && 495 (rdev->pm.power_state[rdev->pm.requested_power_state_index]. 496 clock_info[rdev->pm.requested_clock_mode_index].flags & 497 RADEON_PM_MODE_NO_DISPLAY)) { 498 rdev->pm.requested_clock_mode_index++; 499 } 500 break; 501 case DYNPM_ACTION_UPCLOCK: 502 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) { 503 if (rdev->pm.current_clock_mode_index == 504 (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) { 505 rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index; 506 rdev->pm.dynpm_can_upclock = false; 507 } else 508 rdev->pm.requested_clock_mode_index = 509 rdev->pm.current_clock_mode_index + 1; 510 } else { 511 rdev->pm.requested_clock_mode_index = 512 rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1; 513 rdev->pm.dynpm_can_upclock = false; 514 } 515 break; 516 case DYNPM_ACTION_DEFAULT: 517 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; 518 rdev->pm.requested_clock_mode_index = 0; 519 rdev->pm.dynpm_can_upclock = false; 520 break; 521 case DYNPM_ACTION_NONE: 522 default: 523 DRM_ERROR("Requested mode for not defined action\n"); 524 return; 525 } 526 } 527 528 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n", 529 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 530 clock_info[rdev->pm.requested_clock_mode_index].sclk, 531 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 532 clock_info[rdev->pm.requested_clock_mode_index].mclk, 533 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 534 pcie_lanes); 535 } 536 537 void rs780_pm_init_profile(struct radeon_device *rdev) 538 { 539 if (rdev->pm.num_power_states == 2) { 540 /* default */ 541 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 542 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 543 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 544 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 545 /* low sh */ 546 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0; 547 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0; 548 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 549 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 550 /* mid sh */ 551 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0; 552 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0; 553 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 554 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 555 /* high sh */ 556 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0; 557 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1; 558 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 559 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 560 /* low mh */ 561 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0; 562 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0; 563 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 564 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 565 /* mid mh */ 566 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0; 567 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0; 568 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 569 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 570 /* high mh */ 571 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0; 572 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1; 573 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 574 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 575 } else if (rdev->pm.num_power_states == 3) { 576 /* default */ 577 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 578 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 579 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 580 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 581 /* low sh */ 582 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1; 583 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1; 584 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 585 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 586 /* mid sh */ 587 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1; 588 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; 589 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 590 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 591 /* high sh */ 592 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1; 593 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2; 594 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 595 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 596 /* low mh */ 597 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1; 598 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1; 599 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 600 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 601 /* mid mh */ 602 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1; 603 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1; 604 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 605 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 606 /* high mh */ 607 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1; 608 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2; 609 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 610 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 611 } else { 612 /* default */ 613 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 614 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 615 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 616 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 617 /* low sh */ 618 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2; 619 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2; 620 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 621 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 622 /* mid sh */ 623 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2; 624 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2; 625 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 626 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 627 /* high sh */ 628 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2; 629 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3; 630 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 631 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 632 /* low mh */ 633 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2; 634 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0; 635 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 636 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 637 /* mid mh */ 638 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2; 639 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0; 640 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 641 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 642 /* high mh */ 643 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2; 644 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3; 645 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 646 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 647 } 648 } 649 650 void r600_pm_init_profile(struct radeon_device *rdev) 651 { 652 int idx; 653 654 if (rdev->family == CHIP_R600) { 655 /* XXX */ 656 /* default */ 657 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 658 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 659 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 660 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 661 /* low sh */ 662 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 663 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 664 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 665 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 666 /* mid sh */ 667 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 668 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 669 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 670 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 671 /* high sh */ 672 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 673 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 674 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 675 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 676 /* low mh */ 677 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 678 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 679 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 680 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 681 /* mid mh */ 682 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 683 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 684 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 685 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 686 /* high mh */ 687 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 688 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 689 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 690 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 691 } else { 692 if (rdev->pm.num_power_states < 4) { 693 /* default */ 694 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 695 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 696 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 697 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2; 698 /* low sh */ 699 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1; 700 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1; 701 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 702 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 703 /* mid sh */ 704 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1; 705 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; 706 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 707 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1; 708 /* high sh */ 709 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1; 710 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1; 711 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 712 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2; 713 /* low mh */ 714 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2; 715 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2; 716 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 717 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 718 /* low mh */ 719 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2; 720 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2; 721 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 722 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1; 723 /* high mh */ 724 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2; 725 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2; 726 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 727 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2; 728 } else { 729 /* default */ 730 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 731 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 732 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 733 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2; 734 /* low sh */ 735 if (rdev->flags & RADEON_IS_MOBILITY) 736 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0); 737 else 738 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); 739 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx; 740 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx; 741 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 742 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 743 /* mid sh */ 744 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx; 745 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx; 746 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 747 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1; 748 /* high sh */ 749 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); 750 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx; 751 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx; 752 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 753 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2; 754 /* low mh */ 755 if (rdev->flags & RADEON_IS_MOBILITY) 756 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1); 757 else 758 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1); 759 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx; 760 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx; 761 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 762 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 763 /* mid mh */ 764 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx; 765 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx; 766 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 767 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1; 768 /* high mh */ 769 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1); 770 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx; 771 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx; 772 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 773 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2; 774 } 775 } 776 } 777 778 void r600_pm_misc(struct radeon_device *rdev) 779 { 780 int req_ps_idx = rdev->pm.requested_power_state_index; 781 int req_cm_idx = rdev->pm.requested_clock_mode_index; 782 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx]; 783 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage; 784 785 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) { 786 /* 0xff01 is a flag rather then an actual voltage */ 787 if (voltage->voltage == 0xff01) 788 return; 789 if (voltage->voltage != rdev->pm.current_vddc) { 790 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC); 791 rdev->pm.current_vddc = voltage->voltage; 792 DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage->voltage); 793 } 794 } 795 } 796 797 bool r600_gui_idle(struct radeon_device *rdev) 798 { 799 if (RREG32(GRBM_STATUS) & GUI_ACTIVE) 800 return false; 801 else 802 return true; 803 } 804 805 /* hpd for digital panel detect/disconnect */ 806 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) 807 { 808 bool connected = false; 809 810 if (ASIC_IS_DCE3(rdev)) { 811 switch (hpd) { 812 case RADEON_HPD_1: 813 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE) 814 connected = true; 815 break; 816 case RADEON_HPD_2: 817 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE) 818 connected = true; 819 break; 820 case RADEON_HPD_3: 821 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE) 822 connected = true; 823 break; 824 case RADEON_HPD_4: 825 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE) 826 connected = true; 827 break; 828 /* DCE 3.2 */ 829 case RADEON_HPD_5: 830 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE) 831 connected = true; 832 break; 833 case RADEON_HPD_6: 834 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE) 835 connected = true; 836 break; 837 default: 838 break; 839 } 840 } else { 841 switch (hpd) { 842 case RADEON_HPD_1: 843 if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) 844 connected = true; 845 break; 846 case RADEON_HPD_2: 847 if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) 848 connected = true; 849 break; 850 case RADEON_HPD_3: 851 if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) 852 connected = true; 853 break; 854 default: 855 break; 856 } 857 } 858 return connected; 859 } 860 861 void r600_hpd_set_polarity(struct radeon_device *rdev, 862 enum radeon_hpd_id hpd) 863 { 864 u32 tmp; 865 bool connected = r600_hpd_sense(rdev, hpd); 866 867 if (ASIC_IS_DCE3(rdev)) { 868 switch (hpd) { 869 case RADEON_HPD_1: 870 tmp = RREG32(DC_HPD1_INT_CONTROL); 871 if (connected) 872 tmp &= ~DC_HPDx_INT_POLARITY; 873 else 874 tmp |= DC_HPDx_INT_POLARITY; 875 WREG32(DC_HPD1_INT_CONTROL, tmp); 876 break; 877 case RADEON_HPD_2: 878 tmp = RREG32(DC_HPD2_INT_CONTROL); 879 if (connected) 880 tmp &= ~DC_HPDx_INT_POLARITY; 881 else 882 tmp |= DC_HPDx_INT_POLARITY; 883 WREG32(DC_HPD2_INT_CONTROL, tmp); 884 break; 885 case RADEON_HPD_3: 886 tmp = RREG32(DC_HPD3_INT_CONTROL); 887 if (connected) 888 tmp &= ~DC_HPDx_INT_POLARITY; 889 else 890 tmp |= DC_HPDx_INT_POLARITY; 891 WREG32(DC_HPD3_INT_CONTROL, tmp); 892 break; 893 case RADEON_HPD_4: 894 tmp = RREG32(DC_HPD4_INT_CONTROL); 895 if (connected) 896 tmp &= ~DC_HPDx_INT_POLARITY; 897 else 898 tmp |= DC_HPDx_INT_POLARITY; 899 WREG32(DC_HPD4_INT_CONTROL, tmp); 900 break; 901 case RADEON_HPD_5: 902 tmp = RREG32(DC_HPD5_INT_CONTROL); 903 if (connected) 904 tmp &= ~DC_HPDx_INT_POLARITY; 905 else 906 tmp |= DC_HPDx_INT_POLARITY; 907 WREG32(DC_HPD5_INT_CONTROL, tmp); 908 break; 909 /* DCE 3.2 */ 910 case RADEON_HPD_6: 911 tmp = RREG32(DC_HPD6_INT_CONTROL); 912 if (connected) 913 tmp &= ~DC_HPDx_INT_POLARITY; 914 else 915 tmp |= DC_HPDx_INT_POLARITY; 916 WREG32(DC_HPD6_INT_CONTROL, tmp); 917 break; 918 default: 919 break; 920 } 921 } else { 922 switch (hpd) { 923 case RADEON_HPD_1: 924 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL); 925 if (connected) 926 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; 927 else 928 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; 929 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); 930 break; 931 case RADEON_HPD_2: 932 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL); 933 if (connected) 934 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; 935 else 936 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; 937 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); 938 break; 939 case RADEON_HPD_3: 940 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL); 941 if (connected) 942 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; 943 else 944 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; 945 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); 946 break; 947 default: 948 break; 949 } 950 } 951 } 952 953 void r600_hpd_init(struct radeon_device *rdev) 954 { 955 struct drm_device *dev = rdev->ddev; 956 struct drm_connector *connector; 957 unsigned enable = 0; 958 959 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 960 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 961 962 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || 963 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { 964 /* don't try to enable hpd on eDP or LVDS avoid breaking the 965 * aux dp channel on imac and help (but not completely fix) 966 * https://bugzilla.redhat.com/show_bug.cgi?id=726143 967 */ 968 continue; 969 } 970 if (ASIC_IS_DCE3(rdev)) { 971 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa); 972 if (ASIC_IS_DCE32(rdev)) 973 tmp |= DC_HPDx_EN; 974 975 switch (radeon_connector->hpd.hpd) { 976 case RADEON_HPD_1: 977 WREG32(DC_HPD1_CONTROL, tmp); 978 break; 979 case RADEON_HPD_2: 980 WREG32(DC_HPD2_CONTROL, tmp); 981 break; 982 case RADEON_HPD_3: 983 WREG32(DC_HPD3_CONTROL, tmp); 984 break; 985 case RADEON_HPD_4: 986 WREG32(DC_HPD4_CONTROL, tmp); 987 break; 988 /* DCE 3.2 */ 989 case RADEON_HPD_5: 990 WREG32(DC_HPD5_CONTROL, tmp); 991 break; 992 case RADEON_HPD_6: 993 WREG32(DC_HPD6_CONTROL, tmp); 994 break; 995 default: 996 break; 997 } 998 } else { 999 switch (radeon_connector->hpd.hpd) { 1000 case RADEON_HPD_1: 1001 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN); 1002 break; 1003 case RADEON_HPD_2: 1004 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN); 1005 break; 1006 case RADEON_HPD_3: 1007 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN); 1008 break; 1009 default: 1010 break; 1011 } 1012 } 1013 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) 1014 enable |= 1 << radeon_connector->hpd.hpd; 1015 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); 1016 } 1017 radeon_irq_kms_enable_hpd(rdev, enable); 1018 } 1019 1020 void r600_hpd_fini(struct radeon_device *rdev) 1021 { 1022 struct drm_device *dev = rdev->ddev; 1023 struct drm_connector *connector; 1024 unsigned disable = 0; 1025 1026 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 1027 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1028 if (ASIC_IS_DCE3(rdev)) { 1029 switch (radeon_connector->hpd.hpd) { 1030 case RADEON_HPD_1: 1031 WREG32(DC_HPD1_CONTROL, 0); 1032 break; 1033 case RADEON_HPD_2: 1034 WREG32(DC_HPD2_CONTROL, 0); 1035 break; 1036 case RADEON_HPD_3: 1037 WREG32(DC_HPD3_CONTROL, 0); 1038 break; 1039 case RADEON_HPD_4: 1040 WREG32(DC_HPD4_CONTROL, 0); 1041 break; 1042 /* DCE 3.2 */ 1043 case RADEON_HPD_5: 1044 WREG32(DC_HPD5_CONTROL, 0); 1045 break; 1046 case RADEON_HPD_6: 1047 WREG32(DC_HPD6_CONTROL, 0); 1048 break; 1049 default: 1050 break; 1051 } 1052 } else { 1053 switch (radeon_connector->hpd.hpd) { 1054 case RADEON_HPD_1: 1055 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0); 1056 break; 1057 case RADEON_HPD_2: 1058 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0); 1059 break; 1060 case RADEON_HPD_3: 1061 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0); 1062 break; 1063 default: 1064 break; 1065 } 1066 } 1067 disable |= 1 << radeon_connector->hpd.hpd; 1068 } 1069 radeon_irq_kms_disable_hpd(rdev, disable); 1070 } 1071 1072 #ifdef __NetBSD__ 1073 /* 1074 * XXX Can't use bus_space here because this is all mapped through the 1075 * radeon_bo abstraction. Can't assume we're x86 because this is 1076 * AMD/ATI Radeon, not Intel. 1077 */ 1078 1079 # define __iomem volatile 1080 # define readl fake_readl 1081 1082 static inline uint32_t 1083 fake_readl(const void __iomem *ptr) 1084 { 1085 uint32_t v; 1086 1087 v = *(const uint32_t __iomem *)ptr; 1088 membar_consumer(); 1089 1090 return v; 1091 } 1092 #endif 1093 1094 /* 1095 * R600 PCIE GART 1096 */ 1097 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev) 1098 { 1099 unsigned i; 1100 u32 tmp; 1101 1102 /* flush hdp cache so updates hit vram */ 1103 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) && 1104 !(rdev->flags & RADEON_IS_AGP)) { 1105 void __iomem *ptr = rdev->gart.ptr; 1106 1107 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read 1108 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL 1109 * This seems to cause problems on some AGP cards. Just use the old 1110 * method for them. 1111 */ 1112 WREG32(HDP_DEBUG1, 0); 1113 (void)readl(ptr); 1114 } else 1115 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); 1116 1117 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12); 1118 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12); 1119 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1)); 1120 for (i = 0; i < rdev->usec_timeout; i++) { 1121 /* read MC_STATUS */ 1122 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE); 1123 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT; 1124 if (tmp == 2) { 1125 printk(KERN_WARNING "[drm] r600 flush TLB failed\n"); 1126 return; 1127 } 1128 if (tmp) { 1129 return; 1130 } 1131 udelay(1); 1132 } 1133 } 1134 1135 #ifdef __NetBSD__ 1136 # undef __iomem 1137 # undef readl 1138 #endif 1139 1140 int r600_pcie_gart_init(struct radeon_device *rdev) 1141 { 1142 int r; 1143 1144 if (rdev->gart.robj) { 1145 WARN(1, "R600 PCIE GART already initialized\n"); 1146 return 0; 1147 } 1148 /* Initialize common gart structure */ 1149 r = radeon_gart_init(rdev); 1150 if (r) 1151 return r; 1152 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; 1153 return radeon_gart_table_vram_alloc(rdev); 1154 } 1155 1156 static int r600_pcie_gart_enable(struct radeon_device *rdev) 1157 { 1158 u32 tmp; 1159 int r, i; 1160 1161 if (rdev->gart.robj == NULL) { 1162 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); 1163 return -EINVAL; 1164 } 1165 r = radeon_gart_table_vram_pin(rdev); 1166 if (r) 1167 return r; 1168 1169 /* Setup L2 cache */ 1170 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | 1171 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 1172 EFFECTIVE_L2_QUEUE_SIZE(7)); 1173 WREG32(VM_L2_CNTL2, 0); 1174 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); 1175 /* Setup TLB control */ 1176 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | 1177 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 1178 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | 1179 ENABLE_WAIT_L2_QUERY; 1180 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); 1181 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); 1182 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING); 1183 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); 1184 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); 1185 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); 1186 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); 1187 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); 1188 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); 1189 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); 1190 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); 1191 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); 1192 WREG32(MC_VM_L1_TLB_MCB_RD_UVD_CNTL, tmp); 1193 WREG32(MC_VM_L1_TLB_MCB_WR_UVD_CNTL, tmp); 1194 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); 1195 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); 1196 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); 1197 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); 1198 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); 1199 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | 1200 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); 1201 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 1202 (u32)(rdev->dummy_page.addr >> 12)); 1203 for (i = 1; i < 7; i++) 1204 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 1205 1206 r600_pcie_gart_tlb_flush(rdev); 1207 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 1208 (unsigned)(rdev->mc.gtt_size >> 20), 1209 (unsigned long long)rdev->gart.table_addr); 1210 rdev->gart.ready = true; 1211 return 0; 1212 } 1213 1214 static void r600_pcie_gart_disable(struct radeon_device *rdev) 1215 { 1216 u32 tmp; 1217 int i; 1218 1219 /* Disable all tables */ 1220 for (i = 0; i < 7; i++) 1221 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 1222 1223 /* Disable L2 cache */ 1224 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | 1225 EFFECTIVE_L2_QUEUE_SIZE(7)); 1226 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); 1227 /* Setup L1 TLB control */ 1228 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | 1229 ENABLE_WAIT_L2_QUERY; 1230 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); 1231 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); 1232 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); 1233 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); 1234 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); 1235 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); 1236 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); 1237 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); 1238 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp); 1239 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp); 1240 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); 1241 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); 1242 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp); 1243 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); 1244 WREG32(MC_VM_L1_TLB_MCB_RD_UVD_CNTL, tmp); 1245 WREG32(MC_VM_L1_TLB_MCB_WR_UVD_CNTL, tmp); 1246 radeon_gart_table_vram_unpin(rdev); 1247 } 1248 1249 static void r600_pcie_gart_fini(struct radeon_device *rdev) 1250 { 1251 radeon_gart_fini(rdev); 1252 r600_pcie_gart_disable(rdev); 1253 radeon_gart_table_vram_free(rdev); 1254 } 1255 1256 static void r600_agp_enable(struct radeon_device *rdev) 1257 { 1258 u32 tmp; 1259 int i; 1260 1261 /* Setup L2 cache */ 1262 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | 1263 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 1264 EFFECTIVE_L2_QUEUE_SIZE(7)); 1265 WREG32(VM_L2_CNTL2, 0); 1266 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); 1267 /* Setup TLB control */ 1268 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | 1269 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 1270 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | 1271 ENABLE_WAIT_L2_QUERY; 1272 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); 1273 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); 1274 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING); 1275 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); 1276 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); 1277 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); 1278 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); 1279 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); 1280 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); 1281 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); 1282 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); 1283 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); 1284 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); 1285 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); 1286 for (i = 0; i < 7; i++) 1287 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 1288 } 1289 1290 int r600_mc_wait_for_idle(struct radeon_device *rdev) 1291 { 1292 unsigned i; 1293 u32 tmp; 1294 1295 for (i = 0; i < rdev->usec_timeout; i++) { 1296 /* read MC_STATUS */ 1297 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00; 1298 if (!tmp) 1299 return 0; 1300 udelay(1); 1301 } 1302 return -1; 1303 } 1304 1305 uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg) 1306 { 1307 unsigned long flags; 1308 uint32_t r; 1309 1310 spin_lock_irqsave(&rdev->mc_idx_lock, flags); 1311 WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg)); 1312 r = RREG32(R_0028FC_MC_DATA); 1313 WREG32(R_0028F8_MC_INDEX, ~C_0028F8_MC_IND_ADDR); 1314 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); 1315 return r; 1316 } 1317 1318 void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 1319 { 1320 unsigned long flags; 1321 1322 spin_lock_irqsave(&rdev->mc_idx_lock, flags); 1323 WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg) | 1324 S_0028F8_MC_IND_WR_EN(1)); 1325 WREG32(R_0028FC_MC_DATA, v); 1326 WREG32(R_0028F8_MC_INDEX, 0x7F); 1327 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); 1328 } 1329 1330 static void r600_mc_program(struct radeon_device *rdev) 1331 { 1332 struct rv515_mc_save save; 1333 u32 tmp; 1334 int i, j; 1335 1336 /* Initialize HDP */ 1337 for (i = 0, j = 0; i < 32; i++, j += 0x18) { 1338 WREG32((0x2c14 + j), 0x00000000); 1339 WREG32((0x2c18 + j), 0x00000000); 1340 WREG32((0x2c1c + j), 0x00000000); 1341 WREG32((0x2c20 + j), 0x00000000); 1342 WREG32((0x2c24 + j), 0x00000000); 1343 } 1344 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0); 1345 1346 rv515_mc_stop(rdev, &save); 1347 if (r600_mc_wait_for_idle(rdev)) { 1348 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1349 } 1350 /* Lockout access through VGA aperture (doesn't exist before R600) */ 1351 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); 1352 /* Update configuration */ 1353 if (rdev->flags & RADEON_IS_AGP) { 1354 if (rdev->mc.vram_start < rdev->mc.gtt_start) { 1355 /* VRAM before AGP */ 1356 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 1357 rdev->mc.vram_start >> 12); 1358 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 1359 rdev->mc.gtt_end >> 12); 1360 } else { 1361 /* VRAM after AGP */ 1362 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 1363 rdev->mc.gtt_start >> 12); 1364 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 1365 rdev->mc.vram_end >> 12); 1366 } 1367 } else { 1368 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12); 1369 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12); 1370 } 1371 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12); 1372 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; 1373 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); 1374 WREG32(MC_VM_FB_LOCATION, tmp); 1375 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); 1376 WREG32(HDP_NONSURFACE_INFO, (2 << 7)); 1377 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF); 1378 if (rdev->flags & RADEON_IS_AGP) { 1379 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22); 1380 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22); 1381 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); 1382 } else { 1383 WREG32(MC_VM_AGP_BASE, 0); 1384 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); 1385 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); 1386 } 1387 if (r600_mc_wait_for_idle(rdev)) { 1388 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1389 } 1390 rv515_mc_resume(rdev, &save); 1391 /* we need to own VRAM, so turn off the VGA renderer here 1392 * to stop it overwriting our objects */ 1393 rv515_vga_render_disable(rdev); 1394 } 1395 1396 /** 1397 * r600_vram_gtt_location - try to find VRAM & GTT location 1398 * @rdev: radeon device structure holding all necessary informations 1399 * @mc: memory controller structure holding memory informations 1400 * 1401 * Function will place try to place VRAM at same place as in CPU (PCI) 1402 * address space as some GPU seems to have issue when we reprogram at 1403 * different address space. 1404 * 1405 * If there is not enough space to fit the unvisible VRAM after the 1406 * aperture then we limit the VRAM size to the aperture. 1407 * 1408 * If we are using AGP then place VRAM adjacent to AGP aperture are we need 1409 * them to be in one from GPU point of view so that we can program GPU to 1410 * catch access outside them (weird GPU policy see ??). 1411 * 1412 * This function will never fails, worst case are limiting VRAM or GTT. 1413 * 1414 * Note: GTT start, end, size should be initialized before calling this 1415 * function on AGP platform. 1416 */ 1417 static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) 1418 { 1419 u64 size_bf, size_af; 1420 1421 if (mc->mc_vram_size > 0xE0000000) { 1422 /* leave room for at least 512M GTT */ 1423 dev_warn(rdev->dev, "limiting VRAM\n"); 1424 mc->real_vram_size = 0xE0000000; 1425 mc->mc_vram_size = 0xE0000000; 1426 } 1427 if (rdev->flags & RADEON_IS_AGP) { 1428 size_bf = mc->gtt_start; 1429 size_af = mc->mc_mask - mc->gtt_end; 1430 if (size_bf > size_af) { 1431 if (mc->mc_vram_size > size_bf) { 1432 dev_warn(rdev->dev, "limiting VRAM\n"); 1433 mc->real_vram_size = size_bf; 1434 mc->mc_vram_size = size_bf; 1435 } 1436 mc->vram_start = mc->gtt_start - mc->mc_vram_size; 1437 } else { 1438 if (mc->mc_vram_size > size_af) { 1439 dev_warn(rdev->dev, "limiting VRAM\n"); 1440 mc->real_vram_size = size_af; 1441 mc->mc_vram_size = size_af; 1442 } 1443 mc->vram_start = mc->gtt_end + 1; 1444 } 1445 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; 1446 dev_info(rdev->dev, "VRAM: %"PRIu64"M 0x%08"PRIX64" - 0x%08"PRIX64" (%"PRIu64"M used)\n", 1447 mc->mc_vram_size >> 20, mc->vram_start, 1448 mc->vram_end, mc->real_vram_size >> 20); 1449 } else { 1450 u64 base = 0; 1451 if (rdev->flags & RADEON_IS_IGP) { 1452 base = RREG32(MC_VM_FB_LOCATION) & 0xFFFF; 1453 base <<= 24; 1454 } 1455 radeon_vram_location(rdev, &rdev->mc, base); 1456 rdev->mc.gtt_base_align = 0; 1457 radeon_gtt_location(rdev, mc); 1458 } 1459 } 1460 1461 static int r600_mc_init(struct radeon_device *rdev) 1462 { 1463 u32 tmp; 1464 int chansize, numchan; 1465 uint32_t h_addr, l_addr; 1466 unsigned long long k8_addr; 1467 1468 /* Get VRAM informations */ 1469 rdev->mc.vram_is_ddr = true; 1470 tmp = RREG32(RAMCFG); 1471 if (tmp & CHANSIZE_OVERRIDE) { 1472 chansize = 16; 1473 } else if (tmp & CHANSIZE_MASK) { 1474 chansize = 64; 1475 } else { 1476 chansize = 32; 1477 } 1478 tmp = RREG32(CHMAP); 1479 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { 1480 case 0: 1481 default: 1482 numchan = 1; 1483 break; 1484 case 1: 1485 numchan = 2; 1486 break; 1487 case 2: 1488 numchan = 4; 1489 break; 1490 case 3: 1491 numchan = 8; 1492 break; 1493 } 1494 rdev->mc.vram_width = numchan * chansize; 1495 /* Could aper size report 0 ? */ 1496 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); 1497 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); 1498 /* Setup GPU memory space */ 1499 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); 1500 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); 1501 rdev->mc.visible_vram_size = rdev->mc.aper_size; 1502 r600_vram_gtt_location(rdev, &rdev->mc); 1503 1504 if (rdev->flags & RADEON_IS_IGP) { 1505 rs690_pm_info(rdev); 1506 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); 1507 1508 if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) { 1509 /* Use K8 direct mapping for fast fb access. */ 1510 rdev->fastfb_working = false; 1511 h_addr = G_000012_K8_ADDR_EXT(RREG32_MC(R_000012_MC_MISC_UMA_CNTL)); 1512 l_addr = RREG32_MC(R_000011_K8_FB_LOCATION); 1513 k8_addr = ((unsigned long long)h_addr) << 32 | l_addr; 1514 #if defined(CONFIG_X86_32) && !defined(CONFIG_X86_PAE) 1515 if (k8_addr + rdev->mc.visible_vram_size < 0x100000000ULL) 1516 #endif 1517 { 1518 /* FastFB shall be used with UMA memory. Here it is simply disabled when sideport 1519 * memory is present. 1520 */ 1521 if (rdev->mc.igp_sideport_enabled == false && radeon_fastfb == 1) { 1522 DRM_INFO("Direct mapping: aper base at 0x%llx, replaced by direct mapping base 0x%llx.\n", 1523 (unsigned long long)rdev->mc.aper_base, k8_addr); 1524 rdev->mc.aper_base = (resource_size_t)k8_addr; 1525 rdev->fastfb_working = true; 1526 } 1527 } 1528 } 1529 } 1530 1531 radeon_update_bandwidth_info(rdev); 1532 return 0; 1533 } 1534 1535 int r600_vram_scratch_init(struct radeon_device *rdev) 1536 { 1537 int r; 1538 1539 if (rdev->vram_scratch.robj == NULL) { 1540 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, 1541 PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM, 1542 0, NULL, NULL, &rdev->vram_scratch.robj); 1543 if (r) { 1544 return r; 1545 } 1546 } 1547 1548 r = radeon_bo_reserve(rdev->vram_scratch.robj, false); 1549 if (unlikely(r != 0)) 1550 return r; 1551 r = radeon_bo_pin(rdev->vram_scratch.robj, 1552 RADEON_GEM_DOMAIN_VRAM, &rdev->vram_scratch.gpu_addr); 1553 if (r) { 1554 radeon_bo_unreserve(rdev->vram_scratch.robj); 1555 return r; 1556 } 1557 r = radeon_bo_kmap(rdev->vram_scratch.robj, 1558 (void **)__UNVOLATILE(&rdev->vram_scratch.ptr)); 1559 if (r) 1560 radeon_bo_unpin(rdev->vram_scratch.robj); 1561 radeon_bo_unreserve(rdev->vram_scratch.robj); 1562 1563 return r; 1564 } 1565 1566 void r600_vram_scratch_fini(struct radeon_device *rdev) 1567 { 1568 int r; 1569 1570 if (rdev->vram_scratch.robj == NULL) { 1571 return; 1572 } 1573 r = radeon_bo_reserve(rdev->vram_scratch.robj, false); 1574 if (likely(r == 0)) { 1575 radeon_bo_kunmap(rdev->vram_scratch.robj); 1576 radeon_bo_unpin(rdev->vram_scratch.robj); 1577 radeon_bo_unreserve(rdev->vram_scratch.robj); 1578 } 1579 radeon_bo_unref(&rdev->vram_scratch.robj); 1580 } 1581 1582 void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung) 1583 { 1584 u32 tmp = RREG32(R600_BIOS_3_SCRATCH); 1585 1586 if (hung) 1587 tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG; 1588 else 1589 tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG; 1590 1591 WREG32(R600_BIOS_3_SCRATCH, tmp); 1592 } 1593 1594 static void r600_print_gpu_status_regs(struct radeon_device *rdev) 1595 { 1596 dev_info(rdev->dev, " R_008010_GRBM_STATUS = 0x%08X\n", 1597 RREG32(R_008010_GRBM_STATUS)); 1598 dev_info(rdev->dev, " R_008014_GRBM_STATUS2 = 0x%08X\n", 1599 RREG32(R_008014_GRBM_STATUS2)); 1600 dev_info(rdev->dev, " R_000E50_SRBM_STATUS = 0x%08X\n", 1601 RREG32(R_000E50_SRBM_STATUS)); 1602 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n", 1603 RREG32(CP_STALLED_STAT1)); 1604 dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n", 1605 RREG32(CP_STALLED_STAT2)); 1606 dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n", 1607 RREG32(CP_BUSY_STAT)); 1608 dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n", 1609 RREG32(CP_STAT)); 1610 dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n", 1611 RREG32(DMA_STATUS_REG)); 1612 } 1613 1614 static bool r600_is_display_hung(struct radeon_device *rdev) 1615 { 1616 u32 crtc_hung = 0; 1617 u32 crtc_status[2]; 1618 u32 i, j, tmp; 1619 1620 for (i = 0; i < rdev->num_crtc; i++) { 1621 if (RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN) { 1622 crtc_status[i] = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]); 1623 crtc_hung |= (1 << i); 1624 } 1625 } 1626 1627 for (j = 0; j < 10; j++) { 1628 for (i = 0; i < rdev->num_crtc; i++) { 1629 if (crtc_hung & (1 << i)) { 1630 tmp = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]); 1631 if (tmp != crtc_status[i]) 1632 crtc_hung &= ~(1 << i); 1633 } 1634 } 1635 if (crtc_hung == 0) 1636 return false; 1637 udelay(100); 1638 } 1639 1640 return true; 1641 } 1642 1643 u32 r600_gpu_check_soft_reset(struct radeon_device *rdev) 1644 { 1645 u32 reset_mask = 0; 1646 u32 tmp; 1647 1648 /* GRBM_STATUS */ 1649 tmp = RREG32(R_008010_GRBM_STATUS); 1650 if (rdev->family >= CHIP_RV770) { 1651 if (G_008010_PA_BUSY(tmp) | G_008010_SC_BUSY(tmp) | 1652 G_008010_SH_BUSY(tmp) | G_008010_SX_BUSY(tmp) | 1653 G_008010_TA_BUSY(tmp) | G_008010_VGT_BUSY(tmp) | 1654 G_008010_DB03_BUSY(tmp) | G_008010_CB03_BUSY(tmp) | 1655 G_008010_SPI03_BUSY(tmp) | G_008010_VGT_BUSY_NO_DMA(tmp)) 1656 reset_mask |= RADEON_RESET_GFX; 1657 } else { 1658 if (G_008010_PA_BUSY(tmp) | G_008010_SC_BUSY(tmp) | 1659 G_008010_SH_BUSY(tmp) | G_008010_SX_BUSY(tmp) | 1660 G_008010_TA03_BUSY(tmp) | G_008010_VGT_BUSY(tmp) | 1661 G_008010_DB03_BUSY(tmp) | G_008010_CB03_BUSY(tmp) | 1662 G_008010_SPI03_BUSY(tmp) | G_008010_VGT_BUSY_NO_DMA(tmp)) 1663 reset_mask |= RADEON_RESET_GFX; 1664 } 1665 1666 if (G_008010_CF_RQ_PENDING(tmp) | G_008010_PF_RQ_PENDING(tmp) | 1667 G_008010_CP_BUSY(tmp) | G_008010_CP_COHERENCY_BUSY(tmp)) 1668 reset_mask |= RADEON_RESET_CP; 1669 1670 if (G_008010_GRBM_EE_BUSY(tmp)) 1671 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP; 1672 1673 /* DMA_STATUS_REG */ 1674 tmp = RREG32(DMA_STATUS_REG); 1675 if (!(tmp & DMA_IDLE)) 1676 reset_mask |= RADEON_RESET_DMA; 1677 1678 /* SRBM_STATUS */ 1679 tmp = RREG32(R_000E50_SRBM_STATUS); 1680 if (G_000E50_RLC_RQ_PENDING(tmp) | G_000E50_RLC_BUSY(tmp)) 1681 reset_mask |= RADEON_RESET_RLC; 1682 1683 if (G_000E50_IH_BUSY(tmp)) 1684 reset_mask |= RADEON_RESET_IH; 1685 1686 if (G_000E50_SEM_BUSY(tmp)) 1687 reset_mask |= RADEON_RESET_SEM; 1688 1689 if (G_000E50_GRBM_RQ_PENDING(tmp)) 1690 reset_mask |= RADEON_RESET_GRBM; 1691 1692 if (G_000E50_VMC_BUSY(tmp)) 1693 reset_mask |= RADEON_RESET_VMC; 1694 1695 if (G_000E50_MCB_BUSY(tmp) | G_000E50_MCDZ_BUSY(tmp) | 1696 G_000E50_MCDY_BUSY(tmp) | G_000E50_MCDX_BUSY(tmp) | 1697 G_000E50_MCDW_BUSY(tmp)) 1698 reset_mask |= RADEON_RESET_MC; 1699 1700 if (r600_is_display_hung(rdev)) 1701 reset_mask |= RADEON_RESET_DISPLAY; 1702 1703 /* Skip MC reset as it's mostly likely not hung, just busy */ 1704 if (reset_mask & RADEON_RESET_MC) { 1705 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask); 1706 reset_mask &= ~RADEON_RESET_MC; 1707 } 1708 1709 return reset_mask; 1710 } 1711 1712 static void r600_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask) 1713 { 1714 struct rv515_mc_save save; 1715 u32 grbm_soft_reset = 0, srbm_soft_reset = 0; 1716 u32 tmp; 1717 1718 if (reset_mask == 0) 1719 return; 1720 1721 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask); 1722 1723 r600_print_gpu_status_regs(rdev); 1724 1725 /* Disable CP parsing/prefetching */ 1726 if (rdev->family >= CHIP_RV770) 1727 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1) | S_0086D8_CP_PFP_HALT(1)); 1728 else 1729 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); 1730 1731 /* disable the RLC */ 1732 WREG32(RLC_CNTL, 0); 1733 1734 if (reset_mask & RADEON_RESET_DMA) { 1735 /* Disable DMA */ 1736 tmp = RREG32(DMA_RB_CNTL); 1737 tmp &= ~DMA_RB_ENABLE; 1738 WREG32(DMA_RB_CNTL, tmp); 1739 } 1740 1741 mdelay(50); 1742 1743 rv515_mc_stop(rdev, &save); 1744 if (r600_mc_wait_for_idle(rdev)) { 1745 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1746 } 1747 1748 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) { 1749 if (rdev->family >= CHIP_RV770) 1750 grbm_soft_reset |= S_008020_SOFT_RESET_DB(1) | 1751 S_008020_SOFT_RESET_CB(1) | 1752 S_008020_SOFT_RESET_PA(1) | 1753 S_008020_SOFT_RESET_SC(1) | 1754 S_008020_SOFT_RESET_SPI(1) | 1755 S_008020_SOFT_RESET_SX(1) | 1756 S_008020_SOFT_RESET_SH(1) | 1757 S_008020_SOFT_RESET_TC(1) | 1758 S_008020_SOFT_RESET_TA(1) | 1759 S_008020_SOFT_RESET_VC(1) | 1760 S_008020_SOFT_RESET_VGT(1); 1761 else 1762 grbm_soft_reset |= S_008020_SOFT_RESET_CR(1) | 1763 S_008020_SOFT_RESET_DB(1) | 1764 S_008020_SOFT_RESET_CB(1) | 1765 S_008020_SOFT_RESET_PA(1) | 1766 S_008020_SOFT_RESET_SC(1) | 1767 S_008020_SOFT_RESET_SMX(1) | 1768 S_008020_SOFT_RESET_SPI(1) | 1769 S_008020_SOFT_RESET_SX(1) | 1770 S_008020_SOFT_RESET_SH(1) | 1771 S_008020_SOFT_RESET_TC(1) | 1772 S_008020_SOFT_RESET_TA(1) | 1773 S_008020_SOFT_RESET_VC(1) | 1774 S_008020_SOFT_RESET_VGT(1); 1775 } 1776 1777 if (reset_mask & RADEON_RESET_CP) { 1778 grbm_soft_reset |= S_008020_SOFT_RESET_CP(1) | 1779 S_008020_SOFT_RESET_VGT(1); 1780 1781 srbm_soft_reset |= S_000E60_SOFT_RESET_GRBM(1); 1782 } 1783 1784 if (reset_mask & RADEON_RESET_DMA) { 1785 if (rdev->family >= CHIP_RV770) 1786 srbm_soft_reset |= RV770_SOFT_RESET_DMA; 1787 else 1788 srbm_soft_reset |= SOFT_RESET_DMA; 1789 } 1790 1791 if (reset_mask & RADEON_RESET_RLC) 1792 srbm_soft_reset |= S_000E60_SOFT_RESET_RLC(1); 1793 1794 if (reset_mask & RADEON_RESET_SEM) 1795 srbm_soft_reset |= S_000E60_SOFT_RESET_SEM(1); 1796 1797 if (reset_mask & RADEON_RESET_IH) 1798 srbm_soft_reset |= S_000E60_SOFT_RESET_IH(1); 1799 1800 if (reset_mask & RADEON_RESET_GRBM) 1801 srbm_soft_reset |= S_000E60_SOFT_RESET_GRBM(1); 1802 1803 if (!(rdev->flags & RADEON_IS_IGP)) { 1804 if (reset_mask & RADEON_RESET_MC) 1805 srbm_soft_reset |= S_000E60_SOFT_RESET_MC(1); 1806 } 1807 1808 if (reset_mask & RADEON_RESET_VMC) 1809 srbm_soft_reset |= S_000E60_SOFT_RESET_VMC(1); 1810 1811 if (grbm_soft_reset) { 1812 tmp = RREG32(R_008020_GRBM_SOFT_RESET); 1813 tmp |= grbm_soft_reset; 1814 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp); 1815 WREG32(R_008020_GRBM_SOFT_RESET, tmp); 1816 tmp = RREG32(R_008020_GRBM_SOFT_RESET); 1817 1818 udelay(50); 1819 1820 tmp &= ~grbm_soft_reset; 1821 WREG32(R_008020_GRBM_SOFT_RESET, tmp); 1822 tmp = RREG32(R_008020_GRBM_SOFT_RESET); 1823 } 1824 1825 if (srbm_soft_reset) { 1826 tmp = RREG32(SRBM_SOFT_RESET); 1827 tmp |= srbm_soft_reset; 1828 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1829 WREG32(SRBM_SOFT_RESET, tmp); 1830 tmp = RREG32(SRBM_SOFT_RESET); 1831 1832 udelay(50); 1833 1834 tmp &= ~srbm_soft_reset; 1835 WREG32(SRBM_SOFT_RESET, tmp); 1836 tmp = RREG32(SRBM_SOFT_RESET); 1837 } 1838 1839 /* Wait a little for things to settle down */ 1840 mdelay(1); 1841 1842 rv515_mc_resume(rdev, &save); 1843 udelay(50); 1844 1845 r600_print_gpu_status_regs(rdev); 1846 } 1847 1848 static void r600_gpu_pci_config_reset(struct radeon_device *rdev) 1849 { 1850 struct rv515_mc_save save; 1851 u32 tmp, i; 1852 1853 dev_info(rdev->dev, "GPU pci config reset\n"); 1854 1855 /* disable dpm? */ 1856 1857 /* Disable CP parsing/prefetching */ 1858 if (rdev->family >= CHIP_RV770) 1859 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1) | S_0086D8_CP_PFP_HALT(1)); 1860 else 1861 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); 1862 1863 /* disable the RLC */ 1864 WREG32(RLC_CNTL, 0); 1865 1866 /* Disable DMA */ 1867 tmp = RREG32(DMA_RB_CNTL); 1868 tmp &= ~DMA_RB_ENABLE; 1869 WREG32(DMA_RB_CNTL, tmp); 1870 1871 mdelay(50); 1872 1873 /* set mclk/sclk to bypass */ 1874 if (rdev->family >= CHIP_RV770) 1875 rv770_set_clk_bypass_mode(rdev); 1876 /* disable BM */ 1877 pci_clear_master(rdev->pdev); 1878 /* disable mem access */ 1879 rv515_mc_stop(rdev, &save); 1880 if (r600_mc_wait_for_idle(rdev)) { 1881 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1882 } 1883 1884 /* BIF reset workaround. Not sure if this is needed on 6xx */ 1885 tmp = RREG32(BUS_CNTL); 1886 tmp |= VGA_COHE_SPEC_TIMER_DIS; 1887 WREG32(BUS_CNTL, tmp); 1888 1889 tmp = RREG32(BIF_SCRATCH0); 1890 1891 /* reset */ 1892 radeon_pci_config_reset(rdev); 1893 mdelay(1); 1894 1895 /* BIF reset workaround. Not sure if this is needed on 6xx */ 1896 tmp = SOFT_RESET_BIF; 1897 WREG32(SRBM_SOFT_RESET, tmp); 1898 mdelay(1); 1899 WREG32(SRBM_SOFT_RESET, 0); 1900 1901 /* wait for asic to come out of reset */ 1902 for (i = 0; i < rdev->usec_timeout; i++) { 1903 if (RREG32(CONFIG_MEMSIZE) != 0xffffffff) 1904 break; 1905 udelay(1); 1906 } 1907 } 1908 1909 int r600_asic_reset(struct radeon_device *rdev) 1910 { 1911 u32 reset_mask; 1912 1913 reset_mask = r600_gpu_check_soft_reset(rdev); 1914 1915 if (reset_mask) 1916 r600_set_bios_scratch_engine_hung(rdev, true); 1917 1918 /* try soft reset */ 1919 r600_gpu_soft_reset(rdev, reset_mask); 1920 1921 reset_mask = r600_gpu_check_soft_reset(rdev); 1922 1923 /* try pci config reset */ 1924 if (reset_mask && radeon_hard_reset) 1925 r600_gpu_pci_config_reset(rdev); 1926 1927 reset_mask = r600_gpu_check_soft_reset(rdev); 1928 1929 if (!reset_mask) 1930 r600_set_bios_scratch_engine_hung(rdev, false); 1931 1932 return 0; 1933 } 1934 1935 /** 1936 * r600_gfx_is_lockup - Check if the GFX engine is locked up 1937 * 1938 * @rdev: radeon_device pointer 1939 * @ring: radeon_ring structure holding ring information 1940 * 1941 * Check if the GFX engine is locked up. 1942 * Returns true if the engine appears to be locked up, false if not. 1943 */ 1944 bool r600_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) 1945 { 1946 u32 reset_mask = r600_gpu_check_soft_reset(rdev); 1947 1948 if (!(reset_mask & (RADEON_RESET_GFX | 1949 RADEON_RESET_COMPUTE | 1950 RADEON_RESET_CP))) { 1951 radeon_ring_lockup_update(rdev, ring); 1952 return false; 1953 } 1954 return radeon_ring_test_lockup(rdev, ring); 1955 } 1956 1957 u32 r6xx_remap_render_backend(struct radeon_device *rdev, 1958 u32 tiling_pipe_num, 1959 u32 max_rb_num, 1960 u32 total_max_rb_num, 1961 u32 disabled_rb_mask) 1962 { 1963 u32 rendering_pipe_num, rb_num_width, req_rb_num; 1964 u32 pipe_rb_ratio, pipe_rb_remain, tmp; 1965 u32 data = 0, mask = 1 << (max_rb_num - 1); 1966 unsigned i, j; 1967 1968 /* mask out the RBs that don't exist on that asic */ 1969 tmp = disabled_rb_mask | ((0xff << max_rb_num) & 0xff); 1970 /* make sure at least one RB is available */ 1971 if ((tmp & 0xff) != 0xff) 1972 disabled_rb_mask = tmp; 1973 1974 rendering_pipe_num = 1 << tiling_pipe_num; 1975 req_rb_num = total_max_rb_num - r600_count_pipe_bits(disabled_rb_mask); 1976 BUG_ON(rendering_pipe_num < req_rb_num); 1977 1978 pipe_rb_ratio = rendering_pipe_num / req_rb_num; 1979 pipe_rb_remain = rendering_pipe_num - pipe_rb_ratio * req_rb_num; 1980 1981 if (rdev->family <= CHIP_RV740) { 1982 /* r6xx/r7xx */ 1983 rb_num_width = 2; 1984 } else { 1985 /* eg+ */ 1986 rb_num_width = 4; 1987 } 1988 1989 for (i = 0; i < max_rb_num; i++) { 1990 if (!(mask & disabled_rb_mask)) { 1991 for (j = 0; j < pipe_rb_ratio; j++) { 1992 data <<= rb_num_width; 1993 data |= max_rb_num - i - 1; 1994 } 1995 if (pipe_rb_remain) { 1996 data <<= rb_num_width; 1997 data |= max_rb_num - i - 1; 1998 pipe_rb_remain--; 1999 } 2000 } 2001 mask >>= 1; 2002 } 2003 2004 return data; 2005 } 2006 2007 int r600_count_pipe_bits(uint32_t val) 2008 { 2009 return hweight32(val); 2010 } 2011 2012 static void r600_gpu_init(struct radeon_device *rdev) 2013 { 2014 u32 tiling_config; 2015 u32 ramcfg; 2016 u32 cc_gc_shader_pipe_config; 2017 u32 tmp; 2018 int i, j; 2019 u32 sq_config; 2020 u32 sq_gpr_resource_mgmt_1 = 0; 2021 u32 sq_gpr_resource_mgmt_2 = 0; 2022 u32 sq_thread_resource_mgmt = 0; 2023 u32 sq_stack_resource_mgmt_1 = 0; 2024 u32 sq_stack_resource_mgmt_2 = 0; 2025 u32 disabled_rb_mask; 2026 2027 rdev->config.r600.tiling_group_size = 256; 2028 switch (rdev->family) { 2029 case CHIP_R600: 2030 rdev->config.r600.max_pipes = 4; 2031 rdev->config.r600.max_tile_pipes = 8; 2032 rdev->config.r600.max_simds = 4; 2033 rdev->config.r600.max_backends = 4; 2034 rdev->config.r600.max_gprs = 256; 2035 rdev->config.r600.max_threads = 192; 2036 rdev->config.r600.max_stack_entries = 256; 2037 rdev->config.r600.max_hw_contexts = 8; 2038 rdev->config.r600.max_gs_threads = 16; 2039 rdev->config.r600.sx_max_export_size = 128; 2040 rdev->config.r600.sx_max_export_pos_size = 16; 2041 rdev->config.r600.sx_max_export_smx_size = 128; 2042 rdev->config.r600.sq_num_cf_insts = 2; 2043 break; 2044 case CHIP_RV630: 2045 case CHIP_RV635: 2046 rdev->config.r600.max_pipes = 2; 2047 rdev->config.r600.max_tile_pipes = 2; 2048 rdev->config.r600.max_simds = 3; 2049 rdev->config.r600.max_backends = 1; 2050 rdev->config.r600.max_gprs = 128; 2051 rdev->config.r600.max_threads = 192; 2052 rdev->config.r600.max_stack_entries = 128; 2053 rdev->config.r600.max_hw_contexts = 8; 2054 rdev->config.r600.max_gs_threads = 4; 2055 rdev->config.r600.sx_max_export_size = 128; 2056 rdev->config.r600.sx_max_export_pos_size = 16; 2057 rdev->config.r600.sx_max_export_smx_size = 128; 2058 rdev->config.r600.sq_num_cf_insts = 2; 2059 break; 2060 case CHIP_RV610: 2061 case CHIP_RV620: 2062 case CHIP_RS780: 2063 case CHIP_RS880: 2064 rdev->config.r600.max_pipes = 1; 2065 rdev->config.r600.max_tile_pipes = 1; 2066 rdev->config.r600.max_simds = 2; 2067 rdev->config.r600.max_backends = 1; 2068 rdev->config.r600.max_gprs = 128; 2069 rdev->config.r600.max_threads = 192; 2070 rdev->config.r600.max_stack_entries = 128; 2071 rdev->config.r600.max_hw_contexts = 4; 2072 rdev->config.r600.max_gs_threads = 4; 2073 rdev->config.r600.sx_max_export_size = 128; 2074 rdev->config.r600.sx_max_export_pos_size = 16; 2075 rdev->config.r600.sx_max_export_smx_size = 128; 2076 rdev->config.r600.sq_num_cf_insts = 1; 2077 break; 2078 case CHIP_RV670: 2079 rdev->config.r600.max_pipes = 4; 2080 rdev->config.r600.max_tile_pipes = 4; 2081 rdev->config.r600.max_simds = 4; 2082 rdev->config.r600.max_backends = 4; 2083 rdev->config.r600.max_gprs = 192; 2084 rdev->config.r600.max_threads = 192; 2085 rdev->config.r600.max_stack_entries = 256; 2086 rdev->config.r600.max_hw_contexts = 8; 2087 rdev->config.r600.max_gs_threads = 16; 2088 rdev->config.r600.sx_max_export_size = 128; 2089 rdev->config.r600.sx_max_export_pos_size = 16; 2090 rdev->config.r600.sx_max_export_smx_size = 128; 2091 rdev->config.r600.sq_num_cf_insts = 2; 2092 break; 2093 default: 2094 break; 2095 } 2096 2097 /* Initialize HDP */ 2098 for (i = 0, j = 0; i < 32; i++, j += 0x18) { 2099 WREG32((0x2c14 + j), 0x00000000); 2100 WREG32((0x2c18 + j), 0x00000000); 2101 WREG32((0x2c1c + j), 0x00000000); 2102 WREG32((0x2c20 + j), 0x00000000); 2103 WREG32((0x2c24 + j), 0x00000000); 2104 } 2105 2106 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); 2107 2108 /* Setup tiling */ 2109 tiling_config = 0; 2110 ramcfg = RREG32(RAMCFG); 2111 switch (rdev->config.r600.max_tile_pipes) { 2112 case 1: 2113 tiling_config |= PIPE_TILING(0); 2114 break; 2115 case 2: 2116 tiling_config |= PIPE_TILING(1); 2117 break; 2118 case 4: 2119 tiling_config |= PIPE_TILING(2); 2120 break; 2121 case 8: 2122 tiling_config |= PIPE_TILING(3); 2123 break; 2124 default: 2125 break; 2126 } 2127 rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes; 2128 rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); 2129 tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); 2130 tiling_config |= GROUP_SIZE((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT); 2131 2132 tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT; 2133 if (tmp > 3) { 2134 tiling_config |= ROW_TILING(3); 2135 tiling_config |= SAMPLE_SPLIT(3); 2136 } else { 2137 tiling_config |= ROW_TILING(tmp); 2138 tiling_config |= SAMPLE_SPLIT(tmp); 2139 } 2140 tiling_config |= BANK_SWAPS(1); 2141 2142 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0x00ffff00; 2143 tmp = rdev->config.r600.max_simds - 2144 r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R6XX_MAX_SIMDS_MASK); 2145 rdev->config.r600.active_simds = tmp; 2146 2147 disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R6XX_MAX_BACKENDS_MASK; 2148 tmp = 0; 2149 for (i = 0; i < rdev->config.r600.max_backends; i++) 2150 tmp |= (1 << i); 2151 /* if all the backends are disabled, fix it up here */ 2152 if ((disabled_rb_mask & tmp) == tmp) { 2153 for (i = 0; i < rdev->config.r600.max_backends; i++) 2154 disabled_rb_mask &= ~(1 << i); 2155 } 2156 tmp = (tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT; 2157 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.r600.max_backends, 2158 R6XX_MAX_BACKENDS, disabled_rb_mask); 2159 tiling_config |= tmp << 16; 2160 rdev->config.r600.backend_map = tmp; 2161 2162 rdev->config.r600.tile_config = tiling_config; 2163 WREG32(GB_TILING_CONFIG, tiling_config); 2164 WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff); 2165 WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff); 2166 WREG32(DMA_TILING_CONFIG, tiling_config & 0xffff); 2167 2168 tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8); 2169 WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK); 2170 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK); 2171 2172 /* Setup some CP states */ 2173 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b))); 2174 WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40))); 2175 2176 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT | 2177 SYNC_WALKER | SYNC_ALIGNER)); 2178 /* Setup various GPU states */ 2179 if (rdev->family == CHIP_RV670) 2180 WREG32(ARB_GDEC_RD_CNTL, 0x00000021); 2181 2182 tmp = RREG32(SX_DEBUG_1); 2183 tmp |= SMX_EVENT_RELEASE; 2184 if ((rdev->family > CHIP_R600)) 2185 tmp |= ENABLE_NEW_SMX_ADDRESS; 2186 WREG32(SX_DEBUG_1, tmp); 2187 2188 if (((rdev->family) == CHIP_R600) || 2189 ((rdev->family) == CHIP_RV630) || 2190 ((rdev->family) == CHIP_RV610) || 2191 ((rdev->family) == CHIP_RV620) || 2192 ((rdev->family) == CHIP_RS780) || 2193 ((rdev->family) == CHIP_RS880)) { 2194 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE); 2195 } else { 2196 WREG32(DB_DEBUG, 0); 2197 } 2198 WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) | 2199 DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4))); 2200 2201 WREG32(PA_SC_MULTI_CHIP_CNTL, 0); 2202 WREG32(VGT_NUM_INSTANCES, 0); 2203 2204 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0)); 2205 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0)); 2206 2207 tmp = RREG32(SQ_MS_FIFO_SIZES); 2208 if (((rdev->family) == CHIP_RV610) || 2209 ((rdev->family) == CHIP_RV620) || 2210 ((rdev->family) == CHIP_RS780) || 2211 ((rdev->family) == CHIP_RS880)) { 2212 tmp = (CACHE_FIFO_SIZE(0xa) | 2213 FETCH_FIFO_HIWATER(0xa) | 2214 DONE_FIFO_HIWATER(0xe0) | 2215 ALU_UPDATE_FIFO_HIWATER(0x8)); 2216 } else if (((rdev->family) == CHIP_R600) || 2217 ((rdev->family) == CHIP_RV630)) { 2218 tmp &= ~DONE_FIFO_HIWATER(0xff); 2219 tmp |= DONE_FIFO_HIWATER(0x4); 2220 } 2221 WREG32(SQ_MS_FIFO_SIZES, tmp); 2222 2223 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT 2224 * should be adjusted as needed by the 2D/3D drivers. This just sets default values 2225 */ 2226 sq_config = RREG32(SQ_CONFIG); 2227 sq_config &= ~(PS_PRIO(3) | 2228 VS_PRIO(3) | 2229 GS_PRIO(3) | 2230 ES_PRIO(3U)); 2231 sq_config |= (DX9_CONSTS | 2232 VC_ENABLE | 2233 PS_PRIO(0) | 2234 VS_PRIO(1) | 2235 GS_PRIO(2) | 2236 ES_PRIO(3U)); 2237 2238 if ((rdev->family) == CHIP_R600) { 2239 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) | 2240 NUM_VS_GPRS(124) | 2241 NUM_CLAUSE_TEMP_GPRS(4)); 2242 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) | 2243 NUM_ES_GPRS(0)); 2244 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) | 2245 NUM_VS_THREADS(48) | 2246 NUM_GS_THREADS(4) | 2247 NUM_ES_THREADS(4)); 2248 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) | 2249 NUM_VS_STACK_ENTRIES(128)); 2250 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) | 2251 NUM_ES_STACK_ENTRIES(0)); 2252 } else if (((rdev->family) == CHIP_RV610) || 2253 ((rdev->family) == CHIP_RV620) || 2254 ((rdev->family) == CHIP_RS780) || 2255 ((rdev->family) == CHIP_RS880)) { 2256 /* no vertex cache */ 2257 sq_config &= ~VC_ENABLE; 2258 2259 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | 2260 NUM_VS_GPRS(44) | 2261 NUM_CLAUSE_TEMP_GPRS(2)); 2262 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) | 2263 NUM_ES_GPRS(17)); 2264 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | 2265 NUM_VS_THREADS(78) | 2266 NUM_GS_THREADS(4) | 2267 NUM_ES_THREADS(31)); 2268 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) | 2269 NUM_VS_STACK_ENTRIES(40)); 2270 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) | 2271 NUM_ES_STACK_ENTRIES(16)); 2272 } else if (((rdev->family) == CHIP_RV630) || 2273 ((rdev->family) == CHIP_RV635)) { 2274 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | 2275 NUM_VS_GPRS(44) | 2276 NUM_CLAUSE_TEMP_GPRS(2)); 2277 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) | 2278 NUM_ES_GPRS(18)); 2279 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | 2280 NUM_VS_THREADS(78) | 2281 NUM_GS_THREADS(4) | 2282 NUM_ES_THREADS(31)); 2283 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) | 2284 NUM_VS_STACK_ENTRIES(40)); 2285 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) | 2286 NUM_ES_STACK_ENTRIES(16)); 2287 } else if ((rdev->family) == CHIP_RV670) { 2288 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | 2289 NUM_VS_GPRS(44) | 2290 NUM_CLAUSE_TEMP_GPRS(2)); 2291 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) | 2292 NUM_ES_GPRS(17)); 2293 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | 2294 NUM_VS_THREADS(78) | 2295 NUM_GS_THREADS(4) | 2296 NUM_ES_THREADS(31)); 2297 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) | 2298 NUM_VS_STACK_ENTRIES(64)); 2299 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) | 2300 NUM_ES_STACK_ENTRIES(64)); 2301 } 2302 2303 WREG32(SQ_CONFIG, sq_config); 2304 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1); 2305 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2); 2306 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); 2307 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1); 2308 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2); 2309 2310 if (((rdev->family) == CHIP_RV610) || 2311 ((rdev->family) == CHIP_RV620) || 2312 ((rdev->family) == CHIP_RS780) || 2313 ((rdev->family) == CHIP_RS880)) { 2314 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY)); 2315 } else { 2316 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC)); 2317 } 2318 2319 /* More default values. 2D/3D driver should adjust as needed */ 2320 WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) | 2321 S1_X(0x4) | S1_Y(0xc))); 2322 WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) | 2323 S1_X(0x2) | S1_Y(0x2) | 2324 S2_X(0xa) | S2_Y(0x6) | 2325 S3_X(0x6) | S3_Y(0xaU))); 2326 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) | 2327 S1_X(0x4) | S1_Y(0xc) | 2328 S2_X(0x1) | S2_Y(0x6) | 2329 S3_X(0xa) | S3_Y(0xeU))); 2330 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) | 2331 S5_X(0x0) | S5_Y(0x0) | 2332 S6_X(0xb) | S6_Y(0x4) | 2333 S7_X(0x7) | S7_Y(0x8U))); 2334 2335 WREG32(VGT_STRMOUT_EN, 0); 2336 tmp = rdev->config.r600.max_pipes * 16; 2337 switch (rdev->family) { 2338 case CHIP_RV610: 2339 case CHIP_RV620: 2340 case CHIP_RS780: 2341 case CHIP_RS880: 2342 tmp += 32; 2343 break; 2344 case CHIP_RV670: 2345 tmp += 128; 2346 break; 2347 default: 2348 break; 2349 } 2350 if (tmp > 256) { 2351 tmp = 256; 2352 } 2353 WREG32(VGT_ES_PER_GS, 128); 2354 WREG32(VGT_GS_PER_ES, tmp); 2355 WREG32(VGT_GS_PER_VS, 2); 2356 WREG32(VGT_GS_VERTEX_REUSE, 16); 2357 2358 /* more default values. 2D/3D driver should adjust as needed */ 2359 WREG32(PA_SC_LINE_STIPPLE_STATE, 0); 2360 WREG32(VGT_STRMOUT_EN, 0); 2361 WREG32(SX_MISC, 0); 2362 WREG32(PA_SC_MODE_CNTL, 0); 2363 WREG32(PA_SC_AA_CONFIG, 0); 2364 WREG32(PA_SC_LINE_STIPPLE, 0); 2365 WREG32(SPI_INPUT_Z, 0); 2366 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2)); 2367 WREG32(CB_COLOR7_FRAG, 0); 2368 2369 /* Clear render buffer base addresses */ 2370 WREG32(CB_COLOR0_BASE, 0); 2371 WREG32(CB_COLOR1_BASE, 0); 2372 WREG32(CB_COLOR2_BASE, 0); 2373 WREG32(CB_COLOR3_BASE, 0); 2374 WREG32(CB_COLOR4_BASE, 0); 2375 WREG32(CB_COLOR5_BASE, 0); 2376 WREG32(CB_COLOR6_BASE, 0); 2377 WREG32(CB_COLOR7_BASE, 0); 2378 WREG32(CB_COLOR7_FRAG, 0); 2379 2380 switch (rdev->family) { 2381 case CHIP_RV610: 2382 case CHIP_RV620: 2383 case CHIP_RS780: 2384 case CHIP_RS880: 2385 tmp = TC_L2_SIZE(8); 2386 break; 2387 case CHIP_RV630: 2388 case CHIP_RV635: 2389 tmp = TC_L2_SIZE(4); 2390 break; 2391 case CHIP_R600: 2392 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT; 2393 break; 2394 default: 2395 tmp = TC_L2_SIZE(0); 2396 break; 2397 } 2398 WREG32(TC_CNTL, tmp); 2399 2400 tmp = RREG32(HDP_HOST_PATH_CNTL); 2401 WREG32(HDP_HOST_PATH_CNTL, tmp); 2402 2403 tmp = RREG32(ARB_POP); 2404 tmp |= ENABLE_TC128; 2405 WREG32(ARB_POP, tmp); 2406 2407 WREG32(PA_SC_MULTI_CHIP_CNTL, 0); 2408 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA | 2409 NUM_CLIP_SEQ(3))); 2410 WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095)); 2411 WREG32(VC_ENHANCE, 0); 2412 } 2413 2414 2415 /* 2416 * Indirect registers accessor 2417 */ 2418 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg) 2419 { 2420 unsigned long flags; 2421 u32 r; 2422 2423 spin_lock_irqsave(&rdev->pciep_idx_lock, flags); 2424 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); 2425 (void)RREG32(PCIE_PORT_INDEX); 2426 r = RREG32(PCIE_PORT_DATA); 2427 spin_unlock_irqrestore(&rdev->pciep_idx_lock, flags); 2428 return r; 2429 } 2430 2431 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2432 { 2433 unsigned long flags; 2434 2435 spin_lock_irqsave(&rdev->pciep_idx_lock, flags); 2436 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); 2437 (void)RREG32(PCIE_PORT_INDEX); 2438 WREG32(PCIE_PORT_DATA, (v)); 2439 (void)RREG32(PCIE_PORT_DATA); 2440 spin_unlock_irqrestore(&rdev->pciep_idx_lock, flags); 2441 } 2442 2443 /* 2444 * CP & Ring 2445 */ 2446 void r600_cp_stop(struct radeon_device *rdev) 2447 { 2448 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX) 2449 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 2450 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); 2451 WREG32(SCRATCH_UMSK, 0); 2452 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; 2453 } 2454 2455 int r600_init_microcode(struct radeon_device *rdev) 2456 { 2457 const char *chip_name; 2458 const char *rlc_chip_name; 2459 const char *smc_chip_name = "RV770"; 2460 size_t pfp_req_size, me_req_size, rlc_req_size, smc_req_size = 0; 2461 char fw_name[30]; 2462 int err; 2463 2464 DRM_DEBUG("\n"); 2465 2466 switch (rdev->family) { 2467 case CHIP_R600: 2468 chip_name = "R600"; 2469 rlc_chip_name = "R600"; 2470 break; 2471 case CHIP_RV610: 2472 chip_name = "RV610"; 2473 rlc_chip_name = "R600"; 2474 break; 2475 case CHIP_RV630: 2476 chip_name = "RV630"; 2477 rlc_chip_name = "R600"; 2478 break; 2479 case CHIP_RV620: 2480 chip_name = "RV620"; 2481 rlc_chip_name = "R600"; 2482 break; 2483 case CHIP_RV635: 2484 chip_name = "RV635"; 2485 rlc_chip_name = "R600"; 2486 break; 2487 case CHIP_RV670: 2488 chip_name = "RV670"; 2489 rlc_chip_name = "R600"; 2490 break; 2491 case CHIP_RS780: 2492 case CHIP_RS880: 2493 chip_name = "RS780"; 2494 rlc_chip_name = "R600"; 2495 break; 2496 case CHIP_RV770: 2497 chip_name = "RV770"; 2498 rlc_chip_name = "R700"; 2499 smc_chip_name = "RV770"; 2500 smc_req_size = ALIGN(RV770_SMC_UCODE_SIZE, 4); 2501 break; 2502 case CHIP_RV730: 2503 chip_name = "RV730"; 2504 rlc_chip_name = "R700"; 2505 smc_chip_name = "RV730"; 2506 smc_req_size = ALIGN(RV730_SMC_UCODE_SIZE, 4); 2507 break; 2508 case CHIP_RV710: 2509 chip_name = "RV710"; 2510 rlc_chip_name = "R700"; 2511 smc_chip_name = "RV710"; 2512 smc_req_size = ALIGN(RV710_SMC_UCODE_SIZE, 4); 2513 break; 2514 case CHIP_RV740: 2515 chip_name = "RV730"; 2516 rlc_chip_name = "R700"; 2517 smc_chip_name = "RV740"; 2518 smc_req_size = ALIGN(RV740_SMC_UCODE_SIZE, 4); 2519 break; 2520 case CHIP_CEDAR: 2521 chip_name = "CEDAR"; 2522 rlc_chip_name = "CEDAR"; 2523 smc_chip_name = "CEDAR"; 2524 smc_req_size = ALIGN(CEDAR_SMC_UCODE_SIZE, 4); 2525 break; 2526 case CHIP_REDWOOD: 2527 chip_name = "REDWOOD"; 2528 rlc_chip_name = "REDWOOD"; 2529 smc_chip_name = "REDWOOD"; 2530 smc_req_size = ALIGN(REDWOOD_SMC_UCODE_SIZE, 4); 2531 break; 2532 case CHIP_JUNIPER: 2533 chip_name = "JUNIPER"; 2534 rlc_chip_name = "JUNIPER"; 2535 smc_chip_name = "JUNIPER"; 2536 smc_req_size = ALIGN(JUNIPER_SMC_UCODE_SIZE, 4); 2537 break; 2538 case CHIP_CYPRESS: 2539 case CHIP_HEMLOCK: 2540 chip_name = "CYPRESS"; 2541 rlc_chip_name = "CYPRESS"; 2542 smc_chip_name = "CYPRESS"; 2543 smc_req_size = ALIGN(CYPRESS_SMC_UCODE_SIZE, 4); 2544 break; 2545 case CHIP_PALM: 2546 chip_name = "PALM"; 2547 rlc_chip_name = "SUMO"; 2548 break; 2549 case CHIP_SUMO: 2550 chip_name = "SUMO"; 2551 rlc_chip_name = "SUMO"; 2552 break; 2553 case CHIP_SUMO2: 2554 chip_name = "SUMO2"; 2555 rlc_chip_name = "SUMO"; 2556 break; 2557 default: BUG(); 2558 } 2559 2560 if (rdev->family >= CHIP_CEDAR) { 2561 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4; 2562 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4; 2563 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4; 2564 } else if (rdev->family >= CHIP_RV770) { 2565 pfp_req_size = R700_PFP_UCODE_SIZE * 4; 2566 me_req_size = R700_PM4_UCODE_SIZE * 4; 2567 rlc_req_size = R700_RLC_UCODE_SIZE * 4; 2568 } else { 2569 pfp_req_size = R600_PFP_UCODE_SIZE * 4; 2570 me_req_size = R600_PM4_UCODE_SIZE * 12; 2571 rlc_req_size = R600_RLC_UCODE_SIZE * 4; 2572 } 2573 2574 DRM_INFO("Loading %s Microcode\n", chip_name); 2575 2576 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name); 2577 err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev); 2578 if (err) 2579 goto out; 2580 if (rdev->pfp_fw->size != pfp_req_size) { 2581 printk(KERN_ERR 2582 "r600_cp: Bogus length %zu in firmware \"%s\"\n", 2583 rdev->pfp_fw->size, fw_name); 2584 err = -EINVAL; 2585 goto out; 2586 } 2587 2588 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name); 2589 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev); 2590 if (err) 2591 goto out; 2592 if (rdev->me_fw->size != me_req_size) { 2593 printk(KERN_ERR 2594 "r600_cp: Bogus length %zu in firmware \"%s\"\n", 2595 rdev->me_fw->size, fw_name); 2596 err = -EINVAL; 2597 } 2598 2599 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name); 2600 err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev); 2601 if (err) 2602 goto out; 2603 if (rdev->rlc_fw->size != rlc_req_size) { 2604 printk(KERN_ERR 2605 "r600_rlc: Bogus length %zu in firmware \"%s\"\n", 2606 rdev->rlc_fw->size, fw_name); 2607 err = -EINVAL; 2608 } 2609 2610 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_HEMLOCK)) { 2611 snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", smc_chip_name); 2612 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev); 2613 if (err) { 2614 printk(KERN_ERR 2615 "smc: error loading firmware \"%s\"\n", 2616 fw_name); 2617 release_firmware(rdev->smc_fw); 2618 rdev->smc_fw = NULL; 2619 err = 0; 2620 } else if (rdev->smc_fw->size != smc_req_size) { 2621 printk(KERN_ERR 2622 "smc: Bogus length %zu in firmware \"%s\"\n", 2623 rdev->smc_fw->size, fw_name); 2624 err = -EINVAL; 2625 } 2626 } 2627 2628 out: 2629 if (err) { 2630 if (err != -EINVAL) 2631 printk(KERN_ERR 2632 "r600_cp: Failed to load firmware \"%s\"\n", 2633 fw_name); 2634 release_firmware(rdev->pfp_fw); 2635 rdev->pfp_fw = NULL; 2636 release_firmware(rdev->me_fw); 2637 rdev->me_fw = NULL; 2638 release_firmware(rdev->rlc_fw); 2639 rdev->rlc_fw = NULL; 2640 release_firmware(rdev->smc_fw); 2641 rdev->smc_fw = NULL; 2642 } 2643 return err; 2644 } 2645 2646 u32 r600_gfx_get_rptr(struct radeon_device *rdev, 2647 struct radeon_ring *ring) 2648 { 2649 u32 rptr; 2650 2651 if (rdev->wb.enabled) 2652 rptr = rdev->wb.wb[ring->rptr_offs/4]; 2653 else 2654 rptr = RREG32(R600_CP_RB_RPTR); 2655 2656 return rptr; 2657 } 2658 2659 u32 r600_gfx_get_wptr(struct radeon_device *rdev, 2660 struct radeon_ring *ring) 2661 { 2662 u32 wptr; 2663 2664 wptr = RREG32(R600_CP_RB_WPTR); 2665 2666 return wptr; 2667 } 2668 2669 void r600_gfx_set_wptr(struct radeon_device *rdev, 2670 struct radeon_ring *ring) 2671 { 2672 WREG32(R600_CP_RB_WPTR, ring->wptr); 2673 (void)RREG32(R600_CP_RB_WPTR); 2674 } 2675 2676 static int r600_cp_load_microcode(struct radeon_device *rdev) 2677 { 2678 const __be32 *fw_data; 2679 int i; 2680 2681 if (!rdev->me_fw || !rdev->pfp_fw) 2682 return -EINVAL; 2683 2684 r600_cp_stop(rdev); 2685 2686 WREG32(CP_RB_CNTL, 2687 #ifdef __BIG_ENDIAN 2688 BUF_SWAP_32BIT | 2689 #endif 2690 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); 2691 2692 /* Reset cp */ 2693 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); 2694 RREG32(GRBM_SOFT_RESET); 2695 mdelay(15); 2696 WREG32(GRBM_SOFT_RESET, 0); 2697 2698 WREG32(CP_ME_RAM_WADDR, 0); 2699 2700 fw_data = (const __be32 *)rdev->me_fw->data; 2701 WREG32(CP_ME_RAM_WADDR, 0); 2702 for (i = 0; i < R600_PM4_UCODE_SIZE * 3; i++) 2703 WREG32(CP_ME_RAM_DATA, 2704 be32_to_cpup(fw_data++)); 2705 2706 fw_data = (const __be32 *)rdev->pfp_fw->data; 2707 WREG32(CP_PFP_UCODE_ADDR, 0); 2708 for (i = 0; i < R600_PFP_UCODE_SIZE; i++) 2709 WREG32(CP_PFP_UCODE_DATA, 2710 be32_to_cpup(fw_data++)); 2711 2712 WREG32(CP_PFP_UCODE_ADDR, 0); 2713 WREG32(CP_ME_RAM_WADDR, 0); 2714 WREG32(CP_ME_RAM_RADDR, 0); 2715 return 0; 2716 } 2717 2718 int r600_cp_start(struct radeon_device *rdev) 2719 { 2720 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2721 int r; 2722 uint32_t cp_me; 2723 2724 r = radeon_ring_lock(rdev, ring, 7); 2725 if (r) { 2726 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); 2727 return r; 2728 } 2729 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); 2730 radeon_ring_write(ring, 0x1); 2731 if (rdev->family >= CHIP_RV770) { 2732 radeon_ring_write(ring, 0x0); 2733 radeon_ring_write(ring, rdev->config.rv770.max_hw_contexts - 1); 2734 } else { 2735 radeon_ring_write(ring, 0x3); 2736 radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1); 2737 } 2738 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); 2739 radeon_ring_write(ring, 0); 2740 radeon_ring_write(ring, 0); 2741 radeon_ring_unlock_commit(rdev, ring, false); 2742 2743 cp_me = 0xff; 2744 WREG32(R_0086D8_CP_ME_CNTL, cp_me); 2745 return 0; 2746 } 2747 2748 int r600_cp_resume(struct radeon_device *rdev) 2749 { 2750 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2751 u32 tmp; 2752 u32 rb_bufsz; 2753 int r; 2754 2755 /* Reset cp */ 2756 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); 2757 RREG32(GRBM_SOFT_RESET); 2758 mdelay(15); 2759 WREG32(GRBM_SOFT_RESET, 0); 2760 2761 /* Set ring buffer size */ 2762 rb_bufsz = order_base_2(ring->ring_size / 8); 2763 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 2764 #ifdef __BIG_ENDIAN 2765 tmp |= BUF_SWAP_32BIT; 2766 #endif 2767 WREG32(CP_RB_CNTL, tmp); 2768 WREG32(CP_SEM_WAIT_TIMER, 0x0); 2769 2770 /* Set the write pointer delay */ 2771 WREG32(CP_RB_WPTR_DELAY, 0); 2772 2773 /* Initialize the ring buffer's read and write pointers */ 2774 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA); 2775 WREG32(CP_RB_RPTR_WR, 0); 2776 ring->wptr = 0; 2777 WREG32(CP_RB_WPTR, ring->wptr); 2778 2779 /* set the wb address whether it's enabled or not */ 2780 WREG32(CP_RB_RPTR_ADDR, 2781 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC)); 2782 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); 2783 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); 2784 2785 if (rdev->wb.enabled) 2786 WREG32(SCRATCH_UMSK, 0xff); 2787 else { 2788 tmp |= RB_NO_UPDATE; 2789 WREG32(SCRATCH_UMSK, 0); 2790 } 2791 2792 mdelay(1); 2793 WREG32(CP_RB_CNTL, tmp); 2794 2795 WREG32(CP_RB_BASE, ring->gpu_addr >> 8); 2796 WREG32(CP_DEBUG, (1 << 27) | (1 << 28)); 2797 2798 r600_cp_start(rdev); 2799 ring->ready = true; 2800 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring); 2801 if (r) { 2802 ring->ready = false; 2803 return r; 2804 } 2805 2806 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX) 2807 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); 2808 2809 return 0; 2810 } 2811 2812 void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size) 2813 { 2814 u32 rb_bufsz; 2815 int r; 2816 2817 /* Align ring size */ 2818 rb_bufsz = order_base_2(ring_size / 8); 2819 ring_size = (1 << (rb_bufsz + 1)) * 4; 2820 ring->ring_size = ring_size; 2821 ring->align_mask = 16 - 1; 2822 2823 if (radeon_ring_supports_scratch_reg(rdev, ring)) { 2824 r = radeon_scratch_get(rdev, &ring->rptr_save_reg); 2825 if (r) { 2826 DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r); 2827 ring->rptr_save_reg = 0; 2828 } 2829 } 2830 } 2831 2832 void r600_cp_fini(struct radeon_device *rdev) 2833 { 2834 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2835 r600_cp_stop(rdev); 2836 radeon_ring_fini(rdev, ring); 2837 radeon_scratch_free(rdev, ring->rptr_save_reg); 2838 } 2839 2840 /* 2841 * GPU scratch registers helpers function. 2842 */ 2843 void r600_scratch_init(struct radeon_device *rdev) 2844 { 2845 int i; 2846 2847 rdev->scratch.num_reg = 7; 2848 rdev->scratch.reg_base = SCRATCH_REG0; 2849 for (i = 0; i < rdev->scratch.num_reg; i++) { 2850 rdev->scratch.free[i] = true; 2851 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4); 2852 } 2853 } 2854 2855 int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *ring) 2856 { 2857 uint32_t scratch; 2858 uint32_t tmp = 0; 2859 unsigned i; 2860 int r; 2861 2862 r = radeon_scratch_get(rdev, &scratch); 2863 if (r) { 2864 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r); 2865 return r; 2866 } 2867 WREG32(scratch, 0xCAFEDEAD); 2868 r = radeon_ring_lock(rdev, ring, 3); 2869 if (r) { 2870 DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", ring->idx, r); 2871 radeon_scratch_free(rdev, scratch); 2872 return r; 2873 } 2874 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2875 radeon_ring_write(ring, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); 2876 radeon_ring_write(ring, 0xDEADBEEF); 2877 radeon_ring_unlock_commit(rdev, ring, false); 2878 for (i = 0; i < rdev->usec_timeout; i++) { 2879 tmp = RREG32(scratch); 2880 if (tmp == 0xDEADBEEF) 2881 break; 2882 DRM_UDELAY(1); 2883 } 2884 if (i < rdev->usec_timeout) { 2885 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); 2886 } else { 2887 DRM_ERROR("radeon: ring %d test failed (scratch(0x%04X)=0x%08X)\n", 2888 ring->idx, scratch, tmp); 2889 r = -EINVAL; 2890 } 2891 radeon_scratch_free(rdev, scratch); 2892 return r; 2893 } 2894 2895 /* 2896 * CP fences/semaphores 2897 */ 2898 2899 void r600_fence_ring_emit(struct radeon_device *rdev, 2900 struct radeon_fence *fence) 2901 { 2902 struct radeon_ring *ring = &rdev->ring[fence->ring]; 2903 u32 cp_coher_cntl = PACKET3_TC_ACTION_ENA | PACKET3_VC_ACTION_ENA | 2904 PACKET3_SH_ACTION_ENA; 2905 2906 if (rdev->family >= CHIP_RV770) 2907 cp_coher_cntl |= PACKET3_FULL_CACHE_ENA; 2908 2909 if (rdev->wb.use_event) { 2910 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; 2911 /* flush read cache over gart */ 2912 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 2913 radeon_ring_write(ring, cp_coher_cntl); 2914 radeon_ring_write(ring, 0xFFFFFFFF); 2915 radeon_ring_write(ring, 0); 2916 radeon_ring_write(ring, 10); /* poll interval */ 2917 /* EVENT_WRITE_EOP - flush caches, send int */ 2918 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); 2919 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5)); 2920 radeon_ring_write(ring, lower_32_bits(addr)); 2921 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); 2922 radeon_ring_write(ring, fence->seq); 2923 radeon_ring_write(ring, 0); 2924 } else { 2925 /* flush read cache over gart */ 2926 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 2927 radeon_ring_write(ring, cp_coher_cntl); 2928 radeon_ring_write(ring, 0xFFFFFFFF); 2929 radeon_ring_write(ring, 0); 2930 radeon_ring_write(ring, 10); /* poll interval */ 2931 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); 2932 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0)); 2933 /* wait for 3D idle clean */ 2934 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2935 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); 2936 radeon_ring_write(ring, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit); 2937 /* Emit fence sequence & fire IRQ */ 2938 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2939 radeon_ring_write(ring, ((rdev->fence_drv[fence->ring].scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); 2940 radeon_ring_write(ring, fence->seq); 2941 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */ 2942 radeon_ring_write(ring, PACKET0(CP_INT_STATUS, 0)); 2943 radeon_ring_write(ring, RB_INT_STAT); 2944 } 2945 } 2946 2947 /** 2948 * r600_semaphore_ring_emit - emit a semaphore on the CP ring 2949 * 2950 * @rdev: radeon_device pointer 2951 * @ring: radeon ring buffer object 2952 * @semaphore: radeon semaphore object 2953 * @emit_wait: Is this a sempahore wait? 2954 * 2955 * Emits a semaphore signal/wait packet to the CP ring and prevents the PFP 2956 * from running ahead of semaphore waits. 2957 */ 2958 bool r600_semaphore_ring_emit(struct radeon_device *rdev, 2959 struct radeon_ring *ring, 2960 struct radeon_semaphore *semaphore, 2961 bool emit_wait) 2962 { 2963 uint64_t addr = semaphore->gpu_addr; 2964 unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL; 2965 2966 if (rdev->family < CHIP_CAYMAN) 2967 sel |= PACKET3_SEM_WAIT_ON_SIGNAL; 2968 2969 radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1)); 2970 radeon_ring_write(ring, lower_32_bits(addr)); 2971 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel); 2972 2973 /* PFP_SYNC_ME packet only exists on 7xx+, only enable it on eg+ */ 2974 if (emit_wait && (rdev->family >= CHIP_CEDAR)) { 2975 /* Prevent the PFP from running ahead of the semaphore wait */ 2976 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 2977 radeon_ring_write(ring, 0x0); 2978 } 2979 2980 return true; 2981 } 2982 2983 /** 2984 * r600_copy_cpdma - copy pages using the CP DMA engine 2985 * 2986 * @rdev: radeon_device pointer 2987 * @src_offset: src GPU address 2988 * @dst_offset: dst GPU address 2989 * @num_gpu_pages: number of GPU pages to xfer 2990 * @fence: radeon fence object 2991 * 2992 * Copy GPU paging using the CP DMA engine (r6xx+). 2993 * Used by the radeon ttm implementation to move pages if 2994 * registered as the asic copy callback. 2995 */ 2996 struct radeon_fence *r600_copy_cpdma(struct radeon_device *rdev, 2997 uint64_t src_offset, uint64_t dst_offset, 2998 unsigned num_gpu_pages, 2999 struct reservation_object *resv) 3000 { 3001 struct radeon_fence *fence; 3002 struct radeon_sync sync; 3003 int ring_index = rdev->asic->copy.blit_ring_index; 3004 struct radeon_ring *ring = &rdev->ring[ring_index]; 3005 u32 size_in_bytes, cur_size_in_bytes, tmp; 3006 int i, num_loops; 3007 int r = 0; 3008 3009 radeon_sync_create(&sync); 3010 3011 size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT); 3012 num_loops = DIV_ROUND_UP(size_in_bytes, 0x1fffff); 3013 r = radeon_ring_lock(rdev, ring, num_loops * 6 + 24); 3014 if (r) { 3015 DRM_ERROR("radeon: moving bo (%d).\n", r); 3016 radeon_sync_free(rdev, &sync, NULL); 3017 return ERR_PTR(r); 3018 } 3019 3020 radeon_sync_resv(rdev, &sync, resv, false); 3021 radeon_sync_rings(rdev, &sync, ring->idx); 3022 3023 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 3024 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); 3025 radeon_ring_write(ring, WAIT_3D_IDLE_bit); 3026 for (i = 0; i < num_loops; i++) { 3027 cur_size_in_bytes = size_in_bytes; 3028 if (cur_size_in_bytes > 0x1fffff) 3029 cur_size_in_bytes = 0x1fffff; 3030 size_in_bytes -= cur_size_in_bytes; 3031 tmp = upper_32_bits(src_offset) & 0xff; 3032 if (size_in_bytes == 0) 3033 tmp |= PACKET3_CP_DMA_CP_SYNC; 3034 radeon_ring_write(ring, PACKET3(PACKET3_CP_DMA, 4)); 3035 radeon_ring_write(ring, lower_32_bits(src_offset)); 3036 radeon_ring_write(ring, tmp); 3037 radeon_ring_write(ring, lower_32_bits(dst_offset)); 3038 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff); 3039 radeon_ring_write(ring, cur_size_in_bytes); 3040 src_offset += cur_size_in_bytes; 3041 dst_offset += cur_size_in_bytes; 3042 } 3043 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 3044 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); 3045 radeon_ring_write(ring, WAIT_CP_DMA_IDLE_bit); 3046 3047 r = radeon_fence_emit(rdev, &fence, ring->idx); 3048 if (r) { 3049 radeon_ring_unlock_undo(rdev, ring); 3050 radeon_sync_free(rdev, &sync, NULL); 3051 return ERR_PTR(r); 3052 } 3053 3054 radeon_ring_unlock_commit(rdev, ring, false); 3055 radeon_sync_free(rdev, &sync, fence); 3056 3057 return fence; 3058 } 3059 3060 int r600_set_surface_reg(struct radeon_device *rdev, int reg, 3061 uint32_t tiling_flags, uint32_t pitch, 3062 uint32_t offset, uint32_t obj_size) 3063 { 3064 /* FIXME: implement */ 3065 return 0; 3066 } 3067 3068 void r600_clear_surface_reg(struct radeon_device *rdev, int reg) 3069 { 3070 /* FIXME: implement */ 3071 } 3072 3073 static int r600_startup(struct radeon_device *rdev) 3074 { 3075 struct radeon_ring *ring; 3076 int r; 3077 3078 /* enable pcie gen2 link */ 3079 r600_pcie_gen2_enable(rdev); 3080 3081 /* scratch needs to be initialized before MC */ 3082 r = r600_vram_scratch_init(rdev); 3083 if (r) 3084 return r; 3085 3086 r600_mc_program(rdev); 3087 3088 if (rdev->flags & RADEON_IS_AGP) { 3089 r600_agp_enable(rdev); 3090 } else { 3091 r = r600_pcie_gart_enable(rdev); 3092 if (r) 3093 return r; 3094 } 3095 r600_gpu_init(rdev); 3096 3097 /* allocate wb buffer */ 3098 r = radeon_wb_init(rdev); 3099 if (r) 3100 return r; 3101 3102 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 3103 if (r) { 3104 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 3105 return r; 3106 } 3107 3108 if (rdev->has_uvd) { 3109 r = uvd_v1_0_resume(rdev); 3110 if (!r) { 3111 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_UVD_INDEX); 3112 if (r) { 3113 dev_err(rdev->dev, "failed initializing UVD fences (%d).\n", r); 3114 } 3115 } 3116 if (r) 3117 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0; 3118 } 3119 3120 /* Enable IRQ */ 3121 if (!rdev->irq.installed) { 3122 r = radeon_irq_kms_init(rdev); 3123 if (r) 3124 return r; 3125 } 3126 3127 r = r600_irq_init(rdev); 3128 if (r) { 3129 DRM_ERROR("radeon: IH init failed (%d).\n", r); 3130 radeon_irq_kms_fini(rdev); 3131 return r; 3132 } 3133 r600_irq_set(rdev); 3134 3135 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 3136 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, 3137 RADEON_CP_PACKET2); 3138 if (r) 3139 return r; 3140 3141 r = r600_cp_load_microcode(rdev); 3142 if (r) 3143 return r; 3144 r = r600_cp_resume(rdev); 3145 if (r) 3146 return r; 3147 3148 if (rdev->has_uvd) { 3149 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; 3150 if (ring->ring_size) { 3151 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, 3152 RADEON_CP_PACKET2); 3153 if (!r) 3154 r = uvd_v1_0_init(rdev); 3155 if (r) 3156 DRM_ERROR("radeon: failed initializing UVD (%d).\n", r); 3157 } 3158 } 3159 3160 r = radeon_ib_pool_init(rdev); 3161 if (r) { 3162 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 3163 return r; 3164 } 3165 3166 r = radeon_audio_init(rdev); 3167 if (r) { 3168 DRM_ERROR("radeon: audio init failed\n"); 3169 return r; 3170 } 3171 3172 return 0; 3173 } 3174 3175 void r600_vga_set_state(struct radeon_device *rdev, bool state) 3176 { 3177 uint32_t temp; 3178 3179 temp = RREG32(CONFIG_CNTL); 3180 if (state == false) { 3181 temp &= ~(1<<0); 3182 temp |= (1<<1); 3183 } else { 3184 temp &= ~(1<<1); 3185 } 3186 WREG32(CONFIG_CNTL, temp); 3187 } 3188 3189 int r600_resume(struct radeon_device *rdev) 3190 { 3191 int r; 3192 3193 /* Do not reset GPU before posting, on r600 hw unlike on r500 hw, 3194 * posting will perform necessary task to bring back GPU into good 3195 * shape. 3196 */ 3197 /* post card */ 3198 atom_asic_init(rdev->mode_info.atom_context); 3199 3200 if (rdev->pm.pm_method == PM_METHOD_DPM) 3201 radeon_pm_resume(rdev); 3202 3203 rdev->accel_working = true; 3204 r = r600_startup(rdev); 3205 if (r) { 3206 DRM_ERROR("r600 startup failed on resume\n"); 3207 rdev->accel_working = false; 3208 return r; 3209 } 3210 3211 return r; 3212 } 3213 3214 int r600_suspend(struct radeon_device *rdev) 3215 { 3216 radeon_pm_suspend(rdev); 3217 radeon_audio_fini(rdev); 3218 r600_cp_stop(rdev); 3219 if (rdev->has_uvd) { 3220 uvd_v1_0_fini(rdev); 3221 radeon_uvd_suspend(rdev); 3222 } 3223 r600_irq_suspend(rdev); 3224 radeon_wb_disable(rdev); 3225 r600_pcie_gart_disable(rdev); 3226 3227 return 0; 3228 } 3229 3230 /* Plan is to move initialization in that function and use 3231 * helper function so that radeon_device_init pretty much 3232 * do nothing more than calling asic specific function. This 3233 * should also allow to remove a bunch of callback function 3234 * like vram_info. 3235 */ 3236 int r600_init(struct radeon_device *rdev) 3237 { 3238 int r; 3239 3240 if (r600_debugfs_mc_info_init(rdev)) { 3241 DRM_ERROR("Failed to register debugfs file for mc !\n"); 3242 } 3243 /* Read BIOS */ 3244 if (!radeon_get_bios(rdev)) { 3245 if (ASIC_IS_AVIVO(rdev)) 3246 return -EINVAL; 3247 } 3248 /* Must be an ATOMBIOS */ 3249 if (!rdev->is_atom_bios) { 3250 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n"); 3251 return -EINVAL; 3252 } 3253 r = radeon_atombios_init(rdev); 3254 if (r) 3255 return r; 3256 /* Post card if necessary */ 3257 if (!radeon_card_posted(rdev)) { 3258 if (!rdev->bios) { 3259 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); 3260 return -EINVAL; 3261 } 3262 DRM_INFO("GPU not posted. posting now...\n"); 3263 atom_asic_init(rdev->mode_info.atom_context); 3264 } 3265 /* Initialize scratch registers */ 3266 r600_scratch_init(rdev); 3267 /* Initialize surface registers */ 3268 radeon_surface_init(rdev); 3269 /* Initialize clocks */ 3270 radeon_get_clock_info(rdev->ddev); 3271 /* Fence driver */ 3272 r = radeon_fence_driver_init(rdev); 3273 if (r) 3274 return r; 3275 if (rdev->flags & RADEON_IS_AGP) { 3276 r = radeon_agp_init(rdev); 3277 if (r) 3278 radeon_agp_disable(rdev); 3279 } 3280 r = r600_mc_init(rdev); 3281 if (r) 3282 return r; 3283 /* Memory manager */ 3284 r = radeon_bo_init(rdev); 3285 if (r) 3286 return r; 3287 3288 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { 3289 r = r600_init_microcode(rdev); 3290 if (r) { 3291 DRM_ERROR("Failed to load firmware!\n"); 3292 return r; 3293 } 3294 } 3295 3296 /* Initialize power management */ 3297 radeon_pm_init(rdev); 3298 3299 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL; 3300 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024); 3301 3302 if (rdev->has_uvd) { 3303 r = radeon_uvd_init(rdev); 3304 if (!r) { 3305 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL; 3306 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX], 4096); 3307 } 3308 } 3309 3310 rdev->ih.ring_obj = NULL; 3311 r600_ih_ring_init(rdev, 64 * 1024); 3312 3313 r = r600_pcie_gart_init(rdev); 3314 if (r) 3315 return r; 3316 3317 rdev->accel_working = true; 3318 r = r600_startup(rdev); 3319 if (r) { 3320 dev_err(rdev->dev, "disabling GPU acceleration\n"); 3321 r600_cp_fini(rdev); 3322 r600_irq_fini(rdev); 3323 radeon_wb_fini(rdev); 3324 radeon_ib_pool_fini(rdev); 3325 radeon_irq_kms_fini(rdev); 3326 r600_pcie_gart_fini(rdev); 3327 rdev->accel_working = false; 3328 } 3329 3330 return 0; 3331 } 3332 3333 void r600_fini(struct radeon_device *rdev) 3334 { 3335 radeon_pm_fini(rdev); 3336 radeon_audio_fini(rdev); 3337 r600_cp_fini(rdev); 3338 r600_irq_fini(rdev); 3339 if (rdev->has_uvd) { 3340 uvd_v1_0_fini(rdev); 3341 radeon_uvd_fini(rdev); 3342 } 3343 radeon_wb_fini(rdev); 3344 radeon_ib_pool_fini(rdev); 3345 radeon_irq_kms_fini(rdev); 3346 r600_pcie_gart_fini(rdev); 3347 r600_vram_scratch_fini(rdev); 3348 radeon_agp_fini(rdev); 3349 radeon_gem_fini(rdev); 3350 radeon_fence_driver_fini(rdev); 3351 radeon_bo_fini(rdev); 3352 radeon_atombios_fini(rdev); 3353 kfree(rdev->bios); 3354 rdev->bios = NULL; 3355 } 3356 3357 3358 /* 3359 * CS stuff 3360 */ 3361 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) 3362 { 3363 struct radeon_ring *ring = &rdev->ring[ib->ring]; 3364 u32 next_rptr; 3365 3366 if (ring->rptr_save_reg) { 3367 next_rptr = ring->wptr + 3 + 4; 3368 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 3369 radeon_ring_write(ring, ((ring->rptr_save_reg - 3370 PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); 3371 radeon_ring_write(ring, next_rptr); 3372 } else if (rdev->wb.enabled) { 3373 next_rptr = ring->wptr + 5 + 4; 3374 radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3)); 3375 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); 3376 radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18)); 3377 radeon_ring_write(ring, next_rptr); 3378 radeon_ring_write(ring, 0); 3379 } 3380 3381 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 3382 radeon_ring_write(ring, 3383 #ifdef __BIG_ENDIAN 3384 (2 << 0) | 3385 #endif 3386 (ib->gpu_addr & 0xFFFFFFFC)); 3387 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF); 3388 radeon_ring_write(ring, ib->length_dw); 3389 } 3390 3391 int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) 3392 { 3393 struct radeon_ib ib; 3394 uint32_t scratch; 3395 uint32_t tmp = 0; 3396 unsigned i; 3397 int r; 3398 3399 r = radeon_scratch_get(rdev, &scratch); 3400 if (r) { 3401 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r); 3402 return r; 3403 } 3404 WREG32(scratch, 0xCAFEDEAD); 3405 r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256); 3406 if (r) { 3407 DRM_ERROR("radeon: failed to get ib (%d).\n", r); 3408 goto free_scratch; 3409 } 3410 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1); 3411 ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); 3412 ib.ptr[2] = 0xDEADBEEF; 3413 ib.length_dw = 3; 3414 r = radeon_ib_schedule(rdev, &ib, NULL, false); 3415 if (r) { 3416 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); 3417 goto free_ib; 3418 } 3419 r = radeon_fence_wait(ib.fence, false); 3420 if (r) { 3421 DRM_ERROR("radeon: fence wait failed (%d).\n", r); 3422 goto free_ib; 3423 } 3424 for (i = 0; i < rdev->usec_timeout; i++) { 3425 tmp = RREG32(scratch); 3426 if (tmp == 0xDEADBEEF) 3427 break; 3428 DRM_UDELAY(1); 3429 } 3430 if (i < rdev->usec_timeout) { 3431 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i); 3432 } else { 3433 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n", 3434 scratch, tmp); 3435 r = -EINVAL; 3436 } 3437 free_ib: 3438 radeon_ib_free(rdev, &ib); 3439 free_scratch: 3440 radeon_scratch_free(rdev, scratch); 3441 return r; 3442 } 3443 3444 /* 3445 * Interrupts 3446 * 3447 * Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty 3448 * the same as the CP ring buffer, but in reverse. Rather than the CPU 3449 * writing to the ring and the GPU consuming, the GPU writes to the ring 3450 * and host consumes. As the host irq handler processes interrupts, it 3451 * increments the rptr. When the rptr catches up with the wptr, all the 3452 * current interrupts have been processed. 3453 */ 3454 3455 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size) 3456 { 3457 u32 rb_bufsz; 3458 3459 /* Align ring size */ 3460 rb_bufsz = order_base_2(ring_size / 4); 3461 ring_size = (1 << rb_bufsz) * 4; 3462 rdev->ih.ring_size = ring_size; 3463 rdev->ih.ptr_mask = rdev->ih.ring_size - 1; 3464 rdev->ih.rptr = 0; 3465 } 3466 3467 int r600_ih_ring_alloc(struct radeon_device *rdev) 3468 { 3469 int r; 3470 3471 /* Allocate ring buffer */ 3472 if (rdev->ih.ring_obj == NULL) { 3473 r = radeon_bo_create(rdev, rdev->ih.ring_size, 3474 PAGE_SIZE, true, 3475 RADEON_GEM_DOMAIN_GTT, 0, 3476 NULL, NULL, &rdev->ih.ring_obj); 3477 if (r) { 3478 DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r); 3479 return r; 3480 } 3481 r = radeon_bo_reserve(rdev->ih.ring_obj, false); 3482 if (unlikely(r != 0)) 3483 return r; 3484 r = radeon_bo_pin(rdev->ih.ring_obj, 3485 RADEON_GEM_DOMAIN_GTT, 3486 &rdev->ih.gpu_addr); 3487 if (r) { 3488 radeon_bo_unreserve(rdev->ih.ring_obj); 3489 DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r); 3490 return r; 3491 } 3492 r = radeon_bo_kmap(rdev->ih.ring_obj, 3493 (void **)__UNVOLATILE(&rdev->ih.ring)); 3494 radeon_bo_unreserve(rdev->ih.ring_obj); 3495 if (r) { 3496 DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r); 3497 return r; 3498 } 3499 } 3500 return 0; 3501 } 3502 3503 void r600_ih_ring_fini(struct radeon_device *rdev) 3504 { 3505 int r; 3506 if (rdev->ih.ring_obj) { 3507 r = radeon_bo_reserve(rdev->ih.ring_obj, false); 3508 if (likely(r == 0)) { 3509 radeon_bo_kunmap(rdev->ih.ring_obj); 3510 radeon_bo_unpin(rdev->ih.ring_obj); 3511 radeon_bo_unreserve(rdev->ih.ring_obj); 3512 } 3513 radeon_bo_unref(&rdev->ih.ring_obj); 3514 rdev->ih.ring = NULL; 3515 rdev->ih.ring_obj = NULL; 3516 } 3517 } 3518 3519 void r600_rlc_stop(struct radeon_device *rdev) 3520 { 3521 3522 if ((rdev->family >= CHIP_RV770) && 3523 (rdev->family <= CHIP_RV740)) { 3524 /* r7xx asics need to soft reset RLC before halting */ 3525 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC); 3526 RREG32(SRBM_SOFT_RESET); 3527 mdelay(15); 3528 WREG32(SRBM_SOFT_RESET, 0); 3529 RREG32(SRBM_SOFT_RESET); 3530 } 3531 3532 WREG32(RLC_CNTL, 0); 3533 } 3534 3535 static void r600_rlc_start(struct radeon_device *rdev) 3536 { 3537 WREG32(RLC_CNTL, RLC_ENABLE); 3538 } 3539 3540 static int r600_rlc_resume(struct radeon_device *rdev) 3541 { 3542 u32 i; 3543 const __be32 *fw_data; 3544 3545 if (!rdev->rlc_fw) 3546 return -EINVAL; 3547 3548 r600_rlc_stop(rdev); 3549 3550 WREG32(RLC_HB_CNTL, 0); 3551 3552 WREG32(RLC_HB_BASE, 0); 3553 WREG32(RLC_HB_RPTR, 0); 3554 WREG32(RLC_HB_WPTR, 0); 3555 WREG32(RLC_HB_WPTR_LSB_ADDR, 0); 3556 WREG32(RLC_HB_WPTR_MSB_ADDR, 0); 3557 WREG32(RLC_MC_CNTL, 0); 3558 WREG32(RLC_UCODE_CNTL, 0); 3559 3560 fw_data = (const __be32 *)rdev->rlc_fw->data; 3561 if (rdev->family >= CHIP_RV770) { 3562 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) { 3563 WREG32(RLC_UCODE_ADDR, i); 3564 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); 3565 } 3566 } else { 3567 for (i = 0; i < R600_RLC_UCODE_SIZE; i++) { 3568 WREG32(RLC_UCODE_ADDR, i); 3569 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); 3570 } 3571 } 3572 WREG32(RLC_UCODE_ADDR, 0); 3573 3574 r600_rlc_start(rdev); 3575 3576 return 0; 3577 } 3578 3579 static void r600_enable_interrupts(struct radeon_device *rdev) 3580 { 3581 u32 ih_cntl = RREG32(IH_CNTL); 3582 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); 3583 3584 ih_cntl |= ENABLE_INTR; 3585 ih_rb_cntl |= IH_RB_ENABLE; 3586 WREG32(IH_CNTL, ih_cntl); 3587 WREG32(IH_RB_CNTL, ih_rb_cntl); 3588 rdev->ih.enabled = true; 3589 } 3590 3591 void r600_disable_interrupts(struct radeon_device *rdev) 3592 { 3593 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); 3594 u32 ih_cntl = RREG32(IH_CNTL); 3595 3596 ih_rb_cntl &= ~IH_RB_ENABLE; 3597 ih_cntl &= ~ENABLE_INTR; 3598 WREG32(IH_RB_CNTL, ih_rb_cntl); 3599 WREG32(IH_CNTL, ih_cntl); 3600 /* set rptr, wptr to 0 */ 3601 WREG32(IH_RB_RPTR, 0); 3602 WREG32(IH_RB_WPTR, 0); 3603 rdev->ih.enabled = false; 3604 rdev->ih.rptr = 0; 3605 } 3606 3607 static void r600_disable_interrupt_state(struct radeon_device *rdev) 3608 { 3609 u32 tmp; 3610 3611 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); 3612 tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE; 3613 WREG32(DMA_CNTL, tmp); 3614 WREG32(GRBM_INT_CNTL, 0); 3615 WREG32(DxMODE_INT_MASK, 0); 3616 WREG32(D1GRPH_INTERRUPT_CONTROL, 0); 3617 WREG32(D2GRPH_INTERRUPT_CONTROL, 0); 3618 if (ASIC_IS_DCE3(rdev)) { 3619 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0); 3620 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0); 3621 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3622 WREG32(DC_HPD1_INT_CONTROL, tmp); 3623 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3624 WREG32(DC_HPD2_INT_CONTROL, tmp); 3625 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3626 WREG32(DC_HPD3_INT_CONTROL, tmp); 3627 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3628 WREG32(DC_HPD4_INT_CONTROL, tmp); 3629 if (ASIC_IS_DCE32(rdev)) { 3630 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3631 WREG32(DC_HPD5_INT_CONTROL, tmp); 3632 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3633 WREG32(DC_HPD6_INT_CONTROL, tmp); 3634 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3635 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp); 3636 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3637 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp); 3638 } else { 3639 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3640 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); 3641 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3642 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp); 3643 } 3644 } else { 3645 WREG32(DACA_AUTODETECT_INT_CONTROL, 0); 3646 WREG32(DACB_AUTODETECT_INT_CONTROL, 0); 3647 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; 3648 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); 3649 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; 3650 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); 3651 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; 3652 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); 3653 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3654 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); 3655 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3656 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp); 3657 } 3658 } 3659 3660 int r600_irq_init(struct radeon_device *rdev) 3661 { 3662 int ret = 0; 3663 int rb_bufsz; 3664 u32 interrupt_cntl, ih_cntl, ih_rb_cntl; 3665 3666 /* allocate ring */ 3667 ret = r600_ih_ring_alloc(rdev); 3668 if (ret) 3669 return ret; 3670 3671 /* disable irqs */ 3672 r600_disable_interrupts(rdev); 3673 3674 /* init rlc */ 3675 if (rdev->family >= CHIP_CEDAR) 3676 ret = evergreen_rlc_resume(rdev); 3677 else 3678 ret = r600_rlc_resume(rdev); 3679 if (ret) { 3680 r600_ih_ring_fini(rdev); 3681 return ret; 3682 } 3683 3684 /* setup interrupt control */ 3685 /* set dummy read address to ring address */ 3686 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8); 3687 interrupt_cntl = RREG32(INTERRUPT_CNTL); 3688 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi 3689 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN 3690 */ 3691 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE; 3692 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */ 3693 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN; 3694 WREG32(INTERRUPT_CNTL, interrupt_cntl); 3695 3696 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8); 3697 rb_bufsz = order_base_2(rdev->ih.ring_size / 4); 3698 3699 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE | 3700 IH_WPTR_OVERFLOW_CLEAR | 3701 (rb_bufsz << 1)); 3702 3703 if (rdev->wb.enabled) 3704 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE; 3705 3706 /* set the writeback address whether it's enabled or not */ 3707 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC); 3708 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF); 3709 3710 WREG32(IH_RB_CNTL, ih_rb_cntl); 3711 3712 /* set rptr, wptr to 0 */ 3713 WREG32(IH_RB_RPTR, 0); 3714 WREG32(IH_RB_WPTR, 0); 3715 3716 /* Default settings for IH_CNTL (disabled at first) */ 3717 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10); 3718 /* RPTR_REARM only works if msi's are enabled */ 3719 if (rdev->msi_enabled) 3720 ih_cntl |= RPTR_REARM; 3721 WREG32(IH_CNTL, ih_cntl); 3722 3723 /* force the active interrupt state to all disabled */ 3724 if (rdev->family >= CHIP_CEDAR) 3725 evergreen_disable_interrupt_state(rdev); 3726 else 3727 r600_disable_interrupt_state(rdev); 3728 3729 /* at this point everything should be setup correctly to enable master */ 3730 pci_set_master(rdev->pdev); 3731 3732 /* enable irqs */ 3733 r600_enable_interrupts(rdev); 3734 3735 return ret; 3736 } 3737 3738 void r600_irq_suspend(struct radeon_device *rdev) 3739 { 3740 r600_irq_disable(rdev); 3741 r600_rlc_stop(rdev); 3742 } 3743 3744 void r600_irq_fini(struct radeon_device *rdev) 3745 { 3746 r600_irq_suspend(rdev); 3747 r600_ih_ring_fini(rdev); 3748 } 3749 3750 int r600_irq_set(struct radeon_device *rdev) 3751 { 3752 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE; 3753 u32 mode_int = 0; 3754 u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0; 3755 u32 grbm_int_cntl = 0; 3756 u32 hdmi0, hdmi1; 3757 u32 dma_cntl; 3758 u32 thermal_int = 0; 3759 3760 if (!rdev->irq.installed) { 3761 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); 3762 return -EINVAL; 3763 } 3764 /* don't enable anything if the ih is disabled */ 3765 if (!rdev->ih.enabled) { 3766 r600_disable_interrupts(rdev); 3767 /* force the active interrupt state to all disabled */ 3768 r600_disable_interrupt_state(rdev); 3769 return 0; 3770 } 3771 3772 if (ASIC_IS_DCE3(rdev)) { 3773 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN; 3774 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN; 3775 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN; 3776 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN; 3777 if (ASIC_IS_DCE32(rdev)) { 3778 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN; 3779 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN; 3780 hdmi0 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~AFMT_AZ_FORMAT_WTRIG_MASK; 3781 hdmi1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~AFMT_AZ_FORMAT_WTRIG_MASK; 3782 } else { 3783 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3784 hdmi1 = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3785 } 3786 } else { 3787 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN; 3788 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN; 3789 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN; 3790 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3791 hdmi1 = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3792 } 3793 3794 dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE; 3795 3796 if ((rdev->family > CHIP_R600) && (rdev->family < CHIP_RV770)) { 3797 thermal_int = RREG32(CG_THERMAL_INT) & 3798 ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW); 3799 } else if (rdev->family >= CHIP_RV770) { 3800 thermal_int = RREG32(RV770_CG_THERMAL_INT) & 3801 ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW); 3802 } 3803 if (rdev->irq.dpm_thermal) { 3804 DRM_DEBUG("dpm thermal\n"); 3805 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW; 3806 } 3807 3808 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { 3809 DRM_DEBUG("r600_irq_set: sw int\n"); 3810 cp_int_cntl |= RB_INT_ENABLE; 3811 cp_int_cntl |= TIME_STAMP_INT_ENABLE; 3812 } 3813 3814 if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) { 3815 DRM_DEBUG("r600_irq_set: sw int dma\n"); 3816 dma_cntl |= TRAP_ENABLE; 3817 } 3818 3819 if (rdev->irq.crtc_vblank_int[0] || 3820 atomic_read(&rdev->irq.pflip[0])) { 3821 DRM_DEBUG("r600_irq_set: vblank 0\n"); 3822 mode_int |= D1MODE_VBLANK_INT_MASK; 3823 } 3824 if (rdev->irq.crtc_vblank_int[1] || 3825 atomic_read(&rdev->irq.pflip[1])) { 3826 DRM_DEBUG("r600_irq_set: vblank 1\n"); 3827 mode_int |= D2MODE_VBLANK_INT_MASK; 3828 } 3829 if (rdev->irq.hpd[0]) { 3830 DRM_DEBUG("r600_irq_set: hpd 1\n"); 3831 hpd1 |= DC_HPDx_INT_EN; 3832 } 3833 if (rdev->irq.hpd[1]) { 3834 DRM_DEBUG("r600_irq_set: hpd 2\n"); 3835 hpd2 |= DC_HPDx_INT_EN; 3836 } 3837 if (rdev->irq.hpd[2]) { 3838 DRM_DEBUG("r600_irq_set: hpd 3\n"); 3839 hpd3 |= DC_HPDx_INT_EN; 3840 } 3841 if (rdev->irq.hpd[3]) { 3842 DRM_DEBUG("r600_irq_set: hpd 4\n"); 3843 hpd4 |= DC_HPDx_INT_EN; 3844 } 3845 if (rdev->irq.hpd[4]) { 3846 DRM_DEBUG("r600_irq_set: hpd 5\n"); 3847 hpd5 |= DC_HPDx_INT_EN; 3848 } 3849 if (rdev->irq.hpd[5]) { 3850 DRM_DEBUG("r600_irq_set: hpd 6\n"); 3851 hpd6 |= DC_HPDx_INT_EN; 3852 } 3853 if (rdev->irq.afmt[0]) { 3854 DRM_DEBUG("r600_irq_set: hdmi 0\n"); 3855 hdmi0 |= HDMI0_AZ_FORMAT_WTRIG_MASK; 3856 } 3857 if (rdev->irq.afmt[1]) { 3858 DRM_DEBUG("r600_irq_set: hdmi 0\n"); 3859 hdmi1 |= HDMI0_AZ_FORMAT_WTRIG_MASK; 3860 } 3861 3862 WREG32(CP_INT_CNTL, cp_int_cntl); 3863 WREG32(DMA_CNTL, dma_cntl); 3864 WREG32(DxMODE_INT_MASK, mode_int); 3865 WREG32(D1GRPH_INTERRUPT_CONTROL, DxGRPH_PFLIP_INT_MASK); 3866 WREG32(D2GRPH_INTERRUPT_CONTROL, DxGRPH_PFLIP_INT_MASK); 3867 WREG32(GRBM_INT_CNTL, grbm_int_cntl); 3868 if (ASIC_IS_DCE3(rdev)) { 3869 WREG32(DC_HPD1_INT_CONTROL, hpd1); 3870 WREG32(DC_HPD2_INT_CONTROL, hpd2); 3871 WREG32(DC_HPD3_INT_CONTROL, hpd3); 3872 WREG32(DC_HPD4_INT_CONTROL, hpd4); 3873 if (ASIC_IS_DCE32(rdev)) { 3874 WREG32(DC_HPD5_INT_CONTROL, hpd5); 3875 WREG32(DC_HPD6_INT_CONTROL, hpd6); 3876 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, hdmi0); 3877 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, hdmi1); 3878 } else { 3879 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0); 3880 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, hdmi1); 3881 } 3882 } else { 3883 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1); 3884 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2); 3885 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3); 3886 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0); 3887 WREG32(HDMI1_AUDIO_PACKET_CONTROL, hdmi1); 3888 } 3889 if ((rdev->family > CHIP_R600) && (rdev->family < CHIP_RV770)) { 3890 WREG32(CG_THERMAL_INT, thermal_int); 3891 } else if (rdev->family >= CHIP_RV770) { 3892 WREG32(RV770_CG_THERMAL_INT, thermal_int); 3893 } 3894 3895 /* posting read */ 3896 RREG32(R_000E50_SRBM_STATUS); 3897 3898 return 0; 3899 } 3900 3901 static void r600_irq_ack(struct radeon_device *rdev) 3902 { 3903 u32 tmp; 3904 3905 if (ASIC_IS_DCE3(rdev)) { 3906 rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS); 3907 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE); 3908 rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2); 3909 if (ASIC_IS_DCE32(rdev)) { 3910 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET0); 3911 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET1); 3912 } else { 3913 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS); 3914 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(DCE3_HDMI1_STATUS); 3915 } 3916 } else { 3917 rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS); 3918 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE); 3919 rdev->irq.stat_regs.r600.disp_int_cont2 = 0; 3920 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS); 3921 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(HDMI1_STATUS); 3922 } 3923 rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS); 3924 rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS); 3925 3926 if (rdev->irq.stat_regs.r600.d1grph_int & DxGRPH_PFLIP_INT_OCCURRED) 3927 WREG32(D1GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR); 3928 if (rdev->irq.stat_regs.r600.d2grph_int & DxGRPH_PFLIP_INT_OCCURRED) 3929 WREG32(D2GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR); 3930 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) 3931 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK); 3932 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) 3933 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK); 3934 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) 3935 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK); 3936 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) 3937 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK); 3938 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) { 3939 if (ASIC_IS_DCE3(rdev)) { 3940 tmp = RREG32(DC_HPD1_INT_CONTROL); 3941 tmp |= DC_HPDx_INT_ACK; 3942 WREG32(DC_HPD1_INT_CONTROL, tmp); 3943 } else { 3944 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL); 3945 tmp |= DC_HPDx_INT_ACK; 3946 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); 3947 } 3948 } 3949 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) { 3950 if (ASIC_IS_DCE3(rdev)) { 3951 tmp = RREG32(DC_HPD2_INT_CONTROL); 3952 tmp |= DC_HPDx_INT_ACK; 3953 WREG32(DC_HPD2_INT_CONTROL, tmp); 3954 } else { 3955 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL); 3956 tmp |= DC_HPDx_INT_ACK; 3957 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); 3958 } 3959 } 3960 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) { 3961 if (ASIC_IS_DCE3(rdev)) { 3962 tmp = RREG32(DC_HPD3_INT_CONTROL); 3963 tmp |= DC_HPDx_INT_ACK; 3964 WREG32(DC_HPD3_INT_CONTROL, tmp); 3965 } else { 3966 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL); 3967 tmp |= DC_HPDx_INT_ACK; 3968 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); 3969 } 3970 } 3971 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) { 3972 tmp = RREG32(DC_HPD4_INT_CONTROL); 3973 tmp |= DC_HPDx_INT_ACK; 3974 WREG32(DC_HPD4_INT_CONTROL, tmp); 3975 } 3976 if (ASIC_IS_DCE32(rdev)) { 3977 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) { 3978 tmp = RREG32(DC_HPD5_INT_CONTROL); 3979 tmp |= DC_HPDx_INT_ACK; 3980 WREG32(DC_HPD5_INT_CONTROL, tmp); 3981 } 3982 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) { 3983 tmp = RREG32(DC_HPD6_INT_CONTROL); 3984 tmp |= DC_HPDx_INT_ACK; 3985 WREG32(DC_HPD6_INT_CONTROL, tmp); 3986 } 3987 if (rdev->irq.stat_regs.r600.hdmi0_status & AFMT_AZ_FORMAT_WTRIG) { 3988 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0); 3989 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; 3990 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp); 3991 } 3992 if (rdev->irq.stat_regs.r600.hdmi1_status & AFMT_AZ_FORMAT_WTRIG) { 3993 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1); 3994 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; 3995 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp); 3996 } 3997 } else { 3998 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) { 3999 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL); 4000 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK; 4001 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); 4002 } 4003 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) { 4004 if (ASIC_IS_DCE3(rdev)) { 4005 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL); 4006 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK; 4007 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp); 4008 } else { 4009 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL); 4010 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK; 4011 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp); 4012 } 4013 } 4014 } 4015 } 4016 4017 void r600_irq_disable(struct radeon_device *rdev) 4018 { 4019 r600_disable_interrupts(rdev); 4020 /* Wait and acknowledge irq */ 4021 mdelay(1); 4022 r600_irq_ack(rdev); 4023 r600_disable_interrupt_state(rdev); 4024 } 4025 4026 static u32 r600_get_ih_wptr(struct radeon_device *rdev) 4027 { 4028 u32 wptr, tmp; 4029 4030 if (rdev->wb.enabled) 4031 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]); 4032 else 4033 wptr = RREG32(IH_RB_WPTR); 4034 4035 if (wptr & RB_OVERFLOW) { 4036 wptr &= ~RB_OVERFLOW; 4037 /* When a ring buffer overflow happen start parsing interrupt 4038 * from the last not overwritten vector (wptr + 16). Hopefully 4039 * this should allow us to catchup. 4040 */ 4041 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n", 4042 wptr, rdev->ih.rptr, (wptr + 16) & rdev->ih.ptr_mask); 4043 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask; 4044 tmp = RREG32(IH_RB_CNTL); 4045 tmp |= IH_WPTR_OVERFLOW_CLEAR; 4046 WREG32(IH_RB_CNTL, tmp); 4047 } 4048 return (wptr & rdev->ih.ptr_mask); 4049 } 4050 4051 /* r600 IV Ring 4052 * Each IV ring entry is 128 bits: 4053 * [7:0] - interrupt source id 4054 * [31:8] - reserved 4055 * [59:32] - interrupt source data 4056 * [127:60] - reserved 4057 * 4058 * The basic interrupt vector entries 4059 * are decoded as follows: 4060 * src_id src_data description 4061 * 1 0 D1 Vblank 4062 * 1 1 D1 Vline 4063 * 5 0 D2 Vblank 4064 * 5 1 D2 Vline 4065 * 19 0 FP Hot plug detection A 4066 * 19 1 FP Hot plug detection B 4067 * 19 2 DAC A auto-detection 4068 * 19 3 DAC B auto-detection 4069 * 21 4 HDMI block A 4070 * 21 5 HDMI block B 4071 * 176 - CP_INT RB 4072 * 177 - CP_INT IB1 4073 * 178 - CP_INT IB2 4074 * 181 - EOP Interrupt 4075 * 233 - GUI Idle 4076 * 4077 * Note, these are based on r600 and may need to be 4078 * adjusted or added to on newer asics 4079 */ 4080 4081 int r600_irq_process(struct radeon_device *rdev) 4082 { 4083 u32 wptr; 4084 u32 rptr; 4085 u32 src_id, src_data; 4086 u32 ring_index; 4087 bool queue_hotplug = false; 4088 bool queue_hdmi = false; 4089 bool queue_thermal = false; 4090 4091 if (!rdev->ih.enabled || rdev->shutdown) 4092 return IRQ_NONE; 4093 4094 /* No MSIs, need a dummy read to flush PCI DMAs */ 4095 if (!rdev->msi_enabled) 4096 RREG32(IH_RB_WPTR); 4097 4098 wptr = r600_get_ih_wptr(rdev); 4099 4100 restart_ih: 4101 /* is somebody else already processing irqs? */ 4102 if (atomic_xchg(&rdev->ih.lock, 1)) 4103 return IRQ_NONE; 4104 4105 rptr = rdev->ih.rptr; 4106 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr); 4107 4108 /* Order reading of wptr vs. reading of IH ring data */ 4109 rmb(); 4110 4111 /* display interrupts */ 4112 r600_irq_ack(rdev); 4113 4114 while (rptr != wptr) { 4115 /* wptr/rptr are in bytes! */ 4116 ring_index = rptr / 4; 4117 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff; 4118 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff; 4119 4120 switch (src_id) { 4121 case 1: /* D1 vblank/vline */ 4122 switch (src_data) { 4123 case 0: /* D1 vblank */ 4124 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT)) 4125 DRM_DEBUG("IH: D1 vblank - IH event w/o asserted irq bit?\n"); 4126 4127 if (rdev->irq.crtc_vblank_int[0]) { 4128 drm_handle_vblank(rdev->ddev, 0); 4129 #ifdef __NetBSD__ 4130 spin_lock(&rdev->irq.vblank_lock); 4131 rdev->pm.vblank_sync = true; 4132 DRM_SPIN_WAKEUP_ONE(&rdev->irq.vblank_queue, &rdev->irq.vblank_lock); 4133 spin_unlock(&rdev->irq.vblank_lock); 4134 #else 4135 rdev->pm.vblank_sync = true; 4136 wake_up(&rdev->irq.vblank_queue); 4137 #endif 4138 } 4139 if (atomic_read(&rdev->irq.pflip[0])) 4140 radeon_crtc_handle_vblank(rdev, 0); 4141 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT; 4142 DRM_DEBUG("IH: D1 vblank\n"); 4143 4144 break; 4145 case 1: /* D1 vline */ 4146 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT)) 4147 DRM_DEBUG("IH: D1 vline - IH event w/o asserted irq bit?\n"); 4148 4149 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT; 4150 DRM_DEBUG("IH: D1 vline\n"); 4151 4152 break; 4153 default: 4154 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 4155 break; 4156 } 4157 break; 4158 case 5: /* D2 vblank/vline */ 4159 switch (src_data) { 4160 case 0: /* D2 vblank */ 4161 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT)) 4162 DRM_DEBUG("IH: D2 vblank - IH event w/o asserted irq bit?\n"); 4163 4164 if (rdev->irq.crtc_vblank_int[1]) { 4165 drm_handle_vblank(rdev->ddev, 1); 4166 #ifdef __NetBSD__ 4167 spin_lock(&rdev->irq.vblank_lock); 4168 rdev->pm.vblank_sync = true; 4169 DRM_SPIN_WAKEUP_ONE(&rdev->irq.vblank_queue, &rdev->irq.vblank_lock); 4170 spin_unlock(&rdev->irq.vblank_lock); 4171 #else 4172 rdev->pm.vblank_sync = true; 4173 wake_up(&rdev->irq.vblank_queue); 4174 #endif 4175 } 4176 if (atomic_read(&rdev->irq.pflip[1])) 4177 radeon_crtc_handle_vblank(rdev, 1); 4178 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT; 4179 DRM_DEBUG("IH: D2 vblank\n"); 4180 4181 break; 4182 case 1: /* D1 vline */ 4183 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT)) 4184 DRM_DEBUG("IH: D2 vline - IH event w/o asserted irq bit?\n"); 4185 4186 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT; 4187 DRM_DEBUG("IH: D2 vline\n"); 4188 4189 break; 4190 default: 4191 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 4192 break; 4193 } 4194 break; 4195 case 9: /* D1 pflip */ 4196 DRM_DEBUG("IH: D1 flip\n"); 4197 if (radeon_use_pflipirq > 0) 4198 radeon_crtc_handle_flip(rdev, 0); 4199 break; 4200 case 11: /* D2 pflip */ 4201 DRM_DEBUG("IH: D2 flip\n"); 4202 if (radeon_use_pflipirq > 0) 4203 radeon_crtc_handle_flip(rdev, 1); 4204 break; 4205 case 19: /* HPD/DAC hotplug */ 4206 switch (src_data) { 4207 case 0: 4208 if (!(rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT)) 4209 DRM_DEBUG("IH: HPD1 - IH event w/o asserted irq bit?\n"); 4210 4211 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT; 4212 queue_hotplug = true; 4213 DRM_DEBUG("IH: HPD1\n"); 4214 break; 4215 case 1: 4216 if (!(rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT)) 4217 DRM_DEBUG("IH: HPD2 - IH event w/o asserted irq bit?\n"); 4218 4219 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT; 4220 queue_hotplug = true; 4221 DRM_DEBUG("IH: HPD2\n"); 4222 break; 4223 case 4: 4224 if (!(rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT)) 4225 DRM_DEBUG("IH: HPD3 - IH event w/o asserted irq bit?\n"); 4226 4227 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT; 4228 queue_hotplug = true; 4229 DRM_DEBUG("IH: HPD3\n"); 4230 break; 4231 case 5: 4232 if (!(rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT)) 4233 DRM_DEBUG("IH: HPD4 - IH event w/o asserted irq bit?\n"); 4234 4235 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT; 4236 queue_hotplug = true; 4237 DRM_DEBUG("IH: HPD4\n"); 4238 break; 4239 case 10: 4240 if (!(rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT)) 4241 DRM_DEBUG("IH: HPD5 - IH event w/o asserted irq bit?\n"); 4242 4243 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT; 4244 queue_hotplug = true; 4245 DRM_DEBUG("IH: HPD5\n"); 4246 break; 4247 case 12: 4248 if (!(rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT)) 4249 DRM_DEBUG("IH: HPD6 - IH event w/o asserted irq bit?\n"); 4250 4251 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT; 4252 queue_hotplug = true; 4253 DRM_DEBUG("IH: HPD6\n"); 4254 4255 break; 4256 default: 4257 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 4258 break; 4259 } 4260 break; 4261 case 21: /* hdmi */ 4262 switch (src_data) { 4263 case 4: 4264 if (!(rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG)) 4265 DRM_DEBUG("IH: HDMI0 - IH event w/o asserted irq bit?\n"); 4266 4267 rdev->irq.stat_regs.r600.hdmi0_status &= ~HDMI0_AZ_FORMAT_WTRIG; 4268 queue_hdmi = true; 4269 DRM_DEBUG("IH: HDMI0\n"); 4270 4271 break; 4272 case 5: 4273 if (!(rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG)) 4274 DRM_DEBUG("IH: HDMI1 - IH event w/o asserted irq bit?\n"); 4275 4276 rdev->irq.stat_regs.r600.hdmi1_status &= ~HDMI0_AZ_FORMAT_WTRIG; 4277 queue_hdmi = true; 4278 DRM_DEBUG("IH: HDMI1\n"); 4279 4280 break; 4281 default: 4282 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data); 4283 break; 4284 } 4285 break; 4286 case 124: /* UVD */ 4287 DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data); 4288 radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX); 4289 break; 4290 case 176: /* CP_INT in ring buffer */ 4291 case 177: /* CP_INT in IB1 */ 4292 case 178: /* CP_INT in IB2 */ 4293 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data); 4294 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); 4295 break; 4296 case 181: /* CP EOP event */ 4297 DRM_DEBUG("IH: CP EOP\n"); 4298 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); 4299 break; 4300 case 224: /* DMA trap event */ 4301 DRM_DEBUG("IH: DMA trap\n"); 4302 radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX); 4303 break; 4304 case 230: /* thermal low to high */ 4305 DRM_DEBUG("IH: thermal low to high\n"); 4306 rdev->pm.dpm.thermal.high_to_low = false; 4307 queue_thermal = true; 4308 break; 4309 case 231: /* thermal high to low */ 4310 DRM_DEBUG("IH: thermal high to low\n"); 4311 rdev->pm.dpm.thermal.high_to_low = true; 4312 queue_thermal = true; 4313 break; 4314 case 233: /* GUI IDLE */ 4315 DRM_DEBUG("IH: GUI idle\n"); 4316 break; 4317 default: 4318 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 4319 break; 4320 } 4321 4322 /* wptr/rptr are in bytes! */ 4323 rptr += 16; 4324 rptr &= rdev->ih.ptr_mask; 4325 WREG32(IH_RB_RPTR, rptr); 4326 } 4327 if (queue_hotplug) 4328 schedule_delayed_work(&rdev->hotplug_work, 0); 4329 if (queue_hdmi) 4330 schedule_work(&rdev->audio_work); 4331 if (queue_thermal && rdev->pm.dpm_enabled) 4332 schedule_work(&rdev->pm.dpm.thermal.work); 4333 rdev->ih.rptr = rptr; 4334 atomic_set(&rdev->ih.lock, 0); 4335 4336 /* make sure wptr hasn't changed while processing */ 4337 wptr = r600_get_ih_wptr(rdev); 4338 if (wptr != rptr) 4339 goto restart_ih; 4340 4341 return IRQ_HANDLED; 4342 } 4343 4344 /* 4345 * Debugfs info 4346 */ 4347 #if defined(CONFIG_DEBUG_FS) 4348 4349 static int r600_debugfs_mc_info(struct seq_file *m, void *data) 4350 { 4351 struct drm_info_node *node = (struct drm_info_node *) m->private; 4352 struct drm_device *dev = node->minor->dev; 4353 struct radeon_device *rdev = dev->dev_private; 4354 4355 DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS); 4356 DREG32_SYS(m, rdev, VM_L2_STATUS); 4357 return 0; 4358 } 4359 4360 static struct drm_info_list r600_mc_info_list[] = { 4361 {"r600_mc_info", r600_debugfs_mc_info, 0, NULL}, 4362 }; 4363 #endif 4364 4365 int r600_debugfs_mc_info_init(struct radeon_device *rdev) 4366 { 4367 #if defined(CONFIG_DEBUG_FS) 4368 return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list)); 4369 #else 4370 return 0; 4371 #endif 4372 } 4373 4374 #ifdef __NetBSD__ 4375 # define __iomem volatile 4376 # define readl fake_readl 4377 #endif 4378 4379 /** 4380 * r600_mmio_hdp_flush - flush Host Data Path cache via MMIO 4381 * rdev: radeon device structure 4382 * 4383 * Some R6XX/R7XX don't seem to take into account HDP flushes performed 4384 * through the ring buffer. This leads to corruption in rendering, see 4385 * http://bugzilla.kernel.org/show_bug.cgi?id=15186 . To avoid this, we 4386 * directly perform the HDP flush by writing the register through MMIO. 4387 */ 4388 void r600_mmio_hdp_flush(struct radeon_device *rdev) 4389 { 4390 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read 4391 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL. 4392 * This seems to cause problems on some AGP cards. Just use the old 4393 * method for them. 4394 */ 4395 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) && 4396 rdev->vram_scratch.ptr && !(rdev->flags & RADEON_IS_AGP)) { 4397 void __iomem *ptr = rdev->vram_scratch.ptr; 4398 4399 WREG32(HDP_DEBUG1, 0); 4400 (void)readl(ptr); 4401 } else 4402 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); 4403 } 4404 4405 #ifdef __NetBSD__ 4406 # undef __iomem 4407 # undef readl 4408 #endif 4409 4410 void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes) 4411 { 4412 u32 link_width_cntl, mask; 4413 4414 if (rdev->flags & RADEON_IS_IGP) 4415 return; 4416 4417 if (!(rdev->flags & RADEON_IS_PCIE)) 4418 return; 4419 4420 /* x2 cards have a special sequence */ 4421 if (ASIC_IS_X2(rdev)) 4422 return; 4423 4424 radeon_gui_idle(rdev); 4425 4426 switch (lanes) { 4427 case 0: 4428 mask = RADEON_PCIE_LC_LINK_WIDTH_X0; 4429 break; 4430 case 1: 4431 mask = RADEON_PCIE_LC_LINK_WIDTH_X1; 4432 break; 4433 case 2: 4434 mask = RADEON_PCIE_LC_LINK_WIDTH_X2; 4435 break; 4436 case 4: 4437 mask = RADEON_PCIE_LC_LINK_WIDTH_X4; 4438 break; 4439 case 8: 4440 mask = RADEON_PCIE_LC_LINK_WIDTH_X8; 4441 break; 4442 case 12: 4443 /* not actually supported */ 4444 mask = RADEON_PCIE_LC_LINK_WIDTH_X12; 4445 break; 4446 case 16: 4447 mask = RADEON_PCIE_LC_LINK_WIDTH_X16; 4448 break; 4449 default: 4450 DRM_ERROR("invalid pcie lane request: %d\n", lanes); 4451 return; 4452 } 4453 4454 link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 4455 link_width_cntl &= ~RADEON_PCIE_LC_LINK_WIDTH_MASK; 4456 link_width_cntl |= mask << RADEON_PCIE_LC_LINK_WIDTH_SHIFT; 4457 link_width_cntl |= (RADEON_PCIE_LC_RECONFIG_NOW | 4458 R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE); 4459 4460 WREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4461 } 4462 4463 int r600_get_pcie_lanes(struct radeon_device *rdev) 4464 { 4465 u32 link_width_cntl; 4466 4467 if (rdev->flags & RADEON_IS_IGP) 4468 return 0; 4469 4470 if (!(rdev->flags & RADEON_IS_PCIE)) 4471 return 0; 4472 4473 /* x2 cards have a special sequence */ 4474 if (ASIC_IS_X2(rdev)) 4475 return 0; 4476 4477 radeon_gui_idle(rdev); 4478 4479 link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 4480 4481 switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) { 4482 case RADEON_PCIE_LC_LINK_WIDTH_X1: 4483 return 1; 4484 case RADEON_PCIE_LC_LINK_WIDTH_X2: 4485 return 2; 4486 case RADEON_PCIE_LC_LINK_WIDTH_X4: 4487 return 4; 4488 case RADEON_PCIE_LC_LINK_WIDTH_X8: 4489 return 8; 4490 case RADEON_PCIE_LC_LINK_WIDTH_X12: 4491 /* not actually supported */ 4492 return 12; 4493 case RADEON_PCIE_LC_LINK_WIDTH_X0: 4494 case RADEON_PCIE_LC_LINK_WIDTH_X16: 4495 default: 4496 return 16; 4497 } 4498 } 4499 4500 static void r600_pcie_gen2_enable(struct radeon_device *rdev) 4501 { 4502 #ifndef __NetBSD__ /* XXX radeon pcie */ 4503 u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp; 4504 u16 link_cntl2; 4505 4506 if (radeon_pcie_gen2 == 0) 4507 return; 4508 4509 if (rdev->flags & RADEON_IS_IGP) 4510 return; 4511 4512 if (!(rdev->flags & RADEON_IS_PCIE)) 4513 return; 4514 4515 /* x2 cards have a special sequence */ 4516 if (ASIC_IS_X2(rdev)) 4517 return; 4518 4519 /* only RV6xx+ chips are supported */ 4520 if (rdev->family <= CHIP_R600) 4521 return; 4522 4523 if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) && 4524 (rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT)) 4525 return; 4526 4527 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 4528 if (speed_cntl & LC_CURRENT_DATA_RATE) { 4529 DRM_INFO("PCIE gen 2 link speeds already enabled\n"); 4530 return; 4531 } 4532 4533 DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n"); 4534 4535 /* 55 nm r6xx asics */ 4536 if ((rdev->family == CHIP_RV670) || 4537 (rdev->family == CHIP_RV620) || 4538 (rdev->family == CHIP_RV635)) { 4539 /* advertise upconfig capability */ 4540 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); 4541 link_width_cntl &= ~LC_UPCONFIGURE_DIS; 4542 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4543 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); 4544 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) { 4545 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT; 4546 link_width_cntl &= ~(LC_LINK_WIDTH_MASK | 4547 LC_RECONFIG_ARC_MISSING_ESCAPE); 4548 link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN; 4549 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4550 } else { 4551 link_width_cntl |= LC_UPCONFIGURE_DIS; 4552 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4553 } 4554 } 4555 4556 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 4557 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) && 4558 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) { 4559 4560 /* 55 nm r6xx asics */ 4561 if ((rdev->family == CHIP_RV670) || 4562 (rdev->family == CHIP_RV620) || 4563 (rdev->family == CHIP_RV635)) { 4564 WREG32(MM_CFGREGS_CNTL, 0x8); 4565 link_cntl2 = RREG32(0x4088); 4566 WREG32(MM_CFGREGS_CNTL, 0); 4567 /* not supported yet */ 4568 if (link_cntl2 & SELECTABLE_DEEMPHASIS) 4569 return; 4570 } 4571 4572 speed_cntl &= ~LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK; 4573 speed_cntl |= (0x3 << LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT); 4574 speed_cntl &= ~LC_VOLTAGE_TIMER_SEL_MASK; 4575 speed_cntl &= ~LC_FORCE_DIS_HW_SPEED_CHANGE; 4576 speed_cntl |= LC_FORCE_EN_HW_SPEED_CHANGE; 4577 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); 4578 4579 tmp = RREG32(0x541c); 4580 WREG32(0x541c, tmp | 0x8); 4581 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN); 4582 link_cntl2 = RREG16(0x4088); 4583 link_cntl2 &= ~TARGET_LINK_SPEED_MASK; 4584 link_cntl2 |= 0x2; 4585 WREG16(0x4088, link_cntl2); 4586 WREG32(MM_CFGREGS_CNTL, 0); 4587 4588 if ((rdev->family == CHIP_RV670) || 4589 (rdev->family == CHIP_RV620) || 4590 (rdev->family == CHIP_RV635)) { 4591 training_cntl = RREG32_PCIE_PORT(PCIE_LC_TRAINING_CNTL); 4592 training_cntl &= ~LC_POINT_7_PLUS_EN; 4593 WREG32_PCIE_PORT(PCIE_LC_TRAINING_CNTL, training_cntl); 4594 } else { 4595 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 4596 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN; 4597 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); 4598 } 4599 4600 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 4601 speed_cntl |= LC_GEN2_EN_STRAP; 4602 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); 4603 4604 } else { 4605 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); 4606 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */ 4607 if (1) 4608 link_width_cntl |= LC_UPCONFIGURE_DIS; 4609 else 4610 link_width_cntl &= ~LC_UPCONFIGURE_DIS; 4611 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4612 } 4613 #endif 4614 } 4615 4616 /** 4617 * r600_get_gpu_clock_counter - return GPU clock counter snapshot 4618 * 4619 * @rdev: radeon_device pointer 4620 * 4621 * Fetches a GPU clock counter snapshot (R6xx-cayman). 4622 * Returns the 64 bit clock counter snapshot. 4623 */ 4624 uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev) 4625 { 4626 uint64_t clock; 4627 4628 mutex_lock(&rdev->gpu_clock_mutex); 4629 WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1); 4630 clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) | 4631 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 4632 mutex_unlock(&rdev->gpu_clock_mutex); 4633 return clock; 4634 } 4635
Indexes created Sat Oct 25 16:10:12 GMT 2025