radeon_r600_cs.c revision 1.1.2.2
1 /* $NetBSD: radeon_r600_cs.c,v 1.1.2.2 2018/09/06 06:56:33 pgoyette Exp $ */ 2 3 /* 4 * Copyright 2008 Advanced Micro Devices, Inc. 5 * Copyright 2008 Red Hat Inc. 6 * Copyright 2009 Jerome Glisse. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: Dave Airlie 27 * Alex Deucher 28 * Jerome Glisse 29 */ 30 #include <sys/cdefs.h> 31 __KERNEL_RCSID(0, "$NetBSD: radeon_r600_cs.c,v 1.1.2.2 2018/09/06 06:56:33 pgoyette Exp $"); 32 33 #include <linux/kernel.h> 34 #include <drm/drmP.h> 35 #include "radeon.h" 36 #include "r600d.h" 37 #include "r600_reg_safe.h" 38 39 static int r600_nomm; 40 extern void r600_cs_legacy_get_tiling_conf(struct drm_device *dev, u32 *npipes, u32 *nbanks, u32 *group_size); 41 42 43 struct r600_cs_track { 44 /* configuration we miror so that we use same code btw kms/ums */ 45 u32 group_size; 46 u32 nbanks; 47 u32 npipes; 48 /* value we track */ 49 u32 sq_config; 50 u32 log_nsamples; 51 u32 nsamples; 52 u32 cb_color_base_last[8]; 53 struct radeon_bo *cb_color_bo[8]; 54 u64 cb_color_bo_mc[8]; 55 u64 cb_color_bo_offset[8]; 56 struct radeon_bo *cb_color_frag_bo[8]; 57 u64 cb_color_frag_offset[8]; 58 struct radeon_bo *cb_color_tile_bo[8]; 59 u64 cb_color_tile_offset[8]; 60 u32 cb_color_mask[8]; 61 u32 cb_color_info[8]; 62 u32 cb_color_view[8]; 63 u32 cb_color_size_idx[8]; /* unused */ 64 u32 cb_target_mask; 65 u32 cb_shader_mask; /* unused */ 66 bool is_resolve; 67 u32 cb_color_size[8]; 68 u32 vgt_strmout_en; 69 u32 vgt_strmout_buffer_en; 70 struct radeon_bo *vgt_strmout_bo[4]; 71 u64 vgt_strmout_bo_mc[4]; /* unused */ 72 u32 vgt_strmout_bo_offset[4]; 73 u32 vgt_strmout_size[4]; 74 u32 db_depth_control; 75 u32 db_depth_info; 76 u32 db_depth_size_idx; 77 u32 db_depth_view; 78 u32 db_depth_size; 79 u32 db_offset; 80 struct radeon_bo *db_bo; 81 u64 db_bo_mc; 82 bool sx_misc_kill_all_prims; 83 bool cb_dirty; 84 bool db_dirty; 85 bool streamout_dirty; 86 struct radeon_bo *htile_bo; 87 u64 htile_offset; 88 u32 htile_surface; 89 }; 90 91 #define FMT_8_BIT(fmt, vc) [fmt] = { 1, 1, 1, vc, CHIP_R600 } 92 #define FMT_16_BIT(fmt, vc) [fmt] = { 1, 1, 2, vc, CHIP_R600 } 93 #define FMT_24_BIT(fmt) [fmt] = { 1, 1, 4, 0, CHIP_R600 } 94 #define FMT_32_BIT(fmt, vc) [fmt] = { 1, 1, 4, vc, CHIP_R600 } 95 #define FMT_48_BIT(fmt) [fmt] = { 1, 1, 8, 0, CHIP_R600 } 96 #define FMT_64_BIT(fmt, vc) [fmt] = { 1, 1, 8, vc, CHIP_R600 } 97 #define FMT_96_BIT(fmt) [fmt] = { 1, 1, 12, 0, CHIP_R600 } 98 #define FMT_128_BIT(fmt, vc) [fmt] = { 1, 1, 16,vc, CHIP_R600 } 99 100 struct gpu_formats { 101 unsigned blockwidth; 102 unsigned blockheight; 103 unsigned blocksize; 104 unsigned valid_color; 105 enum radeon_family min_family; 106 }; 107 108 static const struct gpu_formats color_formats_table[] = { 109 /* 8 bit */ 110 FMT_8_BIT(V_038004_COLOR_8, 1), 111 FMT_8_BIT(V_038004_COLOR_4_4, 1), 112 FMT_8_BIT(V_038004_COLOR_3_3_2, 1), 113 FMT_8_BIT(V_038004_FMT_1, 0), 114 115 /* 16-bit */ 116 FMT_16_BIT(V_038004_COLOR_16, 1), 117 FMT_16_BIT(V_038004_COLOR_16_FLOAT, 1), 118 FMT_16_BIT(V_038004_COLOR_8_8, 1), 119 FMT_16_BIT(V_038004_COLOR_5_6_5, 1), 120 FMT_16_BIT(V_038004_COLOR_6_5_5, 1), 121 FMT_16_BIT(V_038004_COLOR_1_5_5_5, 1), 122 FMT_16_BIT(V_038004_COLOR_4_4_4_4, 1), 123 FMT_16_BIT(V_038004_COLOR_5_5_5_1, 1), 124 125 /* 24-bit */ 126 FMT_24_BIT(V_038004_FMT_8_8_8), 127 128 /* 32-bit */ 129 FMT_32_BIT(V_038004_COLOR_32, 1), 130 FMT_32_BIT(V_038004_COLOR_32_FLOAT, 1), 131 FMT_32_BIT(V_038004_COLOR_16_16, 1), 132 FMT_32_BIT(V_038004_COLOR_16_16_FLOAT, 1), 133 FMT_32_BIT(V_038004_COLOR_8_24, 1), 134 FMT_32_BIT(V_038004_COLOR_8_24_FLOAT, 1), 135 FMT_32_BIT(V_038004_COLOR_24_8, 1), 136 FMT_32_BIT(V_038004_COLOR_24_8_FLOAT, 1), 137 FMT_32_BIT(V_038004_COLOR_10_11_11, 1), 138 FMT_32_BIT(V_038004_COLOR_10_11_11_FLOAT, 1), 139 FMT_32_BIT(V_038004_COLOR_11_11_10, 1), 140 FMT_32_BIT(V_038004_COLOR_11_11_10_FLOAT, 1), 141 FMT_32_BIT(V_038004_COLOR_2_10_10_10, 1), 142 FMT_32_BIT(V_038004_COLOR_8_8_8_8, 1), 143 FMT_32_BIT(V_038004_COLOR_10_10_10_2, 1), 144 FMT_32_BIT(V_038004_FMT_5_9_9_9_SHAREDEXP, 0), 145 FMT_32_BIT(V_038004_FMT_32_AS_8, 0), 146 FMT_32_BIT(V_038004_FMT_32_AS_8_8, 0), 147 148 /* 48-bit */ 149 FMT_48_BIT(V_038004_FMT_16_16_16), 150 FMT_48_BIT(V_038004_FMT_16_16_16_FLOAT), 151 152 /* 64-bit */ 153 FMT_64_BIT(V_038004_COLOR_X24_8_32_FLOAT, 1), 154 FMT_64_BIT(V_038004_COLOR_32_32, 1), 155 FMT_64_BIT(V_038004_COLOR_32_32_FLOAT, 1), 156 FMT_64_BIT(V_038004_COLOR_16_16_16_16, 1), 157 FMT_64_BIT(V_038004_COLOR_16_16_16_16_FLOAT, 1), 158 159 FMT_96_BIT(V_038004_FMT_32_32_32), 160 FMT_96_BIT(V_038004_FMT_32_32_32_FLOAT), 161 162 /* 128-bit */ 163 FMT_128_BIT(V_038004_COLOR_32_32_32_32, 1), 164 FMT_128_BIT(V_038004_COLOR_32_32_32_32_FLOAT, 1), 165 166 [V_038004_FMT_GB_GR] = { 2, 1, 4, 0 }, 167 [V_038004_FMT_BG_RG] = { 2, 1, 4, 0 }, 168 169 /* block compressed formats */ 170 [V_038004_FMT_BC1] = { 4, 4, 8, 0 }, 171 [V_038004_FMT_BC2] = { 4, 4, 16, 0 }, 172 [V_038004_FMT_BC3] = { 4, 4, 16, 0 }, 173 [V_038004_FMT_BC4] = { 4, 4, 8, 0 }, 174 [V_038004_FMT_BC5] = { 4, 4, 16, 0}, 175 [V_038004_FMT_BC6] = { 4, 4, 16, 0, CHIP_CEDAR}, /* Evergreen-only */ 176 [V_038004_FMT_BC7] = { 4, 4, 16, 0, CHIP_CEDAR}, /* Evergreen-only */ 177 178 /* The other Evergreen formats */ 179 [V_038004_FMT_32_AS_32_32_32_32] = { 1, 1, 4, 0, CHIP_CEDAR}, 180 }; 181 182 bool r600_fmt_is_valid_color(u32 format) 183 { 184 if (format >= ARRAY_SIZE(color_formats_table)) 185 return false; 186 187 if (color_formats_table[format].valid_color) 188 return true; 189 190 return false; 191 } 192 193 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family) 194 { 195 if (format >= ARRAY_SIZE(color_formats_table)) 196 return false; 197 198 if (family < color_formats_table[format].min_family) 199 return false; 200 201 if (color_formats_table[format].blockwidth > 0) 202 return true; 203 204 return false; 205 } 206 207 int r600_fmt_get_blocksize(u32 format) 208 { 209 if (format >= ARRAY_SIZE(color_formats_table)) 210 return 0; 211 212 return color_formats_table[format].blocksize; 213 } 214 215 int r600_fmt_get_nblocksx(u32 format, u32 w) 216 { 217 unsigned bw; 218 219 if (format >= ARRAY_SIZE(color_formats_table)) 220 return 0; 221 222 bw = color_formats_table[format].blockwidth; 223 if (bw == 0) 224 return 0; 225 226 return (w + bw - 1) / bw; 227 } 228 229 int r600_fmt_get_nblocksy(u32 format, u32 h) 230 { 231 unsigned bh; 232 233 if (format >= ARRAY_SIZE(color_formats_table)) 234 return 0; 235 236 bh = color_formats_table[format].blockheight; 237 if (bh == 0) 238 return 0; 239 240 return (h + bh - 1) / bh; 241 } 242 243 struct array_mode_checker { 244 int array_mode; 245 u32 group_size; 246 u32 nbanks; 247 u32 npipes; 248 u32 nsamples; 249 u32 blocksize; 250 }; 251 252 /* returns alignment in pixels for pitch/height/depth and bytes for base */ 253 static int r600_get_array_mode_alignment(struct array_mode_checker *values, 254 u32 *pitch_align, 255 u32 *height_align, 256 u32 *depth_align, 257 u64 *base_align) 258 { 259 u32 tile_width = 8; 260 u32 tile_height = 8; 261 u32 macro_tile_width = values->nbanks; 262 u32 macro_tile_height = values->npipes; 263 u32 tile_bytes = tile_width * tile_height * values->blocksize * values->nsamples; 264 u32 macro_tile_bytes = macro_tile_width * macro_tile_height * tile_bytes; 265 266 switch (values->array_mode) { 267 case ARRAY_LINEAR_GENERAL: 268 /* technically tile_width/_height for pitch/height */ 269 *pitch_align = 1; /* tile_width */ 270 *height_align = 1; /* tile_height */ 271 *depth_align = 1; 272 *base_align = 1; 273 break; 274 case ARRAY_LINEAR_ALIGNED: 275 *pitch_align = max((u32)64, (u32)(values->group_size / values->blocksize)); 276 *height_align = 1; 277 *depth_align = 1; 278 *base_align = values->group_size; 279 break; 280 case ARRAY_1D_TILED_THIN1: 281 *pitch_align = max((u32)tile_width, 282 (u32)(values->group_size / 283 (tile_height * values->blocksize * values->nsamples))); 284 *height_align = tile_height; 285 *depth_align = 1; 286 *base_align = values->group_size; 287 break; 288 case ARRAY_2D_TILED_THIN1: 289 *pitch_align = max((u32)macro_tile_width * tile_width, 290 (u32)((values->group_size * values->nbanks) / 291 (values->blocksize * values->nsamples * tile_width))); 292 *height_align = macro_tile_height * tile_height; 293 *depth_align = 1; 294 *base_align = max(macro_tile_bytes, 295 (*pitch_align) * values->blocksize * (*height_align) * values->nsamples); 296 break; 297 default: 298 return -EINVAL; 299 } 300 301 return 0; 302 } 303 304 static void r600_cs_track_init(struct r600_cs_track *track) 305 { 306 int i; 307 308 /* assume DX9 mode */ 309 track->sq_config = DX9_CONSTS; 310 for (i = 0; i < 8; i++) { 311 track->cb_color_base_last[i] = 0; 312 track->cb_color_size[i] = 0; 313 track->cb_color_size_idx[i] = 0; 314 track->cb_color_info[i] = 0; 315 track->cb_color_view[i] = 0xFFFFFFFF; 316 track->cb_color_bo[i] = NULL; 317 track->cb_color_bo_offset[i] = 0xFFFFFFFF; 318 track->cb_color_bo_mc[i] = 0xFFFFFFFF; 319 track->cb_color_frag_bo[i] = NULL; 320 track->cb_color_frag_offset[i] = 0xFFFFFFFF; 321 track->cb_color_tile_bo[i] = NULL; 322 track->cb_color_tile_offset[i] = 0xFFFFFFFF; 323 track->cb_color_mask[i] = 0xFFFFFFFF; 324 } 325 track->is_resolve = false; 326 track->nsamples = 16; 327 track->log_nsamples = 4; 328 track->cb_target_mask = 0xFFFFFFFF; 329 track->cb_shader_mask = 0xFFFFFFFF; 330 track->cb_dirty = true; 331 track->db_bo = NULL; 332 track->db_bo_mc = 0xFFFFFFFF; 333 /* assume the biggest format and that htile is enabled */ 334 track->db_depth_info = 7 | (1 << 25); 335 track->db_depth_view = 0xFFFFC000; 336 track->db_depth_size = 0xFFFFFFFF; 337 track->db_depth_size_idx = 0; 338 track->db_depth_control = 0xFFFFFFFF; 339 track->db_dirty = true; 340 track->htile_bo = NULL; 341 track->htile_offset = 0xFFFFFFFF; 342 track->htile_surface = 0; 343 344 for (i = 0; i < 4; i++) { 345 track->vgt_strmout_size[i] = 0; 346 track->vgt_strmout_bo[i] = NULL; 347 track->vgt_strmout_bo_offset[i] = 0xFFFFFFFF; 348 track->vgt_strmout_bo_mc[i] = 0xFFFFFFFF; 349 } 350 track->streamout_dirty = true; 351 track->sx_misc_kill_all_prims = false; 352 } 353 354 static int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i) 355 { 356 struct r600_cs_track *track = p->track; 357 u32 slice_tile_max, size __unused, tmp; 358 u32 height, height_align, pitch, pitch_align, depth_align; 359 u64 base_offset, base_align; 360 struct array_mode_checker array_check; 361 volatile u32 *ib = p->ib.ptr; 362 unsigned array_mode; 363 u32 format; 364 /* When resolve is used, the second colorbuffer has always 1 sample. */ 365 unsigned nsamples = track->is_resolve && i == 1 ? 1 : track->nsamples; 366 367 size = radeon_bo_size(track->cb_color_bo[i]) - track->cb_color_bo_offset[i]; 368 format = G_0280A0_FORMAT(track->cb_color_info[i]); 369 if (!r600_fmt_is_valid_color(format)) { 370 dev_warn(p->dev, "%s:%d cb invalid format %d for %d (0x%08X)\n", 371 __func__, __LINE__, format, 372 i, track->cb_color_info[i]); 373 return -EINVAL; 374 } 375 /* pitch in pixels */ 376 pitch = (G_028060_PITCH_TILE_MAX(track->cb_color_size[i]) + 1) * 8; 377 slice_tile_max = G_028060_SLICE_TILE_MAX(track->cb_color_size[i]) + 1; 378 slice_tile_max *= 64; 379 height = slice_tile_max / pitch; 380 if (height > 8192) 381 height = 8192; 382 array_mode = G_0280A0_ARRAY_MODE(track->cb_color_info[i]); 383 384 base_offset = track->cb_color_bo_mc[i] + track->cb_color_bo_offset[i]; 385 array_check.array_mode = array_mode; 386 array_check.group_size = track->group_size; 387 array_check.nbanks = track->nbanks; 388 array_check.npipes = track->npipes; 389 array_check.nsamples = nsamples; 390 array_check.blocksize = r600_fmt_get_blocksize(format); 391 if (r600_get_array_mode_alignment(&array_check, 392 &pitch_align, &height_align, &depth_align, &base_align)) { 393 dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__, 394 G_0280A0_ARRAY_MODE(track->cb_color_info[i]), i, 395 track->cb_color_info[i]); 396 return -EINVAL; 397 } 398 switch (array_mode) { 399 case V_0280A0_ARRAY_LINEAR_GENERAL: 400 break; 401 case V_0280A0_ARRAY_LINEAR_ALIGNED: 402 break; 403 case V_0280A0_ARRAY_1D_TILED_THIN1: 404 /* avoid breaking userspace */ 405 if (height > 7) 406 height &= ~0x7; 407 break; 408 case V_0280A0_ARRAY_2D_TILED_THIN1: 409 break; 410 default: 411 dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__, 412 G_0280A0_ARRAY_MODE(track->cb_color_info[i]), i, 413 track->cb_color_info[i]); 414 return -EINVAL; 415 } 416 417 if (!IS_ALIGNED(pitch, pitch_align)) { 418 dev_warn(p->dev, "%s:%d cb pitch (%d, 0x%x, %d) invalid\n", 419 __func__, __LINE__, pitch, pitch_align, array_mode); 420 return -EINVAL; 421 } 422 if (!IS_ALIGNED(height, height_align)) { 423 dev_warn(p->dev, "%s:%d cb height (%d, 0x%x, %d) invalid\n", 424 __func__, __LINE__, height, height_align, array_mode); 425 return -EINVAL; 426 } 427 if (!IS_ALIGNED(base_offset, base_align)) { 428 dev_warn(p->dev, "%s offset[%d] 0x%"PRIx64" 0x%"PRIx64", %d not aligned\n", __func__, i, 429 base_offset, base_align, array_mode); 430 return -EINVAL; 431 } 432 433 /* check offset */ 434 tmp = r600_fmt_get_nblocksy(format, height) * r600_fmt_get_nblocksx(format, pitch) * 435 r600_fmt_get_blocksize(format) * nsamples; 436 switch (array_mode) { 437 default: 438 case V_0280A0_ARRAY_LINEAR_GENERAL: 439 case V_0280A0_ARRAY_LINEAR_ALIGNED: 440 tmp += track->cb_color_view[i] & 0xFF; 441 break; 442 case V_0280A0_ARRAY_1D_TILED_THIN1: 443 case V_0280A0_ARRAY_2D_TILED_THIN1: 444 tmp += G_028080_SLICE_MAX(track->cb_color_view[i]) * tmp; 445 break; 446 } 447 if ((tmp + track->cb_color_bo_offset[i]) > radeon_bo_size(track->cb_color_bo[i])) { 448 if (array_mode == V_0280A0_ARRAY_LINEAR_GENERAL) { 449 /* the initial DDX does bad things with the CB size occasionally */ 450 /* it rounds up height too far for slice tile max but the BO is smaller */ 451 /* r600c,g also seem to flush at bad times in some apps resulting in 452 * bogus values here. So for linear just allow anything to avoid breaking 453 * broken userspace. 454 */ 455 } else { 456 dev_warn(p->dev, "%s offset[%d] %d %"PRIu64" %d %lu too big (%d %d) (%d %d %d)\n", 457 __func__, i, array_mode, 458 track->cb_color_bo_offset[i], tmp, 459 radeon_bo_size(track->cb_color_bo[i]), 460 pitch, height, r600_fmt_get_nblocksx(format, pitch), 461 r600_fmt_get_nblocksy(format, height), 462 r600_fmt_get_blocksize(format)); 463 return -EINVAL; 464 } 465 } 466 /* limit max tile */ 467 tmp = (height * pitch) >> 6; 468 if (tmp < slice_tile_max) 469 slice_tile_max = tmp; 470 tmp = S_028060_PITCH_TILE_MAX((pitch / 8) - 1) | 471 S_028060_SLICE_TILE_MAX(slice_tile_max - 1); 472 ib[track->cb_color_size_idx[i]] = tmp; 473 474 /* FMASK/CMASK */ 475 switch (G_0280A0_TILE_MODE(track->cb_color_info[i])) { 476 case V_0280A0_TILE_DISABLE: 477 break; 478 case V_0280A0_FRAG_ENABLE: 479 if (track->nsamples > 1) { 480 uint32_t tile_max = G_028100_FMASK_TILE_MAX(track->cb_color_mask[i]); 481 /* the tile size is 8x8, but the size is in units of bits. 482 * for bytes, do just * 8. */ 483 uint32_t bytes = track->nsamples * track->log_nsamples * 8 * (tile_max + 1); 484 485 if (bytes + track->cb_color_frag_offset[i] > 486 radeon_bo_size(track->cb_color_frag_bo[i])) { 487 dev_warn(p->dev, "%s FMASK_TILE_MAX too large " 488 "(tile_max=%u, bytes=%u, offset=%"PRIu64", bo_size=%lu)\n", 489 __func__, tile_max, bytes, 490 track->cb_color_frag_offset[i], 491 radeon_bo_size(track->cb_color_frag_bo[i])); 492 return -EINVAL; 493 } 494 } 495 /* fall through */ 496 case V_0280A0_CLEAR_ENABLE: 497 { 498 uint32_t block_max = G_028100_CMASK_BLOCK_MAX(track->cb_color_mask[i]); 499 /* One block = 128x128 pixels, one 8x8 tile has 4 bits.. 500 * (128*128) / (8*8) / 2 = 128 bytes per block. */ 501 uint32_t bytes = (block_max + 1) * 128; 502 503 if (bytes + track->cb_color_tile_offset[i] > 504 radeon_bo_size(track->cb_color_tile_bo[i])) { 505 dev_warn(p->dev, "%s CMASK_BLOCK_MAX too large " 506 "(block_max=%u, bytes=%u, offset=%"PRIu64", bo_size=%lu)\n", 507 __func__, block_max, bytes, 508 track->cb_color_tile_offset[i], 509 radeon_bo_size(track->cb_color_tile_bo[i])); 510 return -EINVAL; 511 } 512 break; 513 } 514 default: 515 dev_warn(p->dev, "%s invalid tile mode\n", __func__); 516 return -EINVAL; 517 } 518 return 0; 519 } 520 521 static int r600_cs_track_validate_db(struct radeon_cs_parser *p) 522 { 523 struct r600_cs_track *track = p->track; 524 u32 nviews, bpe, ntiles, size __unused, slice_tile_max, tmp; 525 u32 height_align, pitch_align, depth_align; 526 u32 pitch = 8192; 527 u32 height = 8192; 528 u64 base_offset, base_align; 529 struct array_mode_checker array_check; 530 int array_mode; 531 volatile u32 *ib = p->ib.ptr; 532 533 534 if (track->db_bo == NULL) { 535 dev_warn(p->dev, "z/stencil with no depth buffer\n"); 536 return -EINVAL; 537 } 538 switch (G_028010_FORMAT(track->db_depth_info)) { 539 case V_028010_DEPTH_16: 540 bpe = 2; 541 break; 542 case V_028010_DEPTH_X8_24: 543 case V_028010_DEPTH_8_24: 544 case V_028010_DEPTH_X8_24_FLOAT: 545 case V_028010_DEPTH_8_24_FLOAT: 546 case V_028010_DEPTH_32_FLOAT: 547 bpe = 4; 548 break; 549 case V_028010_DEPTH_X24_8_32_FLOAT: 550 bpe = 8; 551 break; 552 default: 553 dev_warn(p->dev, "z/stencil with invalid format %d\n", G_028010_FORMAT(track->db_depth_info)); 554 return -EINVAL; 555 } 556 if ((track->db_depth_size & 0xFFFFFC00) == 0xFFFFFC00) { 557 if (!track->db_depth_size_idx) { 558 dev_warn(p->dev, "z/stencil buffer size not set\n"); 559 return -EINVAL; 560 } 561 tmp = radeon_bo_size(track->db_bo) - track->db_offset; 562 tmp = (tmp / bpe) >> 6; 563 if (!tmp) { 564 dev_warn(p->dev, "z/stencil buffer too small (0x%08X %d %d %ld)\n", 565 track->db_depth_size, bpe, track->db_offset, 566 radeon_bo_size(track->db_bo)); 567 return -EINVAL; 568 } 569 ib[track->db_depth_size_idx] = S_028000_SLICE_TILE_MAX(tmp - 1) | (track->db_depth_size & 0x3FF); 570 } else { 571 size = radeon_bo_size(track->db_bo); 572 /* pitch in pixels */ 573 pitch = (G_028000_PITCH_TILE_MAX(track->db_depth_size) + 1) * 8; 574 slice_tile_max = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1; 575 slice_tile_max *= 64; 576 height = slice_tile_max / pitch; 577 if (height > 8192) 578 height = 8192; 579 base_offset = track->db_bo_mc + track->db_offset; 580 array_mode = G_028010_ARRAY_MODE(track->db_depth_info); 581 array_check.array_mode = array_mode; 582 array_check.group_size = track->group_size; 583 array_check.nbanks = track->nbanks; 584 array_check.npipes = track->npipes; 585 array_check.nsamples = track->nsamples; 586 array_check.blocksize = bpe; 587 if (r600_get_array_mode_alignment(&array_check, 588 &pitch_align, &height_align, &depth_align, &base_align)) { 589 dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__, 590 G_028010_ARRAY_MODE(track->db_depth_info), 591 track->db_depth_info); 592 return -EINVAL; 593 } 594 switch (array_mode) { 595 case V_028010_ARRAY_1D_TILED_THIN1: 596 /* don't break userspace */ 597 height &= ~0x7; 598 break; 599 case V_028010_ARRAY_2D_TILED_THIN1: 600 break; 601 default: 602 dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__, 603 G_028010_ARRAY_MODE(track->db_depth_info), 604 track->db_depth_info); 605 return -EINVAL; 606 } 607 608 if (!IS_ALIGNED(pitch, pitch_align)) { 609 dev_warn(p->dev, "%s:%d db pitch (%d, 0x%x, %d) invalid\n", 610 __func__, __LINE__, pitch, pitch_align, array_mode); 611 return -EINVAL; 612 } 613 if (!IS_ALIGNED(height, height_align)) { 614 dev_warn(p->dev, "%s:%d db height (%d, 0x%x, %d) invalid\n", 615 __func__, __LINE__, height, height_align, array_mode); 616 return -EINVAL; 617 } 618 if (!IS_ALIGNED(base_offset, base_align)) { 619 dev_warn(p->dev, "%s offset 0x%"PRIx64", 0x%"PRIx64", %d not aligned\n", __func__, 620 base_offset, base_align, array_mode); 621 return -EINVAL; 622 } 623 624 ntiles = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1; 625 nviews = G_028004_SLICE_MAX(track->db_depth_view) + 1; 626 tmp = ntiles * bpe * 64 * nviews * track->nsamples; 627 if ((tmp + track->db_offset) > radeon_bo_size(track->db_bo)) { 628 dev_warn(p->dev, "z/stencil buffer (%d) too small (0x%08X %d %d %d -> %u have %lu)\n", 629 array_mode, 630 track->db_depth_size, ntiles, nviews, bpe, tmp + track->db_offset, 631 radeon_bo_size(track->db_bo)); 632 return -EINVAL; 633 } 634 } 635 636 /* hyperz */ 637 if (G_028010_TILE_SURFACE_ENABLE(track->db_depth_info)) { 638 unsigned long size; 639 unsigned nbx, nby; 640 641 if (track->htile_bo == NULL) { 642 dev_warn(p->dev, "%s:%d htile enabled without htile surface 0x%08x\n", 643 __func__, __LINE__, track->db_depth_info); 644 return -EINVAL; 645 } 646 if ((track->db_depth_size & 0xFFFFFC00) == 0xFFFFFC00) { 647 dev_warn(p->dev, "%s:%d htile can't be enabled with bogus db_depth_size 0x%08x\n", 648 __func__, __LINE__, track->db_depth_size); 649 return -EINVAL; 650 } 651 652 nbx = pitch; 653 nby = height; 654 if (G_028D24_LINEAR(track->htile_surface)) { 655 /* nbx must be 16 htiles aligned == 16 * 8 pixel aligned */ 656 nbx = round_up(nbx, 16 * 8); 657 /* nby is npipes htiles aligned == npipes * 8 pixel aligned */ 658 nby = round_up(nby, track->npipes * 8); 659 } else { 660 /* always assume 8x8 htile */ 661 /* align is htile align * 8, htile align vary according to 662 * number of pipe and tile width and nby 663 */ 664 switch (track->npipes) { 665 case 8: 666 /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/ 667 nbx = round_up(nbx, 64 * 8); 668 nby = round_up(nby, 64 * 8); 669 break; 670 case 4: 671 /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/ 672 nbx = round_up(nbx, 64 * 8); 673 nby = round_up(nby, 32 * 8); 674 break; 675 case 2: 676 /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/ 677 nbx = round_up(nbx, 32 * 8); 678 nby = round_up(nby, 32 * 8); 679 break; 680 case 1: 681 /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/ 682 nbx = round_up(nbx, 32 * 8); 683 nby = round_up(nby, 16 * 8); 684 break; 685 default: 686 dev_warn(p->dev, "%s:%d invalid num pipes %d\n", 687 __func__, __LINE__, track->npipes); 688 return -EINVAL; 689 } 690 } 691 /* compute number of htile */ 692 nbx = nbx >> 3; 693 nby = nby >> 3; 694 /* size must be aligned on npipes * 2K boundary */ 695 size = roundup(nbx * nby * 4, track->npipes * (2 << 10)); 696 size += track->htile_offset; 697 698 if (size > radeon_bo_size(track->htile_bo)) { 699 dev_warn(p->dev, "%s:%d htile surface too small %ld for %ld (%d %d)\n", 700 __func__, __LINE__, radeon_bo_size(track->htile_bo), 701 size, nbx, nby); 702 return -EINVAL; 703 } 704 } 705 706 track->db_dirty = false; 707 return 0; 708 } 709 710 static int r600_cs_track_check(struct radeon_cs_parser *p) 711 { 712 struct r600_cs_track *track = p->track; 713 u32 tmp; 714 int r, i; 715 716 /* on legacy kernel we don't perform advanced check */ 717 if (p->rdev == NULL) 718 return 0; 719 720 /* check streamout */ 721 if (track->streamout_dirty && track->vgt_strmout_en) { 722 for (i = 0; i < 4; i++) { 723 if (track->vgt_strmout_buffer_en & (1 << i)) { 724 if (track->vgt_strmout_bo[i]) { 725 u64 offset = (u64)track->vgt_strmout_bo_offset[i] + 726 (u64)track->vgt_strmout_size[i]; 727 if (offset > radeon_bo_size(track->vgt_strmout_bo[i])) { 728 DRM_ERROR("streamout %d bo too small: 0x%"PRIx64", 0x%lx\n", 729 i, offset, 730 radeon_bo_size(track->vgt_strmout_bo[i])); 731 return -EINVAL; 732 } 733 } else { 734 dev_warn(p->dev, "No buffer for streamout %d\n", i); 735 return -EINVAL; 736 } 737 } 738 } 739 track->streamout_dirty = false; 740 } 741 742 if (track->sx_misc_kill_all_prims) 743 return 0; 744 745 /* check that we have a cb for each enabled target, we don't check 746 * shader_mask because it seems mesa isn't always setting it :( 747 */ 748 if (track->cb_dirty) { 749 tmp = track->cb_target_mask; 750 751 /* We must check both colorbuffers for RESOLVE. */ 752 if (track->is_resolve) { 753 tmp |= 0xff; 754 } 755 756 for (i = 0; i < 8; i++) { 757 u32 format = G_0280A0_FORMAT(track->cb_color_info[i]); 758 759 if (format != V_0280A0_COLOR_INVALID && 760 (tmp >> (i * 4)) & 0xF) { 761 /* at least one component is enabled */ 762 if (track->cb_color_bo[i] == NULL) { 763 dev_warn(p->dev, "%s:%d mask 0x%08X | 0x%08X no cb for %d\n", 764 __func__, __LINE__, track->cb_target_mask, track->cb_shader_mask, i); 765 return -EINVAL; 766 } 767 /* perform rewrite of CB_COLOR[0-7]_SIZE */ 768 r = r600_cs_track_validate_cb(p, i); 769 if (r) 770 return r; 771 } 772 } 773 track->cb_dirty = false; 774 } 775 776 /* Check depth buffer */ 777 if (track->db_dirty && 778 G_028010_FORMAT(track->db_depth_info) != V_028010_DEPTH_INVALID && 779 (G_028800_STENCIL_ENABLE(track->db_depth_control) || 780 G_028800_Z_ENABLE(track->db_depth_control))) { 781 r = r600_cs_track_validate_db(p); 782 if (r) 783 return r; 784 } 785 786 return 0; 787 } 788 789 /** 790 * r600_cs_packet_parse_vline() - parse userspace VLINE packet 791 * @parser: parser structure holding parsing context. 792 * 793 * This is an R600-specific function for parsing VLINE packets. 794 * Real work is done by r600_cs_common_vline_parse function. 795 * Here we just set up ASIC-specific register table and call 796 * the common implementation function. 797 */ 798 static int r600_cs_packet_parse_vline(struct radeon_cs_parser *p) 799 { 800 static uint32_t vline_start_end[2] = {AVIVO_D1MODE_VLINE_START_END, 801 AVIVO_D2MODE_VLINE_START_END}; 802 static uint32_t vline_status[2] = {AVIVO_D1MODE_VLINE_STATUS, 803 AVIVO_D2MODE_VLINE_STATUS}; 804 805 return r600_cs_common_vline_parse(p, vline_start_end, vline_status); 806 } 807 808 /** 809 * r600_cs_common_vline_parse() - common vline parser 810 * @parser: parser structure holding parsing context. 811 * @vline_start_end: table of vline_start_end registers 812 * @vline_status: table of vline_status registers 813 * 814 * Userspace sends a special sequence for VLINE waits. 815 * PACKET0 - VLINE_START_END + value 816 * PACKET3 - WAIT_REG_MEM poll vline status reg 817 * RELOC (P3) - crtc_id in reloc. 818 * 819 * This function parses this and relocates the VLINE START END 820 * and WAIT_REG_MEM packets to the correct crtc. 821 * It also detects a switched off crtc and nulls out the 822 * wait in that case. This function is common for all ASICs that 823 * are R600 and newer. The parsing algorithm is the same, and only 824 * differs in which registers are used. 825 * 826 * Caller is the ASIC-specific function which passes the parser 827 * context and ASIC-specific register table 828 */ 829 int r600_cs_common_vline_parse(struct radeon_cs_parser *p, 830 uint32_t *vline_start_end, 831 uint32_t *vline_status) 832 { 833 struct drm_crtc *crtc; 834 struct radeon_crtc *radeon_crtc; 835 struct radeon_cs_packet p3reloc, wait_reg_mem; 836 int crtc_id; 837 int r; 838 uint32_t header, h_idx, reg, wait_reg_mem_info; 839 volatile uint32_t *ib; 840 841 ib = p->ib.ptr; 842 843 /* parse the WAIT_REG_MEM */ 844 r = radeon_cs_packet_parse(p, &wait_reg_mem, p->idx); 845 if (r) 846 return r; 847 848 /* check its a WAIT_REG_MEM */ 849 if (wait_reg_mem.type != RADEON_PACKET_TYPE3 || 850 wait_reg_mem.opcode != PACKET3_WAIT_REG_MEM) { 851 DRM_ERROR("vline wait missing WAIT_REG_MEM segment\n"); 852 return -EINVAL; 853 } 854 855 wait_reg_mem_info = radeon_get_ib_value(p, wait_reg_mem.idx + 1); 856 /* bit 4 is reg (0) or mem (1) */ 857 if (wait_reg_mem_info & 0x10) { 858 DRM_ERROR("vline WAIT_REG_MEM waiting on MEM instead of REG\n"); 859 return -EINVAL; 860 } 861 /* bit 8 is me (0) or pfp (1) */ 862 if (wait_reg_mem_info & 0x100) { 863 DRM_ERROR("vline WAIT_REG_MEM waiting on PFP instead of ME\n"); 864 return -EINVAL; 865 } 866 /* waiting for value to be equal */ 867 if ((wait_reg_mem_info & 0x7) != 0x3) { 868 DRM_ERROR("vline WAIT_REG_MEM function not equal\n"); 869 return -EINVAL; 870 } 871 if ((radeon_get_ib_value(p, wait_reg_mem.idx + 2) << 2) != vline_status[0]) { 872 DRM_ERROR("vline WAIT_REG_MEM bad reg\n"); 873 return -EINVAL; 874 } 875 876 if (radeon_get_ib_value(p, wait_reg_mem.idx + 5) != RADEON_VLINE_STAT) { 877 DRM_ERROR("vline WAIT_REG_MEM bad bit mask\n"); 878 return -EINVAL; 879 } 880 881 /* jump over the NOP */ 882 r = radeon_cs_packet_parse(p, &p3reloc, p->idx + wait_reg_mem.count + 2); 883 if (r) 884 return r; 885 886 h_idx = p->idx - 2; 887 p->idx += wait_reg_mem.count + 2; 888 p->idx += p3reloc.count + 2; 889 890 header = radeon_get_ib_value(p, h_idx); 891 crtc_id = radeon_get_ib_value(p, h_idx + 2 + 7 + 1); 892 reg = R600_CP_PACKET0_GET_REG(header); 893 894 crtc = drm_crtc_find(p->rdev->ddev, crtc_id); 895 if (!crtc) { 896 DRM_ERROR("cannot find crtc %d\n", crtc_id); 897 return -ENOENT; 898 } 899 radeon_crtc = to_radeon_crtc(crtc); 900 crtc_id = radeon_crtc->crtc_id; 901 902 if (!crtc->enabled) { 903 /* CRTC isn't enabled - we need to nop out the WAIT_REG_MEM */ 904 ib[h_idx + 2] = PACKET2(0); 905 ib[h_idx + 3] = PACKET2(0); 906 ib[h_idx + 4] = PACKET2(0); 907 ib[h_idx + 5] = PACKET2(0); 908 ib[h_idx + 6] = PACKET2(0); 909 ib[h_idx + 7] = PACKET2(0); 910 ib[h_idx + 8] = PACKET2(0); 911 } else if (reg == vline_start_end[0]) { 912 header &= ~R600_CP_PACKET0_REG_MASK; 913 header |= vline_start_end[crtc_id] >> 2; 914 ib[h_idx] = header; 915 ib[h_idx + 4] = vline_status[crtc_id] >> 2; 916 } else { 917 DRM_ERROR("unknown crtc reloc\n"); 918 return -EINVAL; 919 } 920 return 0; 921 } 922 923 static int r600_packet0_check(struct radeon_cs_parser *p, 924 struct radeon_cs_packet *pkt, 925 unsigned idx, unsigned reg) 926 { 927 int r; 928 929 switch (reg) { 930 case AVIVO_D1MODE_VLINE_START_END: 931 r = r600_cs_packet_parse_vline(p); 932 if (r) { 933 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 934 idx, reg); 935 return r; 936 } 937 break; 938 default: 939 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n", 940 reg, idx); 941 return -EINVAL; 942 } 943 return 0; 944 } 945 946 static int r600_cs_parse_packet0(struct radeon_cs_parser *p, 947 struct radeon_cs_packet *pkt) 948 { 949 unsigned reg, i; 950 unsigned idx; 951 int r; 952 953 idx = pkt->idx + 1; 954 reg = pkt->reg; 955 for (i = 0; i <= pkt->count; i++, idx++, reg += 4) { 956 r = r600_packet0_check(p, pkt, idx, reg); 957 if (r) { 958 return r; 959 } 960 } 961 return 0; 962 } 963 964 /** 965 * r600_cs_check_reg() - check if register is authorized or not 966 * @parser: parser structure holding parsing context 967 * @reg: register we are testing 968 * @idx: index into the cs buffer 969 * 970 * This function will test against r600_reg_safe_bm and return 0 971 * if register is safe. If register is not flag as safe this function 972 * will test it against a list of register needind special handling. 973 */ 974 static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) 975 { 976 struct r600_cs_track *track = (struct r600_cs_track *)p->track; 977 struct radeon_bo_list *reloc; 978 u32 m, i, tmp, *ib; 979 int r; 980 981 i = (reg >> 7); 982 if (i >= ARRAY_SIZE(r600_reg_safe_bm)) { 983 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); 984 return -EINVAL; 985 } 986 m = 1 << ((reg >> 2) & 31); 987 if (!(r600_reg_safe_bm[i] & m)) 988 return 0; 989 ib = p->ib.ptr; 990 switch (reg) { 991 /* force following reg to 0 in an attempt to disable out buffer 992 * which will need us to better understand how it works to perform 993 * security check on it (Jerome) 994 */ 995 case R_0288A8_SQ_ESGS_RING_ITEMSIZE: 996 case R_008C44_SQ_ESGS_RING_SIZE: 997 case R_0288B0_SQ_ESTMP_RING_ITEMSIZE: 998 case R_008C54_SQ_ESTMP_RING_SIZE: 999 case R_0288C0_SQ_FBUF_RING_ITEMSIZE: 1000 case R_008C74_SQ_FBUF_RING_SIZE: 1001 case R_0288B4_SQ_GSTMP_RING_ITEMSIZE: 1002 case R_008C5C_SQ_GSTMP_RING_SIZE: 1003 case R_0288AC_SQ_GSVS_RING_ITEMSIZE: 1004 case R_008C4C_SQ_GSVS_RING_SIZE: 1005 case R_0288BC_SQ_PSTMP_RING_ITEMSIZE: 1006 case R_008C6C_SQ_PSTMP_RING_SIZE: 1007 case R_0288C4_SQ_REDUC_RING_ITEMSIZE: 1008 case R_008C7C_SQ_REDUC_RING_SIZE: 1009 case R_0288B8_SQ_VSTMP_RING_ITEMSIZE: 1010 case R_008C64_SQ_VSTMP_RING_SIZE: 1011 case R_0288C8_SQ_GS_VERT_ITEMSIZE: 1012 /* get value to populate the IB don't remove */ 1013 /*tmp =radeon_get_ib_value(p, idx); 1014 ib[idx] = 0;*/ 1015 break; 1016 case SQ_ESGS_RING_BASE: 1017 case SQ_GSVS_RING_BASE: 1018 case SQ_ESTMP_RING_BASE: 1019 case SQ_GSTMP_RING_BASE: 1020 case SQ_PSTMP_RING_BASE: 1021 case SQ_VSTMP_RING_BASE: 1022 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1023 if (r) { 1024 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1025 "0x%04X\n", reg); 1026 return -EINVAL; 1027 } 1028 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); 1029 break; 1030 case SQ_CONFIG: 1031 track->sq_config = radeon_get_ib_value(p, idx); 1032 break; 1033 case R_028800_DB_DEPTH_CONTROL: 1034 track->db_depth_control = radeon_get_ib_value(p, idx); 1035 track->db_dirty = true; 1036 break; 1037 case R_028010_DB_DEPTH_INFO: 1038 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) && 1039 radeon_cs_packet_next_is_pkt3_nop(p)) { 1040 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1041 if (r) { 1042 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1043 "0x%04X\n", reg); 1044 return -EINVAL; 1045 } 1046 track->db_depth_info = radeon_get_ib_value(p, idx); 1047 ib[idx] &= C_028010_ARRAY_MODE; 1048 track->db_depth_info &= C_028010_ARRAY_MODE; 1049 if (reloc->tiling_flags & RADEON_TILING_MACRO) { 1050 ib[idx] |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1); 1051 track->db_depth_info |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1); 1052 } else { 1053 ib[idx] |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1); 1054 track->db_depth_info |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1); 1055 } 1056 } else { 1057 track->db_depth_info = radeon_get_ib_value(p, idx); 1058 } 1059 track->db_dirty = true; 1060 break; 1061 case R_028004_DB_DEPTH_VIEW: 1062 track->db_depth_view = radeon_get_ib_value(p, idx); 1063 track->db_dirty = true; 1064 break; 1065 case R_028000_DB_DEPTH_SIZE: 1066 track->db_depth_size = radeon_get_ib_value(p, idx); 1067 track->db_depth_size_idx = idx; 1068 track->db_dirty = true; 1069 break; 1070 case R_028AB0_VGT_STRMOUT_EN: 1071 track->vgt_strmout_en = radeon_get_ib_value(p, idx); 1072 track->streamout_dirty = true; 1073 break; 1074 case R_028B20_VGT_STRMOUT_BUFFER_EN: 1075 track->vgt_strmout_buffer_en = radeon_get_ib_value(p, idx); 1076 track->streamout_dirty = true; 1077 break; 1078 case VGT_STRMOUT_BUFFER_BASE_0: 1079 case VGT_STRMOUT_BUFFER_BASE_1: 1080 case VGT_STRMOUT_BUFFER_BASE_2: 1081 case VGT_STRMOUT_BUFFER_BASE_3: 1082 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1083 if (r) { 1084 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1085 "0x%04X\n", reg); 1086 return -EINVAL; 1087 } 1088 tmp = (reg - VGT_STRMOUT_BUFFER_BASE_0) / 16; 1089 track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8; 1090 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); 1091 track->vgt_strmout_bo[tmp] = reloc->robj; 1092 track->vgt_strmout_bo_mc[tmp] = reloc->gpu_offset; 1093 track->streamout_dirty = true; 1094 break; 1095 case VGT_STRMOUT_BUFFER_SIZE_0: 1096 case VGT_STRMOUT_BUFFER_SIZE_1: 1097 case VGT_STRMOUT_BUFFER_SIZE_2: 1098 case VGT_STRMOUT_BUFFER_SIZE_3: 1099 tmp = (reg - VGT_STRMOUT_BUFFER_SIZE_0) / 16; 1100 /* size in register is DWs, convert to bytes */ 1101 track->vgt_strmout_size[tmp] = radeon_get_ib_value(p, idx) * 4; 1102 track->streamout_dirty = true; 1103 break; 1104 case CP_COHER_BASE: 1105 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1106 if (r) { 1107 dev_warn(p->dev, "missing reloc for CP_COHER_BASE " 1108 "0x%04X\n", reg); 1109 return -EINVAL; 1110 } 1111 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); 1112 break; 1113 case R_028238_CB_TARGET_MASK: 1114 track->cb_target_mask = radeon_get_ib_value(p, idx); 1115 track->cb_dirty = true; 1116 break; 1117 case R_02823C_CB_SHADER_MASK: 1118 track->cb_shader_mask = radeon_get_ib_value(p, idx); 1119 break; 1120 case R_028C04_PA_SC_AA_CONFIG: 1121 tmp = G_028C04_MSAA_NUM_SAMPLES(radeon_get_ib_value(p, idx)); 1122 track->log_nsamples = tmp; 1123 track->nsamples = 1 << tmp; 1124 track->cb_dirty = true; 1125 break; 1126 case R_028808_CB_COLOR_CONTROL: 1127 tmp = G_028808_SPECIAL_OP(radeon_get_ib_value(p, idx)); 1128 track->is_resolve = tmp == V_028808_SPECIAL_RESOLVE_BOX; 1129 track->cb_dirty = true; 1130 break; 1131 case R_0280A0_CB_COLOR0_INFO: 1132 case R_0280A4_CB_COLOR1_INFO: 1133 case R_0280A8_CB_COLOR2_INFO: 1134 case R_0280AC_CB_COLOR3_INFO: 1135 case R_0280B0_CB_COLOR4_INFO: 1136 case R_0280B4_CB_COLOR5_INFO: 1137 case R_0280B8_CB_COLOR6_INFO: 1138 case R_0280BC_CB_COLOR7_INFO: 1139 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) && 1140 radeon_cs_packet_next_is_pkt3_nop(p)) { 1141 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1142 if (r) { 1143 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg); 1144 return -EINVAL; 1145 } 1146 tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4; 1147 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx); 1148 if (reloc->tiling_flags & RADEON_TILING_MACRO) { 1149 ib[idx] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1); 1150 track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1); 1151 } else if (reloc->tiling_flags & RADEON_TILING_MICRO) { 1152 ib[idx] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1); 1153 track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1); 1154 } 1155 } else { 1156 tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4; 1157 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx); 1158 } 1159 track->cb_dirty = true; 1160 break; 1161 case R_028080_CB_COLOR0_VIEW: 1162 case R_028084_CB_COLOR1_VIEW: 1163 case R_028088_CB_COLOR2_VIEW: 1164 case R_02808C_CB_COLOR3_VIEW: 1165 case R_028090_CB_COLOR4_VIEW: 1166 case R_028094_CB_COLOR5_VIEW: 1167 case R_028098_CB_COLOR6_VIEW: 1168 case R_02809C_CB_COLOR7_VIEW: 1169 tmp = (reg - R_028080_CB_COLOR0_VIEW) / 4; 1170 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx); 1171 track->cb_dirty = true; 1172 break; 1173 case R_028060_CB_COLOR0_SIZE: 1174 case R_028064_CB_COLOR1_SIZE: 1175 case R_028068_CB_COLOR2_SIZE: 1176 case R_02806C_CB_COLOR3_SIZE: 1177 case R_028070_CB_COLOR4_SIZE: 1178 case R_028074_CB_COLOR5_SIZE: 1179 case R_028078_CB_COLOR6_SIZE: 1180 case R_02807C_CB_COLOR7_SIZE: 1181 tmp = (reg - R_028060_CB_COLOR0_SIZE) / 4; 1182 track->cb_color_size[tmp] = radeon_get_ib_value(p, idx); 1183 track->cb_color_size_idx[tmp] = idx; 1184 track->cb_dirty = true; 1185 break; 1186 /* This register were added late, there is userspace 1187 * which does provide relocation for those but set 1188 * 0 offset. In order to avoid breaking old userspace 1189 * we detect this and set address to point to last 1190 * CB_COLOR0_BASE, note that if userspace doesn't set 1191 * CB_COLOR0_BASE before this register we will report 1192 * error. Old userspace always set CB_COLOR0_BASE 1193 * before any of this. 1194 */ 1195 case R_0280E0_CB_COLOR0_FRAG: 1196 case R_0280E4_CB_COLOR1_FRAG: 1197 case R_0280E8_CB_COLOR2_FRAG: 1198 case R_0280EC_CB_COLOR3_FRAG: 1199 case R_0280F0_CB_COLOR4_FRAG: 1200 case R_0280F4_CB_COLOR5_FRAG: 1201 case R_0280F8_CB_COLOR6_FRAG: 1202 case R_0280FC_CB_COLOR7_FRAG: 1203 tmp = (reg - R_0280E0_CB_COLOR0_FRAG) / 4; 1204 if (!radeon_cs_packet_next_is_pkt3_nop(p)) { 1205 if (!track->cb_color_base_last[tmp]) { 1206 dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg); 1207 return -EINVAL; 1208 } 1209 track->cb_color_frag_bo[tmp] = track->cb_color_bo[tmp]; 1210 track->cb_color_frag_offset[tmp] = track->cb_color_bo_offset[tmp]; 1211 ib[idx] = track->cb_color_base_last[tmp]; 1212 } else { 1213 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1214 if (r) { 1215 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg); 1216 return -EINVAL; 1217 } 1218 track->cb_color_frag_bo[tmp] = reloc->robj; 1219 track->cb_color_frag_offset[tmp] = (u64)ib[idx] << 8; 1220 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); 1221 } 1222 if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) { 1223 track->cb_dirty = true; 1224 } 1225 break; 1226 case R_0280C0_CB_COLOR0_TILE: 1227 case R_0280C4_CB_COLOR1_TILE: 1228 case R_0280C8_CB_COLOR2_TILE: 1229 case R_0280CC_CB_COLOR3_TILE: 1230 case R_0280D0_CB_COLOR4_TILE: 1231 case R_0280D4_CB_COLOR5_TILE: 1232 case R_0280D8_CB_COLOR6_TILE: 1233 case R_0280DC_CB_COLOR7_TILE: 1234 tmp = (reg - R_0280C0_CB_COLOR0_TILE) / 4; 1235 if (!radeon_cs_packet_next_is_pkt3_nop(p)) { 1236 if (!track->cb_color_base_last[tmp]) { 1237 dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg); 1238 return -EINVAL; 1239 } 1240 track->cb_color_tile_bo[tmp] = track->cb_color_bo[tmp]; 1241 track->cb_color_tile_offset[tmp] = track->cb_color_bo_offset[tmp]; 1242 ib[idx] = track->cb_color_base_last[tmp]; 1243 } else { 1244 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1245 if (r) { 1246 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg); 1247 return -EINVAL; 1248 } 1249 track->cb_color_tile_bo[tmp] = reloc->robj; 1250 track->cb_color_tile_offset[tmp] = (u64)ib[idx] << 8; 1251 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); 1252 } 1253 if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) { 1254 track->cb_dirty = true; 1255 } 1256 break; 1257 case R_028100_CB_COLOR0_MASK: 1258 case R_028104_CB_COLOR1_MASK: 1259 case R_028108_CB_COLOR2_MASK: 1260 case R_02810C_CB_COLOR3_MASK: 1261 case R_028110_CB_COLOR4_MASK: 1262 case R_028114_CB_COLOR5_MASK: 1263 case R_028118_CB_COLOR6_MASK: 1264 case R_02811C_CB_COLOR7_MASK: 1265 tmp = (reg - R_028100_CB_COLOR0_MASK) / 4; 1266 track->cb_color_mask[tmp] = radeon_get_ib_value(p, idx); 1267 if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) { 1268 track->cb_dirty = true; 1269 } 1270 break; 1271 case CB_COLOR0_BASE: 1272 case CB_COLOR1_BASE: 1273 case CB_COLOR2_BASE: 1274 case CB_COLOR3_BASE: 1275 case CB_COLOR4_BASE: 1276 case CB_COLOR5_BASE: 1277 case CB_COLOR6_BASE: 1278 case CB_COLOR7_BASE: 1279 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1280 if (r) { 1281 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1282 "0x%04X\n", reg); 1283 return -EINVAL; 1284 } 1285 tmp = (reg - CB_COLOR0_BASE) / 4; 1286 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8; 1287 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); 1288 track->cb_color_base_last[tmp] = ib[idx]; 1289 track->cb_color_bo[tmp] = reloc->robj; 1290 track->cb_color_bo_mc[tmp] = reloc->gpu_offset; 1291 track->cb_dirty = true; 1292 break; 1293 case DB_DEPTH_BASE: 1294 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1295 if (r) { 1296 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1297 "0x%04X\n", reg); 1298 return -EINVAL; 1299 } 1300 track->db_offset = radeon_get_ib_value(p, idx) << 8; 1301 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); 1302 track->db_bo = reloc->robj; 1303 track->db_bo_mc = reloc->gpu_offset; 1304 track->db_dirty = true; 1305 break; 1306 case DB_HTILE_DATA_BASE: 1307 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1308 if (r) { 1309 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1310 "0x%04X\n", reg); 1311 return -EINVAL; 1312 } 1313 track->htile_offset = radeon_get_ib_value(p, idx) << 8; 1314 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); 1315 track->htile_bo = reloc->robj; 1316 track->db_dirty = true; 1317 break; 1318 case DB_HTILE_SURFACE: 1319 track->htile_surface = radeon_get_ib_value(p, idx); 1320 /* force 8x8 htile width and height */ 1321 ib[idx] |= 3; 1322 track->db_dirty = true; 1323 break; 1324 case SQ_PGM_START_FS: 1325 case SQ_PGM_START_ES: 1326 case SQ_PGM_START_VS: 1327 case SQ_PGM_START_GS: 1328 case SQ_PGM_START_PS: 1329 case SQ_ALU_CONST_CACHE_GS_0: 1330 case SQ_ALU_CONST_CACHE_GS_1: 1331 case SQ_ALU_CONST_CACHE_GS_2: 1332 case SQ_ALU_CONST_CACHE_GS_3: 1333 case SQ_ALU_CONST_CACHE_GS_4: 1334 case SQ_ALU_CONST_CACHE_GS_5: 1335 case SQ_ALU_CONST_CACHE_GS_6: 1336 case SQ_ALU_CONST_CACHE_GS_7: 1337 case SQ_ALU_CONST_CACHE_GS_8: 1338 case SQ_ALU_CONST_CACHE_GS_9: 1339 case SQ_ALU_CONST_CACHE_GS_10: 1340 case SQ_ALU_CONST_CACHE_GS_11: 1341 case SQ_ALU_CONST_CACHE_GS_12: 1342 case SQ_ALU_CONST_CACHE_GS_13: 1343 case SQ_ALU_CONST_CACHE_GS_14: 1344 case SQ_ALU_CONST_CACHE_GS_15: 1345 case SQ_ALU_CONST_CACHE_PS_0: 1346 case SQ_ALU_CONST_CACHE_PS_1: 1347 case SQ_ALU_CONST_CACHE_PS_2: 1348 case SQ_ALU_CONST_CACHE_PS_3: 1349 case SQ_ALU_CONST_CACHE_PS_4: 1350 case SQ_ALU_CONST_CACHE_PS_5: 1351 case SQ_ALU_CONST_CACHE_PS_6: 1352 case SQ_ALU_CONST_CACHE_PS_7: 1353 case SQ_ALU_CONST_CACHE_PS_8: 1354 case SQ_ALU_CONST_CACHE_PS_9: 1355 case SQ_ALU_CONST_CACHE_PS_10: 1356 case SQ_ALU_CONST_CACHE_PS_11: 1357 case SQ_ALU_CONST_CACHE_PS_12: 1358 case SQ_ALU_CONST_CACHE_PS_13: 1359 case SQ_ALU_CONST_CACHE_PS_14: 1360 case SQ_ALU_CONST_CACHE_PS_15: 1361 case SQ_ALU_CONST_CACHE_VS_0: 1362 case SQ_ALU_CONST_CACHE_VS_1: 1363 case SQ_ALU_CONST_CACHE_VS_2: 1364 case SQ_ALU_CONST_CACHE_VS_3: 1365 case SQ_ALU_CONST_CACHE_VS_4: 1366 case SQ_ALU_CONST_CACHE_VS_5: 1367 case SQ_ALU_CONST_CACHE_VS_6: 1368 case SQ_ALU_CONST_CACHE_VS_7: 1369 case SQ_ALU_CONST_CACHE_VS_8: 1370 case SQ_ALU_CONST_CACHE_VS_9: 1371 case SQ_ALU_CONST_CACHE_VS_10: 1372 case SQ_ALU_CONST_CACHE_VS_11: 1373 case SQ_ALU_CONST_CACHE_VS_12: 1374 case SQ_ALU_CONST_CACHE_VS_13: 1375 case SQ_ALU_CONST_CACHE_VS_14: 1376 case SQ_ALU_CONST_CACHE_VS_15: 1377 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1378 if (r) { 1379 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1380 "0x%04X\n", reg); 1381 return -EINVAL; 1382 } 1383 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); 1384 break; 1385 case SX_MEMORY_EXPORT_BASE: 1386 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1387 if (r) { 1388 dev_warn(p->dev, "bad SET_CONFIG_REG " 1389 "0x%04X\n", reg); 1390 return -EINVAL; 1391 } 1392 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); 1393 break; 1394 case SX_MISC: 1395 track->sx_misc_kill_all_prims = (radeon_get_ib_value(p, idx) & 0x1) != 0; 1396 break; 1397 default: 1398 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); 1399 return -EINVAL; 1400 } 1401 return 0; 1402 } 1403 1404 unsigned r600_mip_minify(unsigned size, unsigned level) 1405 { 1406 unsigned val; 1407 1408 val = max(1U, size >> level); 1409 if (level > 0) 1410 val = roundup_pow_of_two(val); 1411 return val; 1412 } 1413 1414 static void r600_texture_size(unsigned nfaces, unsigned blevel, unsigned llevel, 1415 unsigned w0, unsigned h0, unsigned d0, unsigned nsamples, unsigned format, 1416 unsigned block_align, unsigned height_align, unsigned base_align, 1417 unsigned *l0_size, unsigned *mipmap_size) 1418 { 1419 unsigned offset, i, level; 1420 unsigned width, height, depth, size; 1421 unsigned blocksize; 1422 unsigned nbx, nby; 1423 unsigned nlevels = llevel - blevel + 1; 1424 1425 *l0_size = -1; 1426 blocksize = r600_fmt_get_blocksize(format); 1427 1428 w0 = r600_mip_minify(w0, 0); 1429 h0 = r600_mip_minify(h0, 0); 1430 d0 = r600_mip_minify(d0, 0); 1431 for(i = 0, offset = 0, level = blevel; i < nlevels; i++, level++) { 1432 width = r600_mip_minify(w0, i); 1433 nbx = r600_fmt_get_nblocksx(format, width); 1434 1435 nbx = round_up(nbx, block_align); 1436 1437 height = r600_mip_minify(h0, i); 1438 nby = r600_fmt_get_nblocksy(format, height); 1439 nby = round_up(nby, height_align); 1440 1441 depth = r600_mip_minify(d0, i); 1442 1443 size = nbx * nby * blocksize * nsamples; 1444 if (nfaces) 1445 size *= nfaces; 1446 else 1447 size *= depth; 1448 1449 if (i == 0) 1450 *l0_size = size; 1451 1452 if (i == 0 || i == 1) 1453 offset = round_up(offset, base_align); 1454 1455 offset += size; 1456 } 1457 *mipmap_size = offset; 1458 if (llevel == 0) 1459 *mipmap_size = *l0_size; 1460 if (!blevel) 1461 *mipmap_size -= *l0_size; 1462 } 1463 1464 /** 1465 * r600_check_texture_resource() - check if register is authorized or not 1466 * @p: parser structure holding parsing context 1467 * @idx: index into the cs buffer 1468 * @texture: texture's bo structure 1469 * @mipmap: mipmap's bo structure 1470 * 1471 * This function will check that the resource has valid field and that 1472 * the texture and mipmap bo object are big enough to cover this resource. 1473 */ 1474 static int r600_check_texture_resource(struct radeon_cs_parser *p, u32 idx, 1475 struct radeon_bo *texture, 1476 struct radeon_bo *mipmap, 1477 u64 base_offset, 1478 u64 mip_offset, 1479 u32 tiling_flags) 1480 { 1481 struct r600_cs_track *track = p->track; 1482 u32 dim, nfaces, llevel, blevel, w0, h0, d0; 1483 u32 word0, word1, l0_size, mipmap_size, word2, word3, word4, word5; 1484 u32 height_align, pitch, pitch_align, depth_align; 1485 u32 barray, larray; 1486 u64 base_align; 1487 struct array_mode_checker array_check; 1488 u32 format; 1489 bool is_array; 1490 1491 /* on legacy kernel we don't perform advanced check */ 1492 if (p->rdev == NULL) 1493 return 0; 1494 1495 /* convert to bytes */ 1496 base_offset <<= 8; 1497 mip_offset <<= 8; 1498 1499 word0 = radeon_get_ib_value(p, idx + 0); 1500 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 1501 if (tiling_flags & RADEON_TILING_MACRO) 1502 word0 |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1); 1503 else if (tiling_flags & RADEON_TILING_MICRO) 1504 word0 |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1); 1505 } 1506 word1 = radeon_get_ib_value(p, idx + 1); 1507 word2 = radeon_get_ib_value(p, idx + 2) << 8; 1508 word3 = radeon_get_ib_value(p, idx + 3) << 8; 1509 word4 = radeon_get_ib_value(p, idx + 4); 1510 word5 = radeon_get_ib_value(p, idx + 5); 1511 dim = G_038000_DIM(word0); 1512 w0 = G_038000_TEX_WIDTH(word0) + 1; 1513 pitch = (G_038000_PITCH(word0) + 1) * 8; 1514 h0 = G_038004_TEX_HEIGHT(word1) + 1; 1515 d0 = G_038004_TEX_DEPTH(word1); 1516 format = G_038004_DATA_FORMAT(word1); 1517 blevel = G_038010_BASE_LEVEL(word4); 1518 llevel = G_038014_LAST_LEVEL(word5); 1519 /* pitch in texels */ 1520 array_check.array_mode = G_038000_TILE_MODE(word0); 1521 array_check.group_size = track->group_size; 1522 array_check.nbanks = track->nbanks; 1523 array_check.npipes = track->npipes; 1524 array_check.nsamples = 1; 1525 array_check.blocksize = r600_fmt_get_blocksize(format); 1526 nfaces = 1; 1527 is_array = false; 1528 switch (dim) { 1529 case V_038000_SQ_TEX_DIM_1D: 1530 case V_038000_SQ_TEX_DIM_2D: 1531 case V_038000_SQ_TEX_DIM_3D: 1532 break; 1533 case V_038000_SQ_TEX_DIM_CUBEMAP: 1534 if (p->family >= CHIP_RV770) 1535 nfaces = 8; 1536 else 1537 nfaces = 6; 1538 break; 1539 case V_038000_SQ_TEX_DIM_1D_ARRAY: 1540 case V_038000_SQ_TEX_DIM_2D_ARRAY: 1541 is_array = true; 1542 break; 1543 case V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA: 1544 is_array = true; 1545 /* fall through */ 1546 case V_038000_SQ_TEX_DIM_2D_MSAA: 1547 array_check.nsamples = 1 << llevel; 1548 llevel = 0; 1549 break; 1550 default: 1551 dev_warn(p->dev, "this kernel doesn't support %d texture dim\n", G_038000_DIM(word0)); 1552 return -EINVAL; 1553 } 1554 if (!r600_fmt_is_valid_texture(format, p->family)) { 1555 dev_warn(p->dev, "%s:%d texture invalid format %d\n", 1556 __func__, __LINE__, format); 1557 return -EINVAL; 1558 } 1559 1560 if (r600_get_array_mode_alignment(&array_check, 1561 &pitch_align, &height_align, &depth_align, &base_align)) { 1562 dev_warn(p->dev, "%s:%d tex array mode (%d) invalid\n", 1563 __func__, __LINE__, G_038000_TILE_MODE(word0)); 1564 return -EINVAL; 1565 } 1566 1567 /* XXX check height as well... */ 1568 1569 if (!IS_ALIGNED(pitch, pitch_align)) { 1570 dev_warn(p->dev, "%s:%d tex pitch (%d, 0x%x, %d) invalid\n", 1571 __func__, __LINE__, pitch, pitch_align, G_038000_TILE_MODE(word0)); 1572 return -EINVAL; 1573 } 1574 if (!IS_ALIGNED(base_offset, base_align)) { 1575 dev_warn(p->dev, "%s:%d tex base offset (0x%"PRIx64", 0x%"PRIx64", %d) invalid\n", 1576 __func__, __LINE__, base_offset, base_align, G_038000_TILE_MODE(word0)); 1577 return -EINVAL; 1578 } 1579 if (!IS_ALIGNED(mip_offset, base_align)) { 1580 dev_warn(p->dev, "%s:%d tex mip offset (0x%"PRIx64", 0x%"PRIx64", %d) invalid\n", 1581 __func__, __LINE__, mip_offset, base_align, G_038000_TILE_MODE(word0)); 1582 return -EINVAL; 1583 } 1584 1585 if (blevel > llevel) { 1586 dev_warn(p->dev, "texture blevel %d > llevel %d\n", 1587 blevel, llevel); 1588 } 1589 if (is_array) { 1590 barray = G_038014_BASE_ARRAY(word5); 1591 larray = G_038014_LAST_ARRAY(word5); 1592 1593 nfaces = larray - barray + 1; 1594 } 1595 r600_texture_size(nfaces, blevel, llevel, w0, h0, d0, array_check.nsamples, format, 1596 pitch_align, height_align, base_align, 1597 &l0_size, &mipmap_size); 1598 /* using get ib will give us the offset into the texture bo */ 1599 if ((l0_size + word2) > radeon_bo_size(texture)) { 1600 dev_warn(p->dev, "texture bo too small ((%d %d) (%d %d) %d %d %d -> %d have %ld)\n", 1601 w0, h0, pitch_align, height_align, 1602 array_check.array_mode, format, word2, 1603 l0_size, radeon_bo_size(texture)); 1604 dev_warn(p->dev, "alignments %d %d %d %"PRIu64"\n", pitch, pitch_align, height_align, base_align); 1605 return -EINVAL; 1606 } 1607 /* using get ib will give us the offset into the mipmap bo */ 1608 if ((mipmap_size + word3) > radeon_bo_size(mipmap)) { 1609 /*dev_warn(p->dev, "mipmap bo too small (%d %d %d %d %d %d -> %d have %ld)\n", 1610 w0, h0, format, blevel, nlevels, word3, mipmap_size, radeon_bo_size(texture));*/ 1611 } 1612 return 0; 1613 } 1614 1615 static bool r600_is_safe_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) 1616 { 1617 u32 m, i; 1618 1619 i = (reg >> 7); 1620 if (i >= ARRAY_SIZE(r600_reg_safe_bm)) { 1621 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); 1622 return false; 1623 } 1624 m = 1 << ((reg >> 2) & 31); 1625 if (!(r600_reg_safe_bm[i] & m)) 1626 return true; 1627 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); 1628 return false; 1629 } 1630 1631 static int r600_packet3_check(struct radeon_cs_parser *p, 1632 struct radeon_cs_packet *pkt) 1633 { 1634 struct radeon_bo_list *reloc; 1635 struct r600_cs_track *track; 1636 volatile u32 *ib; 1637 unsigned idx; 1638 unsigned i; 1639 unsigned start_reg, end_reg, reg; 1640 int r; 1641 u32 idx_value; 1642 1643 track = (struct r600_cs_track *)p->track; 1644 ib = p->ib.ptr; 1645 idx = pkt->idx + 1; 1646 idx_value = radeon_get_ib_value(p, idx); 1647 1648 switch (pkt->opcode) { 1649 case PACKET3_SET_PREDICATION: 1650 { 1651 int pred_op; 1652 int tmp; 1653 uint64_t offset; 1654 1655 if (pkt->count != 1) { 1656 DRM_ERROR("bad SET PREDICATION\n"); 1657 return -EINVAL; 1658 } 1659 1660 tmp = radeon_get_ib_value(p, idx + 1); 1661 pred_op = (tmp >> 16) & 0x7; 1662 1663 /* for the clear predicate operation */ 1664 if (pred_op == 0) 1665 return 0; 1666 1667 if (pred_op > 2) { 1668 DRM_ERROR("bad SET PREDICATION operation %d\n", pred_op); 1669 return -EINVAL; 1670 } 1671 1672 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1673 if (r) { 1674 DRM_ERROR("bad SET PREDICATION\n"); 1675 return -EINVAL; 1676 } 1677 1678 offset = reloc->gpu_offset + 1679 (idx_value & 0xfffffff0) + 1680 ((u64)(tmp & 0xff) << 32); 1681 1682 ib[idx + 0] = offset; 1683 ib[idx + 1] = (tmp & 0xffffff00) | (upper_32_bits(offset) & 0xff); 1684 } 1685 break; 1686 1687 case PACKET3_START_3D_CMDBUF: 1688 if (p->family >= CHIP_RV770 || pkt->count) { 1689 DRM_ERROR("bad START_3D\n"); 1690 return -EINVAL; 1691 } 1692 break; 1693 case PACKET3_CONTEXT_CONTROL: 1694 if (pkt->count != 1) { 1695 DRM_ERROR("bad CONTEXT_CONTROL\n"); 1696 return -EINVAL; 1697 } 1698 break; 1699 case PACKET3_INDEX_TYPE: 1700 case PACKET3_NUM_INSTANCES: 1701 if (pkt->count) { 1702 DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES\n"); 1703 return -EINVAL; 1704 } 1705 break; 1706 case PACKET3_DRAW_INDEX: 1707 { 1708 uint64_t offset; 1709 if (pkt->count != 3) { 1710 DRM_ERROR("bad DRAW_INDEX\n"); 1711 return -EINVAL; 1712 } 1713 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1714 if (r) { 1715 DRM_ERROR("bad DRAW_INDEX\n"); 1716 return -EINVAL; 1717 } 1718 1719 offset = reloc->gpu_offset + 1720 idx_value + 1721 ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32); 1722 1723 ib[idx+0] = offset; 1724 ib[idx+1] = upper_32_bits(offset) & 0xff; 1725 1726 r = r600_cs_track_check(p); 1727 if (r) { 1728 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); 1729 return r; 1730 } 1731 break; 1732 } 1733 case PACKET3_DRAW_INDEX_AUTO: 1734 if (pkt->count != 1) { 1735 DRM_ERROR("bad DRAW_INDEX_AUTO\n"); 1736 return -EINVAL; 1737 } 1738 r = r600_cs_track_check(p); 1739 if (r) { 1740 dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx); 1741 return r; 1742 } 1743 break; 1744 case PACKET3_DRAW_INDEX_IMMD_BE: 1745 case PACKET3_DRAW_INDEX_IMMD: 1746 if (pkt->count < 2) { 1747 DRM_ERROR("bad DRAW_INDEX_IMMD\n"); 1748 return -EINVAL; 1749 } 1750 r = r600_cs_track_check(p); 1751 if (r) { 1752 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); 1753 return r; 1754 } 1755 break; 1756 case PACKET3_WAIT_REG_MEM: 1757 if (pkt->count != 5) { 1758 DRM_ERROR("bad WAIT_REG_MEM\n"); 1759 return -EINVAL; 1760 } 1761 /* bit 4 is reg (0) or mem (1) */ 1762 if (idx_value & 0x10) { 1763 uint64_t offset; 1764 1765 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1766 if (r) { 1767 DRM_ERROR("bad WAIT_REG_MEM\n"); 1768 return -EINVAL; 1769 } 1770 1771 offset = reloc->gpu_offset + 1772 (radeon_get_ib_value(p, idx+1) & 0xfffffff0) + 1773 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); 1774 1775 ib[idx+1] = (ib[idx+1] & 0x3) | (offset & 0xfffffff0); 1776 ib[idx+2] = upper_32_bits(offset) & 0xff; 1777 } else if (idx_value & 0x100) { 1778 DRM_ERROR("cannot use PFP on REG wait\n"); 1779 return -EINVAL; 1780 } 1781 break; 1782 case PACKET3_CP_DMA: 1783 { 1784 u32 command, size; 1785 u64 offset, tmp; 1786 if (pkt->count != 4) { 1787 DRM_ERROR("bad CP DMA\n"); 1788 return -EINVAL; 1789 } 1790 command = radeon_get_ib_value(p, idx+4); 1791 size = command & 0x1fffff; 1792 if (command & PACKET3_CP_DMA_CMD_SAS) { 1793 /* src address space is register */ 1794 DRM_ERROR("CP DMA SAS not supported\n"); 1795 return -EINVAL; 1796 } else { 1797 if (command & PACKET3_CP_DMA_CMD_SAIC) { 1798 DRM_ERROR("CP DMA SAIC only supported for registers\n"); 1799 return -EINVAL; 1800 } 1801 /* src address space is memory */ 1802 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1803 if (r) { 1804 DRM_ERROR("bad CP DMA SRC\n"); 1805 return -EINVAL; 1806 } 1807 1808 tmp = radeon_get_ib_value(p, idx) + 1809 ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32); 1810 1811 offset = reloc->gpu_offset + tmp; 1812 1813 if ((tmp + size) > radeon_bo_size(reloc->robj)) { 1814 dev_warn(p->dev, "CP DMA src buffer too small (%"PRIu64" %lu)\n", 1815 tmp + size, radeon_bo_size(reloc->robj)); 1816 return -EINVAL; 1817 } 1818 1819 ib[idx] = offset; 1820 ib[idx+1] = (ib[idx+1] & 0xffffff00) | (upper_32_bits(offset) & 0xff); 1821 } 1822 if (command & PACKET3_CP_DMA_CMD_DAS) { 1823 /* dst address space is register */ 1824 DRM_ERROR("CP DMA DAS not supported\n"); 1825 return -EINVAL; 1826 } else { 1827 /* dst address space is memory */ 1828 if (command & PACKET3_CP_DMA_CMD_DAIC) { 1829 DRM_ERROR("CP DMA DAIC only supported for registers\n"); 1830 return -EINVAL; 1831 } 1832 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1833 if (r) { 1834 DRM_ERROR("bad CP DMA DST\n"); 1835 return -EINVAL; 1836 } 1837 1838 tmp = radeon_get_ib_value(p, idx+2) + 1839 ((u64)(radeon_get_ib_value(p, idx+3) & 0xff) << 32); 1840 1841 offset = reloc->gpu_offset + tmp; 1842 1843 if ((tmp + size) > radeon_bo_size(reloc->robj)) { 1844 dev_warn(p->dev, "CP DMA dst buffer too small (%"PRIu64" %lu)\n", 1845 tmp + size, radeon_bo_size(reloc->robj)); 1846 return -EINVAL; 1847 } 1848 1849 ib[idx+2] = offset; 1850 ib[idx+3] = upper_32_bits(offset) & 0xff; 1851 } 1852 break; 1853 } 1854 case PACKET3_SURFACE_SYNC: 1855 if (pkt->count != 3) { 1856 DRM_ERROR("bad SURFACE_SYNC\n"); 1857 return -EINVAL; 1858 } 1859 /* 0xffffffff/0x0 is flush all cache flag */ 1860 if (radeon_get_ib_value(p, idx + 1) != 0xffffffff || 1861 radeon_get_ib_value(p, idx + 2) != 0) { 1862 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1863 if (r) { 1864 DRM_ERROR("bad SURFACE_SYNC\n"); 1865 return -EINVAL; 1866 } 1867 ib[idx+2] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); 1868 } 1869 break; 1870 case PACKET3_EVENT_WRITE: 1871 if (pkt->count != 2 && pkt->count != 0) { 1872 DRM_ERROR("bad EVENT_WRITE\n"); 1873 return -EINVAL; 1874 } 1875 if (pkt->count) { 1876 uint64_t offset; 1877 1878 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1879 if (r) { 1880 DRM_ERROR("bad EVENT_WRITE\n"); 1881 return -EINVAL; 1882 } 1883 offset = reloc->gpu_offset + 1884 (radeon_get_ib_value(p, idx+1) & 0xfffffff8) + 1885 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); 1886 1887 ib[idx+1] = offset & 0xfffffff8; 1888 ib[idx+2] = upper_32_bits(offset) & 0xff; 1889 } 1890 break; 1891 case PACKET3_EVENT_WRITE_EOP: 1892 { 1893 uint64_t offset; 1894 1895 if (pkt->count != 4) { 1896 DRM_ERROR("bad EVENT_WRITE_EOP\n"); 1897 return -EINVAL; 1898 } 1899 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1900 if (r) { 1901 DRM_ERROR("bad EVENT_WRITE\n"); 1902 return -EINVAL; 1903 } 1904 1905 offset = reloc->gpu_offset + 1906 (radeon_get_ib_value(p, idx+1) & 0xfffffffc) + 1907 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); 1908 1909 ib[idx+1] = offset & 0xfffffffc; 1910 ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff); 1911 break; 1912 } 1913 case PACKET3_SET_CONFIG_REG: 1914 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_OFFSET; 1915 end_reg = 4 * pkt->count + start_reg - 4; 1916 if ((start_reg < PACKET3_SET_CONFIG_REG_OFFSET) || 1917 (start_reg >= PACKET3_SET_CONFIG_REG_END) || 1918 (end_reg >= PACKET3_SET_CONFIG_REG_END)) { 1919 DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n"); 1920 return -EINVAL; 1921 } 1922 for (i = 0; i < pkt->count; i++) { 1923 reg = start_reg + (4 * i); 1924 r = r600_cs_check_reg(p, reg, idx+1+i); 1925 if (r) 1926 return r; 1927 } 1928 break; 1929 case PACKET3_SET_CONTEXT_REG: 1930 start_reg = (idx_value << 2) + PACKET3_SET_CONTEXT_REG_OFFSET; 1931 end_reg = 4 * pkt->count + start_reg - 4; 1932 if ((start_reg < PACKET3_SET_CONTEXT_REG_OFFSET) || 1933 (start_reg >= PACKET3_SET_CONTEXT_REG_END) || 1934 (end_reg >= PACKET3_SET_CONTEXT_REG_END)) { 1935 DRM_ERROR("bad PACKET3_SET_CONTEXT_REG\n"); 1936 return -EINVAL; 1937 } 1938 for (i = 0; i < pkt->count; i++) { 1939 reg = start_reg + (4 * i); 1940 r = r600_cs_check_reg(p, reg, idx+1+i); 1941 if (r) 1942 return r; 1943 } 1944 break; 1945 case PACKET3_SET_RESOURCE: 1946 if (pkt->count % 7) { 1947 DRM_ERROR("bad SET_RESOURCE\n"); 1948 return -EINVAL; 1949 } 1950 start_reg = (idx_value << 2) + PACKET3_SET_RESOURCE_OFFSET; 1951 end_reg = 4 * pkt->count + start_reg - 4; 1952 if ((start_reg < PACKET3_SET_RESOURCE_OFFSET) || 1953 (start_reg >= PACKET3_SET_RESOURCE_END) || 1954 (end_reg >= PACKET3_SET_RESOURCE_END)) { 1955 DRM_ERROR("bad SET_RESOURCE\n"); 1956 return -EINVAL; 1957 } 1958 for (i = 0; i < (pkt->count / 7); i++) { 1959 struct radeon_bo *texture, *mipmap; 1960 u32 size, offset, base_offset, mip_offset; 1961 1962 switch (G__SQ_VTX_CONSTANT_TYPE(radeon_get_ib_value(p, idx+(i*7)+6+1))) { 1963 case SQ_TEX_VTX_VALID_TEXTURE: 1964 /* tex base */ 1965 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1966 if (r) { 1967 DRM_ERROR("bad SET_RESOURCE\n"); 1968 return -EINVAL; 1969 } 1970 base_offset = (u32)((reloc->gpu_offset >> 8) & 0xffffffff); 1971 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 1972 if (reloc->tiling_flags & RADEON_TILING_MACRO) 1973 ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1); 1974 else if (reloc->tiling_flags & RADEON_TILING_MICRO) 1975 ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1); 1976 } 1977 texture = reloc->robj; 1978 /* tex mip base */ 1979 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1980 if (r) { 1981 DRM_ERROR("bad SET_RESOURCE\n"); 1982 return -EINVAL; 1983 } 1984 mip_offset = (u32)((reloc->gpu_offset >> 8) & 0xffffffff); 1985 mipmap = reloc->robj; 1986 r = r600_check_texture_resource(p, idx+(i*7)+1, 1987 texture, mipmap, 1988 base_offset + radeon_get_ib_value(p, idx+1+(i*7)+2), 1989 mip_offset + radeon_get_ib_value(p, idx+1+(i*7)+3), 1990 reloc->tiling_flags); 1991 if (r) 1992 return r; 1993 ib[idx+1+(i*7)+2] += base_offset; 1994 ib[idx+1+(i*7)+3] += mip_offset; 1995 break; 1996 case SQ_TEX_VTX_VALID_BUFFER: 1997 { 1998 uint64_t offset64; 1999 /* vtx base */ 2000 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 2001 if (r) { 2002 DRM_ERROR("bad SET_RESOURCE\n"); 2003 return -EINVAL; 2004 } 2005 offset = radeon_get_ib_value(p, idx+1+(i*7)+0); 2006 size = radeon_get_ib_value(p, idx+1+(i*7)+1) + 1; 2007 if (p->rdev && (size + offset) > radeon_bo_size(reloc->robj)) { 2008 /* force size to size of the buffer */ 2009 dev_warn(p->dev, "vbo resource seems too big (%d) for the bo (%ld)\n", 2010 size + offset, radeon_bo_size(reloc->robj)); 2011 ib[idx+1+(i*7)+1] = radeon_bo_size(reloc->robj) - offset; 2012 } 2013 2014 offset64 = reloc->gpu_offset + offset; 2015 ib[idx+1+(i*8)+0] = offset64; 2016 ib[idx+1+(i*8)+2] = (ib[idx+1+(i*8)+2] & 0xffffff00) | 2017 (upper_32_bits(offset64) & 0xff); 2018 break; 2019 } 2020 case SQ_TEX_VTX_INVALID_TEXTURE: 2021 case SQ_TEX_VTX_INVALID_BUFFER: 2022 default: 2023 DRM_ERROR("bad SET_RESOURCE\n"); 2024 return -EINVAL; 2025 } 2026 } 2027 break; 2028 case PACKET3_SET_ALU_CONST: 2029 if (track->sq_config & DX9_CONSTS) { 2030 start_reg = (idx_value << 2) + PACKET3_SET_ALU_CONST_OFFSET; 2031 end_reg = 4 * pkt->count + start_reg - 4; 2032 if ((start_reg < PACKET3_SET_ALU_CONST_OFFSET) || 2033 (start_reg >= PACKET3_SET_ALU_CONST_END) || 2034 (end_reg >= PACKET3_SET_ALU_CONST_END)) { 2035 DRM_ERROR("bad SET_ALU_CONST\n"); 2036 return -EINVAL; 2037 } 2038 } 2039 break; 2040 case PACKET3_SET_BOOL_CONST: 2041 start_reg = (idx_value << 2) + PACKET3_SET_BOOL_CONST_OFFSET; 2042 end_reg = 4 * pkt->count + start_reg - 4; 2043 if ((start_reg < PACKET3_SET_BOOL_CONST_OFFSET) || 2044 (start_reg >= PACKET3_SET_BOOL_CONST_END) || 2045 (end_reg >= PACKET3_SET_BOOL_CONST_END)) { 2046 DRM_ERROR("bad SET_BOOL_CONST\n"); 2047 return -EINVAL; 2048 } 2049 break; 2050 case PACKET3_SET_LOOP_CONST: 2051 start_reg = (idx_value << 2) + PACKET3_SET_LOOP_CONST_OFFSET; 2052 end_reg = 4 * pkt->count + start_reg - 4; 2053 if ((start_reg < PACKET3_SET_LOOP_CONST_OFFSET) || 2054 (start_reg >= PACKET3_SET_LOOP_CONST_END) || 2055 (end_reg >= PACKET3_SET_LOOP_CONST_END)) { 2056 DRM_ERROR("bad SET_LOOP_CONST\n"); 2057 return -EINVAL; 2058 } 2059 break; 2060 case PACKET3_SET_CTL_CONST: 2061 start_reg = (idx_value << 2) + PACKET3_SET_CTL_CONST_OFFSET; 2062 end_reg = 4 * pkt->count + start_reg - 4; 2063 if ((start_reg < PACKET3_SET_CTL_CONST_OFFSET) || 2064 (start_reg >= PACKET3_SET_CTL_CONST_END) || 2065 (end_reg >= PACKET3_SET_CTL_CONST_END)) { 2066 DRM_ERROR("bad SET_CTL_CONST\n"); 2067 return -EINVAL; 2068 } 2069 break; 2070 case PACKET3_SET_SAMPLER: 2071 if (pkt->count % 3) { 2072 DRM_ERROR("bad SET_SAMPLER\n"); 2073 return -EINVAL; 2074 } 2075 start_reg = (idx_value << 2) + PACKET3_SET_SAMPLER_OFFSET; 2076 end_reg = 4 * pkt->count + start_reg - 4; 2077 if ((start_reg < PACKET3_SET_SAMPLER_OFFSET) || 2078 (start_reg >= PACKET3_SET_SAMPLER_END) || 2079 (end_reg >= PACKET3_SET_SAMPLER_END)) { 2080 DRM_ERROR("bad SET_SAMPLER\n"); 2081 return -EINVAL; 2082 } 2083 break; 2084 case PACKET3_STRMOUT_BASE_UPDATE: 2085 /* RS780 and RS880 also need this */ 2086 if (p->family < CHIP_RS780) { 2087 DRM_ERROR("STRMOUT_BASE_UPDATE only supported on 7xx\n"); 2088 return -EINVAL; 2089 } 2090 if (pkt->count != 1) { 2091 DRM_ERROR("bad STRMOUT_BASE_UPDATE packet count\n"); 2092 return -EINVAL; 2093 } 2094 if (idx_value > 3) { 2095 DRM_ERROR("bad STRMOUT_BASE_UPDATE index\n"); 2096 return -EINVAL; 2097 } 2098 { 2099 u64 offset; 2100 2101 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 2102 if (r) { 2103 DRM_ERROR("bad STRMOUT_BASE_UPDATE reloc\n"); 2104 return -EINVAL; 2105 } 2106 2107 if (reloc->robj != track->vgt_strmout_bo[idx_value]) { 2108 DRM_ERROR("bad STRMOUT_BASE_UPDATE, bo does not match\n"); 2109 return -EINVAL; 2110 } 2111 2112 offset = radeon_get_ib_value(p, idx+1) << 8; 2113 if (offset != track->vgt_strmout_bo_offset[idx_value]) { 2114 DRM_ERROR("bad STRMOUT_BASE_UPDATE, bo offset does not match: 0x%"PRIx64", 0x%x\n", 2115 offset, track->vgt_strmout_bo_offset[idx_value]); 2116 return -EINVAL; 2117 } 2118 2119 if ((offset + 4) > radeon_bo_size(reloc->robj)) { 2120 DRM_ERROR("bad STRMOUT_BASE_UPDATE bo too small: 0x%"PRIx64", 0x%lx\n", 2121 offset + 4, radeon_bo_size(reloc->robj)); 2122 return -EINVAL; 2123 } 2124 ib[idx+1] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); 2125 } 2126 break; 2127 case PACKET3_SURFACE_BASE_UPDATE: 2128 if (p->family >= CHIP_RV770 || p->family == CHIP_R600) { 2129 DRM_ERROR("bad SURFACE_BASE_UPDATE\n"); 2130 return -EINVAL; 2131 } 2132 if (pkt->count) { 2133 DRM_ERROR("bad SURFACE_BASE_UPDATE\n"); 2134 return -EINVAL; 2135 } 2136 break; 2137 case PACKET3_STRMOUT_BUFFER_UPDATE: 2138 if (pkt->count != 4) { 2139 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (invalid count)\n"); 2140 return -EINVAL; 2141 } 2142 /* Updating memory at DST_ADDRESS. */ 2143 if (idx_value & 0x1) { 2144 u64 offset; 2145 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 2146 if (r) { 2147 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing dst reloc)\n"); 2148 return -EINVAL; 2149 } 2150 offset = radeon_get_ib_value(p, idx+1); 2151 offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32; 2152 if ((offset + 4) > radeon_bo_size(reloc->robj)) { 2153 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE dst bo too small: 0x%"PRIx64", 0x%lx\n", 2154 offset + 4, radeon_bo_size(reloc->robj)); 2155 return -EINVAL; 2156 } 2157 offset += reloc->gpu_offset; 2158 ib[idx+1] = offset; 2159 ib[idx+2] = upper_32_bits(offset) & 0xff; 2160 } 2161 /* Reading data from SRC_ADDRESS. */ 2162 if (((idx_value >> 1) & 0x3) == 2) { 2163 u64 offset; 2164 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 2165 if (r) { 2166 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing src reloc)\n"); 2167 return -EINVAL; 2168 } 2169 offset = radeon_get_ib_value(p, idx+3); 2170 offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; 2171 if ((offset + 4) > radeon_bo_size(reloc->robj)) { 2172 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE src bo too small: 0x%"PRIx64", 0x%lx\n", 2173 offset + 4, radeon_bo_size(reloc->robj)); 2174 return -EINVAL; 2175 } 2176 offset += reloc->gpu_offset; 2177 ib[idx+3] = offset; 2178 ib[idx+4] = upper_32_bits(offset) & 0xff; 2179 } 2180 break; 2181 case PACKET3_MEM_WRITE: 2182 { 2183 u64 offset; 2184 2185 if (pkt->count != 3) { 2186 DRM_ERROR("bad MEM_WRITE (invalid count)\n"); 2187 return -EINVAL; 2188 } 2189 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 2190 if (r) { 2191 DRM_ERROR("bad MEM_WRITE (missing reloc)\n"); 2192 return -EINVAL; 2193 } 2194 offset = radeon_get_ib_value(p, idx+0); 2195 offset += ((u64)(radeon_get_ib_value(p, idx+1) & 0xff)) << 32UL; 2196 if (offset & 0x7) { 2197 DRM_ERROR("bad MEM_WRITE (address not qwords aligned)\n"); 2198 return -EINVAL; 2199 } 2200 if ((offset + 8) > radeon_bo_size(reloc->robj)) { 2201 DRM_ERROR("bad MEM_WRITE bo too small: 0x%"PRIx64", 0x%lx\n", 2202 offset + 8, radeon_bo_size(reloc->robj)); 2203 return -EINVAL; 2204 } 2205 offset += reloc->gpu_offset; 2206 ib[idx+0] = offset; 2207 ib[idx+1] = upper_32_bits(offset) & 0xff; 2208 break; 2209 } 2210 case PACKET3_COPY_DW: 2211 if (pkt->count != 4) { 2212 DRM_ERROR("bad COPY_DW (invalid count)\n"); 2213 return -EINVAL; 2214 } 2215 if (idx_value & 0x1) { 2216 u64 offset; 2217 /* SRC is memory. */ 2218 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 2219 if (r) { 2220 DRM_ERROR("bad COPY_DW (missing src reloc)\n"); 2221 return -EINVAL; 2222 } 2223 offset = radeon_get_ib_value(p, idx+1); 2224 offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32; 2225 if ((offset + 4) > radeon_bo_size(reloc->robj)) { 2226 DRM_ERROR("bad COPY_DW src bo too small: 0x%"PRIx64", 0x%lx\n", 2227 offset + 4, radeon_bo_size(reloc->robj)); 2228 return -EINVAL; 2229 } 2230 offset += reloc->gpu_offset; 2231 ib[idx+1] = offset; 2232 ib[idx+2] = upper_32_bits(offset) & 0xff; 2233 } else { 2234 /* SRC is a reg. */ 2235 reg = radeon_get_ib_value(p, idx+1) << 2; 2236 if (!r600_is_safe_reg(p, reg, idx+1)) 2237 return -EINVAL; 2238 } 2239 if (idx_value & 0x2) { 2240 u64 offset; 2241 /* DST is memory. */ 2242 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 2243 if (r) { 2244 DRM_ERROR("bad COPY_DW (missing dst reloc)\n"); 2245 return -EINVAL; 2246 } 2247 offset = radeon_get_ib_value(p, idx+3); 2248 offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; 2249 if ((offset + 4) > radeon_bo_size(reloc->robj)) { 2250 DRM_ERROR("bad COPY_DW dst bo too small: 0x%"PRIx64", 0x%lx\n", 2251 offset + 4, radeon_bo_size(reloc->robj)); 2252 return -EINVAL; 2253 } 2254 offset += reloc->gpu_offset; 2255 ib[idx+3] = offset; 2256 ib[idx+4] = upper_32_bits(offset) & 0xff; 2257 } else { 2258 /* DST is a reg. */ 2259 reg = radeon_get_ib_value(p, idx+3) << 2; 2260 if (!r600_is_safe_reg(p, reg, idx+3)) 2261 return -EINVAL; 2262 } 2263 break; 2264 case PACKET3_NOP: 2265 break; 2266 default: 2267 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode); 2268 return -EINVAL; 2269 } 2270 return 0; 2271 } 2272 2273 int r600_cs_parse(struct radeon_cs_parser *p) 2274 { 2275 struct radeon_cs_packet pkt; 2276 struct r600_cs_track *track; 2277 int r; 2278 2279 if (p->track == NULL) { 2280 /* initialize tracker, we are in kms */ 2281 track = kzalloc(sizeof(*track), GFP_KERNEL); 2282 if (track == NULL) 2283 return -ENOMEM; 2284 r600_cs_track_init(track); 2285 if (p->rdev->family < CHIP_RV770) { 2286 track->npipes = p->rdev->config.r600.tiling_npipes; 2287 track->nbanks = p->rdev->config.r600.tiling_nbanks; 2288 track->group_size = p->rdev->config.r600.tiling_group_size; 2289 } else if (p->rdev->family <= CHIP_RV740) { 2290 track->npipes = p->rdev->config.rv770.tiling_npipes; 2291 track->nbanks = p->rdev->config.rv770.tiling_nbanks; 2292 track->group_size = p->rdev->config.rv770.tiling_group_size; 2293 } 2294 p->track = track; 2295 } 2296 do { 2297 r = radeon_cs_packet_parse(p, &pkt, p->idx); 2298 if (r) { 2299 kfree(p->track); 2300 p->track = NULL; 2301 return r; 2302 } 2303 p->idx += pkt.count + 2; 2304 switch (pkt.type) { 2305 case RADEON_PACKET_TYPE0: 2306 r = r600_cs_parse_packet0(p, &pkt); 2307 break; 2308 case RADEON_PACKET_TYPE2: 2309 break; 2310 case RADEON_PACKET_TYPE3: 2311 r = r600_packet3_check(p, &pkt); 2312 break; 2313 default: 2314 DRM_ERROR("Unknown packet type %d !\n", pkt.type); 2315 kfree(p->track); 2316 p->track = NULL; 2317 return -EINVAL; 2318 } 2319 if (r) { 2320 kfree(p->track); 2321 p->track = NULL; 2322 return r; 2323 } 2324 } while (p->idx < p->chunk_ib->length_dw); 2325 #if 0 2326 for (r = 0; r < p->ib.length_dw; r++) { 2327 printk(KERN_INFO "%05d 0x%08X\n", r, p->ib.ptr[r]); 2328 mdelay(1); 2329 } 2330 #endif 2331 kfree(p->track); 2332 p->track = NULL; 2333 return 0; 2334 } 2335 2336 #ifdef CONFIG_DRM_RADEON_UMS 2337 2338 /** 2339 * cs_parser_fini() - clean parser states 2340 * @parser: parser structure holding parsing context. 2341 * @error: error number 2342 * 2343 * If error is set than unvalidate buffer, otherwise just free memory 2344 * used by parsing context. 2345 **/ 2346 static void r600_cs_parser_fini(struct radeon_cs_parser *parser, int error) 2347 { 2348 unsigned i; 2349 2350 kfree(parser->relocs); 2351 for (i = 0; i < parser->nchunks; i++) 2352 drm_free_large(parser->chunks[i].kdata); 2353 kfree(parser->chunks); 2354 kfree(parser->chunks_array); 2355 } 2356 2357 static int r600_cs_parser_relocs_legacy(struct radeon_cs_parser *p) 2358 { 2359 if (p->chunk_relocs == NULL) { 2360 return 0; 2361 } 2362 p->relocs = kzalloc(sizeof(struct radeon_bo_list), GFP_KERNEL); 2363 if (p->relocs == NULL) { 2364 return -ENOMEM; 2365 } 2366 return 0; 2367 } 2368 2369 int r600_cs_legacy(struct drm_device *dev, void *data, struct drm_file *filp, 2370 unsigned family, u32 *ib, int *l) 2371 { 2372 struct radeon_cs_parser parser; 2373 struct radeon_cs_chunk *ib_chunk; 2374 struct r600_cs_track *track; 2375 int r; 2376 2377 /* initialize tracker */ 2378 track = kzalloc(sizeof(*track), GFP_KERNEL); 2379 if (track == NULL) 2380 return -ENOMEM; 2381 r600_cs_track_init(track); 2382 r600_cs_legacy_get_tiling_conf(dev, &track->npipes, &track->nbanks, &track->group_size); 2383 /* initialize parser */ 2384 memset(&parser, 0, sizeof(struct radeon_cs_parser)); 2385 parser.filp = filp; 2386 parser.dev = &dev->pdev->dev; 2387 parser.rdev = NULL; 2388 parser.family = family; 2389 parser.track = track; 2390 parser.ib.ptr = ib; 2391 r = radeon_cs_parser_init(&parser, data); 2392 if (r) { 2393 DRM_ERROR("Failed to initialize parser !\n"); 2394 r600_cs_parser_fini(&parser, r); 2395 return r; 2396 } 2397 r = r600_cs_parser_relocs_legacy(&parser); 2398 if (r) { 2399 DRM_ERROR("Failed to parse relocation !\n"); 2400 r600_cs_parser_fini(&parser, r); 2401 return r; 2402 } 2403 /* Copy the packet into the IB, the parser will read from the 2404 * input memory (cached) and write to the IB (which can be 2405 * uncached). */ 2406 ib_chunk = parser.chunk_ib; 2407 parser.ib.length_dw = ib_chunk->length_dw; 2408 *l = parser.ib.length_dw; 2409 if (copy_from_user(ib, ib_chunk->user_ptr, ib_chunk->length_dw * 4)) { 2410 r = -EFAULT; 2411 r600_cs_parser_fini(&parser, r); 2412 return r; 2413 } 2414 r = r600_cs_parse(&parser); 2415 if (r) { 2416 DRM_ERROR("Invalid command stream !\n"); 2417 r600_cs_parser_fini(&parser, r); 2418 return r; 2419 } 2420 r600_cs_parser_fini(&parser, r); 2421 return r; 2422 } 2423 2424 void r600_cs_legacy_init(void) 2425 { 2426 r600_nomm = 1; 2427 } 2428 2429 #endif 2430 2431 /* 2432 * DMA 2433 */ 2434 /** 2435 * r600_dma_cs_next_reloc() - parse next reloc 2436 * @p: parser structure holding parsing context. 2437 * @cs_reloc: reloc informations 2438 * 2439 * Return the next reloc, do bo validation and compute 2440 * GPU offset using the provided start. 2441 **/ 2442 int r600_dma_cs_next_reloc(struct radeon_cs_parser *p, 2443 struct radeon_bo_list **cs_reloc) 2444 { 2445 struct radeon_cs_chunk *relocs_chunk __unused; 2446 unsigned idx; 2447 2448 *cs_reloc = NULL; 2449 if (p->chunk_relocs == NULL) { 2450 DRM_ERROR("No relocation chunk !\n"); 2451 return -EINVAL; 2452 } 2453 relocs_chunk = p->chunk_relocs; 2454 idx = p->dma_reloc_idx; 2455 if (idx >= p->nrelocs) { 2456 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n", 2457 idx, p->nrelocs); 2458 return -EINVAL; 2459 } 2460 *cs_reloc = &p->relocs[idx]; 2461 p->dma_reloc_idx++; 2462 return 0; 2463 } 2464 2465 #define GET_DMA_CMD(h) (((h) & 0xf0000000) >> 28) 2466 #define GET_DMA_COUNT(h) ((h) & 0x0000ffff) 2467 #define GET_DMA_T(h) (((h) & 0x00800000) >> 23) 2468 2469 /** 2470 * r600_dma_cs_parse() - parse the DMA IB 2471 * @p: parser structure holding parsing context. 2472 * 2473 * Parses the DMA IB from the CS ioctl and updates 2474 * the GPU addresses based on the reloc information and 2475 * checks for errors. (R6xx-R7xx) 2476 * Returns 0 for success and an error on failure. 2477 **/ 2478 int r600_dma_cs_parse(struct radeon_cs_parser *p) 2479 { 2480 struct radeon_cs_chunk *ib_chunk = p->chunk_ib; 2481 struct radeon_bo_list *src_reloc, *dst_reloc; 2482 u32 header, cmd, count, tiled; 2483 volatile u32 *ib = p->ib.ptr; 2484 u32 idx, idx_value; 2485 u64 src_offset, dst_offset; 2486 int r; 2487 2488 do { 2489 if (p->idx >= ib_chunk->length_dw) { 2490 DRM_ERROR("Can not parse packet at %d after CS end %d !\n", 2491 p->idx, ib_chunk->length_dw); 2492 return -EINVAL; 2493 } 2494 idx = p->idx; 2495 header = radeon_get_ib_value(p, idx); 2496 cmd = GET_DMA_CMD(header); 2497 count = GET_DMA_COUNT(header); 2498 tiled = GET_DMA_T(header); 2499 2500 switch (cmd) { 2501 case DMA_PACKET_WRITE: 2502 r = r600_dma_cs_next_reloc(p, &dst_reloc); 2503 if (r) { 2504 DRM_ERROR("bad DMA_PACKET_WRITE\n"); 2505 return -EINVAL; 2506 } 2507 if (tiled) { 2508 dst_offset = radeon_get_ib_value(p, idx+1); 2509 dst_offset <<= 8; 2510 2511 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); 2512 p->idx += count + 5; 2513 } else { 2514 dst_offset = radeon_get_ib_value(p, idx+1); 2515 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32; 2516 2517 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); 2518 ib[idx+2] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; 2519 p->idx += count + 3; 2520 } 2521 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { 2522 dev_warn(p->dev, "DMA write buffer too small (%"PRIu64" %lu)\n", 2523 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); 2524 return -EINVAL; 2525 } 2526 break; 2527 case DMA_PACKET_COPY: 2528 r = r600_dma_cs_next_reloc(p, &src_reloc); 2529 if (r) { 2530 DRM_ERROR("bad DMA_PACKET_COPY\n"); 2531 return -EINVAL; 2532 } 2533 r = r600_dma_cs_next_reloc(p, &dst_reloc); 2534 if (r) { 2535 DRM_ERROR("bad DMA_PACKET_COPY\n"); 2536 return -EINVAL; 2537 } 2538 if (tiled) { 2539 idx_value = radeon_get_ib_value(p, idx + 2); 2540 /* detile bit */ 2541 if (idx_value & (1 << 31)) { 2542 /* tiled src, linear dst */ 2543 src_offset = radeon_get_ib_value(p, idx+1); 2544 src_offset <<= 8; 2545 ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8); 2546 2547 dst_offset = radeon_get_ib_value(p, idx+5); 2548 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32; 2549 ib[idx+5] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); 2550 ib[idx+6] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; 2551 } else { 2552 /* linear src, tiled dst */ 2553 src_offset = radeon_get_ib_value(p, idx+5); 2554 src_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32; 2555 ib[idx+5] += (u32)(src_reloc->gpu_offset & 0xfffffffc); 2556 ib[idx+6] += upper_32_bits(src_reloc->gpu_offset) & 0xff; 2557 2558 dst_offset = radeon_get_ib_value(p, idx+1); 2559 dst_offset <<= 8; 2560 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); 2561 } 2562 p->idx += 7; 2563 } else { 2564 if (p->family >= CHIP_RV770) { 2565 src_offset = radeon_get_ib_value(p, idx+2); 2566 src_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; 2567 dst_offset = radeon_get_ib_value(p, idx+1); 2568 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32; 2569 2570 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); 2571 ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xfffffffc); 2572 ib[idx+3] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; 2573 ib[idx+4] += upper_32_bits(src_reloc->gpu_offset) & 0xff; 2574 p->idx += 5; 2575 } else { 2576 src_offset = radeon_get_ib_value(p, idx+2); 2577 src_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32; 2578 dst_offset = radeon_get_ib_value(p, idx+1); 2579 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff0000)) << 16; 2580 2581 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); 2582 ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xfffffffc); 2583 ib[idx+3] += upper_32_bits(src_reloc->gpu_offset) & 0xff; 2584 ib[idx+3] += (upper_32_bits(dst_reloc->gpu_offset) & 0xff) << 16; 2585 p->idx += 4; 2586 } 2587 } 2588 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) { 2589 dev_warn(p->dev, "DMA copy src buffer too small (%"PRIu64" %lu)\n", 2590 src_offset + (count * 4), radeon_bo_size(src_reloc->robj)); 2591 return -EINVAL; 2592 } 2593 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { 2594 dev_warn(p->dev, "DMA write dst buffer too small (%"PRIu64" %lu)\n", 2595 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); 2596 return -EINVAL; 2597 } 2598 break; 2599 case DMA_PACKET_CONSTANT_FILL: 2600 if (p->family < CHIP_RV770) { 2601 DRM_ERROR("Constant Fill is 7xx only !\n"); 2602 return -EINVAL; 2603 } 2604 r = r600_dma_cs_next_reloc(p, &dst_reloc); 2605 if (r) { 2606 DRM_ERROR("bad DMA_PACKET_WRITE\n"); 2607 return -EINVAL; 2608 } 2609 dst_offset = radeon_get_ib_value(p, idx+1); 2610 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0x00ff0000)) << 16; 2611 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { 2612 dev_warn(p->dev, "DMA constant fill buffer too small (%"PRIu64" %lu)\n", 2613 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); 2614 return -EINVAL; 2615 } 2616 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); 2617 ib[idx+3] += (upper_32_bits(dst_reloc->gpu_offset) << 16) & 0x00ff0000; 2618 p->idx += 4; 2619 break; 2620 case DMA_PACKET_NOP: 2621 p->idx += 1; 2622 break; 2623 default: 2624 DRM_ERROR("Unknown packet type %d at %d !\n", cmd, idx); 2625 return -EINVAL; 2626 } 2627 } while (p->idx < p->chunk_ib->length_dw); 2628 #if 0 2629 for (r = 0; r < p->ib->length_dw; r++) { 2630 printk(KERN_INFO "%05d 0x%08X\n", r, p->ib.ptr[r]); 2631 mdelay(1); 2632 } 2633 #endif 2634 return 0; 2635 } 2636
Indexes created Wed Oct 22 13:09:56 GMT 2025