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radeon_ring.c revision 1.1.1.1
      1 /*
      2  * Copyright 2008 Advanced Micro Devices, Inc.
      3  * Copyright 2008 Red Hat Inc.
      4  * Copyright 2009 Jerome Glisse.
      5  *
      6  * Permission is hereby granted, free of charge, to any person obtaining a
      7  * copy of this software and associated documentation files (the "Software"),
      8  * to deal in the Software without restriction, including without limitation
      9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
     10  * and/or sell copies of the Software, and to permit persons to whom the
     11  * Software is furnished to do so, subject to the following conditions:
     12  *
     13  * The above copyright notice and this permission notice shall be included in
     14  * all copies or substantial portions of the Software.
     15  *
     16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     22  * OTHER DEALINGS IN THE SOFTWARE.
     23  *
     24  * Authors: Dave Airlie
     25  *          Alex Deucher
     26  *          Jerome Glisse
     27  *          Christian Knig
     28  */
     29 #include <linux/seq_file.h>
     30 #include <linux/slab.h>
     31 #include <drm/drmP.h>
     32 #include <drm/radeon_drm.h>
     33 #include "radeon_reg.h"
     34 #include "radeon.h"
     35 #include "atom.h"
     36 
     37 /*
     38  * IB
     39  * IBs (Indirect Buffers) and areas of GPU accessible memory where
     40  * commands are stored.  You can put a pointer to the IB in the
     41  * command ring and the hw will fetch the commands from the IB
     42  * and execute them.  Generally userspace acceleration drivers
     43  * produce command buffers which are send to the kernel and
     44  * put in IBs for execution by the requested ring.
     45  */
     46 static int radeon_debugfs_sa_init(struct radeon_device *rdev);
     47 
     48 /**
     49  * radeon_ib_get - request an IB (Indirect Buffer)
     50  *
     51  * @rdev: radeon_device pointer
     52  * @ring: ring index the IB is associated with
     53  * @ib: IB object returned
     54  * @size: requested IB size
     55  *
     56  * Request an IB (all asics).  IBs are allocated using the
     57  * suballocator.
     58  * Returns 0 on success, error on failure.
     59  */
     60 int radeon_ib_get(struct radeon_device *rdev, int ring,
     61 		  struct radeon_ib *ib, struct radeon_vm *vm,
     62 		  unsigned size)
     63 {
     64 	int r;
     65 
     66 	r = radeon_sa_bo_new(rdev, &rdev->ring_tmp_bo, &ib->sa_bo, size, 256);
     67 	if (r) {
     68 		dev_err(rdev->dev, "failed to get a new IB (%d)\n", r);
     69 		return r;
     70 	}
     71 
     72 	r = radeon_semaphore_create(rdev, &ib->semaphore);
     73 	if (r) {
     74 		return r;
     75 	}
     76 
     77 	ib->ring = ring;
     78 	ib->fence = NULL;
     79 	ib->ptr = radeon_sa_bo_cpu_addr(ib->sa_bo);
     80 	ib->vm = vm;
     81 	if (vm) {
     82 		/* ib pool is bound at RADEON_VA_IB_OFFSET in virtual address
     83 		 * space and soffset is the offset inside the pool bo
     84 		 */
     85 		ib->gpu_addr = ib->sa_bo->soffset + RADEON_VA_IB_OFFSET;
     86 	} else {
     87 		ib->gpu_addr = radeon_sa_bo_gpu_addr(ib->sa_bo);
     88 	}
     89 	ib->is_const_ib = false;
     90 
     91 	return 0;
     92 }
     93 
     94 /**
     95  * radeon_ib_free - free an IB (Indirect Buffer)
     96  *
     97  * @rdev: radeon_device pointer
     98  * @ib: IB object to free
     99  *
    100  * Free an IB (all asics).
    101  */
    102 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib)
    103 {
    104 	radeon_semaphore_free(rdev, &ib->semaphore, ib->fence);
    105 	radeon_sa_bo_free(rdev, &ib->sa_bo, ib->fence);
    106 	radeon_fence_unref(&ib->fence);
    107 }
    108 
    109 /**
    110  * radeon_ib_schedule - schedule an IB (Indirect Buffer) on the ring
    111  *
    112  * @rdev: radeon_device pointer
    113  * @ib: IB object to schedule
    114  * @const_ib: Const IB to schedule (SI only)
    115  *
    116  * Schedule an IB on the associated ring (all asics).
    117  * Returns 0 on success, error on failure.
    118  *
    119  * On SI, there are two parallel engines fed from the primary ring,
    120  * the CE (Constant Engine) and the DE (Drawing Engine).  Since
    121  * resource descriptors have moved to memory, the CE allows you to
    122  * prime the caches while the DE is updating register state so that
    123  * the resource descriptors will be already in cache when the draw is
    124  * processed.  To accomplish this, the userspace driver submits two
    125  * IBs, one for the CE and one for the DE.  If there is a CE IB (called
    126  * a CONST_IB), it will be put on the ring prior to the DE IB.  Prior
    127  * to SI there was just a DE IB.
    128  */
    129 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
    130 		       struct radeon_ib *const_ib)
    131 {
    132 	struct radeon_ring *ring = &rdev->ring[ib->ring];
    133 	int r = 0;
    134 
    135 	if (!ib->length_dw || !ring->ready) {
    136 		/* TODO: Nothings in the ib we should report. */
    137 		dev_err(rdev->dev, "couldn't schedule ib\n");
    138 		return -EINVAL;
    139 	}
    140 
    141 	/* 64 dwords should be enough for fence too */
    142 	r = radeon_ring_lock(rdev, ring, 64 + RADEON_NUM_SYNCS * 8);
    143 	if (r) {
    144 		dev_err(rdev->dev, "scheduling IB failed (%d).\n", r);
    145 		return r;
    146 	}
    147 
    148 	/* grab a vm id if necessary */
    149 	if (ib->vm) {
    150 		struct radeon_fence *vm_id_fence;
    151 		vm_id_fence = radeon_vm_grab_id(rdev, ib->vm, ib->ring);
    152         	radeon_semaphore_sync_to(ib->semaphore, vm_id_fence);
    153 	}
    154 
    155 	/* sync with other rings */
    156 	r = radeon_semaphore_sync_rings(rdev, ib->semaphore, ib->ring);
    157 	if (r) {
    158 		dev_err(rdev->dev, "failed to sync rings (%d)\n", r);
    159 		radeon_ring_unlock_undo(rdev, ring);
    160 		return r;
    161 	}
    162 
    163 	if (ib->vm)
    164 		radeon_vm_flush(rdev, ib->vm, ib->ring);
    165 
    166 	if (const_ib) {
    167 		radeon_ring_ib_execute(rdev, const_ib->ring, const_ib);
    168 		radeon_semaphore_free(rdev, &const_ib->semaphore, NULL);
    169 	}
    170 	radeon_ring_ib_execute(rdev, ib->ring, ib);
    171 	r = radeon_fence_emit(rdev, &ib->fence, ib->ring);
    172 	if (r) {
    173 		dev_err(rdev->dev, "failed to emit fence for new IB (%d)\n", r);
    174 		radeon_ring_unlock_undo(rdev, ring);
    175 		return r;
    176 	}
    177 	if (const_ib) {
    178 		const_ib->fence = radeon_fence_ref(ib->fence);
    179 	}
    180 
    181 	if (ib->vm)
    182 		radeon_vm_fence(rdev, ib->vm, ib->fence);
    183 
    184 	radeon_ring_unlock_commit(rdev, ring);
    185 	return 0;
    186 }
    187 
    188 /**
    189  * radeon_ib_pool_init - Init the IB (Indirect Buffer) pool
    190  *
    191  * @rdev: radeon_device pointer
    192  *
    193  * Initialize the suballocator to manage a pool of memory
    194  * for use as IBs (all asics).
    195  * Returns 0 on success, error on failure.
    196  */
    197 int radeon_ib_pool_init(struct radeon_device *rdev)
    198 {
    199 	int r;
    200 
    201 	if (rdev->ib_pool_ready) {
    202 		return 0;
    203 	}
    204 	r = radeon_sa_bo_manager_init(rdev, &rdev->ring_tmp_bo,
    205 				      RADEON_IB_POOL_SIZE*64*1024,
    206 				      RADEON_GPU_PAGE_SIZE,
    207 				      RADEON_GEM_DOMAIN_GTT);
    208 	if (r) {
    209 		return r;
    210 	}
    211 
    212 	r = radeon_sa_bo_manager_start(rdev, &rdev->ring_tmp_bo);
    213 	if (r) {
    214 		return r;
    215 	}
    216 
    217 	rdev->ib_pool_ready = true;
    218 	if (radeon_debugfs_sa_init(rdev)) {
    219 		dev_err(rdev->dev, "failed to register debugfs file for SA\n");
    220 	}
    221 	return 0;
    222 }
    223 
    224 /**
    225  * radeon_ib_pool_fini - Free the IB (Indirect Buffer) pool
    226  *
    227  * @rdev: radeon_device pointer
    228  *
    229  * Tear down the suballocator managing the pool of memory
    230  * for use as IBs (all asics).
    231  */
    232 void radeon_ib_pool_fini(struct radeon_device *rdev)
    233 {
    234 	if (rdev->ib_pool_ready) {
    235 		radeon_sa_bo_manager_suspend(rdev, &rdev->ring_tmp_bo);
    236 		radeon_sa_bo_manager_fini(rdev, &rdev->ring_tmp_bo);
    237 		rdev->ib_pool_ready = false;
    238 	}
    239 }
    240 
    241 /**
    242  * radeon_ib_ring_tests - test IBs on the rings
    243  *
    244  * @rdev: radeon_device pointer
    245  *
    246  * Test an IB (Indirect Buffer) on each ring.
    247  * If the test fails, disable the ring.
    248  * Returns 0 on success, error if the primary GFX ring
    249  * IB test fails.
    250  */
    251 int radeon_ib_ring_tests(struct radeon_device *rdev)
    252 {
    253 	unsigned i;
    254 	int r;
    255 
    256 	for (i = 0; i < RADEON_NUM_RINGS; ++i) {
    257 		struct radeon_ring *ring = &rdev->ring[i];
    258 
    259 		if (!ring->ready)
    260 			continue;
    261 
    262 		r = radeon_ib_test(rdev, i, ring);
    263 		if (r) {
    264 			ring->ready = false;
    265 			rdev->needs_reset = false;
    266 
    267 			if (i == RADEON_RING_TYPE_GFX_INDEX) {
    268 				/* oh, oh, that's really bad */
    269 				DRM_ERROR("radeon: failed testing IB on GFX ring (%d).\n", r);
    270 		                rdev->accel_working = false;
    271 				return r;
    272 
    273 			} else {
    274 				/* still not good, but we can live with it */
    275 				DRM_ERROR("radeon: failed testing IB on ring %d (%d).\n", i, r);
    276 			}
    277 		}
    278 	}
    279 	return 0;
    280 }
    281 
    282 /*
    283  * Rings
    284  * Most engines on the GPU are fed via ring buffers.  Ring
    285  * buffers are areas of GPU accessible memory that the host
    286  * writes commands into and the GPU reads commands out of.
    287  * There is a rptr (read pointer) that determines where the
    288  * GPU is currently reading, and a wptr (write pointer)
    289  * which determines where the host has written.  When the
    290  * pointers are equal, the ring is idle.  When the host
    291  * writes commands to the ring buffer, it increments the
    292  * wptr.  The GPU then starts fetching commands and executes
    293  * them until the pointers are equal again.
    294  */
    295 static int radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring);
    296 
    297 /**
    298  * radeon_ring_write - write a value to the ring
    299  *
    300  * @ring: radeon_ring structure holding ring information
    301  * @v: dword (dw) value to write
    302  *
    303  * Write a value to the requested ring buffer (all asics).
    304  */
    305 void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
    306 {
    307 #if DRM_DEBUG_CODE
    308 	if (ring->count_dw <= 0) {
    309 		DRM_ERROR("radeon: writing more dwords to the ring than expected!\n");
    310 	}
    311 #endif
    312 	ring->ring[ring->wptr++] = v;
    313 	ring->wptr &= ring->ptr_mask;
    314 	ring->count_dw--;
    315 	ring->ring_free_dw--;
    316 }
    317 
    318 /**
    319  * radeon_ring_supports_scratch_reg - check if the ring supports
    320  * writing to scratch registers
    321  *
    322  * @rdev: radeon_device pointer
    323  * @ring: radeon_ring structure holding ring information
    324  *
    325  * Check if a specific ring supports writing to scratch registers (all asics).
    326  * Returns true if the ring supports writing to scratch regs, false if not.
    327  */
    328 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
    329 				      struct radeon_ring *ring)
    330 {
    331 	switch (ring->idx) {
    332 	case RADEON_RING_TYPE_GFX_INDEX:
    333 	case CAYMAN_RING_TYPE_CP1_INDEX:
    334 	case CAYMAN_RING_TYPE_CP2_INDEX:
    335 		return true;
    336 	default:
    337 		return false;
    338 	}
    339 }
    340 
    341 /**
    342  * radeon_ring_free_size - update the free size
    343  *
    344  * @rdev: radeon_device pointer
    345  * @ring: radeon_ring structure holding ring information
    346  *
    347  * Update the free dw slots in the ring buffer (all asics).
    348  */
    349 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *ring)
    350 {
    351 	uint32_t rptr = radeon_ring_get_rptr(rdev, ring);
    352 
    353 	/* This works because ring_size is a power of 2 */
    354 	ring->ring_free_dw = rptr + (ring->ring_size / 4);
    355 	ring->ring_free_dw -= ring->wptr;
    356 	ring->ring_free_dw &= ring->ptr_mask;
    357 	if (!ring->ring_free_dw) {
    358 		/* this is an empty ring */
    359 		ring->ring_free_dw = ring->ring_size / 4;
    360 		/*  update lockup info to avoid false positive */
    361 		radeon_ring_lockup_update(rdev, ring);
    362 	}
    363 }
    364 
    365 /**
    366  * radeon_ring_alloc - allocate space on the ring buffer
    367  *
    368  * @rdev: radeon_device pointer
    369  * @ring: radeon_ring structure holding ring information
    370  * @ndw: number of dwords to allocate in the ring buffer
    371  *
    372  * Allocate @ndw dwords in the ring buffer (all asics).
    373  * Returns 0 on success, error on failure.
    374  */
    375 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw)
    376 {
    377 	int r;
    378 
    379 	/* make sure we aren't trying to allocate more space than there is on the ring */
    380 	if (ndw > (ring->ring_size / 4))
    381 		return -ENOMEM;
    382 	/* Align requested size with padding so unlock_commit can
    383 	 * pad safely */
    384 	radeon_ring_free_size(rdev, ring);
    385 	ndw = (ndw + ring->align_mask) & ~ring->align_mask;
    386 	while (ndw > (ring->ring_free_dw - 1)) {
    387 		radeon_ring_free_size(rdev, ring);
    388 		if (ndw < ring->ring_free_dw) {
    389 			break;
    390 		}
    391 		r = radeon_fence_wait_next(rdev, ring->idx);
    392 		if (r)
    393 			return r;
    394 	}
    395 	ring->count_dw = ndw;
    396 	ring->wptr_old = ring->wptr;
    397 	return 0;
    398 }
    399 
    400 /**
    401  * radeon_ring_lock - lock the ring and allocate space on it
    402  *
    403  * @rdev: radeon_device pointer
    404  * @ring: radeon_ring structure holding ring information
    405  * @ndw: number of dwords to allocate in the ring buffer
    406  *
    407  * Lock the ring and allocate @ndw dwords in the ring buffer
    408  * (all asics).
    409  * Returns 0 on success, error on failure.
    410  */
    411 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw)
    412 {
    413 	int r;
    414 
    415 	mutex_lock(&rdev->ring_lock);
    416 	r = radeon_ring_alloc(rdev, ring, ndw);
    417 	if (r) {
    418 		mutex_unlock(&rdev->ring_lock);
    419 		return r;
    420 	}
    421 	return 0;
    422 }
    423 
    424 /**
    425  * radeon_ring_commit - tell the GPU to execute the new
    426  * commands on the ring buffer
    427  *
    428  * @rdev: radeon_device pointer
    429  * @ring: radeon_ring structure holding ring information
    430  *
    431  * Update the wptr (write pointer) to tell the GPU to
    432  * execute new commands on the ring buffer (all asics).
    433  */
    434 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *ring)
    435 {
    436 	/* We pad to match fetch size */
    437 	while (ring->wptr & ring->align_mask) {
    438 		radeon_ring_write(ring, ring->nop);
    439 	}
    440 	mb();
    441 	radeon_ring_set_wptr(rdev, ring);
    442 }
    443 
    444 /**
    445  * radeon_ring_unlock_commit - tell the GPU to execute the new
    446  * commands on the ring buffer and unlock it
    447  *
    448  * @rdev: radeon_device pointer
    449  * @ring: radeon_ring structure holding ring information
    450  *
    451  * Call radeon_ring_commit() then unlock the ring (all asics).
    452  */
    453 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *ring)
    454 {
    455 	radeon_ring_commit(rdev, ring);
    456 	mutex_unlock(&rdev->ring_lock);
    457 }
    458 
    459 /**
    460  * radeon_ring_undo - reset the wptr
    461  *
    462  * @ring: radeon_ring structure holding ring information
    463  *
    464  * Reset the driver's copy of the wptr (all asics).
    465  */
    466 void radeon_ring_undo(struct radeon_ring *ring)
    467 {
    468 	ring->wptr = ring->wptr_old;
    469 }
    470 
    471 /**
    472  * radeon_ring_unlock_undo - reset the wptr and unlock the ring
    473  *
    474  * @ring: radeon_ring structure holding ring information
    475  *
    476  * Call radeon_ring_undo() then unlock the ring (all asics).
    477  */
    478 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *ring)
    479 {
    480 	radeon_ring_undo(ring);
    481 	mutex_unlock(&rdev->ring_lock);
    482 }
    483 
    484 /**
    485  * radeon_ring_lockup_update - update lockup variables
    486  *
    487  * @ring: radeon_ring structure holding ring information
    488  *
    489  * Update the last rptr value and timestamp (all asics).
    490  */
    491 void radeon_ring_lockup_update(struct radeon_device *rdev,
    492 			       struct radeon_ring *ring)
    493 {
    494 	atomic_set(&ring->last_rptr, radeon_ring_get_rptr(rdev, ring));
    495 	atomic64_set(&ring->last_activity, jiffies_64);
    496 }
    497 
    498 /**
    499  * radeon_ring_test_lockup() - check if ring is lockedup by recording information
    500  * @rdev:       radeon device structure
    501  * @ring:       radeon_ring structure holding ring information
    502  *
    503  */
    504 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
    505 {
    506 	uint32_t rptr = radeon_ring_get_rptr(rdev, ring);
    507 	uint64_t last = atomic64_read(&ring->last_activity);
    508 	uint64_t elapsed;
    509 
    510 	if (rptr != atomic_read(&ring->last_rptr)) {
    511 		/* ring is still working, no lockup */
    512 		radeon_ring_lockup_update(rdev, ring);
    513 		return false;
    514 	}
    515 
    516 	elapsed = jiffies_to_msecs(jiffies_64 - last);
    517 	if (radeon_lockup_timeout && elapsed >= radeon_lockup_timeout) {
    518 		dev_err(rdev->dev, "ring %d stalled for more than %llumsec\n",
    519 			ring->idx, elapsed);
    520 		return true;
    521 	}
    522 	/* give a chance to the GPU ... */
    523 	return false;
    524 }
    525 
    526 /**
    527  * radeon_ring_backup - Back up the content of a ring
    528  *
    529  * @rdev: radeon_device pointer
    530  * @ring: the ring we want to back up
    531  *
    532  * Saves all unprocessed commits from a ring, returns the number of dwords saved.
    533  */
    534 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
    535 			    uint32_t **data)
    536 {
    537 	unsigned size, ptr, i;
    538 
    539 	/* just in case lock the ring */
    540 	mutex_lock(&rdev->ring_lock);
    541 	*data = NULL;
    542 
    543 	if (ring->ring_obj == NULL) {
    544 		mutex_unlock(&rdev->ring_lock);
    545 		return 0;
    546 	}
    547 
    548 	/* it doesn't make sense to save anything if all fences are signaled */
    549 	if (!radeon_fence_count_emitted(rdev, ring->idx)) {
    550 		mutex_unlock(&rdev->ring_lock);
    551 		return 0;
    552 	}
    553 
    554 	/* calculate the number of dw on the ring */
    555 	if (ring->rptr_save_reg)
    556 		ptr = RREG32(ring->rptr_save_reg);
    557 	else if (rdev->wb.enabled)
    558 		ptr = le32_to_cpu(*ring->next_rptr_cpu_addr);
    559 	else {
    560 		/* no way to read back the next rptr */
    561 		mutex_unlock(&rdev->ring_lock);
    562 		return 0;
    563 	}
    564 
    565 	size = ring->wptr + (ring->ring_size / 4);
    566 	size -= ptr;
    567 	size &= ring->ptr_mask;
    568 	if (size == 0) {
    569 		mutex_unlock(&rdev->ring_lock);
    570 		return 0;
    571 	}
    572 
    573 	/* and then save the content of the ring */
    574 	*data = kmalloc_array(size, sizeof(uint32_t), GFP_KERNEL);
    575 	if (!*data) {
    576 		mutex_unlock(&rdev->ring_lock);
    577 		return 0;
    578 	}
    579 	for (i = 0; i < size; ++i) {
    580 		(*data)[i] = ring->ring[ptr++];
    581 		ptr &= ring->ptr_mask;
    582 	}
    583 
    584 	mutex_unlock(&rdev->ring_lock);
    585 	return size;
    586 }
    587 
    588 /**
    589  * radeon_ring_restore - append saved commands to the ring again
    590  *
    591  * @rdev: radeon_device pointer
    592  * @ring: ring to append commands to
    593  * @size: number of dwords we want to write
    594  * @data: saved commands
    595  *
    596  * Allocates space on the ring and restore the previously saved commands.
    597  */
    598 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
    599 			unsigned size, uint32_t *data)
    600 {
    601 	int i, r;
    602 
    603 	if (!size || !data)
    604 		return 0;
    605 
    606 	/* restore the saved ring content */
    607 	r = radeon_ring_lock(rdev, ring, size);
    608 	if (r)
    609 		return r;
    610 
    611 	for (i = 0; i < size; ++i) {
    612 		radeon_ring_write(ring, data[i]);
    613 	}
    614 
    615 	radeon_ring_unlock_commit(rdev, ring);
    616 	kfree(data);
    617 	return 0;
    618 }
    619 
    620 /**
    621  * radeon_ring_init - init driver ring struct.
    622  *
    623  * @rdev: radeon_device pointer
    624  * @ring: radeon_ring structure holding ring information
    625  * @ring_size: size of the ring
    626  * @rptr_offs: offset of the rptr writeback location in the WB buffer
    627  * @nop: nop packet for this ring
    628  *
    629  * Initialize the driver information for the selected ring (all asics).
    630  * Returns 0 on success, error on failure.
    631  */
    632 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size,
    633 		     unsigned rptr_offs, u32 nop)
    634 {
    635 	int r;
    636 
    637 	ring->ring_size = ring_size;
    638 	ring->rptr_offs = rptr_offs;
    639 	ring->nop = nop;
    640 	/* Allocate ring buffer */
    641 	if (ring->ring_obj == NULL) {
    642 		r = radeon_bo_create(rdev, ring->ring_size, PAGE_SIZE, true,
    643 				     RADEON_GEM_DOMAIN_GTT,
    644 				     NULL, &ring->ring_obj);
    645 		if (r) {
    646 			dev_err(rdev->dev, "(%d) ring create failed\n", r);
    647 			return r;
    648 		}
    649 		r = radeon_bo_reserve(ring->ring_obj, false);
    650 		if (unlikely(r != 0))
    651 			return r;
    652 		r = radeon_bo_pin(ring->ring_obj, RADEON_GEM_DOMAIN_GTT,
    653 					&ring->gpu_addr);
    654 		if (r) {
    655 			radeon_bo_unreserve(ring->ring_obj);
    656 			dev_err(rdev->dev, "(%d) ring pin failed\n", r);
    657 			return r;
    658 		}
    659 		r = radeon_bo_kmap(ring->ring_obj,
    660 				       (void **)&ring->ring);
    661 		radeon_bo_unreserve(ring->ring_obj);
    662 		if (r) {
    663 			dev_err(rdev->dev, "(%d) ring map failed\n", r);
    664 			return r;
    665 		}
    666 	}
    667 	ring->ptr_mask = (ring->ring_size / 4) - 1;
    668 	ring->ring_free_dw = ring->ring_size / 4;
    669 	if (rdev->wb.enabled) {
    670 		u32 index = RADEON_WB_RING0_NEXT_RPTR + (ring->idx * 4);
    671 		ring->next_rptr_gpu_addr = rdev->wb.gpu_addr + index;
    672 		ring->next_rptr_cpu_addr = &rdev->wb.wb[index/4];
    673 	}
    674 	if (radeon_debugfs_ring_init(rdev, ring)) {
    675 		DRM_ERROR("Failed to register debugfs file for rings !\n");
    676 	}
    677 	radeon_ring_lockup_update(rdev, ring);
    678 	return 0;
    679 }
    680 
    681 /**
    682  * radeon_ring_fini - tear down the driver ring struct.
    683  *
    684  * @rdev: radeon_device pointer
    685  * @ring: radeon_ring structure holding ring information
    686  *
    687  * Tear down the driver information for the selected ring (all asics).
    688  */
    689 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *ring)
    690 {
    691 	int r;
    692 	struct radeon_bo *ring_obj;
    693 
    694 	mutex_lock(&rdev->ring_lock);
    695 	ring_obj = ring->ring_obj;
    696 	ring->ready = false;
    697 	ring->ring = NULL;
    698 	ring->ring_obj = NULL;
    699 	mutex_unlock(&rdev->ring_lock);
    700 
    701 	if (ring_obj) {
    702 		r = radeon_bo_reserve(ring_obj, false);
    703 		if (likely(r == 0)) {
    704 			radeon_bo_kunmap(ring_obj);
    705 			radeon_bo_unpin(ring_obj);
    706 			radeon_bo_unreserve(ring_obj);
    707 		}
    708 		radeon_bo_unref(&ring_obj);
    709 	}
    710 }
    711 
    712 /*
    713  * Debugfs info
    714  */
    715 #if defined(CONFIG_DEBUG_FS)
    716 
    717 static int radeon_debugfs_ring_info(struct seq_file *m, void *data)
    718 {
    719 	struct drm_info_node *node = (struct drm_info_node *) m->private;
    720 	struct drm_device *dev = node->minor->dev;
    721 	struct radeon_device *rdev = dev->dev_private;
    722 	int ridx = *(int*)node->info_ent->data;
    723 	struct radeon_ring *ring = &rdev->ring[ridx];
    724 
    725 	uint32_t rptr, wptr, rptr_next;
    726 	unsigned count, i, j;
    727 
    728 	radeon_ring_free_size(rdev, ring);
    729 	count = (ring->ring_size / 4) - ring->ring_free_dw;
    730 
    731 	wptr = radeon_ring_get_wptr(rdev, ring);
    732 	seq_printf(m, "wptr: 0x%08x [%5d]\n",
    733 		   wptr, wptr);
    734 
    735 	rptr = radeon_ring_get_rptr(rdev, ring);
    736 	seq_printf(m, "rptr: 0x%08x [%5d]\n",
    737 		   rptr, rptr);
    738 
    739 	if (ring->rptr_save_reg) {
    740 		rptr_next = RREG32(ring->rptr_save_reg);
    741 		seq_printf(m, "rptr next(0x%04x): 0x%08x [%5d]\n",
    742 			   ring->rptr_save_reg, rptr_next, rptr_next);
    743 	} else
    744 		rptr_next = ~0;
    745 
    746 	seq_printf(m, "driver's copy of the wptr: 0x%08x [%5d]\n",
    747 		   ring->wptr, ring->wptr);
    748 	seq_printf(m, "last semaphore signal addr : 0x%016llx\n",
    749 		   ring->last_semaphore_signal_addr);
    750 	seq_printf(m, "last semaphore wait addr   : 0x%016llx\n",
    751 		   ring->last_semaphore_wait_addr);
    752 	seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
    753 	seq_printf(m, "%u dwords in ring\n", count);
    754 
    755 	if (!ring->ready)
    756 		return 0;
    757 
    758 	/* print 8 dw before current rptr as often it's the last executed
    759 	 * packet that is the root issue
    760 	 */
    761 	i = (rptr + ring->ptr_mask + 1 - 32) & ring->ptr_mask;
    762 	for (j = 0; j <= (count + 32); j++) {
    763 		seq_printf(m, "r[%5d]=0x%08x", i, ring->ring[i]);
    764 		if (rptr == i)
    765 			seq_puts(m, " *");
    766 		if (rptr_next == i)
    767 			seq_puts(m, " #");
    768 		seq_puts(m, "\n");
    769 		i = (i + 1) & ring->ptr_mask;
    770 	}
    771 	return 0;
    772 }
    773 
    774 static int radeon_gfx_index = RADEON_RING_TYPE_GFX_INDEX;
    775 static int cayman_cp1_index = CAYMAN_RING_TYPE_CP1_INDEX;
    776 static int cayman_cp2_index = CAYMAN_RING_TYPE_CP2_INDEX;
    777 static int radeon_dma1_index = R600_RING_TYPE_DMA_INDEX;
    778 static int radeon_dma2_index = CAYMAN_RING_TYPE_DMA1_INDEX;
    779 static int r600_uvd_index = R600_RING_TYPE_UVD_INDEX;
    780 static int si_vce1_index = TN_RING_TYPE_VCE1_INDEX;
    781 static int si_vce2_index = TN_RING_TYPE_VCE2_INDEX;
    782 
    783 static struct drm_info_list radeon_debugfs_ring_info_list[] = {
    784 	{"radeon_ring_gfx", radeon_debugfs_ring_info, 0, &radeon_gfx_index},
    785 	{"radeon_ring_cp1", radeon_debugfs_ring_info, 0, &cayman_cp1_index},
    786 	{"radeon_ring_cp2", radeon_debugfs_ring_info, 0, &cayman_cp2_index},
    787 	{"radeon_ring_dma1", radeon_debugfs_ring_info, 0, &radeon_dma1_index},
    788 	{"radeon_ring_dma2", radeon_debugfs_ring_info, 0, &radeon_dma2_index},
    789 	{"radeon_ring_uvd", radeon_debugfs_ring_info, 0, &r600_uvd_index},
    790 	{"radeon_ring_vce1", radeon_debugfs_ring_info, 0, &si_vce1_index},
    791 	{"radeon_ring_vce2", radeon_debugfs_ring_info, 0, &si_vce2_index},
    792 };
    793 
    794 static int radeon_debugfs_sa_info(struct seq_file *m, void *data)
    795 {
    796 	struct drm_info_node *node = (struct drm_info_node *) m->private;
    797 	struct drm_device *dev = node->minor->dev;
    798 	struct radeon_device *rdev = dev->dev_private;
    799 
    800 	radeon_sa_bo_dump_debug_info(&rdev->ring_tmp_bo, m);
    801 
    802 	return 0;
    803 
    804 }
    805 
    806 static struct drm_info_list radeon_debugfs_sa_list[] = {
    807         {"radeon_sa_info", &radeon_debugfs_sa_info, 0, NULL},
    808 };
    809 
    810 #endif
    811 
    812 static int radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring)
    813 {
    814 #if defined(CONFIG_DEBUG_FS)
    815 	unsigned i;
    816 	for (i = 0; i < ARRAY_SIZE(radeon_debugfs_ring_info_list); ++i) {
    817 		struct drm_info_list *info = &radeon_debugfs_ring_info_list[i];
    818 		int ridx = *(int*)radeon_debugfs_ring_info_list[i].data;
    819 		unsigned r;
    820 
    821 		if (&rdev->ring[ridx] != ring)
    822 			continue;
    823 
    824 		r = radeon_debugfs_add_files(rdev, info, 1);
    825 		if (r)
    826 			return r;
    827 	}
    828 #endif
    829 	return 0;
    830 }
    831 
    832 static int radeon_debugfs_sa_init(struct radeon_device *rdev)
    833 {
    834 #if defined(CONFIG_DEBUG_FS)
    835 	return radeon_debugfs_add_files(rdev, radeon_debugfs_sa_list, 1);
    836 #else
    837 	return 0;
    838 #endif
    839 }
    840