radeon_rs690.c revision 1.1.6.2
1 /* $NetBSD: radeon_rs690.c,v 1.1.6.2 2019/06/10 22:08:26 christos Exp $ */ 2 3 /* 4 * Copyright 2008 Advanced Micro Devices, Inc. 5 * Copyright 2008 Red Hat Inc. 6 * Copyright 2009 Jerome Glisse. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: Dave Airlie 27 * Alex Deucher 28 * Jerome Glisse 29 */ 30 #include <sys/cdefs.h> 31 __KERNEL_RCSID(0, "$NetBSD: radeon_rs690.c,v 1.1.6.2 2019/06/10 22:08:26 christos Exp $"); 32 33 #include <drm/drmP.h> 34 #include "radeon.h" 35 #include "radeon_asic.h" 36 #include "radeon_audio.h" 37 #include "atom.h" 38 #include "rs690d.h" 39 40 int rs690_mc_wait_for_idle(struct radeon_device *rdev) 41 { 42 unsigned i; 43 uint32_t tmp; 44 45 for (i = 0; i < rdev->usec_timeout; i++) { 46 /* read MC_STATUS */ 47 tmp = RREG32_MC(R_000090_MC_SYSTEM_STATUS); 48 if (G_000090_MC_SYSTEM_IDLE(tmp)) 49 return 0; 50 udelay(1); 51 } 52 return -1; 53 } 54 55 static void rs690_gpu_init(struct radeon_device *rdev) 56 { 57 /* FIXME: is this correct ? */ 58 r420_pipes_init(rdev); 59 if (rs690_mc_wait_for_idle(rdev)) { 60 printk(KERN_WARNING "Failed to wait MC idle while " 61 "programming pipes. Bad things might happen.\n"); 62 } 63 } 64 65 union igp_info { 66 struct _ATOM_INTEGRATED_SYSTEM_INFO info; 67 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_v2; 68 }; 69 70 void rs690_pm_info(struct radeon_device *rdev) 71 { 72 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); 73 union igp_info *info; 74 uint16_t data_offset; 75 uint8_t frev, crev; 76 fixed20_12 tmp; 77 78 if (atom_parse_data_header(rdev->mode_info.atom_context, index, NULL, 79 &frev, &crev, &data_offset)) { 80 info = (union igp_info *)(rdev->mode_info.atom_context->bios + data_offset); 81 82 /* Get various system informations from bios */ 83 switch (crev) { 84 case 1: 85 tmp.full = dfixed_const(100); 86 rdev->pm.igp_sideport_mclk.full = dfixed_const(le32_to_cpu(info->info.ulBootUpMemoryClock)); 87 rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp); 88 if (le16_to_cpu(info->info.usK8MemoryClock)) 89 rdev->pm.igp_system_mclk.full = dfixed_const(le16_to_cpu(info->info.usK8MemoryClock)); 90 else if (rdev->clock.default_mclk) { 91 rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk); 92 rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp); 93 } else 94 rdev->pm.igp_system_mclk.full = dfixed_const(400); 95 rdev->pm.igp_ht_link_clk.full = dfixed_const(le16_to_cpu(info->info.usFSBClock)); 96 rdev->pm.igp_ht_link_width.full = dfixed_const(info->info.ucHTLinkWidth); 97 break; 98 case 2: 99 tmp.full = dfixed_const(100); 100 rdev->pm.igp_sideport_mclk.full = dfixed_const(le32_to_cpu(info->info_v2.ulBootUpSidePortClock)); 101 rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp); 102 if (le32_to_cpu(info->info_v2.ulBootUpUMAClock)) 103 rdev->pm.igp_system_mclk.full = dfixed_const(le32_to_cpu(info->info_v2.ulBootUpUMAClock)); 104 else if (rdev->clock.default_mclk) 105 rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk); 106 else 107 rdev->pm.igp_system_mclk.full = dfixed_const(66700); 108 rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp); 109 rdev->pm.igp_ht_link_clk.full = dfixed_const(le32_to_cpu(info->info_v2.ulHTLinkFreq)); 110 rdev->pm.igp_ht_link_clk.full = dfixed_div(rdev->pm.igp_ht_link_clk, tmp); 111 rdev->pm.igp_ht_link_width.full = dfixed_const(le16_to_cpu(info->info_v2.usMinHTLinkWidth)); 112 break; 113 default: 114 /* We assume the slower possible clock ie worst case */ 115 rdev->pm.igp_sideport_mclk.full = dfixed_const(200); 116 rdev->pm.igp_system_mclk.full = dfixed_const(200); 117 rdev->pm.igp_ht_link_clk.full = dfixed_const(1000); 118 rdev->pm.igp_ht_link_width.full = dfixed_const(8); 119 DRM_ERROR("No integrated system info for your GPU, using safe default\n"); 120 break; 121 } 122 } else { 123 /* We assume the slower possible clock ie worst case */ 124 rdev->pm.igp_sideport_mclk.full = dfixed_const(200); 125 rdev->pm.igp_system_mclk.full = dfixed_const(200); 126 rdev->pm.igp_ht_link_clk.full = dfixed_const(1000); 127 rdev->pm.igp_ht_link_width.full = dfixed_const(8); 128 DRM_ERROR("No integrated system info for your GPU, using safe default\n"); 129 } 130 /* Compute various bandwidth */ 131 /* k8_bandwidth = (memory_clk / 2) * 2 * 8 * 0.5 = memory_clk * 4 */ 132 tmp.full = dfixed_const(4); 133 rdev->pm.k8_bandwidth.full = dfixed_mul(rdev->pm.igp_system_mclk, tmp); 134 /* ht_bandwidth = ht_clk * 2 * ht_width / 8 * 0.8 135 * = ht_clk * ht_width / 5 136 */ 137 tmp.full = dfixed_const(5); 138 rdev->pm.ht_bandwidth.full = dfixed_mul(rdev->pm.igp_ht_link_clk, 139 rdev->pm.igp_ht_link_width); 140 rdev->pm.ht_bandwidth.full = dfixed_div(rdev->pm.ht_bandwidth, tmp); 141 if (tmp.full < rdev->pm.max_bandwidth.full) { 142 /* HT link is a limiting factor */ 143 rdev->pm.max_bandwidth.full = tmp.full; 144 } 145 /* sideport_bandwidth = (sideport_clk / 2) * 2 * 2 * 0.7 146 * = (sideport_clk * 14) / 10 147 */ 148 tmp.full = dfixed_const(14); 149 rdev->pm.sideport_bandwidth.full = dfixed_mul(rdev->pm.igp_sideport_mclk, tmp); 150 tmp.full = dfixed_const(10); 151 rdev->pm.sideport_bandwidth.full = dfixed_div(rdev->pm.sideport_bandwidth, tmp); 152 } 153 154 static void rs690_mc_init(struct radeon_device *rdev) 155 { 156 u64 base; 157 uint32_t h_addr, l_addr; 158 unsigned long long k8_addr; 159 160 rs400_gart_adjust_size(rdev); 161 rdev->mc.vram_is_ddr = true; 162 rdev->mc.vram_width = 128; 163 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); 164 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; 165 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); 166 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); 167 rdev->mc.visible_vram_size = rdev->mc.aper_size; 168 base = RREG32_MC(R_000100_MCCFG_FB_LOCATION); 169 base = G_000100_MC_FB_START(base) << 16; 170 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); 171 /* Some boards seem to be configured for 128MB of sideport memory, 172 * but really only have 64MB. Just skip the sideport and use 173 * UMA memory. 174 */ 175 if (rdev->mc.igp_sideport_enabled && 176 (rdev->mc.real_vram_size == (384 * 1024 * 1024))) { 177 base += 128 * 1024 * 1024; 178 rdev->mc.real_vram_size -= 128 * 1024 * 1024; 179 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; 180 } 181 182 /* Use K8 direct mapping for fast fb access. */ 183 rdev->fastfb_working = false; 184 h_addr = G_00005F_K8_ADDR_EXT(RREG32_MC(R_00005F_MC_MISC_UMA_CNTL)); 185 l_addr = RREG32_MC(R_00001E_K8_FB_LOCATION); 186 k8_addr = ((unsigned long long)h_addr) << 32 | l_addr; 187 #if defined(CONFIG_X86_32) && !defined(CONFIG_X86_PAE) 188 if (k8_addr + rdev->mc.visible_vram_size < 0x100000000ULL) 189 #endif 190 { 191 /* FastFB shall be used with UMA memory. Here it is simply disabled when sideport 192 * memory is present. 193 */ 194 if (rdev->mc.igp_sideport_enabled == false && radeon_fastfb == 1) { 195 DRM_INFO("Direct mapping: aper base at 0x%llx, replaced by direct mapping base 0x%llx.\n", 196 (unsigned long long)rdev->mc.aper_base, k8_addr); 197 rdev->mc.aper_base = (resource_size_t)k8_addr; 198 rdev->fastfb_working = true; 199 } 200 } 201 202 rs690_pm_info(rdev); 203 radeon_vram_location(rdev, &rdev->mc, base); 204 rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1; 205 radeon_gtt_location(rdev, &rdev->mc); 206 radeon_update_bandwidth_info(rdev); 207 } 208 209 void rs690_line_buffer_adjust(struct radeon_device *rdev, 210 struct drm_display_mode *mode1, 211 struct drm_display_mode *mode2) 212 { 213 u32 tmp; 214 215 /* Guess line buffer size to be 8192 pixels */ 216 u32 lb_size = 8192; 217 218 /* 219 * Line Buffer Setup 220 * There is a single line buffer shared by both display controllers. 221 * R_006520_DC_LB_MEMORY_SPLIT controls how that line buffer is shared between 222 * the display controllers. The paritioning can either be done 223 * manually or via one of four preset allocations specified in bits 1:0: 224 * 0 - line buffer is divided in half and shared between crtc 225 * 1 - D1 gets 3/4 of the line buffer, D2 gets 1/4 226 * 2 - D1 gets the whole buffer 227 * 3 - D1 gets 1/4 of the line buffer, D2 gets 3/4 228 * Setting bit 2 of R_006520_DC_LB_MEMORY_SPLIT controls switches to manual 229 * allocation mode. In manual allocation mode, D1 always starts at 0, 230 * D1 end/2 is specified in bits 14:4; D2 allocation follows D1. 231 */ 232 tmp = RREG32(R_006520_DC_LB_MEMORY_SPLIT) & C_006520_DC_LB_MEMORY_SPLIT; 233 tmp &= ~C_006520_DC_LB_MEMORY_SPLIT_MODE; 234 /* auto */ 235 if (mode1 && mode2) { 236 if (mode1->hdisplay > mode2->hdisplay) { 237 if (mode1->hdisplay > 2560) 238 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q; 239 else 240 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF; 241 } else if (mode2->hdisplay > mode1->hdisplay) { 242 if (mode2->hdisplay > 2560) 243 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q; 244 else 245 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF; 246 } else 247 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF; 248 } else if (mode1) { 249 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_ONLY; 250 } else if (mode2) { 251 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q; 252 } 253 WREG32(R_006520_DC_LB_MEMORY_SPLIT, tmp); 254 255 /* Save number of lines the linebuffer leads before the scanout */ 256 if (mode1) 257 rdev->mode_info.crtcs[0]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode1->crtc_hdisplay); 258 259 if (mode2) 260 rdev->mode_info.crtcs[1]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode2->crtc_hdisplay); 261 } 262 263 struct rs690_watermark { 264 u32 lb_request_fifo_depth; 265 fixed20_12 num_line_pair; 266 fixed20_12 estimated_width; 267 fixed20_12 worst_case_latency; 268 fixed20_12 consumption_rate; 269 fixed20_12 active_time; 270 fixed20_12 dbpp; 271 fixed20_12 priority_mark_max; 272 fixed20_12 priority_mark; 273 fixed20_12 sclk; 274 }; 275 276 static void rs690_crtc_bandwidth_compute(struct radeon_device *rdev, 277 struct radeon_crtc *crtc, 278 struct rs690_watermark *wm, 279 bool low) 280 { 281 struct drm_display_mode *mode = &crtc->base.mode; 282 fixed20_12 a, b, c; 283 fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width; 284 fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency; 285 fixed20_12 sclk, core_bandwidth, max_bandwidth; 286 u32 selected_sclk; 287 288 if (!crtc->base.enabled) { 289 /* FIXME: wouldn't it better to set priority mark to maximum */ 290 wm->lb_request_fifo_depth = 4; 291 return; 292 } 293 294 if (((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880)) && 295 (rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) 296 selected_sclk = radeon_dpm_get_sclk(rdev, low); 297 else 298 selected_sclk = rdev->pm.current_sclk; 299 300 /* sclk in Mhz */ 301 a.full = dfixed_const(100); 302 sclk.full = dfixed_const(selected_sclk); 303 sclk.full = dfixed_div(sclk, a); 304 305 /* core_bandwidth = sclk(Mhz) * 16 */ 306 a.full = dfixed_const(16); 307 core_bandwidth.full = dfixed_div(rdev->pm.sclk, a); 308 309 if (crtc->vsc.full > dfixed_const(2)) 310 wm->num_line_pair.full = dfixed_const(2); 311 else 312 wm->num_line_pair.full = dfixed_const(1); 313 314 b.full = dfixed_const(mode->crtc_hdisplay); 315 c.full = dfixed_const(256); 316 a.full = dfixed_div(b, c); 317 request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair); 318 request_fifo_depth.full = dfixed_ceil(request_fifo_depth); 319 if (a.full < dfixed_const(4)) { 320 wm->lb_request_fifo_depth = 4; 321 } else { 322 wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth); 323 } 324 325 /* Determine consumption rate 326 * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000) 327 * vtaps = number of vertical taps, 328 * vsc = vertical scaling ratio, defined as source/destination 329 * hsc = horizontal scaling ration, defined as source/destination 330 */ 331 a.full = dfixed_const(mode->clock); 332 b.full = dfixed_const(1000); 333 a.full = dfixed_div(a, b); 334 pclk.full = dfixed_div(b, a); 335 if (crtc->rmx_type != RMX_OFF) { 336 b.full = dfixed_const(2); 337 if (crtc->vsc.full > b.full) 338 b.full = crtc->vsc.full; 339 b.full = dfixed_mul(b, crtc->hsc); 340 c.full = dfixed_const(2); 341 b.full = dfixed_div(b, c); 342 consumption_time.full = dfixed_div(pclk, b); 343 } else { 344 consumption_time.full = pclk.full; 345 } 346 a.full = dfixed_const(1); 347 wm->consumption_rate.full = dfixed_div(a, consumption_time); 348 349 350 /* Determine line time 351 * LineTime = total time for one line of displayhtotal 352 * LineTime = total number of horizontal pixels 353 * pclk = pixel clock period(ns) 354 */ 355 a.full = dfixed_const(crtc->base.mode.crtc_htotal); 356 line_time.full = dfixed_mul(a, pclk); 357 358 /* Determine active time 359 * ActiveTime = time of active region of display within one line, 360 * hactive = total number of horizontal active pixels 361 * htotal = total number of horizontal pixels 362 */ 363 a.full = dfixed_const(crtc->base.mode.crtc_htotal); 364 b.full = dfixed_const(crtc->base.mode.crtc_hdisplay); 365 wm->active_time.full = dfixed_mul(line_time, b); 366 wm->active_time.full = dfixed_div(wm->active_time, a); 367 368 /* Maximun bandwidth is the minimun bandwidth of all component */ 369 max_bandwidth = core_bandwidth; 370 if (rdev->mc.igp_sideport_enabled) { 371 if (max_bandwidth.full > rdev->pm.sideport_bandwidth.full && 372 rdev->pm.sideport_bandwidth.full) 373 max_bandwidth = rdev->pm.sideport_bandwidth; 374 read_delay_latency.full = dfixed_const(370 * 800); 375 a.full = dfixed_const(1000); 376 b.full = dfixed_div(rdev->pm.igp_sideport_mclk, a); 377 read_delay_latency.full = dfixed_div(read_delay_latency, b); 378 read_delay_latency.full = dfixed_mul(read_delay_latency, a); 379 } else { 380 if (max_bandwidth.full > rdev->pm.k8_bandwidth.full && 381 rdev->pm.k8_bandwidth.full) 382 max_bandwidth = rdev->pm.k8_bandwidth; 383 if (max_bandwidth.full > rdev->pm.ht_bandwidth.full && 384 rdev->pm.ht_bandwidth.full) 385 max_bandwidth = rdev->pm.ht_bandwidth; 386 read_delay_latency.full = dfixed_const(5000); 387 } 388 389 /* sclk = system clocks(ns) = 1000 / max_bandwidth / 16 */ 390 a.full = dfixed_const(16); 391 sclk.full = dfixed_mul(max_bandwidth, a); 392 a.full = dfixed_const(1000); 393 sclk.full = dfixed_div(a, sclk); 394 /* Determine chunk time 395 * ChunkTime = the time it takes the DCP to send one chunk of data 396 * to the LB which consists of pipeline delay and inter chunk gap 397 * sclk = system clock(ns) 398 */ 399 a.full = dfixed_const(256 * 13); 400 chunk_time.full = dfixed_mul(sclk, a); 401 a.full = dfixed_const(10); 402 chunk_time.full = dfixed_div(chunk_time, a); 403 404 /* Determine the worst case latency 405 * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines) 406 * WorstCaseLatency = worst case time from urgent to when the MC starts 407 * to return data 408 * READ_DELAY_IDLE_MAX = constant of 1us 409 * ChunkTime = time it takes the DCP to send one chunk of data to the LB 410 * which consists of pipeline delay and inter chunk gap 411 */ 412 if (dfixed_trunc(wm->num_line_pair) > 1) { 413 a.full = dfixed_const(3); 414 wm->worst_case_latency.full = dfixed_mul(a, chunk_time); 415 wm->worst_case_latency.full += read_delay_latency.full; 416 } else { 417 a.full = dfixed_const(2); 418 wm->worst_case_latency.full = dfixed_mul(a, chunk_time); 419 wm->worst_case_latency.full += read_delay_latency.full; 420 } 421 422 /* Determine the tolerable latency 423 * TolerableLatency = Any given request has only 1 line time 424 * for the data to be returned 425 * LBRequestFifoDepth = Number of chunk requests the LB can 426 * put into the request FIFO for a display 427 * LineTime = total time for one line of display 428 * ChunkTime = the time it takes the DCP to send one chunk 429 * of data to the LB which consists of 430 * pipeline delay and inter chunk gap 431 */ 432 if ((2+wm->lb_request_fifo_depth) >= dfixed_trunc(request_fifo_depth)) { 433 tolerable_latency.full = line_time.full; 434 } else { 435 tolerable_latency.full = dfixed_const(wm->lb_request_fifo_depth - 2); 436 tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full; 437 tolerable_latency.full = dfixed_mul(tolerable_latency, chunk_time); 438 tolerable_latency.full = line_time.full - tolerable_latency.full; 439 } 440 /* We assume worst case 32bits (4 bytes) */ 441 wm->dbpp.full = dfixed_const(4 * 8); 442 443 /* Determine the maximum priority mark 444 * width = viewport width in pixels 445 */ 446 a.full = dfixed_const(16); 447 wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay); 448 wm->priority_mark_max.full = dfixed_div(wm->priority_mark_max, a); 449 wm->priority_mark_max.full = dfixed_ceil(wm->priority_mark_max); 450 451 /* Determine estimated width */ 452 estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full; 453 estimated_width.full = dfixed_div(estimated_width, consumption_time); 454 if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) { 455 wm->priority_mark.full = dfixed_const(10); 456 } else { 457 a.full = dfixed_const(16); 458 wm->priority_mark.full = dfixed_div(estimated_width, a); 459 wm->priority_mark.full = dfixed_ceil(wm->priority_mark); 460 wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full; 461 } 462 } 463 464 static void rs690_compute_mode_priority(struct radeon_device *rdev, 465 struct rs690_watermark *wm0, 466 struct rs690_watermark *wm1, 467 struct drm_display_mode *mode0, 468 struct drm_display_mode *mode1, 469 u32 *d1mode_priority_a_cnt, 470 u32 *d2mode_priority_a_cnt) 471 { 472 fixed20_12 priority_mark02, priority_mark12, fill_rate; 473 fixed20_12 a, b; 474 475 *d1mode_priority_a_cnt = S_006548_D1MODE_PRIORITY_A_OFF(1); 476 *d2mode_priority_a_cnt = S_006548_D1MODE_PRIORITY_A_OFF(1); 477 478 if (mode0 && mode1) { 479 if (dfixed_trunc(wm0->dbpp) > 64) 480 a.full = dfixed_mul(wm0->dbpp, wm0->num_line_pair); 481 else 482 a.full = wm0->num_line_pair.full; 483 if (dfixed_trunc(wm1->dbpp) > 64) 484 b.full = dfixed_mul(wm1->dbpp, wm1->num_line_pair); 485 else 486 b.full = wm1->num_line_pair.full; 487 a.full += b.full; 488 fill_rate.full = dfixed_div(wm0->sclk, a); 489 if (wm0->consumption_rate.full > fill_rate.full) { 490 b.full = wm0->consumption_rate.full - fill_rate.full; 491 b.full = dfixed_mul(b, wm0->active_time); 492 a.full = dfixed_mul(wm0->worst_case_latency, 493 wm0->consumption_rate); 494 a.full = a.full + b.full; 495 b.full = dfixed_const(16 * 1000); 496 priority_mark02.full = dfixed_div(a, b); 497 } else { 498 a.full = dfixed_mul(wm0->worst_case_latency, 499 wm0->consumption_rate); 500 b.full = dfixed_const(16 * 1000); 501 priority_mark02.full = dfixed_div(a, b); 502 } 503 if (wm1->consumption_rate.full > fill_rate.full) { 504 b.full = wm1->consumption_rate.full - fill_rate.full; 505 b.full = dfixed_mul(b, wm1->active_time); 506 a.full = dfixed_mul(wm1->worst_case_latency, 507 wm1->consumption_rate); 508 a.full = a.full + b.full; 509 b.full = dfixed_const(16 * 1000); 510 priority_mark12.full = dfixed_div(a, b); 511 } else { 512 a.full = dfixed_mul(wm1->worst_case_latency, 513 wm1->consumption_rate); 514 b.full = dfixed_const(16 * 1000); 515 priority_mark12.full = dfixed_div(a, b); 516 } 517 if (wm0->priority_mark.full > priority_mark02.full) 518 priority_mark02.full = wm0->priority_mark.full; 519 if (wm0->priority_mark_max.full > priority_mark02.full) 520 priority_mark02.full = wm0->priority_mark_max.full; 521 if (wm1->priority_mark.full > priority_mark12.full) 522 priority_mark12.full = wm1->priority_mark.full; 523 if (wm1->priority_mark_max.full > priority_mark12.full) 524 priority_mark12.full = wm1->priority_mark_max.full; 525 *d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); 526 *d2mode_priority_a_cnt = dfixed_trunc(priority_mark12); 527 if (rdev->disp_priority == 2) { 528 *d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1); 529 *d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1); 530 } 531 } else if (mode0) { 532 if (dfixed_trunc(wm0->dbpp) > 64) 533 a.full = dfixed_mul(wm0->dbpp, wm0->num_line_pair); 534 else 535 a.full = wm0->num_line_pair.full; 536 fill_rate.full = dfixed_div(wm0->sclk, a); 537 if (wm0->consumption_rate.full > fill_rate.full) { 538 b.full = wm0->consumption_rate.full - fill_rate.full; 539 b.full = dfixed_mul(b, wm0->active_time); 540 a.full = dfixed_mul(wm0->worst_case_latency, 541 wm0->consumption_rate); 542 a.full = a.full + b.full; 543 b.full = dfixed_const(16 * 1000); 544 priority_mark02.full = dfixed_div(a, b); 545 } else { 546 a.full = dfixed_mul(wm0->worst_case_latency, 547 wm0->consumption_rate); 548 b.full = dfixed_const(16 * 1000); 549 priority_mark02.full = dfixed_div(a, b); 550 } 551 if (wm0->priority_mark.full > priority_mark02.full) 552 priority_mark02.full = wm0->priority_mark.full; 553 if (wm0->priority_mark_max.full > priority_mark02.full) 554 priority_mark02.full = wm0->priority_mark_max.full; 555 *d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); 556 if (rdev->disp_priority == 2) 557 *d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1); 558 } else if (mode1) { 559 if (dfixed_trunc(wm1->dbpp) > 64) 560 a.full = dfixed_mul(wm1->dbpp, wm1->num_line_pair); 561 else 562 a.full = wm1->num_line_pair.full; 563 fill_rate.full = dfixed_div(wm1->sclk, a); 564 if (wm1->consumption_rate.full > fill_rate.full) { 565 b.full = wm1->consumption_rate.full - fill_rate.full; 566 b.full = dfixed_mul(b, wm1->active_time); 567 a.full = dfixed_mul(wm1->worst_case_latency, 568 wm1->consumption_rate); 569 a.full = a.full + b.full; 570 b.full = dfixed_const(16 * 1000); 571 priority_mark12.full = dfixed_div(a, b); 572 } else { 573 a.full = dfixed_mul(wm1->worst_case_latency, 574 wm1->consumption_rate); 575 b.full = dfixed_const(16 * 1000); 576 priority_mark12.full = dfixed_div(a, b); 577 } 578 if (wm1->priority_mark.full > priority_mark12.full) 579 priority_mark12.full = wm1->priority_mark.full; 580 if (wm1->priority_mark_max.full > priority_mark12.full) 581 priority_mark12.full = wm1->priority_mark_max.full; 582 *d2mode_priority_a_cnt = dfixed_trunc(priority_mark12); 583 if (rdev->disp_priority == 2) 584 *d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1); 585 } 586 } 587 588 void rs690_bandwidth_update(struct radeon_device *rdev) 589 { 590 struct drm_display_mode *mode0 = NULL; 591 struct drm_display_mode *mode1 = NULL; 592 struct rs690_watermark wm0_high, wm0_low; 593 struct rs690_watermark wm1_high, wm1_low; 594 u32 tmp; 595 u32 d1mode_priority_a_cnt, d1mode_priority_b_cnt; 596 u32 d2mode_priority_a_cnt, d2mode_priority_b_cnt; 597 598 if (!rdev->mode_info.mode_config_initialized) 599 return; 600 601 radeon_update_display_priority(rdev); 602 603 if (rdev->mode_info.crtcs[0]->base.enabled) 604 mode0 = &rdev->mode_info.crtcs[0]->base.mode; 605 if (rdev->mode_info.crtcs[1]->base.enabled) 606 mode1 = &rdev->mode_info.crtcs[1]->base.mode; 607 /* 608 * Set display0/1 priority up in the memory controller for 609 * modes if the user specifies HIGH for displaypriority 610 * option. 611 */ 612 if ((rdev->disp_priority == 2) && 613 ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740))) { 614 tmp = RREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER); 615 tmp &= C_000104_MC_DISP0R_INIT_LAT; 616 tmp &= C_000104_MC_DISP1R_INIT_LAT; 617 if (mode0) 618 tmp |= S_000104_MC_DISP0R_INIT_LAT(1); 619 if (mode1) 620 tmp |= S_000104_MC_DISP1R_INIT_LAT(1); 621 WREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER, tmp); 622 } 623 rs690_line_buffer_adjust(rdev, mode0, mode1); 624 625 if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) 626 WREG32(R_006C9C_DCP_CONTROL, 0); 627 if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880)) 628 WREG32(R_006C9C_DCP_CONTROL, 2); 629 630 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_high, false); 631 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_high, false); 632 633 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_low, true); 634 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_low, true); 635 636 tmp = (wm0_high.lb_request_fifo_depth - 1); 637 tmp |= (wm1_high.lb_request_fifo_depth - 1) << 16; 638 WREG32(R_006D58_LB_MAX_REQ_OUTSTANDING, tmp); 639 640 rs690_compute_mode_priority(rdev, 641 &wm0_high, &wm1_high, 642 mode0, mode1, 643 &d1mode_priority_a_cnt, &d2mode_priority_a_cnt); 644 rs690_compute_mode_priority(rdev, 645 &wm0_low, &wm1_low, 646 mode0, mode1, 647 &d1mode_priority_b_cnt, &d2mode_priority_b_cnt); 648 649 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); 650 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_b_cnt); 651 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt); 652 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_b_cnt); 653 } 654 655 uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg) 656 { 657 unsigned long flags; 658 uint32_t r; 659 660 spin_lock_irqsave(&rdev->mc_idx_lock, flags); 661 WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg)); 662 r = RREG32(R_00007C_MC_DATA); 663 WREG32(R_000078_MC_INDEX, ~C_000078_MC_IND_ADDR); 664 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); 665 return r; 666 } 667 668 void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 669 { 670 unsigned long flags; 671 672 spin_lock_irqsave(&rdev->mc_idx_lock, flags); 673 WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg) | 674 S_000078_MC_IND_WR_EN(1)); 675 WREG32(R_00007C_MC_DATA, v); 676 WREG32(R_000078_MC_INDEX, 0x7F); 677 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); 678 } 679 680 static void rs690_mc_program(struct radeon_device *rdev) 681 { 682 struct rv515_mc_save save; 683 684 /* Stops all mc clients */ 685 rv515_mc_stop(rdev, &save); 686 687 /* Wait for mc idle */ 688 if (rs690_mc_wait_for_idle(rdev)) 689 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); 690 /* Program MC, should be a 32bits limited address space */ 691 WREG32_MC(R_000100_MCCFG_FB_LOCATION, 692 S_000100_MC_FB_START(rdev->mc.vram_start >> 16) | 693 S_000100_MC_FB_TOP(rdev->mc.vram_end >> 16)); 694 WREG32(R_000134_HDP_FB_LOCATION, 695 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); 696 697 rv515_mc_resume(rdev, &save); 698 } 699 700 static int rs690_startup(struct radeon_device *rdev) 701 { 702 int r; 703 704 rs690_mc_program(rdev); 705 /* Resume clock */ 706 rv515_clock_startup(rdev); 707 /* Initialize GPU configuration (# pipes, ...) */ 708 rs690_gpu_init(rdev); 709 /* Initialize GART (initialize after TTM so we can allocate 710 * memory through TTM but finalize after TTM) */ 711 r = rs400_gart_enable(rdev); 712 if (r) 713 return r; 714 715 /* allocate wb buffer */ 716 r = radeon_wb_init(rdev); 717 if (r) 718 return r; 719 720 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 721 if (r) { 722 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 723 return r; 724 } 725 726 /* Enable IRQ */ 727 if (!rdev->irq.installed) { 728 r = radeon_irq_kms_init(rdev); 729 if (r) 730 return r; 731 } 732 733 rs600_irq_set(rdev); 734 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 735 /* 1M ring buffer */ 736 r = r100_cp_init(rdev, 1024 * 1024); 737 if (r) { 738 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); 739 return r; 740 } 741 742 r = radeon_ib_pool_init(rdev); 743 if (r) { 744 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 745 return r; 746 } 747 748 r = radeon_audio_init(rdev); 749 if (r) { 750 dev_err(rdev->dev, "failed initializing audio\n"); 751 return r; 752 } 753 754 return 0; 755 } 756 757 int rs690_resume(struct radeon_device *rdev) 758 { 759 int r; 760 761 /* Make sur GART are not working */ 762 rs400_gart_disable(rdev); 763 /* Resume clock before doing reset */ 764 rv515_clock_startup(rdev); 765 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 766 if (radeon_asic_reset(rdev)) { 767 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 768 RREG32(R_000E40_RBBM_STATUS), 769 RREG32(R_0007C0_CP_STAT)); 770 } 771 /* post */ 772 atom_asic_init(rdev->mode_info.atom_context); 773 /* Resume clock after posting */ 774 rv515_clock_startup(rdev); 775 /* Initialize surface registers */ 776 radeon_surface_init(rdev); 777 778 rdev->accel_working = true; 779 r = rs690_startup(rdev); 780 if (r) { 781 rdev->accel_working = false; 782 } 783 return r; 784 } 785 786 int rs690_suspend(struct radeon_device *rdev) 787 { 788 radeon_pm_suspend(rdev); 789 radeon_audio_fini(rdev); 790 r100_cp_disable(rdev); 791 radeon_wb_disable(rdev); 792 rs600_irq_disable(rdev); 793 rs400_gart_disable(rdev); 794 return 0; 795 } 796 797 void rs690_fini(struct radeon_device *rdev) 798 { 799 radeon_pm_fini(rdev); 800 radeon_audio_fini(rdev); 801 r100_cp_fini(rdev); 802 radeon_wb_fini(rdev); 803 radeon_ib_pool_fini(rdev); 804 radeon_gem_fini(rdev); 805 rs400_gart_fini(rdev); 806 radeon_irq_kms_fini(rdev); 807 radeon_fence_driver_fini(rdev); 808 radeon_bo_fini(rdev); 809 radeon_atombios_fini(rdev); 810 kfree(rdev->bios); 811 rdev->bios = NULL; 812 } 813 814 int rs690_init(struct radeon_device *rdev) 815 { 816 int r; 817 818 /* Disable VGA */ 819 rv515_vga_render_disable(rdev); 820 /* Initialize scratch registers */ 821 radeon_scratch_init(rdev); 822 /* Initialize surface registers */ 823 radeon_surface_init(rdev); 824 /* restore some register to sane defaults */ 825 r100_restore_sanity(rdev); 826 /* TODO: disable VGA need to use VGA request */ 827 /* BIOS*/ 828 if (!radeon_get_bios(rdev)) { 829 if (ASIC_IS_AVIVO(rdev)) 830 return -EINVAL; 831 } 832 if (rdev->is_atom_bios) { 833 r = radeon_atombios_init(rdev); 834 if (r) 835 return r; 836 } else { 837 dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n"); 838 return -EINVAL; 839 } 840 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 841 if (radeon_asic_reset(rdev)) { 842 dev_warn(rdev->dev, 843 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 844 RREG32(R_000E40_RBBM_STATUS), 845 RREG32(R_0007C0_CP_STAT)); 846 } 847 /* check if cards are posted or not */ 848 if (radeon_boot_test_post_card(rdev) == false) 849 return -EINVAL; 850 851 /* Initialize clocks */ 852 radeon_get_clock_info(rdev->ddev); 853 /* initialize memory controller */ 854 rs690_mc_init(rdev); 855 rv515_debugfs(rdev); 856 /* Fence driver */ 857 r = radeon_fence_driver_init(rdev); 858 if (r) 859 return r; 860 /* Memory manager */ 861 r = radeon_bo_init(rdev); 862 if (r) 863 return r; 864 r = rs400_gart_init(rdev); 865 if (r) 866 return r; 867 rs600_set_safe_registers(rdev); 868 869 /* Initialize power management */ 870 radeon_pm_init(rdev); 871 872 rdev->accel_working = true; 873 r = rs690_startup(rdev); 874 if (r) { 875 /* Somethings want wront with the accel init stop accel */ 876 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 877 r100_cp_fini(rdev); 878 radeon_wb_fini(rdev); 879 radeon_ib_pool_fini(rdev); 880 rs400_gart_fini(rdev); 881 radeon_irq_kms_fini(rdev); 882 rdev->accel_working = false; 883 } 884 return 0; 885 } 886
Indexes created Wed Oct 22 13:09:56 GMT 2025