radeon_rs780_dpm.c revision 1.1.6.2
1 /* $NetBSD: radeon_rs780_dpm.c,v 1.1.6.2 2019/06/10 22:08:26 christos Exp $ */ 2 3 /* 4 * Copyright 2011 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Alex Deucher 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: radeon_rs780_dpm.c,v 1.1.6.2 2019/06/10 22:08:26 christos Exp $"); 29 30 #include "drmP.h" 31 #include "radeon.h" 32 #include "radeon_asic.h" 33 #include "rs780d.h" 34 #include "r600_dpm.h" 35 #include "rs780_dpm.h" 36 #include "atom.h" 37 #include <linux/seq_file.h> 38 39 static struct igp_ps *rs780_get_ps(struct radeon_ps *rps) 40 { 41 struct igp_ps *ps = rps->ps_priv; 42 43 return ps; 44 } 45 46 static struct igp_power_info *rs780_get_pi(struct radeon_device *rdev) 47 { 48 struct igp_power_info *pi = rdev->pm.dpm.priv; 49 50 return pi; 51 } 52 53 static void rs780_get_pm_mode_parameters(struct radeon_device *rdev) 54 { 55 struct igp_power_info *pi = rs780_get_pi(rdev); 56 struct radeon_mode_info *minfo = &rdev->mode_info; 57 struct drm_crtc *crtc; 58 struct radeon_crtc *radeon_crtc; 59 int i; 60 61 /* defaults */ 62 pi->crtc_id = 0; 63 pi->refresh_rate = 60; 64 65 for (i = 0; i < rdev->num_crtc; i++) { 66 crtc = (struct drm_crtc *)minfo->crtcs[i]; 67 if (crtc && crtc->enabled) { 68 radeon_crtc = to_radeon_crtc(crtc); 69 pi->crtc_id = radeon_crtc->crtc_id; 70 if (crtc->mode.htotal && crtc->mode.vtotal) 71 pi->refresh_rate = drm_mode_vrefresh(&crtc->mode); 72 break; 73 } 74 } 75 } 76 77 static void rs780_voltage_scaling_enable(struct radeon_device *rdev, bool enable); 78 79 static int rs780_initialize_dpm_power_state(struct radeon_device *rdev, 80 struct radeon_ps *boot_ps) 81 { 82 struct atom_clock_dividers dividers; 83 struct igp_ps *default_state = rs780_get_ps(boot_ps); 84 int i, ret; 85 86 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 87 default_state->sclk_low, false, ÷rs); 88 if (ret) 89 return ret; 90 91 r600_engine_clock_entry_set_reference_divider(rdev, 0, dividers.ref_div); 92 r600_engine_clock_entry_set_feedback_divider(rdev, 0, dividers.fb_div); 93 r600_engine_clock_entry_set_post_divider(rdev, 0, dividers.post_div); 94 95 if (dividers.enable_post_div) 96 r600_engine_clock_entry_enable_post_divider(rdev, 0, true); 97 else 98 r600_engine_clock_entry_enable_post_divider(rdev, 0, false); 99 100 r600_engine_clock_entry_set_step_time(rdev, 0, R600_SST_DFLT); 101 r600_engine_clock_entry_enable_pulse_skipping(rdev, 0, false); 102 103 r600_engine_clock_entry_enable(rdev, 0, true); 104 for (i = 1; i < R600_PM_NUMBER_OF_SCLKS; i++) 105 r600_engine_clock_entry_enable(rdev, i, false); 106 107 r600_enable_mclk_control(rdev, false); 108 r600_voltage_control_enable_pins(rdev, 0); 109 110 return 0; 111 } 112 113 static int rs780_initialize_dpm_parameters(struct radeon_device *rdev, 114 struct radeon_ps *boot_ps) 115 { 116 int ret = 0; 117 int i; 118 119 r600_set_bsp(rdev, R600_BSU_DFLT, R600_BSP_DFLT); 120 121 r600_set_at(rdev, 0, 0, 0, 0); 122 123 r600_set_git(rdev, R600_GICST_DFLT); 124 125 for (i = 0; i < R600_PM_NUMBER_OF_TC; i++) 126 r600_set_tc(rdev, i, 0, 0); 127 128 r600_select_td(rdev, R600_TD_DFLT); 129 r600_set_vrc(rdev, 0); 130 131 r600_set_tpu(rdev, R600_TPU_DFLT); 132 r600_set_tpc(rdev, R600_TPC_DFLT); 133 134 r600_set_sstu(rdev, R600_SSTU_DFLT); 135 r600_set_sst(rdev, R600_SST_DFLT); 136 137 r600_set_fctu(rdev, R600_FCTU_DFLT); 138 r600_set_fct(rdev, R600_FCT_DFLT); 139 140 r600_set_vddc3d_oorsu(rdev, R600_VDDC3DOORSU_DFLT); 141 r600_set_vddc3d_oorphc(rdev, R600_VDDC3DOORPHC_DFLT); 142 r600_set_vddc3d_oorsdc(rdev, R600_VDDC3DOORSDC_DFLT); 143 r600_set_ctxcgtt3d_rphc(rdev, R600_CTXCGTT3DRPHC_DFLT); 144 r600_set_ctxcgtt3d_rsdc(rdev, R600_CTXCGTT3DRSDC_DFLT); 145 146 r600_vid_rt_set_vru(rdev, R600_VRU_DFLT); 147 r600_vid_rt_set_vrt(rdev, R600_VOLTAGERESPONSETIME_DFLT); 148 r600_vid_rt_set_ssu(rdev, R600_SPLLSTEPUNIT_DFLT); 149 150 ret = rs780_initialize_dpm_power_state(rdev, boot_ps); 151 152 r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_LOW, 0); 153 r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_MEDIUM, 0); 154 r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_HIGH, 0); 155 156 r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_LOW, 0); 157 r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_MEDIUM, 0); 158 r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_HIGH, 0); 159 160 r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_LOW, 0); 161 r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_MEDIUM, 0); 162 r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_HIGH, 0); 163 164 r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_LOW, R600_DISPLAY_WATERMARK_HIGH); 165 r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_MEDIUM, R600_DISPLAY_WATERMARK_HIGH); 166 r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_HIGH, R600_DISPLAY_WATERMARK_HIGH); 167 168 r600_power_level_enable(rdev, R600_POWER_LEVEL_CTXSW, false); 169 r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, false); 170 r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, false); 171 r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, true); 172 173 r600_power_level_set_enter_index(rdev, R600_POWER_LEVEL_LOW); 174 175 r600_set_vrc(rdev, RS780_CGFTV_DFLT); 176 177 return ret; 178 } 179 180 static void rs780_start_dpm(struct radeon_device *rdev) 181 { 182 r600_enable_sclk_control(rdev, false); 183 r600_enable_mclk_control(rdev, false); 184 185 r600_dynamicpm_enable(rdev, true); 186 187 radeon_wait_for_vblank(rdev, 0); 188 radeon_wait_for_vblank(rdev, 1); 189 190 r600_enable_spll_bypass(rdev, true); 191 r600_wait_for_spll_change(rdev); 192 r600_enable_spll_bypass(rdev, false); 193 r600_wait_for_spll_change(rdev); 194 195 r600_enable_spll_bypass(rdev, true); 196 r600_wait_for_spll_change(rdev); 197 r600_enable_spll_bypass(rdev, false); 198 r600_wait_for_spll_change(rdev); 199 200 r600_enable_sclk_control(rdev, true); 201 } 202 203 204 static void rs780_preset_ranges_slow_clk_fbdiv_en(struct radeon_device *rdev) 205 { 206 WREG32_P(FVTHROT_SLOW_CLK_FEEDBACK_DIV_REG1, RANGE_SLOW_CLK_FEEDBACK_DIV_EN, 207 ~RANGE_SLOW_CLK_FEEDBACK_DIV_EN); 208 209 WREG32_P(FVTHROT_SLOW_CLK_FEEDBACK_DIV_REG1, 210 RANGE0_SLOW_CLK_FEEDBACK_DIV(RS780_SLOWCLKFEEDBACKDIV_DFLT), 211 ~RANGE0_SLOW_CLK_FEEDBACK_DIV_MASK); 212 } 213 214 static void rs780_preset_starting_fbdiv(struct radeon_device *rdev) 215 { 216 u32 fbdiv = (RREG32(CG_SPLL_FUNC_CNTL) & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT; 217 218 WREG32_P(FVTHROT_FBDIV_REG1, STARTING_FEEDBACK_DIV(fbdiv), 219 ~STARTING_FEEDBACK_DIV_MASK); 220 221 WREG32_P(FVTHROT_FBDIV_REG2, FORCED_FEEDBACK_DIV(fbdiv), 222 ~FORCED_FEEDBACK_DIV_MASK); 223 224 WREG32_P(FVTHROT_FBDIV_REG1, FORCE_FEEDBACK_DIV, ~FORCE_FEEDBACK_DIV); 225 } 226 227 static void rs780_voltage_scaling_init(struct radeon_device *rdev) 228 { 229 struct igp_power_info *pi = rs780_get_pi(rdev); 230 struct drm_device *dev = rdev->ddev; 231 u32 fv_throt_pwm_fb_div_range[3]; 232 u32 fv_throt_pwm_range[4]; 233 234 if (dev->pdev->device == 0x9614) { 235 fv_throt_pwm_fb_div_range[0] = RS780D_FVTHROTPWMFBDIVRANGEREG0_DFLT; 236 fv_throt_pwm_fb_div_range[1] = RS780D_FVTHROTPWMFBDIVRANGEREG1_DFLT; 237 fv_throt_pwm_fb_div_range[2] = RS780D_FVTHROTPWMFBDIVRANGEREG2_DFLT; 238 } else if ((dev->pdev->device == 0x9714) || 239 (dev->pdev->device == 0x9715)) { 240 fv_throt_pwm_fb_div_range[0] = RS880D_FVTHROTPWMFBDIVRANGEREG0_DFLT; 241 fv_throt_pwm_fb_div_range[1] = RS880D_FVTHROTPWMFBDIVRANGEREG1_DFLT; 242 fv_throt_pwm_fb_div_range[2] = RS880D_FVTHROTPWMFBDIVRANGEREG2_DFLT; 243 } else { 244 fv_throt_pwm_fb_div_range[0] = RS780_FVTHROTPWMFBDIVRANGEREG0_DFLT; 245 fv_throt_pwm_fb_div_range[1] = RS780_FVTHROTPWMFBDIVRANGEREG1_DFLT; 246 fv_throt_pwm_fb_div_range[2] = RS780_FVTHROTPWMFBDIVRANGEREG2_DFLT; 247 } 248 249 if (pi->pwm_voltage_control) { 250 fv_throt_pwm_range[0] = pi->min_voltage; 251 fv_throt_pwm_range[1] = pi->min_voltage; 252 fv_throt_pwm_range[2] = pi->max_voltage; 253 fv_throt_pwm_range[3] = pi->max_voltage; 254 } else { 255 fv_throt_pwm_range[0] = pi->invert_pwm_required ? 256 RS780_FVTHROTPWMRANGE3_GPIO_DFLT : RS780_FVTHROTPWMRANGE0_GPIO_DFLT; 257 fv_throt_pwm_range[1] = pi->invert_pwm_required ? 258 RS780_FVTHROTPWMRANGE2_GPIO_DFLT : RS780_FVTHROTPWMRANGE1_GPIO_DFLT; 259 fv_throt_pwm_range[2] = pi->invert_pwm_required ? 260 RS780_FVTHROTPWMRANGE1_GPIO_DFLT : RS780_FVTHROTPWMRANGE2_GPIO_DFLT; 261 fv_throt_pwm_range[3] = pi->invert_pwm_required ? 262 RS780_FVTHROTPWMRANGE0_GPIO_DFLT : RS780_FVTHROTPWMRANGE3_GPIO_DFLT; 263 } 264 265 WREG32_P(FVTHROT_PWM_CTRL_REG0, 266 STARTING_PWM_HIGHTIME(pi->max_voltage), 267 ~STARTING_PWM_HIGHTIME_MASK); 268 269 WREG32_P(FVTHROT_PWM_CTRL_REG0, 270 NUMBER_OF_CYCLES_IN_PERIOD(pi->num_of_cycles_in_period), 271 ~NUMBER_OF_CYCLES_IN_PERIOD_MASK); 272 273 WREG32_P(FVTHROT_PWM_CTRL_REG0, FORCE_STARTING_PWM_HIGHTIME, 274 ~FORCE_STARTING_PWM_HIGHTIME); 275 276 if (pi->invert_pwm_required) 277 WREG32_P(FVTHROT_PWM_CTRL_REG0, INVERT_PWM_WAVEFORM, ~INVERT_PWM_WAVEFORM); 278 else 279 WREG32_P(FVTHROT_PWM_CTRL_REG0, 0, ~INVERT_PWM_WAVEFORM); 280 281 rs780_voltage_scaling_enable(rdev, true); 282 283 WREG32(FVTHROT_PWM_CTRL_REG1, 284 (MIN_PWM_HIGHTIME(pi->min_voltage) | 285 MAX_PWM_HIGHTIME(pi->max_voltage))); 286 287 WREG32(FVTHROT_PWM_US_REG0, RS780_FVTHROTPWMUSREG0_DFLT); 288 WREG32(FVTHROT_PWM_US_REG1, RS780_FVTHROTPWMUSREG1_DFLT); 289 WREG32(FVTHROT_PWM_DS_REG0, RS780_FVTHROTPWMDSREG0_DFLT); 290 WREG32(FVTHROT_PWM_DS_REG1, RS780_FVTHROTPWMDSREG1_DFLT); 291 292 WREG32_P(FVTHROT_PWM_FEEDBACK_DIV_REG1, 293 RANGE0_PWM_FEEDBACK_DIV(fv_throt_pwm_fb_div_range[0]), 294 ~RANGE0_PWM_FEEDBACK_DIV_MASK); 295 296 WREG32(FVTHROT_PWM_FEEDBACK_DIV_REG2, 297 (RANGE1_PWM_FEEDBACK_DIV(fv_throt_pwm_fb_div_range[1]) | 298 RANGE2_PWM_FEEDBACK_DIV(fv_throt_pwm_fb_div_range[2]))); 299 300 WREG32(FVTHROT_PWM_FEEDBACK_DIV_REG3, 301 (RANGE0_PWM(fv_throt_pwm_range[1]) | 302 RANGE1_PWM(fv_throt_pwm_range[2]))); 303 WREG32(FVTHROT_PWM_FEEDBACK_DIV_REG4, 304 (RANGE2_PWM(fv_throt_pwm_range[1]) | 305 RANGE3_PWM(fv_throt_pwm_range[2]))); 306 } 307 308 static void rs780_clk_scaling_enable(struct radeon_device *rdev, bool enable) 309 { 310 if (enable) 311 WREG32_P(FVTHROT_CNTRL_REG, ENABLE_FV_THROT | ENABLE_FV_UPDATE, 312 ~(ENABLE_FV_THROT | ENABLE_FV_UPDATE)); 313 else 314 WREG32_P(FVTHROT_CNTRL_REG, 0, 315 ~(ENABLE_FV_THROT | ENABLE_FV_UPDATE)); 316 } 317 318 static void rs780_voltage_scaling_enable(struct radeon_device *rdev, bool enable) 319 { 320 if (enable) 321 WREG32_P(FVTHROT_CNTRL_REG, ENABLE_FV_THROT_IO, ~ENABLE_FV_THROT_IO); 322 else 323 WREG32_P(FVTHROT_CNTRL_REG, 0, ~ENABLE_FV_THROT_IO); 324 } 325 326 static void rs780_set_engine_clock_wfc(struct radeon_device *rdev) 327 { 328 WREG32(FVTHROT_UTC0, RS780_FVTHROTUTC0_DFLT); 329 WREG32(FVTHROT_UTC1, RS780_FVTHROTUTC1_DFLT); 330 WREG32(FVTHROT_UTC2, RS780_FVTHROTUTC2_DFLT); 331 WREG32(FVTHROT_UTC3, RS780_FVTHROTUTC3_DFLT); 332 WREG32(FVTHROT_UTC4, RS780_FVTHROTUTC4_DFLT); 333 334 WREG32(FVTHROT_DTC0, RS780_FVTHROTDTC0_DFLT); 335 WREG32(FVTHROT_DTC1, RS780_FVTHROTDTC1_DFLT); 336 WREG32(FVTHROT_DTC2, RS780_FVTHROTDTC2_DFLT); 337 WREG32(FVTHROT_DTC3, RS780_FVTHROTDTC3_DFLT); 338 WREG32(FVTHROT_DTC4, RS780_FVTHROTDTC4_DFLT); 339 } 340 341 static void rs780_set_engine_clock_sc(struct radeon_device *rdev) 342 { 343 WREG32_P(FVTHROT_FBDIV_REG2, 344 FB_DIV_TIMER_VAL(RS780_FBDIVTIMERVAL_DFLT), 345 ~FB_DIV_TIMER_VAL_MASK); 346 347 WREG32_P(FVTHROT_CNTRL_REG, 348 REFRESH_RATE_DIVISOR(0) | MINIMUM_CIP(0xf), 349 ~(REFRESH_RATE_DIVISOR_MASK | MINIMUM_CIP_MASK)); 350 } 351 352 static void rs780_set_engine_clock_tdc(struct radeon_device *rdev) 353 { 354 WREG32_P(FVTHROT_CNTRL_REG, 0, ~(FORCE_TREND_SEL | TREND_SEL_MODE)); 355 } 356 357 static void rs780_set_engine_clock_ssc(struct radeon_device *rdev) 358 { 359 WREG32(FVTHROT_FB_US_REG0, RS780_FVTHROTFBUSREG0_DFLT); 360 WREG32(FVTHROT_FB_US_REG1, RS780_FVTHROTFBUSREG1_DFLT); 361 WREG32(FVTHROT_FB_DS_REG0, RS780_FVTHROTFBDSREG0_DFLT); 362 WREG32(FVTHROT_FB_DS_REG1, RS780_FVTHROTFBDSREG1_DFLT); 363 364 WREG32_P(FVTHROT_FBDIV_REG1, MAX_FEEDBACK_STEP(1), ~MAX_FEEDBACK_STEP_MASK); 365 } 366 367 static void rs780_program_at(struct radeon_device *rdev) 368 { 369 struct igp_power_info *pi = rs780_get_pi(rdev); 370 371 WREG32(FVTHROT_TARGET_REG, 30000000 / pi->refresh_rate); 372 WREG32(FVTHROT_CB1, 1000000 * 5 / pi->refresh_rate); 373 WREG32(FVTHROT_CB2, 1000000 * 10 / pi->refresh_rate); 374 WREG32(FVTHROT_CB3, 1000000 * 30 / pi->refresh_rate); 375 WREG32(FVTHROT_CB4, 1000000 * 50 / pi->refresh_rate); 376 } 377 378 static void rs780_disable_vbios_powersaving(struct radeon_device *rdev) 379 { 380 WREG32_P(CG_INTGFX_MISC, 0, ~0xFFF00000); 381 } 382 383 static void rs780_force_voltage(struct radeon_device *rdev, u16 voltage) 384 { 385 struct igp_ps *current_state = rs780_get_ps(rdev->pm.dpm.current_ps); 386 387 if ((current_state->max_voltage == RS780_VDDC_LEVEL_HIGH) && 388 (current_state->min_voltage == RS780_VDDC_LEVEL_HIGH)) 389 return; 390 391 WREG32_P(GFX_MACRO_BYPASS_CNTL, SPLL_BYPASS_CNTL, ~SPLL_BYPASS_CNTL); 392 393 udelay(1); 394 395 WREG32_P(FVTHROT_PWM_CTRL_REG0, 396 STARTING_PWM_HIGHTIME(voltage), 397 ~STARTING_PWM_HIGHTIME_MASK); 398 399 WREG32_P(FVTHROT_PWM_CTRL_REG0, 400 FORCE_STARTING_PWM_HIGHTIME, ~FORCE_STARTING_PWM_HIGHTIME); 401 402 WREG32_P(FVTHROT_PWM_FEEDBACK_DIV_REG1, 0, 403 ~RANGE_PWM_FEEDBACK_DIV_EN); 404 405 udelay(1); 406 407 WREG32_P(GFX_MACRO_BYPASS_CNTL, 0, ~SPLL_BYPASS_CNTL); 408 } 409 410 static void rs780_force_fbdiv(struct radeon_device *rdev, u32 fb_div) 411 { 412 struct igp_ps *current_state = rs780_get_ps(rdev->pm.dpm.current_ps); 413 414 if (current_state->sclk_low == current_state->sclk_high) 415 return; 416 417 WREG32_P(GFX_MACRO_BYPASS_CNTL, SPLL_BYPASS_CNTL, ~SPLL_BYPASS_CNTL); 418 419 WREG32_P(FVTHROT_FBDIV_REG2, FORCED_FEEDBACK_DIV(fb_div), 420 ~FORCED_FEEDBACK_DIV_MASK); 421 WREG32_P(FVTHROT_FBDIV_REG1, STARTING_FEEDBACK_DIV(fb_div), 422 ~STARTING_FEEDBACK_DIV_MASK); 423 WREG32_P(FVTHROT_FBDIV_REG1, FORCE_FEEDBACK_DIV, ~FORCE_FEEDBACK_DIV); 424 425 udelay(100); 426 427 WREG32_P(GFX_MACRO_BYPASS_CNTL, 0, ~SPLL_BYPASS_CNTL); 428 } 429 430 static int rs780_set_engine_clock_scaling(struct radeon_device *rdev, 431 struct radeon_ps *new_ps, 432 struct radeon_ps *old_ps) 433 { 434 struct atom_clock_dividers min_dividers, max_dividers, current_max_dividers; 435 struct igp_ps *new_state = rs780_get_ps(new_ps); 436 struct igp_ps *old_state = rs780_get_ps(old_ps); 437 int ret; 438 439 if ((new_state->sclk_high == old_state->sclk_high) && 440 (new_state->sclk_low == old_state->sclk_low)) 441 return 0; 442 443 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 444 new_state->sclk_low, false, &min_dividers); 445 if (ret) 446 return ret; 447 448 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 449 new_state->sclk_high, false, &max_dividers); 450 if (ret) 451 return ret; 452 453 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 454 old_state->sclk_high, false, ¤t_max_dividers); 455 if (ret) 456 return ret; 457 458 if ((min_dividers.ref_div != max_dividers.ref_div) || 459 (min_dividers.post_div != max_dividers.post_div) || 460 (max_dividers.ref_div != current_max_dividers.ref_div) || 461 (max_dividers.post_div != current_max_dividers.post_div)) 462 return -EINVAL; 463 464 rs780_force_fbdiv(rdev, max_dividers.fb_div); 465 466 if (max_dividers.fb_div > min_dividers.fb_div) { 467 WREG32_P(FVTHROT_FBDIV_REG0, 468 MIN_FEEDBACK_DIV(min_dividers.fb_div) | 469 MAX_FEEDBACK_DIV(max_dividers.fb_div), 470 ~(MIN_FEEDBACK_DIV_MASK | MAX_FEEDBACK_DIV_MASK)); 471 472 WREG32_P(FVTHROT_FBDIV_REG1, 0, ~FORCE_FEEDBACK_DIV); 473 } 474 475 return 0; 476 } 477 478 static void rs780_set_engine_clock_spc(struct radeon_device *rdev, 479 struct radeon_ps *new_ps, 480 struct radeon_ps *old_ps) 481 { 482 struct igp_ps *new_state = rs780_get_ps(new_ps); 483 struct igp_ps *old_state = rs780_get_ps(old_ps); 484 struct igp_power_info *pi = rs780_get_pi(rdev); 485 486 if ((new_state->sclk_high == old_state->sclk_high) && 487 (new_state->sclk_low == old_state->sclk_low)) 488 return; 489 490 if (pi->crtc_id == 0) 491 WREG32_P(CG_INTGFX_MISC, 0, ~FVTHROT_VBLANK_SEL); 492 else 493 WREG32_P(CG_INTGFX_MISC, FVTHROT_VBLANK_SEL, ~FVTHROT_VBLANK_SEL); 494 495 } 496 497 static void rs780_activate_engine_clk_scaling(struct radeon_device *rdev, 498 struct radeon_ps *new_ps, 499 struct radeon_ps *old_ps) 500 { 501 struct igp_ps *new_state = rs780_get_ps(new_ps); 502 struct igp_ps *old_state = rs780_get_ps(old_ps); 503 504 if ((new_state->sclk_high == old_state->sclk_high) && 505 (new_state->sclk_low == old_state->sclk_low)) 506 return; 507 508 if (new_state->sclk_high == new_state->sclk_low) 509 return; 510 511 rs780_clk_scaling_enable(rdev, true); 512 } 513 514 static u32 rs780_get_voltage_for_vddc_level(struct radeon_device *rdev, 515 enum rs780_vddc_level vddc) 516 { 517 struct igp_power_info *pi = rs780_get_pi(rdev); 518 519 if (vddc == RS780_VDDC_LEVEL_HIGH) 520 return pi->max_voltage; 521 else if (vddc == RS780_VDDC_LEVEL_LOW) 522 return pi->min_voltage; 523 else 524 return pi->max_voltage; 525 } 526 527 static void rs780_enable_voltage_scaling(struct radeon_device *rdev, 528 struct radeon_ps *new_ps) 529 { 530 struct igp_ps *new_state = rs780_get_ps(new_ps); 531 struct igp_power_info *pi = rs780_get_pi(rdev); 532 enum rs780_vddc_level vddc_high, vddc_low; 533 534 udelay(100); 535 536 if ((new_state->max_voltage == RS780_VDDC_LEVEL_HIGH) && 537 (new_state->min_voltage == RS780_VDDC_LEVEL_HIGH)) 538 return; 539 540 vddc_high = rs780_get_voltage_for_vddc_level(rdev, 541 new_state->max_voltage); 542 vddc_low = rs780_get_voltage_for_vddc_level(rdev, 543 new_state->min_voltage); 544 545 WREG32_P(GFX_MACRO_BYPASS_CNTL, SPLL_BYPASS_CNTL, ~SPLL_BYPASS_CNTL); 546 547 udelay(1); 548 if (vddc_high > vddc_low) { 549 WREG32_P(FVTHROT_PWM_FEEDBACK_DIV_REG1, 550 RANGE_PWM_FEEDBACK_DIV_EN, ~RANGE_PWM_FEEDBACK_DIV_EN); 551 552 WREG32_P(FVTHROT_PWM_CTRL_REG0, 0, ~FORCE_STARTING_PWM_HIGHTIME); 553 } else if (vddc_high == vddc_low) { 554 if (pi->max_voltage != vddc_high) { 555 WREG32_P(FVTHROT_PWM_CTRL_REG0, 556 STARTING_PWM_HIGHTIME(vddc_high), 557 ~STARTING_PWM_HIGHTIME_MASK); 558 559 WREG32_P(FVTHROT_PWM_CTRL_REG0, 560 FORCE_STARTING_PWM_HIGHTIME, 561 ~FORCE_STARTING_PWM_HIGHTIME); 562 } 563 } 564 565 WREG32_P(GFX_MACRO_BYPASS_CNTL, 0, ~SPLL_BYPASS_CNTL); 566 } 567 568 static void rs780_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev, 569 struct radeon_ps *new_ps, 570 struct radeon_ps *old_ps) 571 { 572 struct igp_ps *new_state = rs780_get_ps(new_ps); 573 struct igp_ps *current_state = rs780_get_ps(old_ps); 574 575 if ((new_ps->vclk == old_ps->vclk) && 576 (new_ps->dclk == old_ps->dclk)) 577 return; 578 579 if (new_state->sclk_high >= current_state->sclk_high) 580 return; 581 582 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); 583 } 584 585 static void rs780_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev, 586 struct radeon_ps *new_ps, 587 struct radeon_ps *old_ps) 588 { 589 struct igp_ps *new_state = rs780_get_ps(new_ps); 590 struct igp_ps *current_state = rs780_get_ps(old_ps); 591 592 if ((new_ps->vclk == old_ps->vclk) && 593 (new_ps->dclk == old_ps->dclk)) 594 return; 595 596 if (new_state->sclk_high < current_state->sclk_high) 597 return; 598 599 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); 600 } 601 602 int rs780_dpm_enable(struct radeon_device *rdev) 603 { 604 struct igp_power_info *pi = rs780_get_pi(rdev); 605 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; 606 int ret; 607 608 rs780_get_pm_mode_parameters(rdev); 609 rs780_disable_vbios_powersaving(rdev); 610 611 if (r600_dynamicpm_enabled(rdev)) 612 return -EINVAL; 613 ret = rs780_initialize_dpm_parameters(rdev, boot_ps); 614 if (ret) 615 return ret; 616 rs780_start_dpm(rdev); 617 618 rs780_preset_ranges_slow_clk_fbdiv_en(rdev); 619 rs780_preset_starting_fbdiv(rdev); 620 if (pi->voltage_control) 621 rs780_voltage_scaling_init(rdev); 622 rs780_clk_scaling_enable(rdev, true); 623 rs780_set_engine_clock_sc(rdev); 624 rs780_set_engine_clock_wfc(rdev); 625 rs780_program_at(rdev); 626 rs780_set_engine_clock_tdc(rdev); 627 rs780_set_engine_clock_ssc(rdev); 628 629 if (pi->gfx_clock_gating) 630 r600_gfx_clockgating_enable(rdev, true); 631 632 return 0; 633 } 634 635 void rs780_dpm_disable(struct radeon_device *rdev) 636 { 637 struct igp_power_info *pi = rs780_get_pi(rdev); 638 639 r600_dynamicpm_enable(rdev, false); 640 641 rs780_clk_scaling_enable(rdev, false); 642 rs780_voltage_scaling_enable(rdev, false); 643 644 if (pi->gfx_clock_gating) 645 r600_gfx_clockgating_enable(rdev, false); 646 647 if (rdev->irq.installed && 648 (rdev->pm.int_thermal_type == THERMAL_TYPE_RV6XX)) { 649 rdev->irq.dpm_thermal = false; 650 radeon_irq_set(rdev); 651 } 652 } 653 654 int rs780_dpm_set_power_state(struct radeon_device *rdev) 655 { 656 struct igp_power_info *pi = rs780_get_pi(rdev); 657 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps; 658 struct radeon_ps *old_ps = rdev->pm.dpm.current_ps; 659 int ret; 660 661 rs780_get_pm_mode_parameters(rdev); 662 663 rs780_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps); 664 665 if (pi->voltage_control) { 666 rs780_force_voltage(rdev, pi->max_voltage); 667 mdelay(5); 668 } 669 670 ret = rs780_set_engine_clock_scaling(rdev, new_ps, old_ps); 671 if (ret) 672 return ret; 673 rs780_set_engine_clock_spc(rdev, new_ps, old_ps); 674 675 rs780_activate_engine_clk_scaling(rdev, new_ps, old_ps); 676 677 if (pi->voltage_control) 678 rs780_enable_voltage_scaling(rdev, new_ps); 679 680 rs780_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps); 681 682 return 0; 683 } 684 685 void rs780_dpm_setup_asic(struct radeon_device *rdev) 686 { 687 688 } 689 690 void rs780_dpm_display_configuration_changed(struct radeon_device *rdev) 691 { 692 rs780_get_pm_mode_parameters(rdev); 693 rs780_program_at(rdev); 694 } 695 696 union igp_info { 697 struct _ATOM_INTEGRATED_SYSTEM_INFO info; 698 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2; 699 }; 700 701 union power_info { 702 struct _ATOM_POWERPLAY_INFO info; 703 struct _ATOM_POWERPLAY_INFO_V2 info_2; 704 struct _ATOM_POWERPLAY_INFO_V3 info_3; 705 struct _ATOM_PPLIB_POWERPLAYTABLE pplib; 706 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2; 707 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3; 708 }; 709 710 union pplib_clock_info { 711 struct _ATOM_PPLIB_R600_CLOCK_INFO r600; 712 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780; 713 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; 714 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo; 715 }; 716 717 union pplib_power_state { 718 struct _ATOM_PPLIB_STATE v1; 719 struct _ATOM_PPLIB_STATE_V2 v2; 720 }; 721 722 static void rs780_parse_pplib_non_clock_info(struct radeon_device *rdev, 723 struct radeon_ps *rps, 724 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info, 725 u8 table_rev) 726 { 727 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); 728 rps->class = le16_to_cpu(non_clock_info->usClassification); 729 rps->class2 = le16_to_cpu(non_clock_info->usClassification2); 730 731 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) { 732 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); 733 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); 734 } else { 735 rps->vclk = 0; 736 rps->dclk = 0; 737 } 738 739 if (r600_is_uvd_state(rps->class, rps->class2)) { 740 if ((rps->vclk == 0) || (rps->dclk == 0)) { 741 rps->vclk = RS780_DEFAULT_VCLK_FREQ; 742 rps->dclk = RS780_DEFAULT_DCLK_FREQ; 743 } 744 } 745 746 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) 747 rdev->pm.dpm.boot_ps = rps; 748 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) 749 rdev->pm.dpm.uvd_ps = rps; 750 } 751 752 static void rs780_parse_pplib_clock_info(struct radeon_device *rdev, 753 struct radeon_ps *rps, 754 union pplib_clock_info *clock_info) 755 { 756 struct igp_ps *ps = rs780_get_ps(rps); 757 u32 sclk; 758 759 sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow); 760 sclk |= clock_info->rs780.ucLowEngineClockHigh << 16; 761 ps->sclk_low = sclk; 762 sclk = le16_to_cpu(clock_info->rs780.usHighEngineClockLow); 763 sclk |= clock_info->rs780.ucHighEngineClockHigh << 16; 764 ps->sclk_high = sclk; 765 switch (le16_to_cpu(clock_info->rs780.usVDDC)) { 766 case ATOM_PPLIB_RS780_VOLTAGE_NONE: 767 default: 768 ps->min_voltage = RS780_VDDC_LEVEL_UNKNOWN; 769 ps->max_voltage = RS780_VDDC_LEVEL_UNKNOWN; 770 break; 771 case ATOM_PPLIB_RS780_VOLTAGE_LOW: 772 ps->min_voltage = RS780_VDDC_LEVEL_LOW; 773 ps->max_voltage = RS780_VDDC_LEVEL_LOW; 774 break; 775 case ATOM_PPLIB_RS780_VOLTAGE_HIGH: 776 ps->min_voltage = RS780_VDDC_LEVEL_HIGH; 777 ps->max_voltage = RS780_VDDC_LEVEL_HIGH; 778 break; 779 case ATOM_PPLIB_RS780_VOLTAGE_VARIABLE: 780 ps->min_voltage = RS780_VDDC_LEVEL_LOW; 781 ps->max_voltage = RS780_VDDC_LEVEL_HIGH; 782 break; 783 } 784 ps->flags = le32_to_cpu(clock_info->rs780.ulFlags); 785 786 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) { 787 ps->sclk_low = rdev->clock.default_sclk; 788 ps->sclk_high = rdev->clock.default_sclk; 789 ps->min_voltage = RS780_VDDC_LEVEL_HIGH; 790 ps->max_voltage = RS780_VDDC_LEVEL_HIGH; 791 } 792 } 793 794 static int rs780_parse_power_table(struct radeon_device *rdev) 795 { 796 struct radeon_mode_info *mode_info = &rdev->mode_info; 797 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; 798 union pplib_power_state *power_state; 799 int i; 800 union pplib_clock_info *clock_info; 801 union power_info *power_info; 802 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 803 u16 data_offset; 804 u8 frev, crev; 805 struct igp_ps *ps; 806 807 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, 808 &frev, &crev, &data_offset)) 809 return -EINVAL; 810 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 811 812 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) * 813 power_info->pplib.ucNumStates, GFP_KERNEL); 814 if (!rdev->pm.dpm.ps) 815 return -ENOMEM; 816 817 for (i = 0; i < power_info->pplib.ucNumStates; i++) { 818 power_state = (union pplib_power_state *) 819 (mode_info->atom_context->bios + data_offset + 820 le16_to_cpu(power_info->pplib.usStateArrayOffset) + 821 i * power_info->pplib.ucStateEntrySize); 822 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) 823 (mode_info->atom_context->bios + data_offset + 824 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) + 825 (power_state->v1.ucNonClockStateIndex * 826 power_info->pplib.ucNonClockSize)); 827 if (power_info->pplib.ucStateEntrySize - 1) { 828 clock_info = (union pplib_clock_info *) 829 (mode_info->atom_context->bios + data_offset + 830 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) + 831 (power_state->v1.ucClockStateIndices[0] * 832 power_info->pplib.ucClockInfoSize)); 833 ps = kzalloc(sizeof(struct igp_ps), GFP_KERNEL); 834 if (ps == NULL) { 835 kfree(rdev->pm.dpm.ps); 836 return -ENOMEM; 837 } 838 rdev->pm.dpm.ps[i].ps_priv = ps; 839 rs780_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i], 840 non_clock_info, 841 power_info->pplib.ucNonClockSize); 842 rs780_parse_pplib_clock_info(rdev, 843 &rdev->pm.dpm.ps[i], 844 clock_info); 845 } 846 } 847 rdev->pm.dpm.num_ps = power_info->pplib.ucNumStates; 848 return 0; 849 } 850 851 int rs780_dpm_init(struct radeon_device *rdev) 852 { 853 struct igp_power_info *pi; 854 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); 855 union igp_info *info; 856 u16 data_offset; 857 u8 frev, crev; 858 int ret; 859 860 pi = kzalloc(sizeof(struct igp_power_info), GFP_KERNEL); 861 if (pi == NULL) 862 return -ENOMEM; 863 rdev->pm.dpm.priv = pi; 864 865 ret = r600_get_platform_caps(rdev); 866 if (ret) 867 return ret; 868 869 ret = rs780_parse_power_table(rdev); 870 if (ret) 871 return ret; 872 873 pi->voltage_control = false; 874 pi->gfx_clock_gating = true; 875 876 if (atom_parse_data_header(rdev->mode_info.atom_context, index, NULL, 877 &frev, &crev, &data_offset)) { 878 info = (union igp_info *)(rdev->mode_info.atom_context->bios + data_offset); 879 880 /* Get various system informations from bios */ 881 switch (crev) { 882 case 1: 883 pi->num_of_cycles_in_period = 884 info->info.ucNumberOfCyclesInPeriod; 885 pi->num_of_cycles_in_period |= 886 info->info.ucNumberOfCyclesInPeriodHi << 8; 887 pi->invert_pwm_required = 888 (pi->num_of_cycles_in_period & 0x8000) ? true : false; 889 pi->boot_voltage = info->info.ucStartingPWM_HighTime; 890 pi->max_voltage = info->info.ucMaxNBVoltage; 891 pi->max_voltage |= info->info.ucMaxNBVoltageHigh << 8; 892 pi->min_voltage = info->info.ucMinNBVoltage; 893 pi->min_voltage |= info->info.ucMinNBVoltageHigh << 8; 894 pi->inter_voltage_low = 895 le16_to_cpu(info->info.usInterNBVoltageLow); 896 pi->inter_voltage_high = 897 le16_to_cpu(info->info.usInterNBVoltageHigh); 898 pi->voltage_control = true; 899 pi->bootup_uma_clk = info->info.usK8MemoryClock * 100; 900 break; 901 case 2: 902 pi->num_of_cycles_in_period = 903 le16_to_cpu(info->info_2.usNumberOfCyclesInPeriod); 904 pi->invert_pwm_required = 905 (pi->num_of_cycles_in_period & 0x8000) ? true : false; 906 pi->boot_voltage = 907 le16_to_cpu(info->info_2.usBootUpNBVoltage); 908 pi->max_voltage = 909 le16_to_cpu(info->info_2.usMaxNBVoltage); 910 pi->min_voltage = 911 le16_to_cpu(info->info_2.usMinNBVoltage); 912 pi->system_config = 913 le32_to_cpu(info->info_2.ulSystemConfig); 914 pi->pwm_voltage_control = 915 (pi->system_config & 0x4) ? true : false; 916 pi->voltage_control = true; 917 pi->bootup_uma_clk = le32_to_cpu(info->info_2.ulBootUpUMAClock); 918 break; 919 default: 920 DRM_ERROR("No integrated system info for your GPU\n"); 921 return -EINVAL; 922 } 923 if (pi->min_voltage > pi->max_voltage) 924 pi->voltage_control = false; 925 if (pi->pwm_voltage_control) { 926 if ((pi->num_of_cycles_in_period == 0) || 927 (pi->max_voltage == 0) || 928 (pi->min_voltage == 0)) 929 pi->voltage_control = false; 930 } else { 931 if ((pi->num_of_cycles_in_period == 0) || 932 (pi->max_voltage == 0)) 933 pi->voltage_control = false; 934 } 935 936 return 0; 937 } 938 radeon_dpm_fini(rdev); 939 return -EINVAL; 940 } 941 942 void rs780_dpm_print_power_state(struct radeon_device *rdev, 943 struct radeon_ps *rps) 944 { 945 struct igp_ps *ps = rs780_get_ps(rps); 946 947 r600_dpm_print_class_info(rps->class, rps->class2); 948 r600_dpm_print_cap_info(rps->caps); 949 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); 950 printk("\t\tpower level 0 sclk: %u vddc_index: %d\n", 951 ps->sclk_low, ps->min_voltage); 952 printk("\t\tpower level 1 sclk: %u vddc_index: %d\n", 953 ps->sclk_high, ps->max_voltage); 954 r600_dpm_print_ps_status(rdev, rps); 955 } 956 957 void rs780_dpm_fini(struct radeon_device *rdev) 958 { 959 int i; 960 961 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { 962 kfree(rdev->pm.dpm.ps[i].ps_priv); 963 } 964 kfree(rdev->pm.dpm.ps); 965 kfree(rdev->pm.dpm.priv); 966 } 967 968 u32 rs780_dpm_get_sclk(struct radeon_device *rdev, bool low) 969 { 970 struct igp_ps *requested_state = rs780_get_ps(rdev->pm.dpm.requested_ps); 971 972 if (low) 973 return requested_state->sclk_low; 974 else 975 return requested_state->sclk_high; 976 } 977 978 u32 rs780_dpm_get_mclk(struct radeon_device *rdev, bool low) 979 { 980 struct igp_power_info *pi = rs780_get_pi(rdev); 981 982 return pi->bootup_uma_clk; 983 } 984 985 #ifdef CONFIG_DEBUG_FS 986 void rs780_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 987 struct seq_file *m) 988 { 989 struct radeon_ps *rps = rdev->pm.dpm.current_ps; 990 struct igp_ps *ps = rs780_get_ps(rps); 991 u32 current_fb_div = RREG32(FVTHROT_STATUS_REG0) & CURRENT_FEEDBACK_DIV_MASK; 992 u32 func_cntl = RREG32(CG_SPLL_FUNC_CNTL); 993 u32 ref_div = ((func_cntl & SPLL_REF_DIV_MASK) >> SPLL_REF_DIV_SHIFT) + 1; 994 u32 post_div = ((func_cntl & SPLL_SW_HILEN_MASK) >> SPLL_SW_HILEN_SHIFT) + 1 + 995 ((func_cntl & SPLL_SW_LOLEN_MASK) >> SPLL_SW_LOLEN_SHIFT) + 1; 996 u32 sclk = (rdev->clock.spll.reference_freq * current_fb_div) / 997 (post_div * ref_div); 998 999 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); 1000 1001 /* guess based on the current sclk */ 1002 if (sclk < (ps->sclk_low + 500)) 1003 seq_printf(m, "power level 0 sclk: %u vddc_index: %d\n", 1004 ps->sclk_low, ps->min_voltage); 1005 else 1006 seq_printf(m, "power level 1 sclk: %u vddc_index: %d\n", 1007 ps->sclk_high, ps->max_voltage); 1008 } 1009 #endif 1010 1011 /* get the current sclk in 10 khz units */ 1012 u32 rs780_dpm_get_current_sclk(struct radeon_device *rdev) 1013 { 1014 u32 current_fb_div = RREG32(FVTHROT_STATUS_REG0) & CURRENT_FEEDBACK_DIV_MASK; 1015 u32 func_cntl = RREG32(CG_SPLL_FUNC_CNTL); 1016 u32 ref_div = ((func_cntl & SPLL_REF_DIV_MASK) >> SPLL_REF_DIV_SHIFT) + 1; 1017 u32 post_div = ((func_cntl & SPLL_SW_HILEN_MASK) >> SPLL_SW_HILEN_SHIFT) + 1 + 1018 ((func_cntl & SPLL_SW_LOLEN_MASK) >> SPLL_SW_LOLEN_SHIFT) + 1; 1019 u32 sclk = (rdev->clock.spll.reference_freq * current_fb_div) / 1020 (post_div * ref_div); 1021 1022 return sclk; 1023 } 1024 1025 /* get the current mclk in 10 khz units */ 1026 u32 rs780_dpm_get_current_mclk(struct radeon_device *rdev) 1027 { 1028 struct igp_power_info *pi = rs780_get_pi(rdev); 1029 1030 return pi->bootup_uma_clk; 1031 } 1032 1033 int rs780_dpm_force_performance_level(struct radeon_device *rdev, 1034 enum radeon_dpm_forced_level level) 1035 { 1036 struct igp_power_info *pi = rs780_get_pi(rdev); 1037 struct radeon_ps *rps = rdev->pm.dpm.current_ps; 1038 struct igp_ps *ps = rs780_get_ps(rps); 1039 struct atom_clock_dividers dividers; 1040 int ret; 1041 1042 rs780_clk_scaling_enable(rdev, false); 1043 rs780_voltage_scaling_enable(rdev, false); 1044 1045 if (level == RADEON_DPM_FORCED_LEVEL_HIGH) { 1046 if (pi->voltage_control) 1047 rs780_force_voltage(rdev, pi->max_voltage); 1048 1049 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 1050 ps->sclk_high, false, ÷rs); 1051 if (ret) 1052 return ret; 1053 1054 rs780_force_fbdiv(rdev, dividers.fb_div); 1055 } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) { 1056 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 1057 ps->sclk_low, false, ÷rs); 1058 if (ret) 1059 return ret; 1060 1061 rs780_force_fbdiv(rdev, dividers.fb_div); 1062 1063 if (pi->voltage_control) 1064 rs780_force_voltage(rdev, pi->min_voltage); 1065 } else { 1066 if (pi->voltage_control) 1067 rs780_force_voltage(rdev, pi->max_voltage); 1068 1069 if (ps->sclk_high != ps->sclk_low) { 1070 WREG32_P(FVTHROT_FBDIV_REG1, 0, ~FORCE_FEEDBACK_DIV); 1071 rs780_clk_scaling_enable(rdev, true); 1072 } 1073 1074 if (pi->voltage_control) { 1075 rs780_voltage_scaling_enable(rdev, true); 1076 rs780_enable_voltage_scaling(rdev, rps); 1077 } 1078 } 1079 1080 rdev->pm.dpm.forced_level = level; 1081 1082 return 0; 1083 } 1084
Indexes created Mon Oct 20 05:10:11 GMT 2025