radeon_rv730_dpm.c revision 1.1
1 /* $NetBSD: radeon_rv730_dpm.c,v 1.1 2018/08/27 14:38:20 riastradh Exp $ */ 2 3 /* 4 * Copyright 2011 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Alex Deucher 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: radeon_rv730_dpm.c,v 1.1 2018/08/27 14:38:20 riastradh Exp $"); 29 30 #include "drmP.h" 31 #include "radeon.h" 32 #include "rv730d.h" 33 #include "r600_dpm.h" 34 #include "rv770_dpm.h" 35 #include "atom.h" 36 37 #define MC_CG_ARB_FREQ_F0 0x0a 38 #define MC_CG_ARB_FREQ_F1 0x0b 39 #define MC_CG_ARB_FREQ_F2 0x0c 40 #define MC_CG_ARB_FREQ_F3 0x0d 41 42 struct rv7xx_ps *rv770_get_ps(struct radeon_ps *rps); 43 struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev); 44 45 int rv730_populate_sclk_value(struct radeon_device *rdev, 46 u32 engine_clock, 47 RV770_SMC_SCLK_VALUE *sclk) 48 { 49 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 50 struct atom_clock_dividers dividers; 51 u32 spll_func_cntl = pi->clk_regs.rv730.cg_spll_func_cntl; 52 u32 spll_func_cntl_2 = pi->clk_regs.rv730.cg_spll_func_cntl_2; 53 u32 spll_func_cntl_3 = pi->clk_regs.rv730.cg_spll_func_cntl_3; 54 u32 cg_spll_spread_spectrum = pi->clk_regs.rv730.cg_spll_spread_spectrum; 55 u32 cg_spll_spread_spectrum_2 = pi->clk_regs.rv730.cg_spll_spread_spectrum_2; 56 u64 tmp; 57 u32 reference_clock = rdev->clock.spll.reference_freq; 58 u32 reference_divider, post_divider; 59 u32 fbdiv; 60 int ret; 61 62 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 63 engine_clock, false, ÷rs); 64 if (ret) 65 return ret; 66 67 reference_divider = 1 + dividers.ref_div; 68 69 if (dividers.enable_post_div) 70 post_divider = ((dividers.post_div >> 4) & 0xf) + 71 (dividers.post_div & 0xf) + 2; 72 else 73 post_divider = 1; 74 75 tmp = (u64) engine_clock * reference_divider * post_divider * 16384; 76 do_div(tmp, reference_clock); 77 fbdiv = (u32) tmp; 78 79 /* set up registers */ 80 if (dividers.enable_post_div) 81 spll_func_cntl |= SPLL_DIVEN; 82 else 83 spll_func_cntl &= ~SPLL_DIVEN; 84 spll_func_cntl &= ~(SPLL_HILEN_MASK | SPLL_LOLEN_MASK | SPLL_REF_DIV_MASK); 85 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); 86 spll_func_cntl |= SPLL_HILEN((dividers.post_div >> 4) & 0xf); 87 spll_func_cntl |= SPLL_LOLEN(dividers.post_div & 0xf); 88 89 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; 90 spll_func_cntl_2 |= SCLK_MUX_SEL(2); 91 92 spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK; 93 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv); 94 spll_func_cntl_3 |= SPLL_DITHEN; 95 96 if (pi->sclk_ss) { 97 struct radeon_atom_ss ss; 98 u32 vco_freq = engine_clock * post_divider; 99 100 if (radeon_atombios_get_asic_ss_info(rdev, &ss, 101 ASIC_INTERNAL_ENGINE_SS, vco_freq)) { 102 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); 103 u32 clk_v = ss.percentage * fbdiv / (clk_s * 10000); 104 105 cg_spll_spread_spectrum &= ~CLK_S_MASK; 106 cg_spll_spread_spectrum |= CLK_S(clk_s); 107 cg_spll_spread_spectrum |= SSEN; 108 109 cg_spll_spread_spectrum_2 &= ~CLK_V_MASK; 110 cg_spll_spread_spectrum_2 |= CLK_V(clk_v); 111 } 112 } 113 114 sclk->sclk_value = cpu_to_be32(engine_clock); 115 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl); 116 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2); 117 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3); 118 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(cg_spll_spread_spectrum); 119 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(cg_spll_spread_spectrum_2); 120 121 return 0; 122 } 123 124 int rv730_populate_mclk_value(struct radeon_device *rdev, 125 u32 engine_clock, u32 memory_clock, 126 LPRV7XX_SMC_MCLK_VALUE mclk) 127 { 128 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 129 u32 mclk_pwrmgt_cntl = pi->clk_regs.rv730.mclk_pwrmgt_cntl; 130 u32 dll_cntl = pi->clk_regs.rv730.dll_cntl; 131 u32 mpll_func_cntl = pi->clk_regs.rv730.mpll_func_cntl; 132 u32 mpll_func_cntl_2 = pi->clk_regs.rv730.mpll_func_cntl2; 133 u32 mpll_func_cntl_3 = pi->clk_regs.rv730.mpll_func_cntl3; 134 u32 mpll_ss = pi->clk_regs.rv730.mpll_ss; 135 u32 mpll_ss2 = pi->clk_regs.rv730.mpll_ss2; 136 struct atom_clock_dividers dividers; 137 u32 post_divider, reference_divider; 138 int ret; 139 140 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_MEMORY_PLL_PARAM, 141 memory_clock, false, ÷rs); 142 if (ret) 143 return ret; 144 145 reference_divider = dividers.ref_div + 1; 146 147 if (dividers.enable_post_div) 148 post_divider = ((dividers.post_div >> 4) & 0xf) + 149 (dividers.post_div & 0xf) + 2; 150 else 151 post_divider = 1; 152 153 /* setup the registers */ 154 if (dividers.enable_post_div) 155 mpll_func_cntl |= MPLL_DIVEN; 156 else 157 mpll_func_cntl &= ~MPLL_DIVEN; 158 159 mpll_func_cntl &= ~(MPLL_REF_DIV_MASK | MPLL_HILEN_MASK | MPLL_LOLEN_MASK); 160 mpll_func_cntl |= MPLL_REF_DIV(dividers.ref_div); 161 mpll_func_cntl |= MPLL_HILEN((dividers.post_div >> 4) & 0xf); 162 mpll_func_cntl |= MPLL_LOLEN(dividers.post_div & 0xf); 163 164 mpll_func_cntl_3 &= ~MPLL_FB_DIV_MASK; 165 mpll_func_cntl_3 |= MPLL_FB_DIV(dividers.fb_div); 166 if (dividers.enable_dithen) 167 mpll_func_cntl_3 |= MPLL_DITHEN; 168 else 169 mpll_func_cntl_3 &= ~MPLL_DITHEN; 170 171 if (pi->mclk_ss) { 172 struct radeon_atom_ss ss; 173 u32 vco_freq = memory_clock * post_divider; 174 175 if (radeon_atombios_get_asic_ss_info(rdev, &ss, 176 ASIC_INTERNAL_MEMORY_SS, vco_freq)) { 177 u32 reference_clock = rdev->clock.mpll.reference_freq; 178 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); 179 u32 clk_v = ss.percentage * dividers.fb_div / (clk_s * 10000); 180 181 mpll_ss &= ~CLK_S_MASK; 182 mpll_ss |= CLK_S(clk_s); 183 mpll_ss |= SSEN; 184 185 mpll_ss2 &= ~CLK_V_MASK; 186 mpll_ss |= CLK_V(clk_v); 187 } 188 } 189 190 191 mclk->mclk730.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); 192 mclk->mclk730.vDLL_CNTL = cpu_to_be32(dll_cntl); 193 mclk->mclk730.mclk_value = cpu_to_be32(memory_clock); 194 mclk->mclk730.vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl); 195 mclk->mclk730.vMPLL_FUNC_CNTL2 = cpu_to_be32(mpll_func_cntl_2); 196 mclk->mclk730.vMPLL_FUNC_CNTL3 = cpu_to_be32(mpll_func_cntl_3); 197 mclk->mclk730.vMPLL_SS = cpu_to_be32(mpll_ss); 198 mclk->mclk730.vMPLL_SS2 = cpu_to_be32(mpll_ss2); 199 200 return 0; 201 } 202 203 void rv730_read_clock_registers(struct radeon_device *rdev) 204 { 205 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 206 207 pi->clk_regs.rv730.cg_spll_func_cntl = 208 RREG32(CG_SPLL_FUNC_CNTL); 209 pi->clk_regs.rv730.cg_spll_func_cntl_2 = 210 RREG32(CG_SPLL_FUNC_CNTL_2); 211 pi->clk_regs.rv730.cg_spll_func_cntl_3 = 212 RREG32(CG_SPLL_FUNC_CNTL_3); 213 pi->clk_regs.rv730.cg_spll_spread_spectrum = 214 RREG32(CG_SPLL_SPREAD_SPECTRUM); 215 pi->clk_regs.rv730.cg_spll_spread_spectrum_2 = 216 RREG32(CG_SPLL_SPREAD_SPECTRUM_2); 217 218 pi->clk_regs.rv730.mclk_pwrmgt_cntl = 219 RREG32(TCI_MCLK_PWRMGT_CNTL); 220 pi->clk_regs.rv730.dll_cntl = 221 RREG32(TCI_DLL_CNTL); 222 pi->clk_regs.rv730.mpll_func_cntl = 223 RREG32(CG_MPLL_FUNC_CNTL); 224 pi->clk_regs.rv730.mpll_func_cntl2 = 225 RREG32(CG_MPLL_FUNC_CNTL_2); 226 pi->clk_regs.rv730.mpll_func_cntl3 = 227 RREG32(CG_MPLL_FUNC_CNTL_3); 228 pi->clk_regs.rv730.mpll_ss = 229 RREG32(CG_TCI_MPLL_SPREAD_SPECTRUM); 230 pi->clk_regs.rv730.mpll_ss2 = 231 RREG32(CG_TCI_MPLL_SPREAD_SPECTRUM_2); 232 } 233 234 int rv730_populate_smc_acpi_state(struct radeon_device *rdev, 235 RV770_SMC_STATETABLE *table) 236 { 237 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 238 u32 mpll_func_cntl = 0; 239 u32 mpll_func_cntl_2 = 0 ; 240 u32 mpll_func_cntl_3 = 0; 241 u32 mclk_pwrmgt_cntl; 242 u32 dll_cntl; 243 u32 spll_func_cntl; 244 u32 spll_func_cntl_2; 245 u32 spll_func_cntl_3; 246 247 table->ACPIState = table->initialState; 248 table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC; 249 250 if (pi->acpi_vddc) { 251 rv770_populate_vddc_value(rdev, pi->acpi_vddc, 252 &table->ACPIState.levels[0].vddc); 253 table->ACPIState.levels[0].gen2PCIE = pi->pcie_gen2 ? 254 pi->acpi_pcie_gen2 : 0; 255 table->ACPIState.levels[0].gen2XSP = 256 pi->acpi_pcie_gen2; 257 } else { 258 rv770_populate_vddc_value(rdev, pi->min_vddc_in_table, 259 &table->ACPIState.levels[0].vddc); 260 table->ACPIState.levels[0].gen2PCIE = 0; 261 } 262 263 mpll_func_cntl = pi->clk_regs.rv730.mpll_func_cntl; 264 mpll_func_cntl_2 = pi->clk_regs.rv730.mpll_func_cntl2; 265 mpll_func_cntl_3 = pi->clk_regs.rv730.mpll_func_cntl3; 266 267 mpll_func_cntl |= MPLL_RESET | MPLL_BYPASS_EN; 268 mpll_func_cntl &= ~MPLL_SLEEP; 269 270 mpll_func_cntl_2 &= ~MCLK_MUX_SEL_MASK; 271 mpll_func_cntl_2 |= MCLK_MUX_SEL(1); 272 273 mclk_pwrmgt_cntl = (MRDCKA_RESET | 274 MRDCKB_RESET | 275 MRDCKC_RESET | 276 MRDCKD_RESET | 277 MRDCKE_RESET | 278 MRDCKF_RESET | 279 MRDCKG_RESET | 280 MRDCKH_RESET | 281 MRDCKA_SLEEP | 282 MRDCKB_SLEEP | 283 MRDCKC_SLEEP | 284 MRDCKD_SLEEP | 285 MRDCKE_SLEEP | 286 MRDCKF_SLEEP | 287 MRDCKG_SLEEP | 288 MRDCKH_SLEEP); 289 290 dll_cntl = 0xff000000; 291 292 spll_func_cntl = pi->clk_regs.rv730.cg_spll_func_cntl; 293 spll_func_cntl_2 = pi->clk_regs.rv730.cg_spll_func_cntl_2; 294 spll_func_cntl_3 = pi->clk_regs.rv730.cg_spll_func_cntl_3; 295 296 spll_func_cntl |= SPLL_RESET | SPLL_BYPASS_EN; 297 spll_func_cntl &= ~SPLL_SLEEP; 298 299 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; 300 spll_func_cntl_2 |= SCLK_MUX_SEL(4); 301 302 table->ACPIState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl); 303 table->ACPIState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL2 = cpu_to_be32(mpll_func_cntl_2); 304 table->ACPIState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL3 = cpu_to_be32(mpll_func_cntl_3); 305 table->ACPIState.levels[0].mclk.mclk730.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); 306 table->ACPIState.levels[0].mclk.mclk730.vDLL_CNTL = cpu_to_be32(dll_cntl); 307 308 table->ACPIState.levels[0].mclk.mclk730.mclk_value = 0; 309 310 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl); 311 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2); 312 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3); 313 314 table->ACPIState.levels[0].sclk.sclk_value = 0; 315 316 rv770_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd); 317 318 table->ACPIState.levels[1] = table->ACPIState.levels[0]; 319 table->ACPIState.levels[2] = table->ACPIState.levels[0]; 320 321 return 0; 322 } 323 324 int rv730_populate_smc_initial_state(struct radeon_device *rdev, 325 struct radeon_ps *radeon_state, 326 RV770_SMC_STATETABLE *table) 327 { 328 struct rv7xx_ps *initial_state = rv770_get_ps(radeon_state); 329 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 330 u32 a_t; 331 332 table->initialState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL = 333 cpu_to_be32(pi->clk_regs.rv730.mpll_func_cntl); 334 table->initialState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL2 = 335 cpu_to_be32(pi->clk_regs.rv730.mpll_func_cntl2); 336 table->initialState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL3 = 337 cpu_to_be32(pi->clk_regs.rv730.mpll_func_cntl3); 338 table->initialState.levels[0].mclk.mclk730.vMCLK_PWRMGT_CNTL = 339 cpu_to_be32(pi->clk_regs.rv730.mclk_pwrmgt_cntl); 340 table->initialState.levels[0].mclk.mclk730.vDLL_CNTL = 341 cpu_to_be32(pi->clk_regs.rv730.dll_cntl); 342 table->initialState.levels[0].mclk.mclk730.vMPLL_SS = 343 cpu_to_be32(pi->clk_regs.rv730.mpll_ss); 344 table->initialState.levels[0].mclk.mclk730.vMPLL_SS2 = 345 cpu_to_be32(pi->clk_regs.rv730.mpll_ss2); 346 347 table->initialState.levels[0].mclk.mclk730.mclk_value = 348 cpu_to_be32(initial_state->low.mclk); 349 350 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = 351 cpu_to_be32(pi->clk_regs.rv730.cg_spll_func_cntl); 352 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = 353 cpu_to_be32(pi->clk_regs.rv730.cg_spll_func_cntl_2); 354 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = 355 cpu_to_be32(pi->clk_regs.rv730.cg_spll_func_cntl_3); 356 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM = 357 cpu_to_be32(pi->clk_regs.rv730.cg_spll_spread_spectrum); 358 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 = 359 cpu_to_be32(pi->clk_regs.rv730.cg_spll_spread_spectrum_2); 360 361 table->initialState.levels[0].sclk.sclk_value = 362 cpu_to_be32(initial_state->low.sclk); 363 364 table->initialState.levels[0].arbValue = MC_CG_ARB_FREQ_F0; 365 366 table->initialState.levels[0].seqValue = 367 rv770_get_seq_value(rdev, &initial_state->low); 368 369 rv770_populate_vddc_value(rdev, 370 initial_state->low.vddc, 371 &table->initialState.levels[0].vddc); 372 rv770_populate_initial_mvdd_value(rdev, 373 &table->initialState.levels[0].mvdd); 374 375 a_t = CG_R(0xffff) | CG_L(0); 376 377 table->initialState.levels[0].aT = cpu_to_be32(a_t); 378 379 table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp); 380 381 if (pi->boot_in_gen2) 382 table->initialState.levels[0].gen2PCIE = 1; 383 else 384 table->initialState.levels[0].gen2PCIE = 0; 385 if (initial_state->low.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) 386 table->initialState.levels[0].gen2XSP = 1; 387 else 388 table->initialState.levels[0].gen2XSP = 0; 389 390 table->initialState.levels[1] = table->initialState.levels[0]; 391 table->initialState.levels[2] = table->initialState.levels[0]; 392 393 table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC; 394 395 return 0; 396 } 397 398 void rv730_program_memory_timing_parameters(struct radeon_device *rdev, 399 struct radeon_ps *radeon_state) 400 { 401 struct rv7xx_ps *state = rv770_get_ps(radeon_state); 402 u32 arb_refresh_rate = 0; 403 u32 dram_timing = 0; 404 u32 dram_timing2 = 0; 405 u32 old_dram_timing = 0; 406 u32 old_dram_timing2 = 0; 407 408 arb_refresh_rate = RREG32(MC_ARB_RFSH_RATE) & 409 ~(POWERMODE1_MASK | POWERMODE2_MASK | POWERMODE3_MASK); 410 arb_refresh_rate |= 411 (POWERMODE1(rv770_calculate_memory_refresh_rate(rdev, state->low.sclk)) | 412 POWERMODE2(rv770_calculate_memory_refresh_rate(rdev, state->medium.sclk)) | 413 POWERMODE3(rv770_calculate_memory_refresh_rate(rdev, state->high.sclk))); 414 WREG32(MC_ARB_RFSH_RATE, arb_refresh_rate); 415 416 /* save the boot dram timings */ 417 old_dram_timing = RREG32(MC_ARB_DRAM_TIMING); 418 old_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); 419 420 radeon_atom_set_engine_dram_timings(rdev, 421 state->high.sclk, 422 state->high.mclk); 423 424 dram_timing = RREG32(MC_ARB_DRAM_TIMING); 425 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); 426 427 WREG32(MC_ARB_DRAM_TIMING_3, dram_timing); 428 WREG32(MC_ARB_DRAM_TIMING2_3, dram_timing2); 429 430 radeon_atom_set_engine_dram_timings(rdev, 431 state->medium.sclk, 432 state->medium.mclk); 433 434 dram_timing = RREG32(MC_ARB_DRAM_TIMING); 435 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); 436 437 WREG32(MC_ARB_DRAM_TIMING_2, dram_timing); 438 WREG32(MC_ARB_DRAM_TIMING2_2, dram_timing2); 439 440 radeon_atom_set_engine_dram_timings(rdev, 441 state->low.sclk, 442 state->low.mclk); 443 444 dram_timing = RREG32(MC_ARB_DRAM_TIMING); 445 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); 446 447 WREG32(MC_ARB_DRAM_TIMING_1, dram_timing); 448 WREG32(MC_ARB_DRAM_TIMING2_1, dram_timing2); 449 450 /* restore the boot dram timings */ 451 WREG32(MC_ARB_DRAM_TIMING, old_dram_timing); 452 WREG32(MC_ARB_DRAM_TIMING2, old_dram_timing2); 453 454 } 455 456 void rv730_start_dpm(struct radeon_device *rdev) 457 { 458 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF); 459 460 WREG32_P(TCI_MCLK_PWRMGT_CNTL, 0, ~MPLL_PWRMGT_OFF); 461 462 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN); 463 } 464 465 void rv730_stop_dpm(struct radeon_device *rdev) 466 { 467 PPSMC_Result result; 468 469 result = rv770_send_msg_to_smc(rdev, PPSMC_MSG_TwoLevelsDisabled); 470 471 if (result != PPSMC_Result_OK) 472 DRM_DEBUG("Could not force DPM to low\n"); 473 474 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN); 475 476 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF); 477 478 WREG32_P(TCI_MCLK_PWRMGT_CNTL, MPLL_PWRMGT_OFF, ~MPLL_PWRMGT_OFF); 479 } 480 481 void rv730_program_dcodt(struct radeon_device *rdev, bool use_dcodt) 482 { 483 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 484 u32 i = use_dcodt ? 0 : 1; 485 u32 mc4_io_pad_cntl; 486 487 mc4_io_pad_cntl = RREG32(MC4_IO_DQ_PAD_CNTL_D0_I0); 488 mc4_io_pad_cntl &= 0xFFFFFF00; 489 mc4_io_pad_cntl |= pi->odt_value_0[i]; 490 WREG32(MC4_IO_DQ_PAD_CNTL_D0_I0, mc4_io_pad_cntl); 491 WREG32(MC4_IO_DQ_PAD_CNTL_D0_I1, mc4_io_pad_cntl); 492 493 mc4_io_pad_cntl = RREG32(MC4_IO_QS_PAD_CNTL_D0_I0); 494 mc4_io_pad_cntl &= 0xFFFFFF00; 495 mc4_io_pad_cntl |= pi->odt_value_1[i]; 496 WREG32(MC4_IO_QS_PAD_CNTL_D0_I0, mc4_io_pad_cntl); 497 WREG32(MC4_IO_QS_PAD_CNTL_D0_I1, mc4_io_pad_cntl); 498 } 499 500 void rv730_get_odt_values(struct radeon_device *rdev) 501 { 502 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 503 u32 mc4_io_pad_cntl; 504 505 pi->odt_value_0[0] = (u8)0; 506 pi->odt_value_1[0] = (u8)0x80; 507 508 mc4_io_pad_cntl = RREG32(MC4_IO_DQ_PAD_CNTL_D0_I0); 509 pi->odt_value_0[1] = (u8)(mc4_io_pad_cntl & 0xff); 510 511 mc4_io_pad_cntl = RREG32(MC4_IO_QS_PAD_CNTL_D0_I0); 512 pi->odt_value_1[1] = (u8)(mc4_io_pad_cntl & 0xff); 513 } 514
Indexes created Thu Oct 23 18:09:57 GMT 2025