radeon_rv770.c revision 1.1
1 /* $NetBSD: radeon_rv770.c,v 1.1 2018/08/27 14:38:20 riastradh Exp $ */ 2 3 /* 4 * Copyright 2008 Advanced Micro Devices, Inc. 5 * Copyright 2008 Red Hat Inc. 6 * Copyright 2009 Jerome Glisse. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: Dave Airlie 27 * Alex Deucher 28 * Jerome Glisse 29 */ 30 #include <sys/cdefs.h> 31 __KERNEL_RCSID(0, "$NetBSD: radeon_rv770.c,v 1.1 2018/08/27 14:38:20 riastradh Exp $"); 32 33 #include <linux/firmware.h> 34 #include <linux/slab.h> 35 #include <drm/drmP.h> 36 #include "radeon.h" 37 #include "radeon_asic.h" 38 #include "radeon_audio.h" 39 #include <drm/radeon_drm.h> 40 #include "rv770d.h" 41 #include "atom.h" 42 #include "avivod.h" 43 44 #define R700_PFP_UCODE_SIZE 848 45 #define R700_PM4_UCODE_SIZE 1360 46 47 static void rv770_gpu_init(struct radeon_device *rdev); 48 void rv770_fini(struct radeon_device *rdev); 49 static void rv770_pcie_gen2_enable(struct radeon_device *rdev); 50 int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); 51 52 int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) 53 { 54 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0; 55 int r; 56 57 /* RV740 uses evergreen uvd clk programming */ 58 if (rdev->family == CHIP_RV740) 59 return evergreen_set_uvd_clocks(rdev, vclk, dclk); 60 61 /* bypass vclk and dclk with bclk */ 62 WREG32_P(CG_UPLL_FUNC_CNTL_2, 63 VCLK_SRC_SEL(1) | DCLK_SRC_SEL(1), 64 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK)); 65 66 if (!vclk || !dclk) { 67 /* keep the Bypass mode, put PLL to sleep */ 68 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK); 69 return 0; 70 } 71 72 r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 50000, 160000, 73 43663, 0x03FFFFFE, 1, 30, ~0, 74 &fb_div, &vclk_div, &dclk_div); 75 if (r) 76 return r; 77 78 fb_div |= 1; 79 vclk_div -= 1; 80 dclk_div -= 1; 81 82 /* set UPLL_FB_DIV to 0x50000 */ 83 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(0x50000), ~UPLL_FB_DIV_MASK); 84 85 /* deassert UPLL_RESET and UPLL_SLEEP */ 86 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~(UPLL_RESET_MASK | UPLL_SLEEP_MASK)); 87 88 /* assert BYPASS EN and FB_DIV[0] <- ??? why? */ 89 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK); 90 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(1), ~UPLL_FB_DIV(1)); 91 92 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL); 93 if (r) 94 return r; 95 96 /* assert PLL_RESET */ 97 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK); 98 99 /* set the required FB_DIV, REF_DIV, Post divder values */ 100 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_REF_DIV(1), ~UPLL_REF_DIV_MASK); 101 WREG32_P(CG_UPLL_FUNC_CNTL_2, 102 UPLL_SW_HILEN(vclk_div >> 1) | 103 UPLL_SW_LOLEN((vclk_div >> 1) + (vclk_div & 1)) | 104 UPLL_SW_HILEN2(dclk_div >> 1) | 105 UPLL_SW_LOLEN2((dclk_div >> 1) + (dclk_div & 1)), 106 ~UPLL_SW_MASK); 107 108 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), 109 ~UPLL_FB_DIV_MASK); 110 111 /* give the PLL some time to settle */ 112 mdelay(15); 113 114 /* deassert PLL_RESET */ 115 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); 116 117 mdelay(15); 118 119 /* deassert BYPASS EN and FB_DIV[0] <- ??? why? */ 120 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK); 121 WREG32_P(CG_UPLL_FUNC_CNTL_3, 0, ~UPLL_FB_DIV(1)); 122 123 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL); 124 if (r) 125 return r; 126 127 /* switch VCLK and DCLK selection */ 128 WREG32_P(CG_UPLL_FUNC_CNTL_2, 129 VCLK_SRC_SEL(2) | DCLK_SRC_SEL(2), 130 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK)); 131 132 mdelay(100); 133 134 return 0; 135 } 136 137 static const u32 r7xx_golden_registers[] = 138 { 139 0x8d00, 0xffffffff, 0x0e0e0074, 140 0x8d04, 0xffffffff, 0x013a2b34, 141 0x9508, 0xffffffff, 0x00000002, 142 0x8b20, 0xffffffff, 0, 143 0x88c4, 0xffffffff, 0x000000c2, 144 0x28350, 0xffffffff, 0, 145 0x9058, 0xffffffff, 0x0fffc40f, 146 0x240c, 0xffffffff, 0x00000380, 147 0x733c, 0xffffffff, 0x00000002, 148 0x2650, 0x00040000, 0, 149 0x20bc, 0x00040000, 0, 150 0x7300, 0xffffffff, 0x001000f0 151 }; 152 153 static const u32 r7xx_golden_dyn_gpr_registers[] = 154 { 155 0x8db0, 0xffffffff, 0x98989898, 156 0x8db4, 0xffffffff, 0x98989898, 157 0x8db8, 0xffffffff, 0x98989898, 158 0x8dbc, 0xffffffff, 0x98989898, 159 0x8dc0, 0xffffffff, 0x98989898, 160 0x8dc4, 0xffffffff, 0x98989898, 161 0x8dc8, 0xffffffff, 0x98989898, 162 0x8dcc, 0xffffffff, 0x98989898, 163 0x88c4, 0xffffffff, 0x00000082 164 }; 165 166 static const u32 rv770_golden_registers[] = 167 { 168 0x562c, 0xffffffff, 0, 169 0x3f90, 0xffffffff, 0, 170 0x9148, 0xffffffff, 0, 171 0x3f94, 0xffffffff, 0, 172 0x914c, 0xffffffff, 0, 173 0x9698, 0x18000000, 0x18000000 174 }; 175 176 static const u32 rv770ce_golden_registers[] = 177 { 178 0x562c, 0xffffffff, 0, 179 0x3f90, 0xffffffff, 0x00cc0000, 180 0x9148, 0xffffffff, 0x00cc0000, 181 0x3f94, 0xffffffff, 0x00cc0000, 182 0x914c, 0xffffffff, 0x00cc0000, 183 0x9b7c, 0xffffffff, 0x00fa0000, 184 0x3f8c, 0xffffffff, 0x00fa0000, 185 0x9698, 0x18000000, 0x18000000 186 }; 187 188 static const u32 rv770_mgcg_init[] = 189 { 190 0x8bcc, 0xffffffff, 0x130300f9, 191 0x5448, 0xffffffff, 0x100, 192 0x55e4, 0xffffffff, 0x100, 193 0x160c, 0xffffffff, 0x100, 194 0x5644, 0xffffffff, 0x100, 195 0xc164, 0xffffffff, 0x100, 196 0x8a18, 0xffffffff, 0x100, 197 0x897c, 0xffffffff, 0x8000100, 198 0x8b28, 0xffffffff, 0x3c000100, 199 0x9144, 0xffffffff, 0x100, 200 0x9a1c, 0xffffffff, 0x10000, 201 0x9a50, 0xffffffff, 0x100, 202 0x9a1c, 0xffffffff, 0x10001, 203 0x9a50, 0xffffffff, 0x100, 204 0x9a1c, 0xffffffff, 0x10002, 205 0x9a50, 0xffffffff, 0x100, 206 0x9a1c, 0xffffffff, 0x10003, 207 0x9a50, 0xffffffff, 0x100, 208 0x9a1c, 0xffffffff, 0x0, 209 0x9870, 0xffffffff, 0x100, 210 0x8d58, 0xffffffff, 0x100, 211 0x9500, 0xffffffff, 0x0, 212 0x9510, 0xffffffff, 0x100, 213 0x9500, 0xffffffff, 0x1, 214 0x9510, 0xffffffff, 0x100, 215 0x9500, 0xffffffff, 0x2, 216 0x9510, 0xffffffff, 0x100, 217 0x9500, 0xffffffff, 0x3, 218 0x9510, 0xffffffff, 0x100, 219 0x9500, 0xffffffff, 0x4, 220 0x9510, 0xffffffff, 0x100, 221 0x9500, 0xffffffff, 0x5, 222 0x9510, 0xffffffff, 0x100, 223 0x9500, 0xffffffff, 0x6, 224 0x9510, 0xffffffff, 0x100, 225 0x9500, 0xffffffff, 0x7, 226 0x9510, 0xffffffff, 0x100, 227 0x9500, 0xffffffff, 0x8, 228 0x9510, 0xffffffff, 0x100, 229 0x9500, 0xffffffff, 0x9, 230 0x9510, 0xffffffff, 0x100, 231 0x9500, 0xffffffff, 0x8000, 232 0x9490, 0xffffffff, 0x0, 233 0x949c, 0xffffffff, 0x100, 234 0x9490, 0xffffffff, 0x1, 235 0x949c, 0xffffffff, 0x100, 236 0x9490, 0xffffffff, 0x2, 237 0x949c, 0xffffffff, 0x100, 238 0x9490, 0xffffffff, 0x3, 239 0x949c, 0xffffffff, 0x100, 240 0x9490, 0xffffffff, 0x4, 241 0x949c, 0xffffffff, 0x100, 242 0x9490, 0xffffffff, 0x5, 243 0x949c, 0xffffffff, 0x100, 244 0x9490, 0xffffffff, 0x6, 245 0x949c, 0xffffffff, 0x100, 246 0x9490, 0xffffffff, 0x7, 247 0x949c, 0xffffffff, 0x100, 248 0x9490, 0xffffffff, 0x8, 249 0x949c, 0xffffffff, 0x100, 250 0x9490, 0xffffffff, 0x9, 251 0x949c, 0xffffffff, 0x100, 252 0x9490, 0xffffffff, 0x8000, 253 0x9604, 0xffffffff, 0x0, 254 0x9654, 0xffffffff, 0x100, 255 0x9604, 0xffffffff, 0x1, 256 0x9654, 0xffffffff, 0x100, 257 0x9604, 0xffffffff, 0x2, 258 0x9654, 0xffffffff, 0x100, 259 0x9604, 0xffffffff, 0x3, 260 0x9654, 0xffffffff, 0x100, 261 0x9604, 0xffffffff, 0x4, 262 0x9654, 0xffffffff, 0x100, 263 0x9604, 0xffffffff, 0x5, 264 0x9654, 0xffffffff, 0x100, 265 0x9604, 0xffffffff, 0x6, 266 0x9654, 0xffffffff, 0x100, 267 0x9604, 0xffffffff, 0x7, 268 0x9654, 0xffffffff, 0x100, 269 0x9604, 0xffffffff, 0x8, 270 0x9654, 0xffffffff, 0x100, 271 0x9604, 0xffffffff, 0x9, 272 0x9654, 0xffffffff, 0x100, 273 0x9604, 0xffffffff, 0x80000000, 274 0x9030, 0xffffffff, 0x100, 275 0x9034, 0xffffffff, 0x100, 276 0x9038, 0xffffffff, 0x100, 277 0x903c, 0xffffffff, 0x100, 278 0x9040, 0xffffffff, 0x100, 279 0xa200, 0xffffffff, 0x100, 280 0xa204, 0xffffffff, 0x100, 281 0xa208, 0xffffffff, 0x100, 282 0xa20c, 0xffffffff, 0x100, 283 0x971c, 0xffffffff, 0x100, 284 0x915c, 0xffffffff, 0x00020001, 285 0x9160, 0xffffffff, 0x00040003, 286 0x916c, 0xffffffff, 0x00060005, 287 0x9170, 0xffffffff, 0x00080007, 288 0x9174, 0xffffffff, 0x000a0009, 289 0x9178, 0xffffffff, 0x000c000b, 290 0x917c, 0xffffffff, 0x000e000d, 291 0x9180, 0xffffffff, 0x0010000f, 292 0x918c, 0xffffffff, 0x00120011, 293 0x9190, 0xffffffff, 0x00140013, 294 0x9194, 0xffffffff, 0x00020001, 295 0x9198, 0xffffffff, 0x00040003, 296 0x919c, 0xffffffff, 0x00060005, 297 0x91a8, 0xffffffff, 0x00080007, 298 0x91ac, 0xffffffff, 0x000a0009, 299 0x91b0, 0xffffffff, 0x000c000b, 300 0x91b4, 0xffffffff, 0x000e000d, 301 0x91b8, 0xffffffff, 0x0010000f, 302 0x91c4, 0xffffffff, 0x00120011, 303 0x91c8, 0xffffffff, 0x00140013, 304 0x91cc, 0xffffffff, 0x00020001, 305 0x91d0, 0xffffffff, 0x00040003, 306 0x91d4, 0xffffffff, 0x00060005, 307 0x91e0, 0xffffffff, 0x00080007, 308 0x91e4, 0xffffffff, 0x000a0009, 309 0x91e8, 0xffffffff, 0x000c000b, 310 0x91ec, 0xffffffff, 0x00020001, 311 0x91f0, 0xffffffff, 0x00040003, 312 0x91f4, 0xffffffff, 0x00060005, 313 0x9200, 0xffffffff, 0x00080007, 314 0x9204, 0xffffffff, 0x000a0009, 315 0x9208, 0xffffffff, 0x000c000b, 316 0x920c, 0xffffffff, 0x000e000d, 317 0x9210, 0xffffffff, 0x0010000f, 318 0x921c, 0xffffffff, 0x00120011, 319 0x9220, 0xffffffff, 0x00140013, 320 0x9224, 0xffffffff, 0x00020001, 321 0x9228, 0xffffffff, 0x00040003, 322 0x922c, 0xffffffff, 0x00060005, 323 0x9238, 0xffffffff, 0x00080007, 324 0x923c, 0xffffffff, 0x000a0009, 325 0x9240, 0xffffffff, 0x000c000b, 326 0x9244, 0xffffffff, 0x000e000d, 327 0x9248, 0xffffffff, 0x0010000f, 328 0x9254, 0xffffffff, 0x00120011, 329 0x9258, 0xffffffff, 0x00140013, 330 0x925c, 0xffffffff, 0x00020001, 331 0x9260, 0xffffffff, 0x00040003, 332 0x9264, 0xffffffff, 0x00060005, 333 0x9270, 0xffffffff, 0x00080007, 334 0x9274, 0xffffffff, 0x000a0009, 335 0x9278, 0xffffffff, 0x000c000b, 336 0x927c, 0xffffffff, 0x000e000d, 337 0x9280, 0xffffffff, 0x0010000f, 338 0x928c, 0xffffffff, 0x00120011, 339 0x9290, 0xffffffff, 0x00140013, 340 0x9294, 0xffffffff, 0x00020001, 341 0x929c, 0xffffffff, 0x00040003, 342 0x92a0, 0xffffffff, 0x00060005, 343 0x92a4, 0xffffffff, 0x00080007 344 }; 345 346 static const u32 rv710_golden_registers[] = 347 { 348 0x3f90, 0x00ff0000, 0x00fc0000, 349 0x9148, 0x00ff0000, 0x00fc0000, 350 0x3f94, 0x00ff0000, 0x00fc0000, 351 0x914c, 0x00ff0000, 0x00fc0000, 352 0xb4c, 0x00000020, 0x00000020, 353 0xa180, 0xffffffff, 0x00003f3f 354 }; 355 356 static const u32 rv710_mgcg_init[] = 357 { 358 0x8bcc, 0xffffffff, 0x13030040, 359 0x5448, 0xffffffff, 0x100, 360 0x55e4, 0xffffffff, 0x100, 361 0x160c, 0xffffffff, 0x100, 362 0x5644, 0xffffffff, 0x100, 363 0xc164, 0xffffffff, 0x100, 364 0x8a18, 0xffffffff, 0x100, 365 0x897c, 0xffffffff, 0x8000100, 366 0x8b28, 0xffffffff, 0x3c000100, 367 0x9144, 0xffffffff, 0x100, 368 0x9a1c, 0xffffffff, 0x10000, 369 0x9a50, 0xffffffff, 0x100, 370 0x9a1c, 0xffffffff, 0x0, 371 0x9870, 0xffffffff, 0x100, 372 0x8d58, 0xffffffff, 0x100, 373 0x9500, 0xffffffff, 0x0, 374 0x9510, 0xffffffff, 0x100, 375 0x9500, 0xffffffff, 0x1, 376 0x9510, 0xffffffff, 0x100, 377 0x9500, 0xffffffff, 0x8000, 378 0x9490, 0xffffffff, 0x0, 379 0x949c, 0xffffffff, 0x100, 380 0x9490, 0xffffffff, 0x1, 381 0x949c, 0xffffffff, 0x100, 382 0x9490, 0xffffffff, 0x8000, 383 0x9604, 0xffffffff, 0x0, 384 0x9654, 0xffffffff, 0x100, 385 0x9604, 0xffffffff, 0x1, 386 0x9654, 0xffffffff, 0x100, 387 0x9604, 0xffffffff, 0x80000000, 388 0x9030, 0xffffffff, 0x100, 389 0x9034, 0xffffffff, 0x100, 390 0x9038, 0xffffffff, 0x100, 391 0x903c, 0xffffffff, 0x100, 392 0x9040, 0xffffffff, 0x100, 393 0xa200, 0xffffffff, 0x100, 394 0xa204, 0xffffffff, 0x100, 395 0xa208, 0xffffffff, 0x100, 396 0xa20c, 0xffffffff, 0x100, 397 0x971c, 0xffffffff, 0x100, 398 0x915c, 0xffffffff, 0x00020001, 399 0x9174, 0xffffffff, 0x00000003, 400 0x9178, 0xffffffff, 0x00050001, 401 0x917c, 0xffffffff, 0x00030002, 402 0x918c, 0xffffffff, 0x00000004, 403 0x9190, 0xffffffff, 0x00070006, 404 0x9194, 0xffffffff, 0x00050001, 405 0x9198, 0xffffffff, 0x00030002, 406 0x91a8, 0xffffffff, 0x00000004, 407 0x91ac, 0xffffffff, 0x00070006, 408 0x91e8, 0xffffffff, 0x00000001, 409 0x9294, 0xffffffff, 0x00000001, 410 0x929c, 0xffffffff, 0x00000002, 411 0x92a0, 0xffffffff, 0x00040003, 412 0x9150, 0xffffffff, 0x4d940000 413 }; 414 415 static const u32 rv730_golden_registers[] = 416 { 417 0x3f90, 0x00ff0000, 0x00f00000, 418 0x9148, 0x00ff0000, 0x00f00000, 419 0x3f94, 0x00ff0000, 0x00f00000, 420 0x914c, 0x00ff0000, 0x00f00000, 421 0x900c, 0xffffffff, 0x003b033f, 422 0xb4c, 0x00000020, 0x00000020, 423 0xa180, 0xffffffff, 0x00003f3f 424 }; 425 426 static const u32 rv730_mgcg_init[] = 427 { 428 0x8bcc, 0xffffffff, 0x130300f9, 429 0x5448, 0xffffffff, 0x100, 430 0x55e4, 0xffffffff, 0x100, 431 0x160c, 0xffffffff, 0x100, 432 0x5644, 0xffffffff, 0x100, 433 0xc164, 0xffffffff, 0x100, 434 0x8a18, 0xffffffff, 0x100, 435 0x897c, 0xffffffff, 0x8000100, 436 0x8b28, 0xffffffff, 0x3c000100, 437 0x9144, 0xffffffff, 0x100, 438 0x9a1c, 0xffffffff, 0x10000, 439 0x9a50, 0xffffffff, 0x100, 440 0x9a1c, 0xffffffff, 0x10001, 441 0x9a50, 0xffffffff, 0x100, 442 0x9a1c, 0xffffffff, 0x0, 443 0x9870, 0xffffffff, 0x100, 444 0x8d58, 0xffffffff, 0x100, 445 0x9500, 0xffffffff, 0x0, 446 0x9510, 0xffffffff, 0x100, 447 0x9500, 0xffffffff, 0x1, 448 0x9510, 0xffffffff, 0x100, 449 0x9500, 0xffffffff, 0x2, 450 0x9510, 0xffffffff, 0x100, 451 0x9500, 0xffffffff, 0x3, 452 0x9510, 0xffffffff, 0x100, 453 0x9500, 0xffffffff, 0x4, 454 0x9510, 0xffffffff, 0x100, 455 0x9500, 0xffffffff, 0x5, 456 0x9510, 0xffffffff, 0x100, 457 0x9500, 0xffffffff, 0x6, 458 0x9510, 0xffffffff, 0x100, 459 0x9500, 0xffffffff, 0x7, 460 0x9510, 0xffffffff, 0x100, 461 0x9500, 0xffffffff, 0x8000, 462 0x9490, 0xffffffff, 0x0, 463 0x949c, 0xffffffff, 0x100, 464 0x9490, 0xffffffff, 0x1, 465 0x949c, 0xffffffff, 0x100, 466 0x9490, 0xffffffff, 0x2, 467 0x949c, 0xffffffff, 0x100, 468 0x9490, 0xffffffff, 0x3, 469 0x949c, 0xffffffff, 0x100, 470 0x9490, 0xffffffff, 0x4, 471 0x949c, 0xffffffff, 0x100, 472 0x9490, 0xffffffff, 0x5, 473 0x949c, 0xffffffff, 0x100, 474 0x9490, 0xffffffff, 0x6, 475 0x949c, 0xffffffff, 0x100, 476 0x9490, 0xffffffff, 0x7, 477 0x949c, 0xffffffff, 0x100, 478 0x9490, 0xffffffff, 0x8000, 479 0x9604, 0xffffffff, 0x0, 480 0x9654, 0xffffffff, 0x100, 481 0x9604, 0xffffffff, 0x1, 482 0x9654, 0xffffffff, 0x100, 483 0x9604, 0xffffffff, 0x2, 484 0x9654, 0xffffffff, 0x100, 485 0x9604, 0xffffffff, 0x3, 486 0x9654, 0xffffffff, 0x100, 487 0x9604, 0xffffffff, 0x4, 488 0x9654, 0xffffffff, 0x100, 489 0x9604, 0xffffffff, 0x5, 490 0x9654, 0xffffffff, 0x100, 491 0x9604, 0xffffffff, 0x6, 492 0x9654, 0xffffffff, 0x100, 493 0x9604, 0xffffffff, 0x7, 494 0x9654, 0xffffffff, 0x100, 495 0x9604, 0xffffffff, 0x80000000, 496 0x9030, 0xffffffff, 0x100, 497 0x9034, 0xffffffff, 0x100, 498 0x9038, 0xffffffff, 0x100, 499 0x903c, 0xffffffff, 0x100, 500 0x9040, 0xffffffff, 0x100, 501 0xa200, 0xffffffff, 0x100, 502 0xa204, 0xffffffff, 0x100, 503 0xa208, 0xffffffff, 0x100, 504 0xa20c, 0xffffffff, 0x100, 505 0x971c, 0xffffffff, 0x100, 506 0x915c, 0xffffffff, 0x00020001, 507 0x916c, 0xffffffff, 0x00040003, 508 0x9170, 0xffffffff, 0x00000005, 509 0x9178, 0xffffffff, 0x00050001, 510 0x917c, 0xffffffff, 0x00030002, 511 0x918c, 0xffffffff, 0x00000004, 512 0x9190, 0xffffffff, 0x00070006, 513 0x9194, 0xffffffff, 0x00050001, 514 0x9198, 0xffffffff, 0x00030002, 515 0x91a8, 0xffffffff, 0x00000004, 516 0x91ac, 0xffffffff, 0x00070006, 517 0x91b0, 0xffffffff, 0x00050001, 518 0x91b4, 0xffffffff, 0x00030002, 519 0x91c4, 0xffffffff, 0x00000004, 520 0x91c8, 0xffffffff, 0x00070006, 521 0x91cc, 0xffffffff, 0x00050001, 522 0x91d0, 0xffffffff, 0x00030002, 523 0x91e0, 0xffffffff, 0x00000004, 524 0x91e4, 0xffffffff, 0x00070006, 525 0x91e8, 0xffffffff, 0x00000001, 526 0x91ec, 0xffffffff, 0x00050001, 527 0x91f0, 0xffffffff, 0x00030002, 528 0x9200, 0xffffffff, 0x00000004, 529 0x9204, 0xffffffff, 0x00070006, 530 0x9208, 0xffffffff, 0x00050001, 531 0x920c, 0xffffffff, 0x00030002, 532 0x921c, 0xffffffff, 0x00000004, 533 0x9220, 0xffffffff, 0x00070006, 534 0x9224, 0xffffffff, 0x00050001, 535 0x9228, 0xffffffff, 0x00030002, 536 0x9238, 0xffffffff, 0x00000004, 537 0x923c, 0xffffffff, 0x00070006, 538 0x9240, 0xffffffff, 0x00050001, 539 0x9244, 0xffffffff, 0x00030002, 540 0x9254, 0xffffffff, 0x00000004, 541 0x9258, 0xffffffff, 0x00070006, 542 0x9294, 0xffffffff, 0x00000001, 543 0x929c, 0xffffffff, 0x00000002, 544 0x92a0, 0xffffffff, 0x00040003, 545 0x92a4, 0xffffffff, 0x00000005 546 }; 547 548 static const u32 rv740_golden_registers[] = 549 { 550 0x88c4, 0xffffffff, 0x00000082, 551 0x28a50, 0xfffffffc, 0x00000004, 552 0x2650, 0x00040000, 0, 553 0x20bc, 0x00040000, 0, 554 0x733c, 0xffffffff, 0x00000002, 555 0x7300, 0xffffffff, 0x001000f0, 556 0x3f90, 0x00ff0000, 0, 557 0x9148, 0x00ff0000, 0, 558 0x3f94, 0x00ff0000, 0, 559 0x914c, 0x00ff0000, 0, 560 0x240c, 0xffffffff, 0x00000380, 561 0x8a14, 0x00000007, 0x00000007, 562 0x8b24, 0xffffffff, 0x00ff0fff, 563 0x28a4c, 0xffffffff, 0x00004000, 564 0xa180, 0xffffffff, 0x00003f3f, 565 0x8d00, 0xffffffff, 0x0e0e003a, 566 0x8d04, 0xffffffff, 0x013a0e2a, 567 0x8c00, 0xffffffff, 0xe400000f, 568 0x8db0, 0xffffffff, 0x98989898, 569 0x8db4, 0xffffffff, 0x98989898, 570 0x8db8, 0xffffffff, 0x98989898, 571 0x8dbc, 0xffffffff, 0x98989898, 572 0x8dc0, 0xffffffff, 0x98989898, 573 0x8dc4, 0xffffffff, 0x98989898, 574 0x8dc8, 0xffffffff, 0x98989898, 575 0x8dcc, 0xffffffff, 0x98989898, 576 0x9058, 0xffffffff, 0x0fffc40f, 577 0x900c, 0xffffffff, 0x003b033f, 578 0x28350, 0xffffffff, 0, 579 0x8cf0, 0x1fffffff, 0x08e00420, 580 0x9508, 0xffffffff, 0x00000002, 581 0x88c4, 0xffffffff, 0x000000c2, 582 0x9698, 0x18000000, 0x18000000 583 }; 584 585 static const u32 rv740_mgcg_init[] = 586 { 587 0x8bcc, 0xffffffff, 0x13030100, 588 0x5448, 0xffffffff, 0x100, 589 0x55e4, 0xffffffff, 0x100, 590 0x160c, 0xffffffff, 0x100, 591 0x5644, 0xffffffff, 0x100, 592 0xc164, 0xffffffff, 0x100, 593 0x8a18, 0xffffffff, 0x100, 594 0x897c, 0xffffffff, 0x100, 595 0x8b28, 0xffffffff, 0x100, 596 0x9144, 0xffffffff, 0x100, 597 0x9a1c, 0xffffffff, 0x10000, 598 0x9a50, 0xffffffff, 0x100, 599 0x9a1c, 0xffffffff, 0x10001, 600 0x9a50, 0xffffffff, 0x100, 601 0x9a1c, 0xffffffff, 0x10002, 602 0x9a50, 0xffffffff, 0x100, 603 0x9a1c, 0xffffffff, 0x10003, 604 0x9a50, 0xffffffff, 0x100, 605 0x9a1c, 0xffffffff, 0x0, 606 0x9870, 0xffffffff, 0x100, 607 0x8d58, 0xffffffff, 0x100, 608 0x9500, 0xffffffff, 0x0, 609 0x9510, 0xffffffff, 0x100, 610 0x9500, 0xffffffff, 0x1, 611 0x9510, 0xffffffff, 0x100, 612 0x9500, 0xffffffff, 0x2, 613 0x9510, 0xffffffff, 0x100, 614 0x9500, 0xffffffff, 0x3, 615 0x9510, 0xffffffff, 0x100, 616 0x9500, 0xffffffff, 0x4, 617 0x9510, 0xffffffff, 0x100, 618 0x9500, 0xffffffff, 0x5, 619 0x9510, 0xffffffff, 0x100, 620 0x9500, 0xffffffff, 0x6, 621 0x9510, 0xffffffff, 0x100, 622 0x9500, 0xffffffff, 0x7, 623 0x9510, 0xffffffff, 0x100, 624 0x9500, 0xffffffff, 0x8000, 625 0x9490, 0xffffffff, 0x0, 626 0x949c, 0xffffffff, 0x100, 627 0x9490, 0xffffffff, 0x1, 628 0x949c, 0xffffffff, 0x100, 629 0x9490, 0xffffffff, 0x2, 630 0x949c, 0xffffffff, 0x100, 631 0x9490, 0xffffffff, 0x3, 632 0x949c, 0xffffffff, 0x100, 633 0x9490, 0xffffffff, 0x4, 634 0x949c, 0xffffffff, 0x100, 635 0x9490, 0xffffffff, 0x5, 636 0x949c, 0xffffffff, 0x100, 637 0x9490, 0xffffffff, 0x6, 638 0x949c, 0xffffffff, 0x100, 639 0x9490, 0xffffffff, 0x7, 640 0x949c, 0xffffffff, 0x100, 641 0x9490, 0xffffffff, 0x8000, 642 0x9604, 0xffffffff, 0x0, 643 0x9654, 0xffffffff, 0x100, 644 0x9604, 0xffffffff, 0x1, 645 0x9654, 0xffffffff, 0x100, 646 0x9604, 0xffffffff, 0x2, 647 0x9654, 0xffffffff, 0x100, 648 0x9604, 0xffffffff, 0x3, 649 0x9654, 0xffffffff, 0x100, 650 0x9604, 0xffffffff, 0x4, 651 0x9654, 0xffffffff, 0x100, 652 0x9604, 0xffffffff, 0x5, 653 0x9654, 0xffffffff, 0x100, 654 0x9604, 0xffffffff, 0x6, 655 0x9654, 0xffffffff, 0x100, 656 0x9604, 0xffffffff, 0x7, 657 0x9654, 0xffffffff, 0x100, 658 0x9604, 0xffffffff, 0x80000000, 659 0x9030, 0xffffffff, 0x100, 660 0x9034, 0xffffffff, 0x100, 661 0x9038, 0xffffffff, 0x100, 662 0x903c, 0xffffffff, 0x100, 663 0x9040, 0xffffffff, 0x100, 664 0xa200, 0xffffffff, 0x100, 665 0xa204, 0xffffffff, 0x100, 666 0xa208, 0xffffffff, 0x100, 667 0xa20c, 0xffffffff, 0x100, 668 0x971c, 0xffffffff, 0x100, 669 0x915c, 0xffffffff, 0x00020001, 670 0x9160, 0xffffffff, 0x00040003, 671 0x916c, 0xffffffff, 0x00060005, 672 0x9170, 0xffffffff, 0x00080007, 673 0x9174, 0xffffffff, 0x000a0009, 674 0x9178, 0xffffffff, 0x000c000b, 675 0x917c, 0xffffffff, 0x000e000d, 676 0x9180, 0xffffffff, 0x0010000f, 677 0x918c, 0xffffffff, 0x00120011, 678 0x9190, 0xffffffff, 0x00140013, 679 0x9194, 0xffffffff, 0x00020001, 680 0x9198, 0xffffffff, 0x00040003, 681 0x919c, 0xffffffff, 0x00060005, 682 0x91a8, 0xffffffff, 0x00080007, 683 0x91ac, 0xffffffff, 0x000a0009, 684 0x91b0, 0xffffffff, 0x000c000b, 685 0x91b4, 0xffffffff, 0x000e000d, 686 0x91b8, 0xffffffff, 0x0010000f, 687 0x91c4, 0xffffffff, 0x00120011, 688 0x91c8, 0xffffffff, 0x00140013, 689 0x91cc, 0xffffffff, 0x00020001, 690 0x91d0, 0xffffffff, 0x00040003, 691 0x91d4, 0xffffffff, 0x00060005, 692 0x91e0, 0xffffffff, 0x00080007, 693 0x91e4, 0xffffffff, 0x000a0009, 694 0x91e8, 0xffffffff, 0x000c000b, 695 0x91ec, 0xffffffff, 0x00020001, 696 0x91f0, 0xffffffff, 0x00040003, 697 0x91f4, 0xffffffff, 0x00060005, 698 0x9200, 0xffffffff, 0x00080007, 699 0x9204, 0xffffffff, 0x000a0009, 700 0x9208, 0xffffffff, 0x000c000b, 701 0x920c, 0xffffffff, 0x000e000d, 702 0x9210, 0xffffffff, 0x0010000f, 703 0x921c, 0xffffffff, 0x00120011, 704 0x9220, 0xffffffff, 0x00140013, 705 0x9224, 0xffffffff, 0x00020001, 706 0x9228, 0xffffffff, 0x00040003, 707 0x922c, 0xffffffff, 0x00060005, 708 0x9238, 0xffffffff, 0x00080007, 709 0x923c, 0xffffffff, 0x000a0009, 710 0x9240, 0xffffffff, 0x000c000b, 711 0x9244, 0xffffffff, 0x000e000d, 712 0x9248, 0xffffffff, 0x0010000f, 713 0x9254, 0xffffffff, 0x00120011, 714 0x9258, 0xffffffff, 0x00140013, 715 0x9294, 0xffffffff, 0x00020001, 716 0x929c, 0xffffffff, 0x00040003, 717 0x92a0, 0xffffffff, 0x00060005, 718 0x92a4, 0xffffffff, 0x00080007 719 }; 720 721 static void rv770_init_golden_registers(struct radeon_device *rdev) 722 { 723 switch (rdev->family) { 724 case CHIP_RV770: 725 radeon_program_register_sequence(rdev, 726 r7xx_golden_registers, 727 (const u32)ARRAY_SIZE(r7xx_golden_registers)); 728 radeon_program_register_sequence(rdev, 729 r7xx_golden_dyn_gpr_registers, 730 (const u32)ARRAY_SIZE(r7xx_golden_dyn_gpr_registers)); 731 if (rdev->pdev->device == 0x994e) 732 radeon_program_register_sequence(rdev, 733 rv770ce_golden_registers, 734 (const u32)ARRAY_SIZE(rv770ce_golden_registers)); 735 else 736 radeon_program_register_sequence(rdev, 737 rv770_golden_registers, 738 (const u32)ARRAY_SIZE(rv770_golden_registers)); 739 radeon_program_register_sequence(rdev, 740 rv770_mgcg_init, 741 (const u32)ARRAY_SIZE(rv770_mgcg_init)); 742 break; 743 case CHIP_RV730: 744 radeon_program_register_sequence(rdev, 745 r7xx_golden_registers, 746 (const u32)ARRAY_SIZE(r7xx_golden_registers)); 747 radeon_program_register_sequence(rdev, 748 r7xx_golden_dyn_gpr_registers, 749 (const u32)ARRAY_SIZE(r7xx_golden_dyn_gpr_registers)); 750 radeon_program_register_sequence(rdev, 751 rv730_golden_registers, 752 (const u32)ARRAY_SIZE(rv730_golden_registers)); 753 radeon_program_register_sequence(rdev, 754 rv730_mgcg_init, 755 (const u32)ARRAY_SIZE(rv730_mgcg_init)); 756 break; 757 case CHIP_RV710: 758 radeon_program_register_sequence(rdev, 759 r7xx_golden_registers, 760 (const u32)ARRAY_SIZE(r7xx_golden_registers)); 761 radeon_program_register_sequence(rdev, 762 r7xx_golden_dyn_gpr_registers, 763 (const u32)ARRAY_SIZE(r7xx_golden_dyn_gpr_registers)); 764 radeon_program_register_sequence(rdev, 765 rv710_golden_registers, 766 (const u32)ARRAY_SIZE(rv710_golden_registers)); 767 radeon_program_register_sequence(rdev, 768 rv710_mgcg_init, 769 (const u32)ARRAY_SIZE(rv710_mgcg_init)); 770 break; 771 case CHIP_RV740: 772 radeon_program_register_sequence(rdev, 773 rv740_golden_registers, 774 (const u32)ARRAY_SIZE(rv740_golden_registers)); 775 radeon_program_register_sequence(rdev, 776 rv740_mgcg_init, 777 (const u32)ARRAY_SIZE(rv740_mgcg_init)); 778 break; 779 default: 780 break; 781 } 782 } 783 784 #define PCIE_BUS_CLK 10000 785 #define TCLK (PCIE_BUS_CLK / 10) 786 787 /** 788 * rv770_get_xclk - get the xclk 789 * 790 * @rdev: radeon_device pointer 791 * 792 * Returns the reference clock used by the gfx engine 793 * (r7xx-cayman). 794 */ 795 u32 rv770_get_xclk(struct radeon_device *rdev) 796 { 797 u32 reference_clock = rdev->clock.spll.reference_freq; 798 u32 tmp = RREG32(CG_CLKPIN_CNTL); 799 800 if (tmp & MUX_TCLK_TO_XCLK) 801 return TCLK; 802 803 if (tmp & XTALIN_DIVIDE) 804 return reference_clock / 4; 805 806 return reference_clock; 807 } 808 809 void rv770_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base) 810 { 811 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 812 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset); 813 int i; 814 815 /* Lock the graphics update lock */ 816 tmp |= AVIVO_D1GRPH_UPDATE_LOCK; 817 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); 818 819 /* update the scanout addresses */ 820 if (radeon_crtc->crtc_id) { 821 WREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); 822 WREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); 823 } else { 824 WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); 825 WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); 826 } 827 WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 828 (u32)crtc_base); 829 WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 830 (u32)crtc_base); 831 832 /* Wait for update_pending to go high. */ 833 for (i = 0; i < rdev->usec_timeout; i++) { 834 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) 835 break; 836 udelay(1); 837 } 838 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n"); 839 840 /* Unlock the lock, so double-buffering can take place inside vblank */ 841 tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK; 842 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); 843 } 844 845 bool rv770_page_flip_pending(struct radeon_device *rdev, int crtc_id) 846 { 847 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 848 849 /* Return current update_pending status: */ 850 return !!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & 851 AVIVO_D1GRPH_SURFACE_UPDATE_PENDING); 852 } 853 854 /* get temperature in millidegrees */ 855 int rv770_get_temp(struct radeon_device *rdev) 856 { 857 u32 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >> 858 ASIC_T_SHIFT; 859 int actual_temp; 860 861 if (temp & 0x400) 862 actual_temp = -256; 863 else if (temp & 0x200) 864 actual_temp = 255; 865 else if (temp & 0x100) { 866 actual_temp = temp & 0x1ff; 867 actual_temp |= ~0x1ff; 868 } else 869 actual_temp = temp & 0xff; 870 871 return (actual_temp * 1000) / 2; 872 } 873 874 void rv770_pm_misc(struct radeon_device *rdev) 875 { 876 int req_ps_idx = rdev->pm.requested_power_state_index; 877 int req_cm_idx = rdev->pm.requested_clock_mode_index; 878 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx]; 879 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage; 880 881 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) { 882 /* 0xff01 is a flag rather then an actual voltage */ 883 if (voltage->voltage == 0xff01) 884 return; 885 if (voltage->voltage != rdev->pm.current_vddc) { 886 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC); 887 rdev->pm.current_vddc = voltage->voltage; 888 DRM_DEBUG("Setting: v: %d\n", voltage->voltage); 889 } 890 } 891 } 892 893 /* 894 * GART 895 */ 896 static int rv770_pcie_gart_enable(struct radeon_device *rdev) 897 { 898 u32 tmp; 899 int r, i; 900 901 if (rdev->gart.robj == NULL) { 902 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); 903 return -EINVAL; 904 } 905 r = radeon_gart_table_vram_pin(rdev); 906 if (r) 907 return r; 908 /* Setup L2 cache */ 909 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | 910 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 911 EFFECTIVE_L2_QUEUE_SIZE(7)); 912 WREG32(VM_L2_CNTL2, 0); 913 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); 914 /* Setup TLB control */ 915 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | 916 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 917 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | 918 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); 919 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); 920 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); 921 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); 922 if (rdev->family == CHIP_RV740) 923 WREG32(MC_VM_MD_L1_TLB3_CNTL, tmp); 924 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); 925 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); 926 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); 927 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); 928 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); 929 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); 930 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); 931 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | 932 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); 933 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 934 (u32)(rdev->dummy_page.addr >> 12)); 935 for (i = 1; i < 7; i++) 936 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 937 938 r600_pcie_gart_tlb_flush(rdev); 939 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 940 (unsigned)(rdev->mc.gtt_size >> 20), 941 (unsigned long long)rdev->gart.table_addr); 942 rdev->gart.ready = true; 943 return 0; 944 } 945 946 static void rv770_pcie_gart_disable(struct radeon_device *rdev) 947 { 948 u32 tmp; 949 int i; 950 951 /* Disable all tables */ 952 for (i = 0; i < 7; i++) 953 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 954 955 /* Setup L2 cache */ 956 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | 957 EFFECTIVE_L2_QUEUE_SIZE(7)); 958 WREG32(VM_L2_CNTL2, 0); 959 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); 960 /* Setup TLB control */ 961 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); 962 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); 963 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); 964 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); 965 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); 966 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); 967 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); 968 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); 969 radeon_gart_table_vram_unpin(rdev); 970 } 971 972 static void rv770_pcie_gart_fini(struct radeon_device *rdev) 973 { 974 radeon_gart_fini(rdev); 975 rv770_pcie_gart_disable(rdev); 976 radeon_gart_table_vram_free(rdev); 977 } 978 979 980 static void rv770_agp_enable(struct radeon_device *rdev) 981 { 982 u32 tmp; 983 int i; 984 985 /* Setup L2 cache */ 986 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | 987 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 988 EFFECTIVE_L2_QUEUE_SIZE(7)); 989 WREG32(VM_L2_CNTL2, 0); 990 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); 991 /* Setup TLB control */ 992 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | 993 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 994 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | 995 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); 996 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); 997 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); 998 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); 999 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); 1000 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); 1001 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); 1002 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); 1003 for (i = 0; i < 7; i++) 1004 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 1005 } 1006 1007 static void rv770_mc_program(struct radeon_device *rdev) 1008 { 1009 struct rv515_mc_save save; 1010 u32 tmp; 1011 int i, j; 1012 1013 /* Initialize HDP */ 1014 for (i = 0, j = 0; i < 32; i++, j += 0x18) { 1015 WREG32((0x2c14 + j), 0x00000000); 1016 WREG32((0x2c18 + j), 0x00000000); 1017 WREG32((0x2c1c + j), 0x00000000); 1018 WREG32((0x2c20 + j), 0x00000000); 1019 WREG32((0x2c24 + j), 0x00000000); 1020 } 1021 /* r7xx hw bug. Read from HDP_DEBUG1 rather 1022 * than writing to HDP_REG_COHERENCY_FLUSH_CNTL 1023 */ 1024 tmp = RREG32(HDP_DEBUG1); 1025 1026 rv515_mc_stop(rdev, &save); 1027 if (r600_mc_wait_for_idle(rdev)) { 1028 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1029 } 1030 /* Lockout access through VGA aperture*/ 1031 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); 1032 /* Update configuration */ 1033 if (rdev->flags & RADEON_IS_AGP) { 1034 if (rdev->mc.vram_start < rdev->mc.gtt_start) { 1035 /* VRAM before AGP */ 1036 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 1037 rdev->mc.vram_start >> 12); 1038 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 1039 rdev->mc.gtt_end >> 12); 1040 } else { 1041 /* VRAM after AGP */ 1042 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 1043 rdev->mc.gtt_start >> 12); 1044 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 1045 rdev->mc.vram_end >> 12); 1046 } 1047 } else { 1048 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 1049 rdev->mc.vram_start >> 12); 1050 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 1051 rdev->mc.vram_end >> 12); 1052 } 1053 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12); 1054 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; 1055 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); 1056 WREG32(MC_VM_FB_LOCATION, tmp); 1057 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); 1058 WREG32(HDP_NONSURFACE_INFO, (2 << 7)); 1059 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF); 1060 if (rdev->flags & RADEON_IS_AGP) { 1061 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16); 1062 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16); 1063 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); 1064 } else { 1065 WREG32(MC_VM_AGP_BASE, 0); 1066 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); 1067 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); 1068 } 1069 if (r600_mc_wait_for_idle(rdev)) { 1070 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1071 } 1072 rv515_mc_resume(rdev, &save); 1073 /* we need to own VRAM, so turn off the VGA renderer here 1074 * to stop it overwriting our objects */ 1075 rv515_vga_render_disable(rdev); 1076 } 1077 1078 1079 /* 1080 * CP. 1081 */ 1082 void r700_cp_stop(struct radeon_device *rdev) 1083 { 1084 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX) 1085 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 1086 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT)); 1087 WREG32(SCRATCH_UMSK, 0); 1088 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; 1089 } 1090 1091 static int rv770_cp_load_microcode(struct radeon_device *rdev) 1092 { 1093 const __be32 *fw_data; 1094 int i; 1095 1096 if (!rdev->me_fw || !rdev->pfp_fw) 1097 return -EINVAL; 1098 1099 r700_cp_stop(rdev); 1100 WREG32(CP_RB_CNTL, 1101 #ifdef __BIG_ENDIAN 1102 BUF_SWAP_32BIT | 1103 #endif 1104 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); 1105 1106 /* Reset cp */ 1107 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); 1108 RREG32(GRBM_SOFT_RESET); 1109 mdelay(15); 1110 WREG32(GRBM_SOFT_RESET, 0); 1111 1112 fw_data = (const __be32 *)rdev->pfp_fw->data; 1113 WREG32(CP_PFP_UCODE_ADDR, 0); 1114 for (i = 0; i < R700_PFP_UCODE_SIZE; i++) 1115 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++)); 1116 WREG32(CP_PFP_UCODE_ADDR, 0); 1117 1118 fw_data = (const __be32 *)rdev->me_fw->data; 1119 WREG32(CP_ME_RAM_WADDR, 0); 1120 for (i = 0; i < R700_PM4_UCODE_SIZE; i++) 1121 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++)); 1122 1123 WREG32(CP_PFP_UCODE_ADDR, 0); 1124 WREG32(CP_ME_RAM_WADDR, 0); 1125 WREG32(CP_ME_RAM_RADDR, 0); 1126 return 0; 1127 } 1128 1129 void r700_cp_fini(struct radeon_device *rdev) 1130 { 1131 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 1132 r700_cp_stop(rdev); 1133 radeon_ring_fini(rdev, ring); 1134 radeon_scratch_free(rdev, ring->rptr_save_reg); 1135 } 1136 1137 void rv770_set_clk_bypass_mode(struct radeon_device *rdev) 1138 { 1139 u32 tmp, i; 1140 1141 if (rdev->flags & RADEON_IS_IGP) 1142 return; 1143 1144 tmp = RREG32(CG_SPLL_FUNC_CNTL_2); 1145 tmp &= SCLK_MUX_SEL_MASK; 1146 tmp |= SCLK_MUX_SEL(1) | SCLK_MUX_UPDATE; 1147 WREG32(CG_SPLL_FUNC_CNTL_2, tmp); 1148 1149 for (i = 0; i < rdev->usec_timeout; i++) { 1150 if (RREG32(CG_SPLL_STATUS) & SPLL_CHG_STATUS) 1151 break; 1152 udelay(1); 1153 } 1154 1155 tmp &= ~SCLK_MUX_UPDATE; 1156 WREG32(CG_SPLL_FUNC_CNTL_2, tmp); 1157 1158 tmp = RREG32(MPLL_CNTL_MODE); 1159 if ((rdev->family == CHIP_RV710) || (rdev->family == CHIP_RV730)) 1160 tmp &= ~RV730_MPLL_MCLK_SEL; 1161 else 1162 tmp &= ~MPLL_MCLK_SEL; 1163 WREG32(MPLL_CNTL_MODE, tmp); 1164 } 1165 1166 /* 1167 * Core functions 1168 */ 1169 static void rv770_gpu_init(struct radeon_device *rdev) 1170 { 1171 int i, j, num_qd_pipes; 1172 u32 ta_aux_cntl; 1173 u32 sx_debug_1; 1174 u32 smx_dc_ctl0; 1175 u32 db_debug3; 1176 u32 num_gs_verts_per_thread; 1177 u32 vgt_gs_per_es; 1178 u32 gs_prim_buffer_depth = 0; 1179 u32 sq_ms_fifo_sizes; 1180 u32 sq_config; 1181 u32 sq_thread_resource_mgmt; 1182 u32 hdp_host_path_cntl; 1183 u32 sq_dyn_gpr_size_simd_ab_0; 1184 u32 gb_tiling_config = 0; 1185 u32 cc_gc_shader_pipe_config = 0; 1186 u32 mc_arb_ramcfg; 1187 u32 db_debug4, tmp; 1188 u32 inactive_pipes, shader_pipe_config; 1189 u32 disabled_rb_mask; 1190 unsigned active_number; 1191 1192 /* setup chip specs */ 1193 rdev->config.rv770.tiling_group_size = 256; 1194 switch (rdev->family) { 1195 case CHIP_RV770: 1196 rdev->config.rv770.max_pipes = 4; 1197 rdev->config.rv770.max_tile_pipes = 8; 1198 rdev->config.rv770.max_simds = 10; 1199 rdev->config.rv770.max_backends = 4; 1200 rdev->config.rv770.max_gprs = 256; 1201 rdev->config.rv770.max_threads = 248; 1202 rdev->config.rv770.max_stack_entries = 512; 1203 rdev->config.rv770.max_hw_contexts = 8; 1204 rdev->config.rv770.max_gs_threads = 16 * 2; 1205 rdev->config.rv770.sx_max_export_size = 128; 1206 rdev->config.rv770.sx_max_export_pos_size = 16; 1207 rdev->config.rv770.sx_max_export_smx_size = 112; 1208 rdev->config.rv770.sq_num_cf_insts = 2; 1209 1210 rdev->config.rv770.sx_num_of_sets = 7; 1211 rdev->config.rv770.sc_prim_fifo_size = 0xF9; 1212 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; 1213 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; 1214 break; 1215 case CHIP_RV730: 1216 rdev->config.rv770.max_pipes = 2; 1217 rdev->config.rv770.max_tile_pipes = 4; 1218 rdev->config.rv770.max_simds = 8; 1219 rdev->config.rv770.max_backends = 2; 1220 rdev->config.rv770.max_gprs = 128; 1221 rdev->config.rv770.max_threads = 248; 1222 rdev->config.rv770.max_stack_entries = 256; 1223 rdev->config.rv770.max_hw_contexts = 8; 1224 rdev->config.rv770.max_gs_threads = 16 * 2; 1225 rdev->config.rv770.sx_max_export_size = 256; 1226 rdev->config.rv770.sx_max_export_pos_size = 32; 1227 rdev->config.rv770.sx_max_export_smx_size = 224; 1228 rdev->config.rv770.sq_num_cf_insts = 2; 1229 1230 rdev->config.rv770.sx_num_of_sets = 7; 1231 rdev->config.rv770.sc_prim_fifo_size = 0xf9; 1232 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; 1233 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; 1234 if (rdev->config.rv770.sx_max_export_pos_size > 16) { 1235 rdev->config.rv770.sx_max_export_pos_size -= 16; 1236 rdev->config.rv770.sx_max_export_smx_size += 16; 1237 } 1238 break; 1239 case CHIP_RV710: 1240 rdev->config.rv770.max_pipes = 2; 1241 rdev->config.rv770.max_tile_pipes = 2; 1242 rdev->config.rv770.max_simds = 2; 1243 rdev->config.rv770.max_backends = 1; 1244 rdev->config.rv770.max_gprs = 256; 1245 rdev->config.rv770.max_threads = 192; 1246 rdev->config.rv770.max_stack_entries = 256; 1247 rdev->config.rv770.max_hw_contexts = 4; 1248 rdev->config.rv770.max_gs_threads = 8 * 2; 1249 rdev->config.rv770.sx_max_export_size = 128; 1250 rdev->config.rv770.sx_max_export_pos_size = 16; 1251 rdev->config.rv770.sx_max_export_smx_size = 112; 1252 rdev->config.rv770.sq_num_cf_insts = 1; 1253 1254 rdev->config.rv770.sx_num_of_sets = 7; 1255 rdev->config.rv770.sc_prim_fifo_size = 0x40; 1256 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; 1257 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; 1258 break; 1259 case CHIP_RV740: 1260 rdev->config.rv770.max_pipes = 4; 1261 rdev->config.rv770.max_tile_pipes = 4; 1262 rdev->config.rv770.max_simds = 8; 1263 rdev->config.rv770.max_backends = 4; 1264 rdev->config.rv770.max_gprs = 256; 1265 rdev->config.rv770.max_threads = 248; 1266 rdev->config.rv770.max_stack_entries = 512; 1267 rdev->config.rv770.max_hw_contexts = 8; 1268 rdev->config.rv770.max_gs_threads = 16 * 2; 1269 rdev->config.rv770.sx_max_export_size = 256; 1270 rdev->config.rv770.sx_max_export_pos_size = 32; 1271 rdev->config.rv770.sx_max_export_smx_size = 224; 1272 rdev->config.rv770.sq_num_cf_insts = 2; 1273 1274 rdev->config.rv770.sx_num_of_sets = 7; 1275 rdev->config.rv770.sc_prim_fifo_size = 0x100; 1276 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; 1277 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; 1278 1279 if (rdev->config.rv770.sx_max_export_pos_size > 16) { 1280 rdev->config.rv770.sx_max_export_pos_size -= 16; 1281 rdev->config.rv770.sx_max_export_smx_size += 16; 1282 } 1283 break; 1284 default: 1285 break; 1286 } 1287 1288 /* Initialize HDP */ 1289 j = 0; 1290 for (i = 0; i < 32; i++) { 1291 WREG32((0x2c14 + j), 0x00000000); 1292 WREG32((0x2c18 + j), 0x00000000); 1293 WREG32((0x2c1c + j), 0x00000000); 1294 WREG32((0x2c20 + j), 0x00000000); 1295 WREG32((0x2c24 + j), 0x00000000); 1296 j += 0x18; 1297 } 1298 1299 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); 1300 1301 /* setup tiling, simd, pipe config */ 1302 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG); 1303 1304 shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG); 1305 inactive_pipes = (shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> INACTIVE_QD_PIPES_SHIFT; 1306 for (i = 0, tmp = 1, active_number = 0; i < R7XX_MAX_PIPES; i++) { 1307 if (!(inactive_pipes & tmp)) { 1308 active_number++; 1309 } 1310 tmp <<= 1; 1311 } 1312 if (active_number == 1) { 1313 WREG32(SPI_CONFIG_CNTL, DISABLE_INTERP_1); 1314 } else { 1315 WREG32(SPI_CONFIG_CNTL, 0); 1316 } 1317 1318 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00; 1319 tmp = rdev->config.rv770.max_simds - 1320 r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R7XX_MAX_SIMDS_MASK); 1321 rdev->config.rv770.active_simds = tmp; 1322 1323 switch (rdev->config.rv770.max_tile_pipes) { 1324 case 1: 1325 default: 1326 gb_tiling_config = PIPE_TILING(0); 1327 break; 1328 case 2: 1329 gb_tiling_config = PIPE_TILING(1); 1330 break; 1331 case 4: 1332 gb_tiling_config = PIPE_TILING(2); 1333 break; 1334 case 8: 1335 gb_tiling_config = PIPE_TILING(3); 1336 break; 1337 } 1338 rdev->config.rv770.tiling_npipes = rdev->config.rv770.max_tile_pipes; 1339 1340 disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R7XX_MAX_BACKENDS_MASK; 1341 tmp = 0; 1342 for (i = 0; i < rdev->config.rv770.max_backends; i++) 1343 tmp |= (1 << i); 1344 /* if all the backends are disabled, fix it up here */ 1345 if ((disabled_rb_mask & tmp) == tmp) { 1346 for (i = 0; i < rdev->config.rv770.max_backends; i++) 1347 disabled_rb_mask &= ~(1 << i); 1348 } 1349 tmp = (gb_tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT; 1350 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.rv770.max_backends, 1351 R7XX_MAX_BACKENDS, disabled_rb_mask); 1352 gb_tiling_config |= tmp << 16; 1353 rdev->config.rv770.backend_map = tmp; 1354 1355 if (rdev->family == CHIP_RV770) 1356 gb_tiling_config |= BANK_TILING(1); 1357 else { 1358 if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) 1359 gb_tiling_config |= BANK_TILING(1); 1360 else 1361 gb_tiling_config |= BANK_TILING(0); 1362 } 1363 rdev->config.rv770.tiling_nbanks = 4 << ((gb_tiling_config >> 4) & 0x3); 1364 gb_tiling_config |= GROUP_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT); 1365 if (((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT) > 3) { 1366 gb_tiling_config |= ROW_TILING(3); 1367 gb_tiling_config |= SAMPLE_SPLIT(3); 1368 } else { 1369 gb_tiling_config |= 1370 ROW_TILING(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT)); 1371 gb_tiling_config |= 1372 SAMPLE_SPLIT(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT)); 1373 } 1374 1375 gb_tiling_config |= BANK_SWAPS(1); 1376 rdev->config.rv770.tile_config = gb_tiling_config; 1377 1378 WREG32(GB_TILING_CONFIG, gb_tiling_config); 1379 WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff)); 1380 WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff)); 1381 WREG32(DMA_TILING_CONFIG, (gb_tiling_config & 0xffff)); 1382 WREG32(DMA_TILING_CONFIG2, (gb_tiling_config & 0xffff)); 1383 if (rdev->family == CHIP_RV730) { 1384 WREG32(UVD_UDEC_DB_TILING_CONFIG, (gb_tiling_config & 0xffff)); 1385 WREG32(UVD_UDEC_DBW_TILING_CONFIG, (gb_tiling_config & 0xffff)); 1386 WREG32(UVD_UDEC_TILING_CONFIG, (gb_tiling_config & 0xffff)); 1387 } 1388 1389 WREG32(CGTS_SYS_TCC_DISABLE, 0); 1390 WREG32(CGTS_TCC_DISABLE, 0); 1391 WREG32(CGTS_USER_SYS_TCC_DISABLE, 0); 1392 WREG32(CGTS_USER_TCC_DISABLE, 0); 1393 1394 1395 num_qd_pipes = R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8); 1396 WREG32(VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & DEALLOC_DIST_MASK); 1397 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & VTX_REUSE_DEPTH_MASK); 1398 1399 /* set HW defaults for 3D engine */ 1400 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | 1401 ROQ_IB2_START(0x2b))); 1402 1403 WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30)); 1404 1405 ta_aux_cntl = RREG32(TA_CNTL_AUX); 1406 WREG32(TA_CNTL_AUX, ta_aux_cntl | DISABLE_CUBE_ANISO); 1407 1408 sx_debug_1 = RREG32(SX_DEBUG_1); 1409 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS; 1410 WREG32(SX_DEBUG_1, sx_debug_1); 1411 1412 smx_dc_ctl0 = RREG32(SMX_DC_CTL0); 1413 smx_dc_ctl0 &= ~CACHE_DEPTH(0x1ff); 1414 smx_dc_ctl0 |= CACHE_DEPTH((rdev->config.rv770.sx_num_of_sets * 64) - 1); 1415 WREG32(SMX_DC_CTL0, smx_dc_ctl0); 1416 1417 if (rdev->family != CHIP_RV740) 1418 WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) | 1419 GS_FLUSH_CTL(4) | 1420 ACK_FLUSH_CTL(3) | 1421 SYNC_FLUSH_CTL)); 1422 1423 if (rdev->family != CHIP_RV770) 1424 WREG32(SMX_SAR_CTL0, 0x00003f3f); 1425 1426 db_debug3 = RREG32(DB_DEBUG3); 1427 db_debug3 &= ~DB_CLK_OFF_DELAY(0x1f); 1428 switch (rdev->family) { 1429 case CHIP_RV770: 1430 case CHIP_RV740: 1431 db_debug3 |= DB_CLK_OFF_DELAY(0x1f); 1432 break; 1433 case CHIP_RV710: 1434 case CHIP_RV730: 1435 default: 1436 db_debug3 |= DB_CLK_OFF_DELAY(2); 1437 break; 1438 } 1439 WREG32(DB_DEBUG3, db_debug3); 1440 1441 if (rdev->family != CHIP_RV770) { 1442 db_debug4 = RREG32(DB_DEBUG4); 1443 db_debug4 |= DISABLE_TILE_COVERED_FOR_PS_ITER; 1444 WREG32(DB_DEBUG4, db_debug4); 1445 } 1446 1447 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) | 1448 POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) | 1449 SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1))); 1450 1451 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) | 1452 SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) | 1453 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize))); 1454 1455 WREG32(PA_SC_MULTI_CHIP_CNTL, 0); 1456 1457 WREG32(VGT_NUM_INSTANCES, 1); 1458 1459 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4)); 1460 1461 WREG32(CP_PERFMON_CNTL, 0); 1462 1463 sq_ms_fifo_sizes = (CACHE_FIFO_SIZE(16 * rdev->config.rv770.sq_num_cf_insts) | 1464 DONE_FIFO_HIWATER(0xe0) | 1465 ALU_UPDATE_FIFO_HIWATER(0x8)); 1466 switch (rdev->family) { 1467 case CHIP_RV770: 1468 case CHIP_RV730: 1469 case CHIP_RV710: 1470 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x1); 1471 break; 1472 case CHIP_RV740: 1473 default: 1474 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x4); 1475 break; 1476 } 1477 WREG32(SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes); 1478 1479 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT 1480 * should be adjusted as needed by the 2D/3D drivers. This just sets default values 1481 */ 1482 sq_config = RREG32(SQ_CONFIG); 1483 sq_config &= ~(PS_PRIO(3) | 1484 VS_PRIO(3) | 1485 GS_PRIO(3) | 1486 ES_PRIO(3)); 1487 sq_config |= (DX9_CONSTS | 1488 VC_ENABLE | 1489 EXPORT_SRC_C | 1490 PS_PRIO(0) | 1491 VS_PRIO(1) | 1492 GS_PRIO(2) | 1493 ES_PRIO(3)); 1494 if (rdev->family == CHIP_RV710) 1495 /* no vertex cache */ 1496 sq_config &= ~VC_ENABLE; 1497 1498 WREG32(SQ_CONFIG, sq_config); 1499 1500 WREG32(SQ_GPR_RESOURCE_MGMT_1, (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) | 1501 NUM_VS_GPRS((rdev->config.rv770.max_gprs * 24)/64) | 1502 NUM_CLAUSE_TEMP_GPRS(((rdev->config.rv770.max_gprs * 24)/64)/2))); 1503 1504 WREG32(SQ_GPR_RESOURCE_MGMT_2, (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) | 1505 NUM_ES_GPRS((rdev->config.rv770.max_gprs * 7)/64))); 1506 1507 sq_thread_resource_mgmt = (NUM_PS_THREADS((rdev->config.rv770.max_threads * 4)/8) | 1508 NUM_VS_THREADS((rdev->config.rv770.max_threads * 2)/8) | 1509 NUM_ES_THREADS((rdev->config.rv770.max_threads * 1)/8)); 1510 if (((rdev->config.rv770.max_threads * 1) / 8) > rdev->config.rv770.max_gs_threads) 1511 sq_thread_resource_mgmt |= NUM_GS_THREADS(rdev->config.rv770.max_gs_threads); 1512 else 1513 sq_thread_resource_mgmt |= NUM_GS_THREADS((rdev->config.rv770.max_gs_threads * 1)/8); 1514 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); 1515 1516 WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) | 1517 NUM_VS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4))); 1518 1519 WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) | 1520 NUM_ES_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4))); 1521 1522 sq_dyn_gpr_size_simd_ab_0 = (SIMDA_RING0((rdev->config.rv770.max_gprs * 38)/64) | 1523 SIMDA_RING1((rdev->config.rv770.max_gprs * 38)/64) | 1524 SIMDB_RING0((rdev->config.rv770.max_gprs * 38)/64) | 1525 SIMDB_RING1((rdev->config.rv770.max_gprs * 38)/64)); 1526 1527 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0); 1528 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0); 1529 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0); 1530 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0); 1531 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0); 1532 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0); 1533 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0); 1534 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0); 1535 1536 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) | 1537 FORCE_EOV_MAX_REZ_CNT(255))); 1538 1539 if (rdev->family == CHIP_RV710) 1540 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(TC_ONLY) | 1541 AUTO_INVLD_EN(ES_AND_GS_AUTO))); 1542 else 1543 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(VC_AND_TC) | 1544 AUTO_INVLD_EN(ES_AND_GS_AUTO))); 1545 1546 switch (rdev->family) { 1547 case CHIP_RV770: 1548 case CHIP_RV730: 1549 case CHIP_RV740: 1550 gs_prim_buffer_depth = 384; 1551 break; 1552 case CHIP_RV710: 1553 gs_prim_buffer_depth = 128; 1554 break; 1555 default: 1556 break; 1557 } 1558 1559 num_gs_verts_per_thread = rdev->config.rv770.max_pipes * 16; 1560 vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread; 1561 /* Max value for this is 256 */ 1562 if (vgt_gs_per_es > 256) 1563 vgt_gs_per_es = 256; 1564 1565 WREG32(VGT_ES_PER_GS, 128); 1566 WREG32(VGT_GS_PER_ES, vgt_gs_per_es); 1567 WREG32(VGT_GS_PER_VS, 2); 1568 1569 /* more default values. 2D/3D driver should adjust as needed */ 1570 WREG32(VGT_GS_VERTEX_REUSE, 16); 1571 WREG32(PA_SC_LINE_STIPPLE_STATE, 0); 1572 WREG32(VGT_STRMOUT_EN, 0); 1573 WREG32(SX_MISC, 0); 1574 WREG32(PA_SC_MODE_CNTL, 0); 1575 WREG32(PA_SC_EDGERULE, 0xaaaaaaaa); 1576 WREG32(PA_SC_AA_CONFIG, 0); 1577 WREG32(PA_SC_CLIPRECT_RULE, 0xffff); 1578 WREG32(PA_SC_LINE_STIPPLE, 0); 1579 WREG32(SPI_INPUT_Z, 0); 1580 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2)); 1581 WREG32(CB_COLOR7_FRAG, 0); 1582 1583 /* clear render buffer base addresses */ 1584 WREG32(CB_COLOR0_BASE, 0); 1585 WREG32(CB_COLOR1_BASE, 0); 1586 WREG32(CB_COLOR2_BASE, 0); 1587 WREG32(CB_COLOR3_BASE, 0); 1588 WREG32(CB_COLOR4_BASE, 0); 1589 WREG32(CB_COLOR5_BASE, 0); 1590 WREG32(CB_COLOR6_BASE, 0); 1591 WREG32(CB_COLOR7_BASE, 0); 1592 1593 WREG32(TCP_CNTL, 0); 1594 1595 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL); 1596 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl); 1597 1598 WREG32(PA_SC_MULTI_CHIP_CNTL, 0); 1599 1600 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA | 1601 NUM_CLIP_SEQ(3))); 1602 WREG32(VC_ENHANCE, 0); 1603 } 1604 1605 void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) 1606 { 1607 u64 size_bf, size_af; 1608 1609 if (mc->mc_vram_size > 0xE0000000) { 1610 /* leave room for at least 512M GTT */ 1611 dev_warn(rdev->dev, "limiting VRAM\n"); 1612 mc->real_vram_size = 0xE0000000; 1613 mc->mc_vram_size = 0xE0000000; 1614 } 1615 if (rdev->flags & RADEON_IS_AGP) { 1616 size_bf = mc->gtt_start; 1617 size_af = mc->mc_mask - mc->gtt_end; 1618 if (size_bf > size_af) { 1619 if (mc->mc_vram_size > size_bf) { 1620 dev_warn(rdev->dev, "limiting VRAM\n"); 1621 mc->real_vram_size = size_bf; 1622 mc->mc_vram_size = size_bf; 1623 } 1624 mc->vram_start = mc->gtt_start - mc->mc_vram_size; 1625 } else { 1626 if (mc->mc_vram_size > size_af) { 1627 dev_warn(rdev->dev, "limiting VRAM\n"); 1628 mc->real_vram_size = size_af; 1629 mc->mc_vram_size = size_af; 1630 } 1631 mc->vram_start = mc->gtt_end + 1; 1632 } 1633 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; 1634 dev_info(rdev->dev, "VRAM: %"PRIu64"M 0x%08"PRIX64" - 0x%08"PRIX64" (%"PRIu64"M used)\n", 1635 mc->mc_vram_size >> 20, mc->vram_start, 1636 mc->vram_end, mc->real_vram_size >> 20); 1637 } else { 1638 radeon_vram_location(rdev, &rdev->mc, 0); 1639 rdev->mc.gtt_base_align = 0; 1640 radeon_gtt_location(rdev, mc); 1641 } 1642 } 1643 1644 static int rv770_mc_init(struct radeon_device *rdev) 1645 { 1646 u32 tmp; 1647 int chansize, numchan; 1648 1649 /* Get VRAM informations */ 1650 rdev->mc.vram_is_ddr = true; 1651 tmp = RREG32(MC_ARB_RAMCFG); 1652 if (tmp & CHANSIZE_OVERRIDE) { 1653 chansize = 16; 1654 } else if (tmp & CHANSIZE_MASK) { 1655 chansize = 64; 1656 } else { 1657 chansize = 32; 1658 } 1659 tmp = RREG32(MC_SHARED_CHMAP); 1660 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { 1661 case 0: 1662 default: 1663 numchan = 1; 1664 break; 1665 case 1: 1666 numchan = 2; 1667 break; 1668 case 2: 1669 numchan = 4; 1670 break; 1671 case 3: 1672 numchan = 8; 1673 break; 1674 } 1675 rdev->mc.vram_width = numchan * chansize; 1676 /* Could aper size report 0 ? */ 1677 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); 1678 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); 1679 /* Setup GPU memory space */ 1680 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); 1681 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); 1682 rdev->mc.visible_vram_size = rdev->mc.aper_size; 1683 r700_vram_gtt_location(rdev, &rdev->mc); 1684 radeon_update_bandwidth_info(rdev); 1685 1686 return 0; 1687 } 1688 1689 static int rv770_startup(struct radeon_device *rdev) 1690 { 1691 struct radeon_ring *ring; 1692 int r; 1693 1694 /* enable pcie gen2 link */ 1695 rv770_pcie_gen2_enable(rdev); 1696 1697 /* scratch needs to be initialized before MC */ 1698 r = r600_vram_scratch_init(rdev); 1699 if (r) 1700 return r; 1701 1702 rv770_mc_program(rdev); 1703 1704 if (rdev->flags & RADEON_IS_AGP) { 1705 rv770_agp_enable(rdev); 1706 } else { 1707 r = rv770_pcie_gart_enable(rdev); 1708 if (r) 1709 return r; 1710 } 1711 1712 rv770_gpu_init(rdev); 1713 1714 /* allocate wb buffer */ 1715 r = radeon_wb_init(rdev); 1716 if (r) 1717 return r; 1718 1719 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 1720 if (r) { 1721 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 1722 return r; 1723 } 1724 1725 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX); 1726 if (r) { 1727 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r); 1728 return r; 1729 } 1730 1731 r = uvd_v2_2_resume(rdev); 1732 if (!r) { 1733 r = radeon_fence_driver_start_ring(rdev, 1734 R600_RING_TYPE_UVD_INDEX); 1735 if (r) 1736 dev_err(rdev->dev, "UVD fences init error (%d).\n", r); 1737 } 1738 1739 if (r) 1740 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0; 1741 1742 /* Enable IRQ */ 1743 if (!rdev->irq.installed) { 1744 r = radeon_irq_kms_init(rdev); 1745 if (r) 1746 return r; 1747 } 1748 1749 r = r600_irq_init(rdev); 1750 if (r) { 1751 DRM_ERROR("radeon: IH init failed (%d).\n", r); 1752 radeon_irq_kms_fini(rdev); 1753 return r; 1754 } 1755 r600_irq_set(rdev); 1756 1757 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 1758 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, 1759 RADEON_CP_PACKET2); 1760 if (r) 1761 return r; 1762 1763 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; 1764 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET, 1765 DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0)); 1766 if (r) 1767 return r; 1768 1769 r = rv770_cp_load_microcode(rdev); 1770 if (r) 1771 return r; 1772 r = r600_cp_resume(rdev); 1773 if (r) 1774 return r; 1775 1776 r = r600_dma_resume(rdev); 1777 if (r) 1778 return r; 1779 1780 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; 1781 if (ring->ring_size) { 1782 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, 1783 RADEON_CP_PACKET2); 1784 if (!r) 1785 r = uvd_v1_0_init(rdev); 1786 1787 if (r) 1788 DRM_ERROR("radeon: failed initializing UVD (%d).\n", r); 1789 } 1790 1791 r = radeon_ib_pool_init(rdev); 1792 if (r) { 1793 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 1794 return r; 1795 } 1796 1797 r = radeon_audio_init(rdev); 1798 if (r) { 1799 DRM_ERROR("radeon: audio init failed\n"); 1800 return r; 1801 } 1802 1803 return 0; 1804 } 1805 1806 int rv770_resume(struct radeon_device *rdev) 1807 { 1808 int r; 1809 1810 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw, 1811 * posting will perform necessary task to bring back GPU into good 1812 * shape. 1813 */ 1814 /* post card */ 1815 atom_asic_init(rdev->mode_info.atom_context); 1816 1817 /* init golden registers */ 1818 rv770_init_golden_registers(rdev); 1819 1820 if (rdev->pm.pm_method == PM_METHOD_DPM) 1821 radeon_pm_resume(rdev); 1822 1823 rdev->accel_working = true; 1824 r = rv770_startup(rdev); 1825 if (r) { 1826 DRM_ERROR("r600 startup failed on resume\n"); 1827 rdev->accel_working = false; 1828 return r; 1829 } 1830 1831 return r; 1832 1833 } 1834 1835 int rv770_suspend(struct radeon_device *rdev) 1836 { 1837 radeon_pm_suspend(rdev); 1838 radeon_audio_fini(rdev); 1839 uvd_v1_0_fini(rdev); 1840 radeon_uvd_suspend(rdev); 1841 r700_cp_stop(rdev); 1842 r600_dma_stop(rdev); 1843 r600_irq_suspend(rdev); 1844 radeon_wb_disable(rdev); 1845 rv770_pcie_gart_disable(rdev); 1846 1847 return 0; 1848 } 1849 1850 /* Plan is to move initialization in that function and use 1851 * helper function so that radeon_device_init pretty much 1852 * do nothing more than calling asic specific function. This 1853 * should also allow to remove a bunch of callback function 1854 * like vram_info. 1855 */ 1856 int rv770_init(struct radeon_device *rdev) 1857 { 1858 int r; 1859 1860 /* Read BIOS */ 1861 if (!radeon_get_bios(rdev)) { 1862 if (ASIC_IS_AVIVO(rdev)) 1863 return -EINVAL; 1864 } 1865 /* Must be an ATOMBIOS */ 1866 if (!rdev->is_atom_bios) { 1867 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n"); 1868 return -EINVAL; 1869 } 1870 r = radeon_atombios_init(rdev); 1871 if (r) 1872 return r; 1873 /* Post card if necessary */ 1874 if (!radeon_card_posted(rdev)) { 1875 if (!rdev->bios) { 1876 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); 1877 return -EINVAL; 1878 } 1879 DRM_INFO("GPU not posted. posting now...\n"); 1880 atom_asic_init(rdev->mode_info.atom_context); 1881 } 1882 /* init golden registers */ 1883 rv770_init_golden_registers(rdev); 1884 /* Initialize scratch registers */ 1885 r600_scratch_init(rdev); 1886 /* Initialize surface registers */ 1887 radeon_surface_init(rdev); 1888 /* Initialize clocks */ 1889 radeon_get_clock_info(rdev->ddev); 1890 /* Fence driver */ 1891 r = radeon_fence_driver_init(rdev); 1892 if (r) 1893 return r; 1894 /* initialize AGP */ 1895 if (rdev->flags & RADEON_IS_AGP) { 1896 r = radeon_agp_init(rdev); 1897 if (r) 1898 radeon_agp_disable(rdev); 1899 } 1900 r = rv770_mc_init(rdev); 1901 if (r) 1902 return r; 1903 /* Memory manager */ 1904 r = radeon_bo_init(rdev); 1905 if (r) 1906 return r; 1907 1908 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { 1909 r = r600_init_microcode(rdev); 1910 if (r) { 1911 DRM_ERROR("Failed to load firmware!\n"); 1912 return r; 1913 } 1914 } 1915 1916 /* Initialize power management */ 1917 radeon_pm_init(rdev); 1918 1919 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL; 1920 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024); 1921 1922 rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL; 1923 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024); 1924 1925 r = radeon_uvd_init(rdev); 1926 if (!r) { 1927 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL; 1928 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX], 1929 4096); 1930 } 1931 1932 rdev->ih.ring_obj = NULL; 1933 r600_ih_ring_init(rdev, 64 * 1024); 1934 1935 r = r600_pcie_gart_init(rdev); 1936 if (r) 1937 return r; 1938 1939 rdev->accel_working = true; 1940 r = rv770_startup(rdev); 1941 if (r) { 1942 dev_err(rdev->dev, "disabling GPU acceleration\n"); 1943 r700_cp_fini(rdev); 1944 r600_dma_fini(rdev); 1945 r600_irq_fini(rdev); 1946 radeon_wb_fini(rdev); 1947 radeon_ib_pool_fini(rdev); 1948 radeon_irq_kms_fini(rdev); 1949 rv770_pcie_gart_fini(rdev); 1950 rdev->accel_working = false; 1951 } 1952 1953 return 0; 1954 } 1955 1956 void rv770_fini(struct radeon_device *rdev) 1957 { 1958 radeon_pm_fini(rdev); 1959 r700_cp_fini(rdev); 1960 r600_dma_fini(rdev); 1961 r600_irq_fini(rdev); 1962 radeon_wb_fini(rdev); 1963 radeon_ib_pool_fini(rdev); 1964 radeon_irq_kms_fini(rdev); 1965 uvd_v1_0_fini(rdev); 1966 radeon_uvd_fini(rdev); 1967 rv770_pcie_gart_fini(rdev); 1968 r600_vram_scratch_fini(rdev); 1969 radeon_gem_fini(rdev); 1970 radeon_fence_driver_fini(rdev); 1971 radeon_agp_fini(rdev); 1972 radeon_bo_fini(rdev); 1973 radeon_atombios_fini(rdev); 1974 kfree(rdev->bios); 1975 rdev->bios = NULL; 1976 } 1977 1978 static void rv770_pcie_gen2_enable(struct radeon_device *rdev) 1979 { 1980 #ifndef __NetBSD__ /* XXX radeon pcie */ 1981 u32 link_width_cntl, lanes, speed_cntl, tmp; 1982 u16 link_cntl2; 1983 1984 if (radeon_pcie_gen2 == 0) 1985 return; 1986 1987 if (rdev->flags & RADEON_IS_IGP) 1988 return; 1989 1990 if (!(rdev->flags & RADEON_IS_PCIE)) 1991 return; 1992 1993 /* x2 cards have a special sequence */ 1994 if (ASIC_IS_X2(rdev)) 1995 return; 1996 1997 if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) && 1998 (rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT)) 1999 return; 2000 2001 DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n"); 2002 2003 /* advertise upconfig capability */ 2004 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); 2005 link_width_cntl &= ~LC_UPCONFIGURE_DIS; 2006 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 2007 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); 2008 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) { 2009 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT; 2010 link_width_cntl &= ~(LC_LINK_WIDTH_MASK | 2011 LC_RECONFIG_ARC_MISSING_ESCAPE); 2012 link_width_cntl |= lanes | LC_RECONFIG_NOW | 2013 LC_RENEGOTIATE_EN | LC_UPCONFIGURE_SUPPORT; 2014 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 2015 } else { 2016 link_width_cntl |= LC_UPCONFIGURE_DIS; 2017 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 2018 } 2019 2020 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 2021 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) && 2022 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) { 2023 2024 tmp = RREG32(0x541c); 2025 WREG32(0x541c, tmp | 0x8); 2026 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN); 2027 link_cntl2 = RREG16(0x4088); 2028 link_cntl2 &= ~TARGET_LINK_SPEED_MASK; 2029 link_cntl2 |= 0x2; 2030 WREG16(0x4088, link_cntl2); 2031 WREG32(MM_CFGREGS_CNTL, 0); 2032 2033 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 2034 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN; 2035 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); 2036 2037 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 2038 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT; 2039 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); 2040 2041 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 2042 speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT; 2043 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); 2044 2045 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 2046 speed_cntl |= LC_GEN2_EN_STRAP; 2047 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); 2048 2049 } else { 2050 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); 2051 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */ 2052 if (1) 2053 link_width_cntl |= LC_UPCONFIGURE_DIS; 2054 else 2055 link_width_cntl &= ~LC_UPCONFIGURE_DIS; 2056 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 2057 } 2058 #endif 2059 } 2060
Indexes created Mon Oct 20 16:09:52 GMT 2025