radeon_sumo_dpm.c revision 1.1.2.2
1 /* $NetBSD: radeon_sumo_dpm.c,v 1.1.2.2 2018/09/06 06:56:33 pgoyette Exp $ */ 2 3 /* 4 * Copyright 2012 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 26 #include <sys/cdefs.h> 27 __KERNEL_RCSID(0, "$NetBSD: radeon_sumo_dpm.c,v 1.1.2.2 2018/09/06 06:56:33 pgoyette Exp $"); 28 29 #include "drmP.h" 30 #include "radeon.h" 31 #include "radeon_asic.h" 32 #include "sumod.h" 33 #include "r600_dpm.h" 34 #include "cypress_dpm.h" 35 #include "sumo_dpm.h" 36 #include <linux/seq_file.h> 37 38 #define SUMO_MAX_DEEPSLEEP_DIVIDER_ID 5 39 #define SUMO_MINIMUM_ENGINE_CLOCK 800 40 #define BOOST_DPM_LEVEL 7 41 42 static const u32 sumo_utc[SUMO_PM_NUMBER_OF_TC] = 43 { 44 SUMO_UTC_DFLT_00, 45 SUMO_UTC_DFLT_01, 46 SUMO_UTC_DFLT_02, 47 SUMO_UTC_DFLT_03, 48 SUMO_UTC_DFLT_04, 49 SUMO_UTC_DFLT_05, 50 SUMO_UTC_DFLT_06, 51 SUMO_UTC_DFLT_07, 52 SUMO_UTC_DFLT_08, 53 SUMO_UTC_DFLT_09, 54 SUMO_UTC_DFLT_10, 55 SUMO_UTC_DFLT_11, 56 SUMO_UTC_DFLT_12, 57 SUMO_UTC_DFLT_13, 58 SUMO_UTC_DFLT_14, 59 }; 60 61 static const u32 sumo_dtc[SUMO_PM_NUMBER_OF_TC] = 62 { 63 SUMO_DTC_DFLT_00, 64 SUMO_DTC_DFLT_01, 65 SUMO_DTC_DFLT_02, 66 SUMO_DTC_DFLT_03, 67 SUMO_DTC_DFLT_04, 68 SUMO_DTC_DFLT_05, 69 SUMO_DTC_DFLT_06, 70 SUMO_DTC_DFLT_07, 71 SUMO_DTC_DFLT_08, 72 SUMO_DTC_DFLT_09, 73 SUMO_DTC_DFLT_10, 74 SUMO_DTC_DFLT_11, 75 SUMO_DTC_DFLT_12, 76 SUMO_DTC_DFLT_13, 77 SUMO_DTC_DFLT_14, 78 }; 79 80 static struct sumo_ps *sumo_get_ps(struct radeon_ps *rps) 81 { 82 struct sumo_ps *ps = rps->ps_priv; 83 84 return ps; 85 } 86 87 struct sumo_power_info *sumo_get_pi(struct radeon_device *rdev) 88 { 89 struct sumo_power_info *pi = rdev->pm.dpm.priv; 90 91 return pi; 92 } 93 94 static void sumo_gfx_clockgating_enable(struct radeon_device *rdev, bool enable) 95 { 96 if (enable) 97 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN); 98 else { 99 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN); 100 WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON); 101 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON); 102 RREG32(GB_ADDR_CONFIG); 103 } 104 } 105 106 #define CGCG_CGTT_LOCAL0_MASK 0xE5BFFFFF 107 #define CGCG_CGTT_LOCAL1_MASK 0xEFFF07FF 108 109 static void sumo_mg_clockgating_enable(struct radeon_device *rdev, bool enable) 110 { 111 u32 local0; 112 u32 local1; 113 114 local0 = RREG32(CG_CGTT_LOCAL_0); 115 local1 = RREG32(CG_CGTT_LOCAL_1); 116 117 if (enable) { 118 WREG32(CG_CGTT_LOCAL_0, (0 & CGCG_CGTT_LOCAL0_MASK) | (local0 & ~CGCG_CGTT_LOCAL0_MASK) ); 119 WREG32(CG_CGTT_LOCAL_1, (0 & CGCG_CGTT_LOCAL1_MASK) | (local1 & ~CGCG_CGTT_LOCAL1_MASK) ); 120 } else { 121 WREG32(CG_CGTT_LOCAL_0, (0xFFFFFFFF & CGCG_CGTT_LOCAL0_MASK) | (local0 & ~CGCG_CGTT_LOCAL0_MASK) ); 122 WREG32(CG_CGTT_LOCAL_1, (0xFFFFCFFF & CGCG_CGTT_LOCAL1_MASK) | (local1 & ~CGCG_CGTT_LOCAL1_MASK) ); 123 } 124 } 125 126 static void sumo_program_git(struct radeon_device *rdev) 127 { 128 u32 p, u; 129 u32 xclk = radeon_get_xclk(rdev); 130 131 r600_calculate_u_and_p(SUMO_GICST_DFLT, 132 xclk, 16, &p, &u); 133 134 WREG32_P(CG_GIT, CG_GICST(p), ~CG_GICST_MASK); 135 } 136 137 static void sumo_program_grsd(struct radeon_device *rdev) 138 { 139 u32 p, u; 140 u32 xclk = radeon_get_xclk(rdev); 141 u32 grs = 256 * 25 / 100; 142 143 r600_calculate_u_and_p(1, xclk, 14, &p, &u); 144 145 WREG32(CG_GCOOR, PHC(grs) | SDC(p) | SU(u)); 146 } 147 148 void sumo_gfx_clockgating_initialize(struct radeon_device *rdev) 149 { 150 sumo_program_git(rdev); 151 sumo_program_grsd(rdev); 152 } 153 154 static void sumo_gfx_powergating_initialize(struct radeon_device *rdev) 155 { 156 u32 rcu_pwr_gating_cntl; 157 u32 p, u; 158 u32 p_c, p_p, d_p; 159 u32 r_t, i_t; 160 u32 xclk = radeon_get_xclk(rdev); 161 162 if (rdev->family == CHIP_PALM) { 163 p_c = 4; 164 d_p = 10; 165 r_t = 10; 166 i_t = 4; 167 p_p = 50 + 1000/200 + 6 * 32; 168 } else { 169 p_c = 16; 170 d_p = 50; 171 r_t = 50; 172 i_t = 50; 173 p_p = 113; 174 } 175 176 WREG32(CG_SCRATCH2, 0x01B60A17); 177 178 r600_calculate_u_and_p(SUMO_GFXPOWERGATINGT_DFLT, 179 xclk, 16, &p, &u); 180 181 WREG32_P(CG_PWR_GATING_CNTL, PGP(p) | PGU(u), 182 ~(PGP_MASK | PGU_MASK)); 183 184 r600_calculate_u_and_p(SUMO_VOLTAGEDROPT_DFLT, 185 xclk, 16, &p, &u); 186 187 WREG32_P(CG_CG_VOLTAGE_CNTL, PGP(p) | PGU(u), 188 ~(PGP_MASK | PGU_MASK)); 189 190 if (rdev->family == CHIP_PALM) { 191 WREG32_RCU(RCU_PWR_GATING_SEQ0, 0x10103210); 192 WREG32_RCU(RCU_PWR_GATING_SEQ1, 0x10101010); 193 } else { 194 WREG32_RCU(RCU_PWR_GATING_SEQ0, 0x76543210); 195 WREG32_RCU(RCU_PWR_GATING_SEQ1, 0xFEDCBA98); 196 } 197 198 rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL); 199 rcu_pwr_gating_cntl &= 200 ~(RSVD_MASK | PCV_MASK | PGS_MASK); 201 rcu_pwr_gating_cntl |= PCV(p_c) | PGS(1) | PWR_GATING_EN; 202 if (rdev->family == CHIP_PALM) { 203 rcu_pwr_gating_cntl &= ~PCP_MASK; 204 rcu_pwr_gating_cntl |= PCP(0x77); 205 } 206 WREG32_RCU(RCU_PWR_GATING_CNTL, rcu_pwr_gating_cntl); 207 208 rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_2); 209 rcu_pwr_gating_cntl &= ~(MPPU_MASK | MPPD_MASK); 210 rcu_pwr_gating_cntl |= MPPU(p_p) | MPPD(50); 211 WREG32_RCU(RCU_PWR_GATING_CNTL_2, rcu_pwr_gating_cntl); 212 213 rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_3); 214 rcu_pwr_gating_cntl &= ~(DPPU_MASK | DPPD_MASK); 215 rcu_pwr_gating_cntl |= DPPU(d_p) | DPPD(50); 216 WREG32_RCU(RCU_PWR_GATING_CNTL_3, rcu_pwr_gating_cntl); 217 218 rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_4); 219 rcu_pwr_gating_cntl &= ~(RT_MASK | IT_MASK); 220 rcu_pwr_gating_cntl |= RT(r_t) | IT(i_t); 221 WREG32_RCU(RCU_PWR_GATING_CNTL_4, rcu_pwr_gating_cntl); 222 223 if (rdev->family == CHIP_PALM) 224 WREG32_RCU(RCU_PWR_GATING_CNTL_5, 0xA02); 225 226 sumo_smu_pg_init(rdev); 227 228 rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL); 229 rcu_pwr_gating_cntl &= 230 ~(RSVD_MASK | PCV_MASK | PGS_MASK); 231 rcu_pwr_gating_cntl |= PCV(p_c) | PGS(4) | PWR_GATING_EN; 232 if (rdev->family == CHIP_PALM) { 233 rcu_pwr_gating_cntl &= ~PCP_MASK; 234 rcu_pwr_gating_cntl |= PCP(0x77); 235 } 236 WREG32_RCU(RCU_PWR_GATING_CNTL, rcu_pwr_gating_cntl); 237 238 if (rdev->family == CHIP_PALM) { 239 rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_2); 240 rcu_pwr_gating_cntl &= ~(MPPU_MASK | MPPD_MASK); 241 rcu_pwr_gating_cntl |= MPPU(113) | MPPD(50); 242 WREG32_RCU(RCU_PWR_GATING_CNTL_2, rcu_pwr_gating_cntl); 243 244 rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_3); 245 rcu_pwr_gating_cntl &= ~(DPPU_MASK | DPPD_MASK); 246 rcu_pwr_gating_cntl |= DPPU(16) | DPPD(50); 247 WREG32_RCU(RCU_PWR_GATING_CNTL_3, rcu_pwr_gating_cntl); 248 } 249 250 sumo_smu_pg_init(rdev); 251 252 rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL); 253 rcu_pwr_gating_cntl &= 254 ~(RSVD_MASK | PCV_MASK | PGS_MASK); 255 rcu_pwr_gating_cntl |= PGS(5) | PWR_GATING_EN; 256 257 if (rdev->family == CHIP_PALM) { 258 rcu_pwr_gating_cntl |= PCV(4); 259 rcu_pwr_gating_cntl &= ~PCP_MASK; 260 rcu_pwr_gating_cntl |= PCP(0x77); 261 } else 262 rcu_pwr_gating_cntl |= PCV(11); 263 WREG32_RCU(RCU_PWR_GATING_CNTL, rcu_pwr_gating_cntl); 264 265 if (rdev->family == CHIP_PALM) { 266 rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_2); 267 rcu_pwr_gating_cntl &= ~(MPPU_MASK | MPPD_MASK); 268 rcu_pwr_gating_cntl |= MPPU(113) | MPPD(50); 269 WREG32_RCU(RCU_PWR_GATING_CNTL_2, rcu_pwr_gating_cntl); 270 271 rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_3); 272 rcu_pwr_gating_cntl &= ~(DPPU_MASK | DPPD_MASK); 273 rcu_pwr_gating_cntl |= DPPU(22) | DPPD(50); 274 WREG32_RCU(RCU_PWR_GATING_CNTL_3, rcu_pwr_gating_cntl); 275 } 276 277 sumo_smu_pg_init(rdev); 278 } 279 280 static void sumo_gfx_powergating_enable(struct radeon_device *rdev, bool enable) 281 { 282 if (enable) 283 WREG32_P(CG_PWR_GATING_CNTL, DYN_PWR_DOWN_EN, ~DYN_PWR_DOWN_EN); 284 else { 285 WREG32_P(CG_PWR_GATING_CNTL, 0, ~DYN_PWR_DOWN_EN); 286 RREG32(GB_ADDR_CONFIG); 287 } 288 } 289 290 static int sumo_enable_clock_power_gating(struct radeon_device *rdev) 291 { 292 struct sumo_power_info *pi = sumo_get_pi(rdev); 293 294 if (pi->enable_gfx_clock_gating) 295 sumo_gfx_clockgating_initialize(rdev); 296 if (pi->enable_gfx_power_gating) 297 sumo_gfx_powergating_initialize(rdev); 298 if (pi->enable_mg_clock_gating) 299 sumo_mg_clockgating_enable(rdev, true); 300 if (pi->enable_gfx_clock_gating) 301 sumo_gfx_clockgating_enable(rdev, true); 302 if (pi->enable_gfx_power_gating) 303 sumo_gfx_powergating_enable(rdev, true); 304 305 return 0; 306 } 307 308 static void sumo_disable_clock_power_gating(struct radeon_device *rdev) 309 { 310 struct sumo_power_info *pi = sumo_get_pi(rdev); 311 312 if (pi->enable_gfx_clock_gating) 313 sumo_gfx_clockgating_enable(rdev, false); 314 if (pi->enable_gfx_power_gating) 315 sumo_gfx_powergating_enable(rdev, false); 316 if (pi->enable_mg_clock_gating) 317 sumo_mg_clockgating_enable(rdev, false); 318 } 319 320 static void sumo_calculate_bsp(struct radeon_device *rdev, 321 u32 high_clk) 322 { 323 struct sumo_power_info *pi = sumo_get_pi(rdev); 324 u32 xclk = radeon_get_xclk(rdev); 325 326 pi->pasi = 65535 * 100 / high_clk; 327 pi->asi = 65535 * 100 / high_clk; 328 329 r600_calculate_u_and_p(pi->asi, 330 xclk, 16, &pi->bsp, &pi->bsu); 331 332 r600_calculate_u_and_p(pi->pasi, 333 xclk, 16, &pi->pbsp, &pi->pbsu); 334 335 pi->dsp = BSP(pi->bsp) | BSU(pi->bsu); 336 pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu); 337 } 338 339 static void sumo_init_bsp(struct radeon_device *rdev) 340 { 341 struct sumo_power_info *pi = sumo_get_pi(rdev); 342 343 WREG32(CG_BSP_0, pi->psp); 344 } 345 346 347 static void sumo_program_bsp(struct radeon_device *rdev, 348 struct radeon_ps *rps) 349 { 350 struct sumo_power_info *pi = sumo_get_pi(rdev); 351 struct sumo_ps *ps = sumo_get_ps(rps); 352 u32 i; 353 u32 highest_engine_clock = ps->levels[ps->num_levels - 1].sclk; 354 355 if (ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE) 356 highest_engine_clock = pi->boost_pl.sclk; 357 358 sumo_calculate_bsp(rdev, highest_engine_clock); 359 360 for (i = 0; i < ps->num_levels - 1; i++) 361 WREG32(CG_BSP_0 + (i * 4), pi->dsp); 362 363 WREG32(CG_BSP_0 + (i * 4), pi->psp); 364 365 if (ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE) 366 WREG32(CG_BSP_0 + (BOOST_DPM_LEVEL * 4), pi->psp); 367 } 368 369 static void sumo_write_at(struct radeon_device *rdev, 370 u32 index, u32 value) 371 { 372 if (index == 0) 373 WREG32(CG_AT_0, value); 374 else if (index == 1) 375 WREG32(CG_AT_1, value); 376 else if (index == 2) 377 WREG32(CG_AT_2, value); 378 else if (index == 3) 379 WREG32(CG_AT_3, value); 380 else if (index == 4) 381 WREG32(CG_AT_4, value); 382 else if (index == 5) 383 WREG32(CG_AT_5, value); 384 else if (index == 6) 385 WREG32(CG_AT_6, value); 386 else if (index == 7) 387 WREG32(CG_AT_7, value); 388 } 389 390 static void sumo_program_at(struct radeon_device *rdev, 391 struct radeon_ps *rps) 392 { 393 struct sumo_power_info *pi = sumo_get_pi(rdev); 394 struct sumo_ps *ps = sumo_get_ps(rps); 395 u32 asi; 396 u32 i; 397 u32 m_a; 398 u32 a_t; 399 u32 r[SUMO_MAX_HARDWARE_POWERLEVELS]; 400 u32 l[SUMO_MAX_HARDWARE_POWERLEVELS]; 401 402 r[0] = SUMO_R_DFLT0; 403 r[1] = SUMO_R_DFLT1; 404 r[2] = SUMO_R_DFLT2; 405 r[3] = SUMO_R_DFLT3; 406 r[4] = SUMO_R_DFLT4; 407 408 l[0] = SUMO_L_DFLT0; 409 l[1] = SUMO_L_DFLT1; 410 l[2] = SUMO_L_DFLT2; 411 l[3] = SUMO_L_DFLT3; 412 l[4] = SUMO_L_DFLT4; 413 414 for (i = 0; i < ps->num_levels; i++) { 415 asi = (i == ps->num_levels - 1) ? pi->pasi : pi->asi; 416 417 m_a = asi * ps->levels[i].sclk / 100; 418 419 a_t = CG_R(m_a * r[i] / 100) | CG_L(m_a * l[i] / 100); 420 421 sumo_write_at(rdev, i, a_t); 422 } 423 424 if (ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE) { 425 asi = pi->pasi; 426 427 m_a = asi * pi->boost_pl.sclk / 100; 428 429 a_t = CG_R(m_a * r[ps->num_levels - 1] / 100) | 430 CG_L(m_a * l[ps->num_levels - 1] / 100); 431 432 sumo_write_at(rdev, BOOST_DPM_LEVEL, a_t); 433 } 434 } 435 436 static void sumo_program_tp(struct radeon_device *rdev) 437 { 438 int i; 439 enum r600_td td = R600_TD_DFLT; 440 441 for (i = 0; i < SUMO_PM_NUMBER_OF_TC; i++) { 442 WREG32_P(CG_FFCT_0 + (i * 4), UTC_0(sumo_utc[i]), ~UTC_0_MASK); 443 WREG32_P(CG_FFCT_0 + (i * 4), DTC_0(sumo_dtc[i]), ~DTC_0_MASK); 444 } 445 446 if (td == R600_TD_AUTO) 447 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL); 448 else 449 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL); 450 451 if (td == R600_TD_UP) 452 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE); 453 454 if (td == R600_TD_DOWN) 455 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE); 456 } 457 458 void sumo_program_vc(struct radeon_device *rdev, u32 vrc) 459 { 460 WREG32(CG_FTV, vrc); 461 } 462 463 void sumo_clear_vc(struct radeon_device *rdev) 464 { 465 WREG32(CG_FTV, 0); 466 } 467 468 void sumo_program_sstp(struct radeon_device *rdev) 469 { 470 u32 p, u; 471 u32 xclk = radeon_get_xclk(rdev); 472 473 r600_calculate_u_and_p(SUMO_SST_DFLT, 474 xclk, 16, &p, &u); 475 476 WREG32(CG_SSP, SSTU(u) | SST(p)); 477 } 478 479 static void sumo_set_divider_value(struct radeon_device *rdev, 480 u32 index, u32 divider) 481 { 482 u32 reg_index = index / 4; 483 u32 field_index = index % 4; 484 485 if (field_index == 0) 486 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4), 487 SCLK_FSTATE_0_DIV(divider), ~SCLK_FSTATE_0_DIV_MASK); 488 else if (field_index == 1) 489 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4), 490 SCLK_FSTATE_1_DIV(divider), ~SCLK_FSTATE_1_DIV_MASK); 491 else if (field_index == 2) 492 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4), 493 SCLK_FSTATE_2_DIV(divider), ~SCLK_FSTATE_2_DIV_MASK); 494 else if (field_index == 3) 495 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4), 496 SCLK_FSTATE_3_DIV(divider), ~SCLK_FSTATE_3_DIV_MASK); 497 } 498 499 static void sumo_set_ds_dividers(struct radeon_device *rdev, 500 u32 index, u32 divider) 501 { 502 struct sumo_power_info *pi = sumo_get_pi(rdev); 503 504 if (pi->enable_sclk_ds) { 505 u32 dpm_ctrl = RREG32(CG_SCLK_DPM_CTRL_6); 506 507 dpm_ctrl &= ~(0x7 << (index * 3)); 508 dpm_ctrl |= (divider << (index * 3)); 509 WREG32(CG_SCLK_DPM_CTRL_6, dpm_ctrl); 510 } 511 } 512 513 static void sumo_set_ss_dividers(struct radeon_device *rdev, 514 u32 index, u32 divider) 515 { 516 struct sumo_power_info *pi = sumo_get_pi(rdev); 517 518 if (pi->enable_sclk_ds) { 519 u32 dpm_ctrl = RREG32(CG_SCLK_DPM_CTRL_11); 520 521 dpm_ctrl &= ~(0x7 << (index * 3)); 522 dpm_ctrl |= (divider << (index * 3)); 523 WREG32(CG_SCLK_DPM_CTRL_11, dpm_ctrl); 524 } 525 } 526 527 static void sumo_set_vid(struct radeon_device *rdev, u32 index, u32 vid) 528 { 529 u32 voltage_cntl = RREG32(CG_DPM_VOLTAGE_CNTL); 530 531 voltage_cntl &= ~(DPM_STATE0_LEVEL_MASK << (index * 2)); 532 voltage_cntl |= (vid << (DPM_STATE0_LEVEL_SHIFT + index * 2)); 533 WREG32(CG_DPM_VOLTAGE_CNTL, voltage_cntl); 534 } 535 536 static void sumo_set_allos_gnb_slow(struct radeon_device *rdev, u32 index, u32 gnb_slow) 537 { 538 struct sumo_power_info *pi = sumo_get_pi(rdev); 539 u32 temp = gnb_slow; 540 u32 cg_sclk_dpm_ctrl_3; 541 542 if (pi->driver_nbps_policy_disable) 543 temp = 1; 544 545 cg_sclk_dpm_ctrl_3 = RREG32(CG_SCLK_DPM_CTRL_3); 546 cg_sclk_dpm_ctrl_3 &= ~(GNB_SLOW_FSTATE_0_MASK << index); 547 cg_sclk_dpm_ctrl_3 |= (temp << (GNB_SLOW_FSTATE_0_SHIFT + index)); 548 549 WREG32(CG_SCLK_DPM_CTRL_3, cg_sclk_dpm_ctrl_3); 550 } 551 552 static void sumo_program_power_level(struct radeon_device *rdev, 553 struct sumo_pl *pl, u32 index) 554 { 555 struct sumo_power_info *pi = sumo_get_pi(rdev); 556 int ret; 557 struct atom_clock_dividers dividers; 558 u32 ds_en = RREG32(DEEP_SLEEP_CNTL) & ENABLE_DS; 559 560 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 561 pl->sclk, false, ÷rs); 562 if (ret) 563 return; 564 565 sumo_set_divider_value(rdev, index, dividers.post_div); 566 567 sumo_set_vid(rdev, index, pl->vddc_index); 568 569 if (pl->ss_divider_index == 0 || pl->ds_divider_index == 0) { 570 if (ds_en) 571 WREG32_P(DEEP_SLEEP_CNTL, 0, ~ENABLE_DS); 572 } else { 573 sumo_set_ss_dividers(rdev, index, pl->ss_divider_index); 574 sumo_set_ds_dividers(rdev, index, pl->ds_divider_index); 575 576 if (!ds_en) 577 WREG32_P(DEEP_SLEEP_CNTL, ENABLE_DS, ~ENABLE_DS); 578 } 579 580 sumo_set_allos_gnb_slow(rdev, index, pl->allow_gnb_slow); 581 582 if (pi->enable_boost) 583 sumo_set_tdp_limit(rdev, index, pl->sclk_dpm_tdp_limit); 584 } 585 586 static void sumo_power_level_enable(struct radeon_device *rdev, u32 index, bool enable) 587 { 588 u32 reg_index = index / 4; 589 u32 field_index = index % 4; 590 591 if (field_index == 0) 592 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4), 593 enable ? SCLK_FSTATE_0_VLD : 0, ~SCLK_FSTATE_0_VLD); 594 else if (field_index == 1) 595 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4), 596 enable ? SCLK_FSTATE_1_VLD : 0, ~SCLK_FSTATE_1_VLD); 597 else if (field_index == 2) 598 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4), 599 enable ? SCLK_FSTATE_2_VLD : 0, ~SCLK_FSTATE_2_VLD); 600 else if (field_index == 3) 601 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4), 602 enable ? SCLK_FSTATE_3_VLD : 0, ~SCLK_FSTATE_3_VLD); 603 } 604 605 static bool sumo_dpm_enabled(struct radeon_device *rdev) 606 { 607 if (RREG32(CG_SCLK_DPM_CTRL_3) & DPM_SCLK_ENABLE) 608 return true; 609 else 610 return false; 611 } 612 613 static void sumo_start_dpm(struct radeon_device *rdev) 614 { 615 WREG32_P(CG_SCLK_DPM_CTRL_3, DPM_SCLK_ENABLE, ~DPM_SCLK_ENABLE); 616 } 617 618 static void sumo_stop_dpm(struct radeon_device *rdev) 619 { 620 WREG32_P(CG_SCLK_DPM_CTRL_3, 0, ~DPM_SCLK_ENABLE); 621 } 622 623 static void sumo_set_forced_mode(struct radeon_device *rdev, bool enable) 624 { 625 if (enable) 626 WREG32_P(CG_SCLK_DPM_CTRL_3, FORCE_SCLK_STATE_EN, ~FORCE_SCLK_STATE_EN); 627 else 628 WREG32_P(CG_SCLK_DPM_CTRL_3, 0, ~FORCE_SCLK_STATE_EN); 629 } 630 631 static void sumo_set_forced_mode_enabled(struct radeon_device *rdev) 632 { 633 int i; 634 635 sumo_set_forced_mode(rdev, true); 636 for (i = 0; i < rdev->usec_timeout; i++) { 637 if (RREG32(CG_SCLK_STATUS) & SCLK_OVERCLK_DETECT) 638 break; 639 udelay(1); 640 } 641 } 642 643 static void sumo_wait_for_level_0(struct radeon_device *rdev) 644 { 645 int i; 646 647 for (i = 0; i < rdev->usec_timeout; i++) { 648 if ((RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_SCLK_INDEX_MASK) == 0) 649 break; 650 udelay(1); 651 } 652 for (i = 0; i < rdev->usec_timeout; i++) { 653 if ((RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_INDEX_MASK) == 0) 654 break; 655 udelay(1); 656 } 657 } 658 659 static void sumo_set_forced_mode_disabled(struct radeon_device *rdev) 660 { 661 sumo_set_forced_mode(rdev, false); 662 } 663 664 static void sumo_enable_power_level_0(struct radeon_device *rdev) 665 { 666 sumo_power_level_enable(rdev, 0, true); 667 } 668 669 static void sumo_patch_boost_state(struct radeon_device *rdev, 670 struct radeon_ps *rps) 671 { 672 struct sumo_power_info *pi = sumo_get_pi(rdev); 673 struct sumo_ps *new_ps = sumo_get_ps(rps); 674 675 if (new_ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE) { 676 pi->boost_pl = new_ps->levels[new_ps->num_levels - 1]; 677 pi->boost_pl.sclk = pi->sys_info.boost_sclk; 678 pi->boost_pl.vddc_index = pi->sys_info.boost_vid_2bit; 679 pi->boost_pl.sclk_dpm_tdp_limit = pi->sys_info.sclk_dpm_tdp_limit_boost; 680 } 681 } 682 683 static void sumo_pre_notify_alt_vddnb_change(struct radeon_device *rdev, 684 struct radeon_ps *new_rps, 685 struct radeon_ps *old_rps) 686 { 687 struct sumo_ps *new_ps = sumo_get_ps(new_rps); 688 struct sumo_ps *old_ps = sumo_get_ps(old_rps); 689 u32 nbps1_old = 0; 690 u32 nbps1_new = 0; 691 692 if (old_ps != NULL) 693 nbps1_old = (old_ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE) ? 1 : 0; 694 695 nbps1_new = (new_ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE) ? 1 : 0; 696 697 if (nbps1_old == 1 && nbps1_new == 0) 698 sumo_smu_notify_alt_vddnb_change(rdev, 0, 0); 699 } 700 701 static void sumo_post_notify_alt_vddnb_change(struct radeon_device *rdev, 702 struct radeon_ps *new_rps, 703 struct radeon_ps *old_rps) 704 { 705 struct sumo_ps *new_ps = sumo_get_ps(new_rps); 706 struct sumo_ps *old_ps = sumo_get_ps(old_rps); 707 u32 nbps1_old = 0; 708 u32 nbps1_new = 0; 709 710 if (old_ps != NULL) 711 nbps1_old = (old_ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE)? 1 : 0; 712 713 nbps1_new = (new_ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE)? 1 : 0; 714 715 if (nbps1_old == 0 && nbps1_new == 1) 716 sumo_smu_notify_alt_vddnb_change(rdev, 1, 1); 717 } 718 719 static void sumo_enable_boost(struct radeon_device *rdev, 720 struct radeon_ps *rps, 721 bool enable) 722 { 723 struct sumo_ps *new_ps = sumo_get_ps(rps); 724 725 if (enable) { 726 if (new_ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE) 727 sumo_boost_state_enable(rdev, true); 728 } else 729 sumo_boost_state_enable(rdev, false); 730 } 731 732 static void sumo_set_forced_level(struct radeon_device *rdev, u32 index) 733 { 734 WREG32_P(CG_SCLK_DPM_CTRL_3, FORCE_SCLK_STATE(index), ~FORCE_SCLK_STATE_MASK); 735 } 736 737 static void sumo_set_forced_level_0(struct radeon_device *rdev) 738 { 739 sumo_set_forced_level(rdev, 0); 740 } 741 742 static void sumo_program_wl(struct radeon_device *rdev, 743 struct radeon_ps *rps) 744 { 745 struct sumo_ps *new_ps = sumo_get_ps(rps); 746 u32 dpm_ctrl4 = RREG32(CG_SCLK_DPM_CTRL_4); 747 748 dpm_ctrl4 &= 0xFFFFFF00; 749 dpm_ctrl4 |= (1 << (new_ps->num_levels - 1)); 750 751 if (new_ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE) 752 dpm_ctrl4 |= (1 << BOOST_DPM_LEVEL); 753 754 WREG32(CG_SCLK_DPM_CTRL_4, dpm_ctrl4); 755 } 756 757 static void sumo_program_power_levels_0_to_n(struct radeon_device *rdev, 758 struct radeon_ps *new_rps, 759 struct radeon_ps *old_rps) 760 { 761 struct sumo_power_info *pi = sumo_get_pi(rdev); 762 struct sumo_ps *new_ps = sumo_get_ps(new_rps); 763 struct sumo_ps *old_ps = sumo_get_ps(old_rps); 764 u32 i; 765 u32 n_current_state_levels = (old_ps == NULL) ? 1 : old_ps->num_levels; 766 767 for (i = 0; i < new_ps->num_levels; i++) { 768 sumo_program_power_level(rdev, &new_ps->levels[i], i); 769 sumo_power_level_enable(rdev, i, true); 770 } 771 772 for (i = new_ps->num_levels; i < n_current_state_levels; i++) 773 sumo_power_level_enable(rdev, i, false); 774 775 if (new_ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE) 776 sumo_program_power_level(rdev, &pi->boost_pl, BOOST_DPM_LEVEL); 777 } 778 779 static void sumo_enable_acpi_pm(struct radeon_device *rdev) 780 { 781 WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN); 782 } 783 784 static void sumo_program_power_level_enter_state(struct radeon_device *rdev) 785 { 786 WREG32_P(CG_SCLK_DPM_CTRL_5, SCLK_FSTATE_BOOTUP(0), ~SCLK_FSTATE_BOOTUP_MASK); 787 } 788 789 static void sumo_program_acpi_power_level(struct radeon_device *rdev) 790 { 791 struct sumo_power_info *pi = sumo_get_pi(rdev); 792 struct atom_clock_dividers dividers; 793 int ret; 794 795 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 796 pi->acpi_pl.sclk, 797 false, ÷rs); 798 if (ret) 799 return; 800 801 WREG32_P(CG_ACPI_CNTL, SCLK_ACPI_DIV(dividers.post_div), ~SCLK_ACPI_DIV_MASK); 802 WREG32_P(CG_ACPI_VOLTAGE_CNTL, 0, ~ACPI_VOLTAGE_EN); 803 } 804 805 static void sumo_program_bootup_state(struct radeon_device *rdev) 806 { 807 struct sumo_power_info *pi = sumo_get_pi(rdev); 808 u32 dpm_ctrl4 = RREG32(CG_SCLK_DPM_CTRL_4); 809 u32 i; 810 811 sumo_program_power_level(rdev, &pi->boot_pl, 0); 812 813 dpm_ctrl4 &= 0xFFFFFF00; 814 WREG32(CG_SCLK_DPM_CTRL_4, dpm_ctrl4); 815 816 for (i = 1; i < 8; i++) 817 sumo_power_level_enable(rdev, i, false); 818 } 819 820 static void sumo_setup_uvd_clocks(struct radeon_device *rdev, 821 struct radeon_ps *new_rps, 822 struct radeon_ps *old_rps) 823 { 824 struct sumo_power_info *pi = sumo_get_pi(rdev); 825 826 if (pi->enable_gfx_power_gating) { 827 sumo_gfx_powergating_enable(rdev, false); 828 } 829 830 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); 831 832 if (pi->enable_gfx_power_gating) { 833 if (!pi->disable_gfx_power_gating_in_uvd || 834 !r600_is_uvd_state(new_rps->class, new_rps->class2)) 835 sumo_gfx_powergating_enable(rdev, true); 836 } 837 } 838 839 static void sumo_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev, 840 struct radeon_ps *new_rps, 841 struct radeon_ps *old_rps) 842 { 843 struct sumo_ps *new_ps = sumo_get_ps(new_rps); 844 struct sumo_ps *current_ps = sumo_get_ps(old_rps); 845 846 if ((new_rps->vclk == old_rps->vclk) && 847 (new_rps->dclk == old_rps->dclk)) 848 return; 849 850 if (new_ps->levels[new_ps->num_levels - 1].sclk >= 851 current_ps->levels[current_ps->num_levels - 1].sclk) 852 return; 853 854 sumo_setup_uvd_clocks(rdev, new_rps, old_rps); 855 } 856 857 static void sumo_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev, 858 struct radeon_ps *new_rps, 859 struct radeon_ps *old_rps) 860 { 861 struct sumo_ps *new_ps = sumo_get_ps(new_rps); 862 struct sumo_ps *current_ps = sumo_get_ps(old_rps); 863 864 if ((new_rps->vclk == old_rps->vclk) && 865 (new_rps->dclk == old_rps->dclk)) 866 return; 867 868 if (new_ps->levels[new_ps->num_levels - 1].sclk < 869 current_ps->levels[current_ps->num_levels - 1].sclk) 870 return; 871 872 sumo_setup_uvd_clocks(rdev, new_rps, old_rps); 873 } 874 875 void sumo_take_smu_control(struct radeon_device *rdev, bool enable) 876 { 877 /* This bit selects who handles display phy powergating. 878 * Clear the bit to let atom handle it. 879 * Set it to let the driver handle it. 880 * For now we just let atom handle it. 881 */ 882 #if 0 883 u32 v = RREG32(DOUT_SCRATCH3); 884 885 if (enable) 886 v |= 0x4; 887 else 888 v &= 0xFFFFFFFB; 889 890 WREG32(DOUT_SCRATCH3, v); 891 #endif 892 } 893 894 static void sumo_enable_sclk_ds(struct radeon_device *rdev, bool enable) 895 { 896 if (enable) { 897 u32 deep_sleep_cntl = RREG32(DEEP_SLEEP_CNTL); 898 u32 deep_sleep_cntl2 = RREG32(DEEP_SLEEP_CNTL2); 899 u32 t = 1; 900 901 deep_sleep_cntl &= ~R_DIS; 902 deep_sleep_cntl &= ~HS_MASK; 903 deep_sleep_cntl |= HS(t > 4095 ? 4095 : t); 904 905 deep_sleep_cntl2 |= LB_UFP_EN; 906 deep_sleep_cntl2 &= INOUT_C_MASK; 907 deep_sleep_cntl2 |= INOUT_C(0xf); 908 909 WREG32(DEEP_SLEEP_CNTL2, deep_sleep_cntl2); 910 WREG32(DEEP_SLEEP_CNTL, deep_sleep_cntl); 911 } else 912 WREG32_P(DEEP_SLEEP_CNTL, 0, ~ENABLE_DS); 913 } 914 915 static void sumo_program_bootup_at(struct radeon_device *rdev) 916 { 917 WREG32_P(CG_AT_0, CG_R(0xffff), ~CG_R_MASK); 918 WREG32_P(CG_AT_0, CG_L(0), ~CG_L_MASK); 919 } 920 921 static void sumo_reset_am(struct radeon_device *rdev) 922 { 923 WREG32_P(SCLK_PWRMGT_CNTL, FIR_RESET, ~FIR_RESET); 924 } 925 926 static void sumo_start_am(struct radeon_device *rdev) 927 { 928 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_RESET); 929 } 930 931 static void sumo_program_ttp(struct radeon_device *rdev) 932 { 933 u32 xclk = radeon_get_xclk(rdev); 934 u32 p, u; 935 u32 cg_sclk_dpm_ctrl_5 = RREG32(CG_SCLK_DPM_CTRL_5); 936 937 r600_calculate_u_and_p(1000, 938 xclk, 16, &p, &u); 939 940 cg_sclk_dpm_ctrl_5 &= ~(TT_TP_MASK | TT_TU_MASK); 941 cg_sclk_dpm_ctrl_5 |= TT_TP(p) | TT_TU(u); 942 943 WREG32(CG_SCLK_DPM_CTRL_5, cg_sclk_dpm_ctrl_5); 944 } 945 946 static void sumo_program_ttt(struct radeon_device *rdev) 947 { 948 u32 cg_sclk_dpm_ctrl_3 = RREG32(CG_SCLK_DPM_CTRL_3); 949 struct sumo_power_info *pi = sumo_get_pi(rdev); 950 951 cg_sclk_dpm_ctrl_3 &= ~(GNB_TT_MASK | GNB_THERMTHRO_MASK); 952 cg_sclk_dpm_ctrl_3 |= GNB_TT(pi->thermal_auto_throttling + 49); 953 954 WREG32(CG_SCLK_DPM_CTRL_3, cg_sclk_dpm_ctrl_3); 955 } 956 957 958 static void sumo_enable_voltage_scaling(struct radeon_device *rdev, bool enable) 959 { 960 if (enable) { 961 WREG32_P(CG_DPM_VOLTAGE_CNTL, DPM_VOLTAGE_EN, ~DPM_VOLTAGE_EN); 962 WREG32_P(CG_CG_VOLTAGE_CNTL, 0, ~CG_VOLTAGE_EN); 963 } else { 964 WREG32_P(CG_CG_VOLTAGE_CNTL, CG_VOLTAGE_EN, ~CG_VOLTAGE_EN); 965 WREG32_P(CG_DPM_VOLTAGE_CNTL, 0, ~DPM_VOLTAGE_EN); 966 } 967 } 968 969 static void sumo_override_cnb_thermal_events(struct radeon_device *rdev) 970 { 971 WREG32_P(CG_SCLK_DPM_CTRL_3, CNB_THERMTHRO_MASK_SCLK, 972 ~CNB_THERMTHRO_MASK_SCLK); 973 } 974 975 static void sumo_program_dc_hto(struct radeon_device *rdev) 976 { 977 u32 cg_sclk_dpm_ctrl_4 = RREG32(CG_SCLK_DPM_CTRL_4); 978 u32 p, u; 979 u32 xclk = radeon_get_xclk(rdev); 980 981 r600_calculate_u_and_p(100000, 982 xclk, 14, &p, &u); 983 984 cg_sclk_dpm_ctrl_4 &= ~(DC_HDC_MASK | DC_HU_MASK); 985 cg_sclk_dpm_ctrl_4 |= DC_HDC(p) | DC_HU(u); 986 987 WREG32(CG_SCLK_DPM_CTRL_4, cg_sclk_dpm_ctrl_4); 988 } 989 990 static void sumo_force_nbp_state(struct radeon_device *rdev, 991 struct radeon_ps *rps) 992 { 993 struct sumo_power_info *pi = sumo_get_pi(rdev); 994 struct sumo_ps *new_ps = sumo_get_ps(rps); 995 996 if (!pi->driver_nbps_policy_disable) { 997 if (new_ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE) 998 WREG32_P(CG_SCLK_DPM_CTRL_3, FORCE_NB_PSTATE_1, ~FORCE_NB_PSTATE_1); 999 else 1000 WREG32_P(CG_SCLK_DPM_CTRL_3, 0, ~FORCE_NB_PSTATE_1); 1001 } 1002 } 1003 1004 u32 sumo_get_sleep_divider_from_id(u32 id) 1005 { 1006 return 1 << id; 1007 } 1008 1009 u32 sumo_get_sleep_divider_id_from_clock(struct radeon_device *rdev, 1010 u32 sclk, 1011 u32 min_sclk_in_sr) 1012 { 1013 struct sumo_power_info *pi = sumo_get_pi(rdev); 1014 u32 i; 1015 u32 temp; 1016 u32 vmin = (min_sclk_in_sr > SUMO_MINIMUM_ENGINE_CLOCK) ? 1017 min_sclk_in_sr : SUMO_MINIMUM_ENGINE_CLOCK; 1018 1019 if (sclk < vmin) 1020 return 0; 1021 1022 if (!pi->enable_sclk_ds) 1023 return 0; 1024 1025 for (i = SUMO_MAX_DEEPSLEEP_DIVIDER_ID; ; i--) { 1026 temp = sclk / sumo_get_sleep_divider_from_id(i); 1027 1028 if (temp >= vmin || i == 0) 1029 break; 1030 } 1031 return i; 1032 } 1033 1034 static u32 sumo_get_valid_engine_clock(struct radeon_device *rdev, 1035 u32 lower_limit) 1036 { 1037 struct sumo_power_info *pi = sumo_get_pi(rdev); 1038 u32 i; 1039 1040 for (i = 0; i < pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries; i++) { 1041 if (pi->sys_info.sclk_voltage_mapping_table.entries[i].sclk_frequency >= lower_limit) 1042 return pi->sys_info.sclk_voltage_mapping_table.entries[i].sclk_frequency; 1043 } 1044 1045 return pi->sys_info.sclk_voltage_mapping_table.entries[pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries - 1].sclk_frequency; 1046 } 1047 1048 static void sumo_patch_thermal_state(struct radeon_device *rdev, 1049 struct sumo_ps *ps, 1050 struct sumo_ps *current_ps) 1051 { 1052 struct sumo_power_info *pi = sumo_get_pi(rdev); 1053 u32 sclk_in_sr = pi->sys_info.min_sclk; /* ??? */ 1054 u32 current_vddc; 1055 u32 current_sclk; 1056 u32 current_index = 0; 1057 1058 if (current_ps) { 1059 current_vddc = current_ps->levels[current_index].vddc_index; 1060 current_sclk = current_ps->levels[current_index].sclk; 1061 } else { 1062 current_vddc = pi->boot_pl.vddc_index; 1063 current_sclk = pi->boot_pl.sclk; 1064 } 1065 1066 ps->levels[0].vddc_index = current_vddc; 1067 1068 if (ps->levels[0].sclk > current_sclk) 1069 ps->levels[0].sclk = current_sclk; 1070 1071 ps->levels[0].ss_divider_index = 1072 sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[0].sclk, sclk_in_sr); 1073 1074 ps->levels[0].ds_divider_index = 1075 sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[0].sclk, SUMO_MINIMUM_ENGINE_CLOCK); 1076 1077 if (ps->levels[0].ds_divider_index > ps->levels[0].ss_divider_index + 1) 1078 ps->levels[0].ds_divider_index = ps->levels[0].ss_divider_index + 1; 1079 1080 if (ps->levels[0].ss_divider_index == ps->levels[0].ds_divider_index) { 1081 if (ps->levels[0].ss_divider_index > 1) 1082 ps->levels[0].ss_divider_index = ps->levels[0].ss_divider_index - 1; 1083 } 1084 1085 if (ps->levels[0].ss_divider_index == 0) 1086 ps->levels[0].ds_divider_index = 0; 1087 1088 if (ps->levels[0].ds_divider_index == 0) 1089 ps->levels[0].ss_divider_index = 0; 1090 } 1091 1092 static void sumo_apply_state_adjust_rules(struct radeon_device *rdev, 1093 struct radeon_ps *new_rps, 1094 struct radeon_ps *old_rps) 1095 { 1096 struct sumo_ps *ps = sumo_get_ps(new_rps); 1097 struct sumo_ps *current_ps = sumo_get_ps(old_rps); 1098 struct sumo_power_info *pi = sumo_get_pi(rdev); 1099 u32 min_voltage = 0; /* ??? */ 1100 u32 min_sclk = pi->sys_info.min_sclk; /* XXX check against disp reqs */ 1101 u32 sclk_in_sr = pi->sys_info.min_sclk; /* ??? */ 1102 u32 i; 1103 1104 if (new_rps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL) 1105 return sumo_patch_thermal_state(rdev, ps, current_ps); 1106 1107 if (pi->enable_boost) { 1108 if (new_rps->class & ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) 1109 ps->flags |= SUMO_POWERSTATE_FLAGS_BOOST_STATE; 1110 } 1111 1112 if ((new_rps->class & ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) || 1113 (new_rps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE) || 1114 (new_rps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)) 1115 ps->flags |= SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE; 1116 1117 for (i = 0; i < ps->num_levels; i++) { 1118 if (ps->levels[i].vddc_index < min_voltage) 1119 ps->levels[i].vddc_index = min_voltage; 1120 1121 if (ps->levels[i].sclk < min_sclk) 1122 ps->levels[i].sclk = 1123 sumo_get_valid_engine_clock(rdev, min_sclk); 1124 1125 ps->levels[i].ss_divider_index = 1126 sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[i].sclk, sclk_in_sr); 1127 1128 ps->levels[i].ds_divider_index = 1129 sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[i].sclk, SUMO_MINIMUM_ENGINE_CLOCK); 1130 1131 if (ps->levels[i].ds_divider_index > ps->levels[i].ss_divider_index + 1) 1132 ps->levels[i].ds_divider_index = ps->levels[i].ss_divider_index + 1; 1133 1134 if (ps->levels[i].ss_divider_index == ps->levels[i].ds_divider_index) { 1135 if (ps->levels[i].ss_divider_index > 1) 1136 ps->levels[i].ss_divider_index = ps->levels[i].ss_divider_index - 1; 1137 } 1138 1139 if (ps->levels[i].ss_divider_index == 0) 1140 ps->levels[i].ds_divider_index = 0; 1141 1142 if (ps->levels[i].ds_divider_index == 0) 1143 ps->levels[i].ss_divider_index = 0; 1144 1145 if (ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE) 1146 ps->levels[i].allow_gnb_slow = 1; 1147 else if ((new_rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) || 1148 (new_rps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)) 1149 ps->levels[i].allow_gnb_slow = 0; 1150 else if (i == ps->num_levels - 1) 1151 ps->levels[i].allow_gnb_slow = 0; 1152 else 1153 ps->levels[i].allow_gnb_slow = 1; 1154 } 1155 } 1156 1157 static void sumo_cleanup_asic(struct radeon_device *rdev) 1158 { 1159 sumo_take_smu_control(rdev, false); 1160 } 1161 1162 static int sumo_set_thermal_temperature_range(struct radeon_device *rdev, 1163 int min_temp, int max_temp) 1164 { 1165 int low_temp = 0 * 1000; 1166 int high_temp = 255 * 1000; 1167 1168 if (low_temp < min_temp) 1169 low_temp = min_temp; 1170 if (high_temp > max_temp) 1171 high_temp = max_temp; 1172 if (high_temp < low_temp) { 1173 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp); 1174 return -EINVAL; 1175 } 1176 1177 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(49 + (high_temp / 1000)), ~DIG_THERM_INTH_MASK); 1178 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(49 + (low_temp / 1000)), ~DIG_THERM_INTL_MASK); 1179 1180 rdev->pm.dpm.thermal.min_temp = low_temp; 1181 rdev->pm.dpm.thermal.max_temp = high_temp; 1182 1183 return 0; 1184 } 1185 1186 static void sumo_update_current_ps(struct radeon_device *rdev, 1187 struct radeon_ps *rps) 1188 { 1189 struct sumo_ps *new_ps = sumo_get_ps(rps); 1190 struct sumo_power_info *pi = sumo_get_pi(rdev); 1191 1192 pi->current_rps = *rps; 1193 pi->current_ps = *new_ps; 1194 pi->current_rps.ps_priv = &pi->current_ps; 1195 } 1196 1197 static void sumo_update_requested_ps(struct radeon_device *rdev, 1198 struct radeon_ps *rps) 1199 { 1200 struct sumo_ps *new_ps = sumo_get_ps(rps); 1201 struct sumo_power_info *pi = sumo_get_pi(rdev); 1202 1203 pi->requested_rps = *rps; 1204 pi->requested_ps = *new_ps; 1205 pi->requested_rps.ps_priv = &pi->requested_ps; 1206 } 1207 1208 int sumo_dpm_enable(struct radeon_device *rdev) 1209 { 1210 struct sumo_power_info *pi = sumo_get_pi(rdev); 1211 1212 if (sumo_dpm_enabled(rdev)) 1213 return -EINVAL; 1214 1215 sumo_program_bootup_state(rdev); 1216 sumo_init_bsp(rdev); 1217 sumo_reset_am(rdev); 1218 sumo_program_tp(rdev); 1219 sumo_program_bootup_at(rdev); 1220 sumo_start_am(rdev); 1221 if (pi->enable_auto_thermal_throttling) { 1222 sumo_program_ttp(rdev); 1223 sumo_program_ttt(rdev); 1224 } 1225 sumo_program_dc_hto(rdev); 1226 sumo_program_power_level_enter_state(rdev); 1227 sumo_enable_voltage_scaling(rdev, true); 1228 sumo_program_sstp(rdev); 1229 sumo_program_vc(rdev, SUMO_VRC_DFLT); 1230 sumo_override_cnb_thermal_events(rdev); 1231 sumo_start_dpm(rdev); 1232 sumo_wait_for_level_0(rdev); 1233 if (pi->enable_sclk_ds) 1234 sumo_enable_sclk_ds(rdev, true); 1235 if (pi->enable_boost) 1236 sumo_enable_boost_timer(rdev); 1237 1238 sumo_update_current_ps(rdev, rdev->pm.dpm.boot_ps); 1239 1240 return 0; 1241 } 1242 1243 int sumo_dpm_late_enable(struct radeon_device *rdev) 1244 { 1245 int ret; 1246 1247 ret = sumo_enable_clock_power_gating(rdev); 1248 if (ret) 1249 return ret; 1250 1251 if (rdev->irq.installed && 1252 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) { 1253 ret = sumo_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); 1254 if (ret) 1255 return ret; 1256 rdev->irq.dpm_thermal = true; 1257 radeon_irq_set(rdev); 1258 } 1259 1260 return 0; 1261 } 1262 1263 void sumo_dpm_disable(struct radeon_device *rdev) 1264 { 1265 struct sumo_power_info *pi = sumo_get_pi(rdev); 1266 1267 if (!sumo_dpm_enabled(rdev)) 1268 return; 1269 sumo_disable_clock_power_gating(rdev); 1270 if (pi->enable_sclk_ds) 1271 sumo_enable_sclk_ds(rdev, false); 1272 sumo_clear_vc(rdev); 1273 sumo_wait_for_level_0(rdev); 1274 sumo_stop_dpm(rdev); 1275 sumo_enable_voltage_scaling(rdev, false); 1276 1277 if (rdev->irq.installed && 1278 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) { 1279 rdev->irq.dpm_thermal = false; 1280 radeon_irq_set(rdev); 1281 } 1282 1283 sumo_update_current_ps(rdev, rdev->pm.dpm.boot_ps); 1284 } 1285 1286 int sumo_dpm_pre_set_power_state(struct radeon_device *rdev) 1287 { 1288 struct sumo_power_info *pi = sumo_get_pi(rdev); 1289 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps; 1290 struct radeon_ps *new_ps = &requested_ps; 1291 1292 sumo_update_requested_ps(rdev, new_ps); 1293 1294 if (pi->enable_dynamic_patch_ps) 1295 sumo_apply_state_adjust_rules(rdev, 1296 &pi->requested_rps, 1297 &pi->current_rps); 1298 1299 return 0; 1300 } 1301 1302 int sumo_dpm_set_power_state(struct radeon_device *rdev) 1303 { 1304 struct sumo_power_info *pi = sumo_get_pi(rdev); 1305 struct radeon_ps *new_ps = &pi->requested_rps; 1306 struct radeon_ps *old_ps = &pi->current_rps; 1307 1308 if (pi->enable_dpm) 1309 sumo_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps); 1310 if (pi->enable_boost) { 1311 sumo_enable_boost(rdev, new_ps, false); 1312 sumo_patch_boost_state(rdev, new_ps); 1313 } 1314 if (pi->enable_dpm) { 1315 sumo_pre_notify_alt_vddnb_change(rdev, new_ps, old_ps); 1316 sumo_enable_power_level_0(rdev); 1317 sumo_set_forced_level_0(rdev); 1318 sumo_set_forced_mode_enabled(rdev); 1319 sumo_wait_for_level_0(rdev); 1320 sumo_program_power_levels_0_to_n(rdev, new_ps, old_ps); 1321 sumo_program_wl(rdev, new_ps); 1322 sumo_program_bsp(rdev, new_ps); 1323 sumo_program_at(rdev, new_ps); 1324 sumo_force_nbp_state(rdev, new_ps); 1325 sumo_set_forced_mode_disabled(rdev); 1326 sumo_set_forced_mode_enabled(rdev); 1327 sumo_set_forced_mode_disabled(rdev); 1328 sumo_post_notify_alt_vddnb_change(rdev, new_ps, old_ps); 1329 } 1330 if (pi->enable_boost) 1331 sumo_enable_boost(rdev, new_ps, true); 1332 if (pi->enable_dpm) 1333 sumo_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps); 1334 1335 return 0; 1336 } 1337 1338 void sumo_dpm_post_set_power_state(struct radeon_device *rdev) 1339 { 1340 struct sumo_power_info *pi = sumo_get_pi(rdev); 1341 struct radeon_ps *new_ps = &pi->requested_rps; 1342 1343 sumo_update_current_ps(rdev, new_ps); 1344 } 1345 1346 #if 0 1347 void sumo_dpm_reset_asic(struct radeon_device *rdev) 1348 { 1349 sumo_program_bootup_state(rdev); 1350 sumo_enable_power_level_0(rdev); 1351 sumo_set_forced_level_0(rdev); 1352 sumo_set_forced_mode_enabled(rdev); 1353 sumo_wait_for_level_0(rdev); 1354 sumo_set_forced_mode_disabled(rdev); 1355 sumo_set_forced_mode_enabled(rdev); 1356 sumo_set_forced_mode_disabled(rdev); 1357 } 1358 #endif 1359 1360 void sumo_dpm_setup_asic(struct radeon_device *rdev) 1361 { 1362 struct sumo_power_info *pi = sumo_get_pi(rdev); 1363 1364 sumo_initialize_m3_arb(rdev); 1365 pi->fw_version = sumo_get_running_fw_version(rdev); 1366 DRM_INFO("Found smc ucode version: 0x%08x\n", pi->fw_version); 1367 sumo_program_acpi_power_level(rdev); 1368 sumo_enable_acpi_pm(rdev); 1369 sumo_take_smu_control(rdev, true); 1370 } 1371 1372 void sumo_dpm_display_configuration_changed(struct radeon_device *rdev) 1373 { 1374 1375 } 1376 1377 union power_info { 1378 struct _ATOM_POWERPLAY_INFO info; 1379 struct _ATOM_POWERPLAY_INFO_V2 info_2; 1380 struct _ATOM_POWERPLAY_INFO_V3 info_3; 1381 struct _ATOM_PPLIB_POWERPLAYTABLE pplib; 1382 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2; 1383 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3; 1384 }; 1385 1386 union pplib_clock_info { 1387 struct _ATOM_PPLIB_R600_CLOCK_INFO r600; 1388 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780; 1389 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; 1390 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo; 1391 }; 1392 1393 union pplib_power_state { 1394 struct _ATOM_PPLIB_STATE v1; 1395 struct _ATOM_PPLIB_STATE_V2 v2; 1396 }; 1397 1398 static void sumo_patch_boot_state(struct radeon_device *rdev, 1399 struct sumo_ps *ps) 1400 { 1401 struct sumo_power_info *pi = sumo_get_pi(rdev); 1402 1403 ps->num_levels = 1; 1404 ps->flags = 0; 1405 ps->levels[0] = pi->boot_pl; 1406 } 1407 1408 static void sumo_parse_pplib_non_clock_info(struct radeon_device *rdev, 1409 struct radeon_ps *rps, 1410 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info, 1411 u8 table_rev) 1412 { 1413 struct sumo_ps *ps = sumo_get_ps(rps); 1414 1415 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); 1416 rps->class = le16_to_cpu(non_clock_info->usClassification); 1417 rps->class2 = le16_to_cpu(non_clock_info->usClassification2); 1418 1419 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) { 1420 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); 1421 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); 1422 } else { 1423 rps->vclk = 0; 1424 rps->dclk = 0; 1425 } 1426 1427 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) { 1428 rdev->pm.dpm.boot_ps = rps; 1429 sumo_patch_boot_state(rdev, ps); 1430 } 1431 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) 1432 rdev->pm.dpm.uvd_ps = rps; 1433 } 1434 1435 static void sumo_parse_pplib_clock_info(struct radeon_device *rdev, 1436 struct radeon_ps *rps, int index, 1437 union pplib_clock_info *clock_info) 1438 { 1439 struct sumo_power_info *pi = sumo_get_pi(rdev); 1440 struct sumo_ps *ps = sumo_get_ps(rps); 1441 struct sumo_pl *pl = &ps->levels[index]; 1442 u32 sclk; 1443 1444 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow); 1445 sclk |= clock_info->sumo.ucEngineClockHigh << 16; 1446 pl->sclk = sclk; 1447 pl->vddc_index = clock_info->sumo.vddcIndex; 1448 pl->sclk_dpm_tdp_limit = clock_info->sumo.tdpLimit; 1449 1450 ps->num_levels = index + 1; 1451 1452 if (pi->enable_sclk_ds) { 1453 pl->ds_divider_index = 5; 1454 pl->ss_divider_index = 4; 1455 } 1456 } 1457 1458 static int sumo_parse_power_table(struct radeon_device *rdev) 1459 { 1460 struct radeon_mode_info *mode_info = &rdev->mode_info; 1461 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; 1462 union pplib_power_state *power_state; 1463 int i, j, k, non_clock_array_index, clock_array_index; 1464 union pplib_clock_info *clock_info; 1465 struct _StateArray *state_array; 1466 struct _ClockInfoArray *clock_info_array; 1467 struct _NonClockInfoArray *non_clock_info_array; 1468 union power_info *power_info; 1469 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 1470 u16 data_offset; 1471 u8 frev, crev; 1472 u8 *power_state_offset; 1473 struct sumo_ps *ps; 1474 1475 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, 1476 &frev, &crev, &data_offset)) 1477 return -EINVAL; 1478 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 1479 1480 state_array = (struct _StateArray *) 1481 (mode_info->atom_context->bios + data_offset + 1482 le16_to_cpu(power_info->pplib.usStateArrayOffset)); 1483 clock_info_array = (struct _ClockInfoArray *) 1484 (mode_info->atom_context->bios + data_offset + 1485 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset)); 1486 non_clock_info_array = (struct _NonClockInfoArray *) 1487 (mode_info->atom_context->bios + data_offset + 1488 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset)); 1489 1490 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) * 1491 state_array->ucNumEntries, GFP_KERNEL); 1492 if (!rdev->pm.dpm.ps) 1493 return -ENOMEM; 1494 power_state_offset = (u8 *)state_array->states; 1495 for (i = 0; i < state_array->ucNumEntries; i++) { 1496 u8 *idx; 1497 power_state = (union pplib_power_state *)power_state_offset; 1498 non_clock_array_index = power_state->v2.nonClockInfoIndex; 1499 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) 1500 &non_clock_info_array->nonClockInfo[non_clock_array_index]; 1501 if (!rdev->pm.power_state[i].clock_info) 1502 return -EINVAL; 1503 ps = kzalloc(sizeof(struct sumo_ps), GFP_KERNEL); 1504 if (ps == NULL) { 1505 kfree(rdev->pm.dpm.ps); 1506 return -ENOMEM; 1507 } 1508 rdev->pm.dpm.ps[i].ps_priv = ps; 1509 k = 0; 1510 idx = (u8 *)&power_state->v2.clockInfoIndex[0]; 1511 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { 1512 clock_array_index = idx[j]; 1513 if (k >= SUMO_MAX_HARDWARE_POWERLEVELS) 1514 break; 1515 1516 clock_info = (union pplib_clock_info *) 1517 ((u8 *)&clock_info_array->clockInfo[0] + 1518 (clock_array_index * clock_info_array->ucEntrySize)); 1519 sumo_parse_pplib_clock_info(rdev, 1520 &rdev->pm.dpm.ps[i], k, 1521 clock_info); 1522 k++; 1523 } 1524 sumo_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i], 1525 non_clock_info, 1526 non_clock_info_array->ucEntrySize); 1527 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; 1528 } 1529 rdev->pm.dpm.num_ps = state_array->ucNumEntries; 1530 return 0; 1531 } 1532 1533 u32 sumo_convert_vid2_to_vid7(struct radeon_device *rdev, 1534 struct sumo_vid_mapping_table *vid_mapping_table, 1535 u32 vid_2bit) 1536 { 1537 u32 i; 1538 1539 for (i = 0; i < vid_mapping_table->num_entries; i++) { 1540 if (vid_mapping_table->entries[i].vid_2bit == vid_2bit) 1541 return vid_mapping_table->entries[i].vid_7bit; 1542 } 1543 1544 return vid_mapping_table->entries[vid_mapping_table->num_entries - 1].vid_7bit; 1545 } 1546 1547 #if 0 1548 u32 sumo_convert_vid7_to_vid2(struct radeon_device *rdev, 1549 struct sumo_vid_mapping_table *vid_mapping_table, 1550 u32 vid_7bit) 1551 { 1552 u32 i; 1553 1554 for (i = 0; i < vid_mapping_table->num_entries; i++) { 1555 if (vid_mapping_table->entries[i].vid_7bit == vid_7bit) 1556 return vid_mapping_table->entries[i].vid_2bit; 1557 } 1558 1559 return vid_mapping_table->entries[vid_mapping_table->num_entries - 1].vid_2bit; 1560 } 1561 #endif 1562 1563 static u16 sumo_convert_voltage_index_to_value(struct radeon_device *rdev, 1564 u32 vid_2bit) 1565 { 1566 struct sumo_power_info *pi = sumo_get_pi(rdev); 1567 u32 vid_7bit = sumo_convert_vid2_to_vid7(rdev, &pi->sys_info.vid_mapping_table, vid_2bit); 1568 1569 if (vid_7bit > 0x7C) 1570 return 0; 1571 1572 return (15500 - vid_7bit * 125 + 5) / 10; 1573 } 1574 1575 static void sumo_construct_display_voltage_mapping_table(struct radeon_device *rdev, 1576 struct sumo_disp_clock_voltage_mapping_table *disp_clk_voltage_mapping_table, 1577 ATOM_CLK_VOLT_CAPABILITY *table) 1578 { 1579 u32 i; 1580 1581 for (i = 0; i < SUMO_MAX_NUMBER_VOLTAGES; i++) { 1582 if (table[i].ulMaximumSupportedCLK == 0) 1583 break; 1584 1585 disp_clk_voltage_mapping_table->display_clock_frequency[i] = 1586 table[i].ulMaximumSupportedCLK; 1587 } 1588 1589 disp_clk_voltage_mapping_table->num_max_voltage_levels = i; 1590 1591 if (disp_clk_voltage_mapping_table->num_max_voltage_levels == 0) { 1592 disp_clk_voltage_mapping_table->display_clock_frequency[0] = 80000; 1593 disp_clk_voltage_mapping_table->num_max_voltage_levels = 1; 1594 } 1595 } 1596 1597 void sumo_construct_sclk_voltage_mapping_table(struct radeon_device *rdev, 1598 struct sumo_sclk_voltage_mapping_table *sclk_voltage_mapping_table, 1599 ATOM_AVAILABLE_SCLK_LIST *table) 1600 { 1601 u32 i; 1602 u32 n = 0; 1603 u32 prev_sclk = 0; 1604 1605 for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++) { 1606 if (table[i].ulSupportedSCLK > prev_sclk) { 1607 sclk_voltage_mapping_table->entries[n].sclk_frequency = 1608 table[i].ulSupportedSCLK; 1609 sclk_voltage_mapping_table->entries[n].vid_2bit = 1610 table[i].usVoltageIndex; 1611 prev_sclk = table[i].ulSupportedSCLK; 1612 n++; 1613 } 1614 } 1615 1616 sclk_voltage_mapping_table->num_max_dpm_entries = n; 1617 } 1618 1619 void sumo_construct_vid_mapping_table(struct radeon_device *rdev, 1620 struct sumo_vid_mapping_table *vid_mapping_table, 1621 ATOM_AVAILABLE_SCLK_LIST *table) 1622 { 1623 u32 i, j; 1624 1625 for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++) { 1626 if (table[i].ulSupportedSCLK != 0) { 1627 vid_mapping_table->entries[table[i].usVoltageIndex].vid_7bit = 1628 table[i].usVoltageID; 1629 vid_mapping_table->entries[table[i].usVoltageIndex].vid_2bit = 1630 table[i].usVoltageIndex; 1631 } 1632 } 1633 1634 for (i = 0; i < SUMO_MAX_NUMBER_VOLTAGES; i++) { 1635 if (vid_mapping_table->entries[i].vid_7bit == 0) { 1636 for (j = i + 1; j < SUMO_MAX_NUMBER_VOLTAGES; j++) { 1637 if (vid_mapping_table->entries[j].vid_7bit != 0) { 1638 vid_mapping_table->entries[i] = 1639 vid_mapping_table->entries[j]; 1640 vid_mapping_table->entries[j].vid_7bit = 0; 1641 break; 1642 } 1643 } 1644 1645 if (j == SUMO_MAX_NUMBER_VOLTAGES) 1646 break; 1647 } 1648 } 1649 1650 vid_mapping_table->num_entries = i; 1651 } 1652 1653 union igp_info { 1654 struct _ATOM_INTEGRATED_SYSTEM_INFO info; 1655 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2; 1656 struct _ATOM_INTEGRATED_SYSTEM_INFO_V5 info_5; 1657 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6; 1658 }; 1659 1660 static int sumo_parse_sys_info_table(struct radeon_device *rdev) 1661 { 1662 struct sumo_power_info *pi = sumo_get_pi(rdev); 1663 struct radeon_mode_info *mode_info = &rdev->mode_info; 1664 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); 1665 union igp_info *igp_info; 1666 u8 frev, crev; 1667 u16 data_offset; 1668 int i; 1669 1670 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1671 &frev, &crev, &data_offset)) { 1672 igp_info = (union igp_info *)(mode_info->atom_context->bios + 1673 data_offset); 1674 1675 if (crev != 6) { 1676 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev); 1677 return -EINVAL; 1678 } 1679 pi->sys_info.bootup_sclk = le32_to_cpu(igp_info->info_6.ulBootUpEngineClock); 1680 pi->sys_info.min_sclk = le32_to_cpu(igp_info->info_6.ulMinEngineClock); 1681 pi->sys_info.bootup_uma_clk = le32_to_cpu(igp_info->info_6.ulBootUpUMAClock); 1682 pi->sys_info.bootup_nb_voltage_index = 1683 le16_to_cpu(igp_info->info_6.usBootUpNBVoltage); 1684 if (igp_info->info_6.ucHtcTmpLmt == 0) 1685 pi->sys_info.htc_tmp_lmt = 203; 1686 else 1687 pi->sys_info.htc_tmp_lmt = igp_info->info_6.ucHtcTmpLmt; 1688 if (igp_info->info_6.ucHtcHystLmt == 0) 1689 pi->sys_info.htc_hyst_lmt = 5; 1690 else 1691 pi->sys_info.htc_hyst_lmt = igp_info->info_6.ucHtcHystLmt; 1692 if (pi->sys_info.htc_tmp_lmt <= pi->sys_info.htc_hyst_lmt) { 1693 DRM_ERROR("The htcTmpLmt should be larger than htcHystLmt.\n"); 1694 } 1695 for (i = 0; i < NUMBER_OF_M3ARB_PARAM_SETS; i++) { 1696 pi->sys_info.csr_m3_arb_cntl_default[i] = 1697 le32_to_cpu(igp_info->info_6.ulCSR_M3_ARB_CNTL_DEFAULT[i]); 1698 pi->sys_info.csr_m3_arb_cntl_uvd[i] = 1699 le32_to_cpu(igp_info->info_6.ulCSR_M3_ARB_CNTL_UVD[i]); 1700 pi->sys_info.csr_m3_arb_cntl_fs3d[i] = 1701 le32_to_cpu(igp_info->info_6.ulCSR_M3_ARB_CNTL_FS3D[i]); 1702 } 1703 pi->sys_info.sclk_dpm_boost_margin = 1704 le32_to_cpu(igp_info->info_6.SclkDpmBoostMargin); 1705 pi->sys_info.sclk_dpm_throttle_margin = 1706 le32_to_cpu(igp_info->info_6.SclkDpmThrottleMargin); 1707 pi->sys_info.sclk_dpm_tdp_limit_pg = 1708 le16_to_cpu(igp_info->info_6.SclkDpmTdpLimitPG); 1709 pi->sys_info.gnb_tdp_limit = le16_to_cpu(igp_info->info_6.GnbTdpLimit); 1710 pi->sys_info.sclk_dpm_tdp_limit_boost = 1711 le16_to_cpu(igp_info->info_6.SclkDpmTdpLimitBoost); 1712 pi->sys_info.boost_sclk = le32_to_cpu(igp_info->info_6.ulBoostEngineCLock); 1713 pi->sys_info.boost_vid_2bit = igp_info->info_6.ulBoostVid_2bit; 1714 if (igp_info->info_6.EnableBoost) 1715 pi->sys_info.enable_boost = true; 1716 else 1717 pi->sys_info.enable_boost = false; 1718 sumo_construct_display_voltage_mapping_table(rdev, 1719 &pi->sys_info.disp_clk_voltage_mapping_table, 1720 igp_info->info_6.sDISPCLK_Voltage); 1721 sumo_construct_sclk_voltage_mapping_table(rdev, 1722 &pi->sys_info.sclk_voltage_mapping_table, 1723 igp_info->info_6.sAvail_SCLK); 1724 sumo_construct_vid_mapping_table(rdev, &pi->sys_info.vid_mapping_table, 1725 igp_info->info_6.sAvail_SCLK); 1726 1727 } 1728 return 0; 1729 } 1730 1731 static void sumo_construct_boot_and_acpi_state(struct radeon_device *rdev) 1732 { 1733 struct sumo_power_info *pi = sumo_get_pi(rdev); 1734 1735 pi->boot_pl.sclk = pi->sys_info.bootup_sclk; 1736 pi->boot_pl.vddc_index = pi->sys_info.bootup_nb_voltage_index; 1737 pi->boot_pl.ds_divider_index = 0; 1738 pi->boot_pl.ss_divider_index = 0; 1739 pi->boot_pl.allow_gnb_slow = 1; 1740 pi->acpi_pl = pi->boot_pl; 1741 pi->current_ps.num_levels = 1; 1742 pi->current_ps.levels[0] = pi->boot_pl; 1743 } 1744 1745 int sumo_dpm_init(struct radeon_device *rdev) 1746 { 1747 struct sumo_power_info *pi; 1748 u32 hw_rev = (RREG32(HW_REV) & ATI_REV_ID_MASK) >> ATI_REV_ID_SHIFT; 1749 int ret; 1750 1751 pi = kzalloc(sizeof(struct sumo_power_info), GFP_KERNEL); 1752 if (pi == NULL) 1753 return -ENOMEM; 1754 rdev->pm.dpm.priv = pi; 1755 1756 pi->driver_nbps_policy_disable = false; 1757 if ((rdev->family == CHIP_PALM) && (hw_rev < 3)) 1758 pi->disable_gfx_power_gating_in_uvd = true; 1759 else 1760 pi->disable_gfx_power_gating_in_uvd = false; 1761 pi->enable_alt_vddnb = true; 1762 pi->enable_sclk_ds = true; 1763 pi->enable_dynamic_m3_arbiter = false; 1764 pi->enable_dynamic_patch_ps = true; 1765 /* Some PALM chips don't seem to properly ungate gfx when UVD is in use; 1766 * for now just disable gfx PG. 1767 */ 1768 if (rdev->family == CHIP_PALM) 1769 pi->enable_gfx_power_gating = false; 1770 else 1771 pi->enable_gfx_power_gating = true; 1772 pi->enable_gfx_clock_gating = true; 1773 pi->enable_mg_clock_gating = true; 1774 pi->enable_auto_thermal_throttling = true; 1775 1776 ret = sumo_parse_sys_info_table(rdev); 1777 if (ret) 1778 return ret; 1779 1780 sumo_construct_boot_and_acpi_state(rdev); 1781 1782 ret = r600_get_platform_caps(rdev); 1783 if (ret) 1784 return ret; 1785 1786 ret = sumo_parse_power_table(rdev); 1787 if (ret) 1788 return ret; 1789 1790 pi->pasi = CYPRESS_HASI_DFLT; 1791 pi->asi = RV770_ASI_DFLT; 1792 pi->thermal_auto_throttling = pi->sys_info.htc_tmp_lmt; 1793 pi->enable_boost = pi->sys_info.enable_boost; 1794 pi->enable_dpm = true; 1795 1796 return 0; 1797 } 1798 1799 void sumo_dpm_print_power_state(struct radeon_device *rdev, 1800 struct radeon_ps *rps) 1801 { 1802 int i; 1803 struct sumo_ps *ps = sumo_get_ps(rps); 1804 1805 r600_dpm_print_class_info(rps->class, rps->class2); 1806 r600_dpm_print_cap_info(rps->caps); 1807 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); 1808 for (i = 0; i < ps->num_levels; i++) { 1809 struct sumo_pl *pl = &ps->levels[i]; 1810 printk("\t\tpower level %d sclk: %u vddc: %u\n", 1811 i, pl->sclk, 1812 sumo_convert_voltage_index_to_value(rdev, pl->vddc_index)); 1813 } 1814 r600_dpm_print_ps_status(rdev, rps); 1815 } 1816 1817 #ifdef CONFIG_DEBUG_FS 1818 void sumo_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 1819 struct seq_file *m) 1820 { 1821 struct sumo_power_info *pi = sumo_get_pi(rdev); 1822 struct radeon_ps *rps = &pi->current_rps; 1823 struct sumo_ps *ps = sumo_get_ps(rps); 1824 struct sumo_pl *pl; 1825 u32 current_index = 1826 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_INDEX_MASK) >> 1827 CURR_INDEX_SHIFT; 1828 1829 if (current_index == BOOST_DPM_LEVEL) { 1830 pl = &pi->boost_pl; 1831 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); 1832 seq_printf(m, "power level %d sclk: %u vddc: %u\n", 1833 current_index, pl->sclk, 1834 sumo_convert_voltage_index_to_value(rdev, pl->vddc_index)); 1835 } else if (current_index >= ps->num_levels) { 1836 seq_printf(m, "invalid dpm profile %d\n", current_index); 1837 } else { 1838 pl = &ps->levels[current_index]; 1839 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); 1840 seq_printf(m, "power level %d sclk: %u vddc: %u\n", 1841 current_index, pl->sclk, 1842 sumo_convert_voltage_index_to_value(rdev, pl->vddc_index)); 1843 } 1844 } 1845 #endif 1846 1847 u32 sumo_dpm_get_current_sclk(struct radeon_device *rdev) 1848 { 1849 struct sumo_power_info *pi = sumo_get_pi(rdev); 1850 struct radeon_ps *rps = &pi->current_rps; 1851 struct sumo_ps *ps = sumo_get_ps(rps); 1852 struct sumo_pl *pl; 1853 u32 current_index = 1854 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_INDEX_MASK) >> 1855 CURR_INDEX_SHIFT; 1856 1857 if (current_index == BOOST_DPM_LEVEL) { 1858 pl = &pi->boost_pl; 1859 return pl->sclk; 1860 } else if (current_index >= ps->num_levels) { 1861 return 0; 1862 } else { 1863 pl = &ps->levels[current_index]; 1864 return pl->sclk; 1865 } 1866 } 1867 1868 u32 sumo_dpm_get_current_mclk(struct radeon_device *rdev) 1869 { 1870 struct sumo_power_info *pi = sumo_get_pi(rdev); 1871 1872 return pi->sys_info.bootup_uma_clk; 1873 } 1874 1875 void sumo_dpm_fini(struct radeon_device *rdev) 1876 { 1877 int i; 1878 1879 sumo_cleanup_asic(rdev); /* ??? */ 1880 1881 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { 1882 kfree(rdev->pm.dpm.ps[i].ps_priv); 1883 } 1884 kfree(rdev->pm.dpm.ps); 1885 kfree(rdev->pm.dpm.priv); 1886 } 1887 1888 u32 sumo_dpm_get_sclk(struct radeon_device *rdev, bool low) 1889 { 1890 struct sumo_power_info *pi = sumo_get_pi(rdev); 1891 struct sumo_ps *requested_state = sumo_get_ps(&pi->requested_rps); 1892 1893 if (low) 1894 return requested_state->levels[0].sclk; 1895 else 1896 return requested_state->levels[requested_state->num_levels - 1].sclk; 1897 } 1898 1899 u32 sumo_dpm_get_mclk(struct radeon_device *rdev, bool low) 1900 { 1901 struct sumo_power_info *pi = sumo_get_pi(rdev); 1902 1903 return pi->sys_info.bootup_uma_clk; 1904 } 1905 1906 int sumo_dpm_force_performance_level(struct radeon_device *rdev, 1907 enum radeon_dpm_forced_level level) 1908 { 1909 struct sumo_power_info *pi = sumo_get_pi(rdev); 1910 struct radeon_ps *rps = &pi->current_rps; 1911 struct sumo_ps *ps = sumo_get_ps(rps); 1912 int i; 1913 1914 if (ps->num_levels <= 1) 1915 return 0; 1916 1917 if (level == RADEON_DPM_FORCED_LEVEL_HIGH) { 1918 if (pi->enable_boost) 1919 sumo_enable_boost(rdev, rps, false); 1920 sumo_power_level_enable(rdev, ps->num_levels - 1, true); 1921 sumo_set_forced_level(rdev, ps->num_levels - 1); 1922 sumo_set_forced_mode_enabled(rdev); 1923 for (i = 0; i < ps->num_levels - 1; i++) { 1924 sumo_power_level_enable(rdev, i, false); 1925 } 1926 sumo_set_forced_mode(rdev, false); 1927 sumo_set_forced_mode_enabled(rdev); 1928 sumo_set_forced_mode(rdev, false); 1929 } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) { 1930 if (pi->enable_boost) 1931 sumo_enable_boost(rdev, rps, false); 1932 sumo_power_level_enable(rdev, 0, true); 1933 sumo_set_forced_level(rdev, 0); 1934 sumo_set_forced_mode_enabled(rdev); 1935 for (i = 1; i < ps->num_levels; i++) { 1936 sumo_power_level_enable(rdev, i, false); 1937 } 1938 sumo_set_forced_mode(rdev, false); 1939 sumo_set_forced_mode_enabled(rdev); 1940 sumo_set_forced_mode(rdev, false); 1941 } else { 1942 for (i = 0; i < ps->num_levels; i++) { 1943 sumo_power_level_enable(rdev, i, true); 1944 } 1945 if (pi->enable_boost) 1946 sumo_enable_boost(rdev, rps, true); 1947 } 1948 1949 rdev->pm.dpm.forced_level = level; 1950 1951 return 0; 1952 } 1953
Indexes created Mon Oct 20 16:09:52 GMT 2025