radeon_ttm.c revision 1.17 1 /* $NetBSD: radeon_ttm.c,v 1.17 2020/04/27 16:57:31 tsutsui Exp $ */
2
3 /*
4 * Copyright 2009 Jerome Glisse.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * The above copyright notice and this permission notice (including the
24 * next paragraph) shall be included in all copies or substantial portions
25 * of the Software.
26 *
27 */
28 /*
29 * Authors:
30 * Jerome Glisse <glisse (at) freedesktop.org>
31 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
32 * Dave Airlie
33 */
34 #include <sys/cdefs.h>
35 __KERNEL_RCSID(0, "$NetBSD: radeon_ttm.c,v 1.17 2020/04/27 16:57:31 tsutsui Exp $");
36
37 #include <ttm/ttm_bo_api.h>
38 #include <ttm/ttm_bo_driver.h>
39 #include <ttm/ttm_placement.h>
40 #include <ttm/ttm_module.h>
41 #include <ttm/ttm_page_alloc.h>
42 #include <drm/drmP.h>
43 #include <drm/radeon_drm.h>
44 #include <linux/seq_file.h>
45 #include <linux/slab.h>
46 #include <linux/swiotlb.h>
47 #include <linux/swap.h>
48 #include <linux/pagemap.h>
49 #include <linux/debugfs.h>
50 #include "radeon_reg.h"
51 #include "radeon.h"
52
53 #ifdef __NetBSD__
54 #include <uvm/uvm_extern.h>
55 #include <uvm/uvm_fault.h>
56 #include <uvm/uvm_param.h>
57 #include <drm/bus_dma_hacks.h>
58 #endif
59
60 #ifdef _LP64
61 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
62 #else
63 #define DRM_FILE_PAGE_OFFSET (0xa0000000UL >> PAGE_SHIFT)
64 #endif
65
66 static int radeon_ttm_debugfs_init(struct radeon_device *rdev);
67 static void radeon_ttm_debugfs_fini(struct radeon_device *rdev);
68
69 static struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev)
70 {
71 struct radeon_mman *mman;
72 struct radeon_device *rdev;
73
74 mman = container_of(bdev, struct radeon_mman, bdev);
75 rdev = container_of(mman, struct radeon_device, mman);
76 return rdev;
77 }
78
79
80 /*
81 * Global memory.
82 */
83 static int radeon_ttm_mem_global_init(struct drm_global_reference *ref)
84 {
85 return ttm_mem_global_init(ref->object);
86 }
87
88 static void radeon_ttm_mem_global_release(struct drm_global_reference *ref)
89 {
90 ttm_mem_global_release(ref->object);
91 }
92
93 static int radeon_ttm_global_init(struct radeon_device *rdev)
94 {
95 struct drm_global_reference *global_ref;
96 int r;
97
98 rdev->mman.mem_global_referenced = false;
99 global_ref = &rdev->mman.mem_global_ref;
100 global_ref->global_type = DRM_GLOBAL_TTM_MEM;
101 global_ref->size = sizeof(struct ttm_mem_global);
102 global_ref->init = &radeon_ttm_mem_global_init;
103 global_ref->release = &radeon_ttm_mem_global_release;
104 r = drm_global_item_ref(global_ref);
105 if (r != 0) {
106 DRM_ERROR("Failed setting up TTM memory accounting "
107 "subsystem.\n");
108 return r;
109 }
110
111 rdev->mman.bo_global_ref.mem_glob =
112 rdev->mman.mem_global_ref.object;
113 global_ref = &rdev->mman.bo_global_ref.ref;
114 global_ref->global_type = DRM_GLOBAL_TTM_BO;
115 global_ref->size = sizeof(struct ttm_bo_global);
116 global_ref->init = &ttm_bo_global_init;
117 global_ref->release = &ttm_bo_global_release;
118 r = drm_global_item_ref(global_ref);
119 if (r != 0) {
120 DRM_ERROR("Failed setting up TTM BO subsystem.\n");
121 drm_global_item_unref(&rdev->mman.mem_global_ref);
122 return r;
123 }
124
125 rdev->mman.mem_global_referenced = true;
126 return 0;
127 }
128
129 static void radeon_ttm_global_fini(struct radeon_device *rdev)
130 {
131 if (rdev->mman.mem_global_referenced) {
132 drm_global_item_unref(&rdev->mman.bo_global_ref.ref);
133 drm_global_item_unref(&rdev->mman.mem_global_ref);
134 rdev->mman.mem_global_referenced = false;
135 }
136 }
137
138 static int radeon_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
139 {
140 return 0;
141 }
142
143 static int radeon_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
144 struct ttm_mem_type_manager *man)
145 {
146 struct radeon_device *rdev;
147
148 rdev = radeon_get_rdev(bdev);
149
150 switch (type) {
151 case TTM_PL_SYSTEM:
152 /* System memory */
153 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
154 man->available_caching = TTM_PL_MASK_CACHING;
155 man->default_caching = TTM_PL_FLAG_CACHED;
156 break;
157 case TTM_PL_TT:
158 man->func = &ttm_bo_manager_func;
159 man->gpu_offset = rdev->mc.gtt_start;
160 man->available_caching = TTM_PL_MASK_CACHING;
161 man->default_caching = TTM_PL_FLAG_CACHED;
162 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
163 #if IS_ENABLED(CONFIG_AGP)
164 if (rdev->flags & RADEON_IS_AGP) {
165 if (!rdev->ddev->agp) {
166 DRM_ERROR("AGP is not enabled for memory type %u\n",
167 (unsigned)type);
168 return -EINVAL;
169 }
170 if (!rdev->ddev->agp->cant_use_aperture)
171 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
172 man->available_caching = TTM_PL_FLAG_UNCACHED |
173 TTM_PL_FLAG_WC;
174 man->default_caching = TTM_PL_FLAG_WC;
175 }
176 #endif
177 break;
178 case TTM_PL_VRAM:
179 /* "On-card" video ram */
180 man->func = &ttm_bo_manager_func;
181 man->gpu_offset = rdev->mc.vram_start;
182 man->flags = TTM_MEMTYPE_FLAG_FIXED |
183 TTM_MEMTYPE_FLAG_MAPPABLE;
184 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
185 man->default_caching = TTM_PL_FLAG_WC;
186 break;
187 default:
188 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
189 return -EINVAL;
190 }
191 return 0;
192 }
193
194 static void radeon_evict_flags(struct ttm_buffer_object *bo,
195 struct ttm_placement *placement)
196 {
197 static struct ttm_place placements = {
198 .fpfn = 0,
199 .lpfn = 0,
200 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM
201 };
202
203 struct radeon_bo *rbo;
204
205 if (!radeon_ttm_bo_is_radeon_bo(bo)) {
206 placement->placement = &placements;
207 placement->busy_placement = &placements;
208 placement->num_placement = 1;
209 placement->num_busy_placement = 1;
210 return;
211 }
212 rbo = container_of(bo, struct radeon_bo, tbo);
213 switch (bo->mem.mem_type) {
214 case TTM_PL_VRAM:
215 if (rbo->rdev->ring[radeon_copy_ring_index(rbo->rdev)].ready == false)
216 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU);
217 else if (rbo->rdev->mc.visible_vram_size < rbo->rdev->mc.real_vram_size &&
218 bo->mem.start < (rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT)) {
219 unsigned fpfn = rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
220 int i;
221
222 /* Try evicting to the CPU inaccessible part of VRAM
223 * first, but only set GTT as busy placement, so this
224 * BO will be evicted to GTT rather than causing other
225 * BOs to be evicted from VRAM
226 */
227 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM |
228 RADEON_GEM_DOMAIN_GTT);
229 rbo->placement.num_busy_placement = 0;
230 for (i = 0; i < rbo->placement.num_placement; i++) {
231 if (rbo->placements[i].flags & TTM_PL_FLAG_VRAM) {
232 if (rbo->placements[i].fpfn < fpfn)
233 rbo->placements[i].fpfn = fpfn;
234 } else {
235 rbo->placement.busy_placement =
236 &rbo->placements[i];
237 rbo->placement.num_busy_placement = 1;
238 }
239 }
240 } else
241 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT);
242 break;
243 case TTM_PL_TT:
244 default:
245 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU);
246 }
247 *placement = rbo->placement;
248 }
249
250 static int radeon_verify_access(struct ttm_buffer_object *bo, struct file *filp)
251 {
252 struct radeon_bo *rbo = container_of(bo, struct radeon_bo, tbo);
253
254 if (radeon_ttm_tt_has_userptr(bo->ttm))
255 return -EPERM;
256 return drm_vma_node_verify_access(&rbo->gem_base.vma_node, filp);
257 }
258
259 static void radeon_move_null(struct ttm_buffer_object *bo,
260 struct ttm_mem_reg *new_mem)
261 {
262 struct ttm_mem_reg *old_mem = &bo->mem;
263
264 BUG_ON(old_mem->mm_node != NULL);
265 *old_mem = *new_mem;
266 new_mem->mm_node = NULL;
267 }
268
269 static int radeon_move_blit(struct ttm_buffer_object *bo,
270 bool evict, bool no_wait_gpu,
271 struct ttm_mem_reg *new_mem,
272 struct ttm_mem_reg *old_mem)
273 {
274 struct radeon_device *rdev;
275 uint64_t old_start, new_start;
276 struct radeon_fence *fence;
277 unsigned num_pages;
278 int r, ridx;
279
280 rdev = radeon_get_rdev(bo->bdev);
281 ridx = radeon_copy_ring_index(rdev);
282 old_start = (u64)old_mem->start << PAGE_SHIFT;
283 new_start = (u64)new_mem->start << PAGE_SHIFT;
284
285 switch (old_mem->mem_type) {
286 case TTM_PL_VRAM:
287 old_start += rdev->mc.vram_start;
288 break;
289 case TTM_PL_TT:
290 old_start += rdev->mc.gtt_start;
291 break;
292 default:
293 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
294 return -EINVAL;
295 }
296 switch (new_mem->mem_type) {
297 case TTM_PL_VRAM:
298 new_start += rdev->mc.vram_start;
299 break;
300 case TTM_PL_TT:
301 new_start += rdev->mc.gtt_start;
302 break;
303 default:
304 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
305 return -EINVAL;
306 }
307 if (!rdev->ring[ridx].ready) {
308 DRM_ERROR("Trying to move memory with ring turned off.\n");
309 return -EINVAL;
310 }
311
312 BUILD_BUG_ON((PAGE_SIZE % RADEON_GPU_PAGE_SIZE) != 0);
313
314 num_pages = new_mem->num_pages * (PAGE_SIZE / RADEON_GPU_PAGE_SIZE);
315 fence = radeon_copy(rdev, old_start, new_start, num_pages, bo->resv);
316 if (IS_ERR(fence))
317 return PTR_ERR(fence);
318
319 r = ttm_bo_move_accel_cleanup(bo, &fence->base,
320 evict, no_wait_gpu, new_mem);
321 radeon_fence_unref(&fence);
322 return r;
323 }
324
325 static int radeon_move_vram_ram(struct ttm_buffer_object *bo,
326 bool evict, bool interruptible,
327 bool no_wait_gpu,
328 struct ttm_mem_reg *new_mem)
329 {
330 struct radeon_device *rdev __unused;
331 struct ttm_mem_reg *old_mem = &bo->mem;
332 struct ttm_mem_reg tmp_mem;
333 struct ttm_place placements;
334 struct ttm_placement placement;
335 int r;
336
337 rdev = radeon_get_rdev(bo->bdev);
338 tmp_mem = *new_mem;
339 tmp_mem.mm_node = NULL;
340 placement.num_placement = 1;
341 placement.placement = &placements;
342 placement.num_busy_placement = 1;
343 placement.busy_placement = &placements;
344 placements.fpfn = 0;
345 placements.lpfn = 0;
346 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
347 r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
348 interruptible, no_wait_gpu);
349 if (unlikely(r)) {
350 return r;
351 }
352
353 r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
354 if (unlikely(r)) {
355 goto out_cleanup;
356 }
357
358 r = ttm_tt_bind(bo->ttm, &tmp_mem);
359 if (unlikely(r)) {
360 goto out_cleanup;
361 }
362 r = radeon_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem);
363 if (unlikely(r)) {
364 goto out_cleanup;
365 }
366 r = ttm_bo_move_ttm(bo, true, no_wait_gpu, new_mem);
367 out_cleanup:
368 ttm_bo_mem_put(bo, &tmp_mem);
369 return r;
370 }
371
372 static int radeon_move_ram_vram(struct ttm_buffer_object *bo,
373 bool evict, bool interruptible,
374 bool no_wait_gpu,
375 struct ttm_mem_reg *new_mem)
376 {
377 struct radeon_device *rdev __unused;
378 struct ttm_mem_reg *old_mem = &bo->mem;
379 struct ttm_mem_reg tmp_mem;
380 struct ttm_placement placement;
381 struct ttm_place placements;
382 int r;
383
384 rdev = radeon_get_rdev(bo->bdev);
385 tmp_mem = *new_mem;
386 tmp_mem.mm_node = NULL;
387 placement.num_placement = 1;
388 placement.placement = &placements;
389 placement.num_busy_placement = 1;
390 placement.busy_placement = &placements;
391 placements.fpfn = 0;
392 placements.lpfn = 0;
393 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
394 r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
395 interruptible, no_wait_gpu);
396 if (unlikely(r)) {
397 return r;
398 }
399 r = ttm_bo_move_ttm(bo, true, no_wait_gpu, &tmp_mem);
400 if (unlikely(r)) {
401 goto out_cleanup;
402 }
403 r = radeon_move_blit(bo, true, no_wait_gpu, new_mem, old_mem);
404 if (unlikely(r)) {
405 goto out_cleanup;
406 }
407 out_cleanup:
408 ttm_bo_mem_put(bo, &tmp_mem);
409 return r;
410 }
411
412 static int radeon_bo_move(struct ttm_buffer_object *bo,
413 bool evict, bool interruptible,
414 bool no_wait_gpu,
415 struct ttm_mem_reg *new_mem)
416 {
417 struct radeon_device *rdev;
418 struct ttm_mem_reg *old_mem = &bo->mem;
419 int r;
420
421 rdev = radeon_get_rdev(bo->bdev);
422 if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
423 radeon_move_null(bo, new_mem);
424 return 0;
425 }
426 if ((old_mem->mem_type == TTM_PL_TT &&
427 new_mem->mem_type == TTM_PL_SYSTEM) ||
428 (old_mem->mem_type == TTM_PL_SYSTEM &&
429 new_mem->mem_type == TTM_PL_TT)) {
430 /* bind is enough */
431 radeon_move_null(bo, new_mem);
432 return 0;
433 }
434 if (!rdev->ring[radeon_copy_ring_index(rdev)].ready ||
435 rdev->asic->copy.copy == NULL) {
436 /* use memcpy */
437 goto memcpy;
438 }
439
440 if (old_mem->mem_type == TTM_PL_VRAM &&
441 new_mem->mem_type == TTM_PL_SYSTEM) {
442 r = radeon_move_vram_ram(bo, evict, interruptible,
443 no_wait_gpu, new_mem);
444 } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
445 new_mem->mem_type == TTM_PL_VRAM) {
446 r = radeon_move_ram_vram(bo, evict, interruptible,
447 no_wait_gpu, new_mem);
448 } else {
449 r = radeon_move_blit(bo, evict, no_wait_gpu, new_mem, old_mem);
450 }
451
452 if (r) {
453 memcpy:
454 r = ttm_bo_move_memcpy(bo, evict, no_wait_gpu, new_mem);
455 if (r) {
456 return r;
457 }
458 }
459
460 /* update statistics */
461 atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &rdev->num_bytes_moved);
462 return 0;
463 }
464
465 static int radeon_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
466 {
467 struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
468 struct radeon_device *rdev = radeon_get_rdev(bdev);
469
470 mem->bus.addr = NULL;
471 mem->bus.offset = 0;
472 mem->bus.size = mem->num_pages << PAGE_SHIFT;
473 mem->bus.base = 0;
474 mem->bus.is_iomem = false;
475 if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
476 return -EINVAL;
477 switch (mem->mem_type) {
478 case TTM_PL_SYSTEM:
479 /* system memory */
480 return 0;
481 case TTM_PL_TT:
482 #if IS_ENABLED(CONFIG_AGP)
483 if (rdev->flags & RADEON_IS_AGP) {
484 /* RADEON_IS_AGP is set only if AGP is active */
485 mem->bus.offset = mem->start << PAGE_SHIFT;
486 mem->bus.base = rdev->mc.agp_base;
487 mem->bus.is_iomem = !rdev->ddev->agp->cant_use_aperture;
488 KASSERTMSG((mem->bus.base & (PAGE_SIZE - 1)) == 0,
489 "agp aperture is not page-aligned: %lx",
490 mem->bus.base);
491 KASSERT((mem->bus.offset & (PAGE_SIZE - 1)) == 0);
492 }
493 #endif
494 break;
495 case TTM_PL_VRAM:
496 mem->bus.offset = mem->start << PAGE_SHIFT;
497 /* check if it's visible */
498 if ((mem->bus.offset + mem->bus.size) > rdev->mc.visible_vram_size)
499 return -EINVAL;
500 mem->bus.base = rdev->mc.aper_base;
501 mem->bus.is_iomem = true;
502 #ifdef __alpha__
503 /*
504 * Alpha: use bus.addr to hold the ioremap() return,
505 * so we can modify bus.base below.
506 */
507 if (mem->placement & TTM_PL_FLAG_WC)
508 mem->bus.addr =
509 ioremap_wc(mem->bus.base + mem->bus.offset,
510 mem->bus.size);
511 else
512 mem->bus.addr =
513 ioremap_nocache(mem->bus.base + mem->bus.offset,
514 mem->bus.size);
515
516 /*
517 * Alpha: Use just the bus offset plus
518 * the hose/domain memory base for bus.base.
519 * It then can be used to build PTEs for VRAM
520 * access, as done in ttm_bo_vm_fault().
521 */
522 mem->bus.base = (mem->bus.base & 0x0ffffffffUL) +
523 rdev->ddev->hose->dense_mem_base;
524 #endif
525 KASSERTMSG((mem->bus.base & (PAGE_SIZE - 1)) == 0,
526 "mc aperture is not page-aligned: %lx",
527 mem->bus.base);
528 KASSERT((mem->bus.offset & (PAGE_SIZE - 1)) == 0);
529 break;
530 default:
531 return -EINVAL;
532 }
533 return 0;
534 }
535
536 static void radeon_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
537 {
538 }
539
540 /*
541 * TTM backend functions.
542 */
543 struct radeon_ttm_tt {
544 struct ttm_dma_tt ttm;
545 struct radeon_device *rdev;
546 u64 offset;
547
548 uint64_t userptr;
549 #ifdef __NetBSD__
550 struct vmspace *usermm;
551 #else
552 struct mm_struct *usermm;
553 #endif
554 uint32_t userflags;
555 };
556
557 /* prepare the sg table with the user pages */
558 static int radeon_ttm_tt_pin_userptr(struct ttm_tt *ttm)
559 {
560 struct radeon_device *rdev = radeon_get_rdev(ttm->bdev);
561 struct radeon_ttm_tt *gtt = (void *)ttm;
562 #ifndef __NetBSD__
563 unsigned pinned = 0, nents;
564 #endif
565 int r;
566
567 int write = !(gtt->userflags & RADEON_GEM_USERPTR_READONLY);
568 #ifndef __NetBSD__
569 enum dma_data_direction direction = write ?
570 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
571 #endif
572
573 #ifdef __NetBSD__
574 if (curproc->p_vmspace != gtt->usermm)
575 return -EPERM;
576 #else
577 if (current->mm != gtt->usermm)
578 return -EPERM;
579 #endif
580
581 if (gtt->userflags & RADEON_GEM_USERPTR_ANONONLY) {
582 /* check that we only pin down anonymous memory
583 to prevent problems with writeback */
584 unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE;
585 #ifdef __NetBSD__
586 /* XXX ??? TOCTOU, anyone? */
587 /* XXX should do range_test */
588 struct vm_map_entry *entry;
589 bool ok;
590 vm_map_lock_read(>t->usermm->vm_map);
591 ok = uvm_map_lookup_entry(>t->usermm->vm_map,
592 (vaddr_t)gtt->userptr, &entry);
593 if (ok)
594 ok = !UVM_ET_ISOBJ(entry) && end <= entry->end;
595 vm_map_unlock_read(>t->usermm->vm_map);
596 if (!ok)
597 return -EPERM;
598 #else
599 struct vm_area_struct *vma;
600 vma = find_vma(gtt->usermm, gtt->userptr);
601 if (!vma || vma->vm_file || vma->vm_end < end)
602 return -EPERM;
603 #endif
604 }
605
606 #ifdef __NetBSD__
607 struct iovec iov = {
608 .iov_base = (void *)(vaddr_t)gtt->userptr,
609 .iov_len = ttm->num_pages << PAGE_SHIFT,
610 };
611 struct uio uio = {
612 .uio_iov = &iov,
613 .uio_iovcnt = 1,
614 .uio_offset = 0,
615 .uio_resid = ttm->num_pages << PAGE_SHIFT,
616 .uio_rw = (write ? UIO_READ : UIO_WRITE), /* XXX ??? */
617 .uio_vmspace = gtt->usermm,
618 };
619 unsigned long i;
620
621 /* Wire the relevant part of the user's address space. */
622 /* XXX What happens if user does munmap? */
623 /* XXX errno NetBSD->Linux */
624 r = -uvm_vslock(gtt->usermm, (void *)(vaddr_t)gtt->userptr,
625 ttm->num_pages << PAGE_SHIFT,
626 (write ? VM_PROT_WRITE : VM_PROT_READ)); /* XXX ??? */
627 if (r)
628 goto fail0;
629
630 /* Load it up for DMA. */
631 /* XXX errno NetBSD->Linux */
632 r = -bus_dmamap_load_uio(rdev->ddev->dmat, gtt->ttm.dma_address, &uio,
633 BUS_DMA_WAITOK);
634 if (r)
635 goto fail1;
636
637 /* Get each of the pages as ttm requests. */
638 for (i = 0; i < ttm->num_pages; i++) {
639 vaddr_t va = (vaddr_t)gtt->userptr + (i << PAGE_SHIFT);
640 paddr_t pa;
641 struct vm_page *vmp;
642
643 if (!pmap_extract(gtt->usermm->vm_map.pmap, va, &pa)) {
644 r = -EFAULT;
645 goto fail2;
646 }
647 vmp = PHYS_TO_VM_PAGE(pa);
648 ttm->pages[i] = container_of(vmp, struct page, p_vmp);
649 }
650
651 /* Success! */
652 return 0;
653
654 fail2: while (i --> 0)
655 ttm->pages[i] = NULL; /* paranoia */
656 bus_dmamap_unload(rdev->ddev->dmat, gtt->ttm.dma_address);
657 fail1: uvm_vsunlock(gtt->usermm, (void *)(vaddr_t)gtt->userptr,
658 ttm->num_pages << PAGE_SHIFT);
659 fail0: return r;
660 #else
661 do {
662 unsigned num_pages = ttm->num_pages - pinned;
663 uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE;
664 struct page **pages = ttm->pages + pinned;
665
666 r = get_user_pages(current, current->mm, userptr, num_pages,
667 write, 0, pages, NULL);
668 if (r < 0)
669 goto release_pages;
670
671 pinned += r;
672
673 } while (pinned < ttm->num_pages);
674
675 r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
676 ttm->num_pages << PAGE_SHIFT,
677 GFP_KERNEL);
678 if (r)
679 goto release_sg;
680
681 r = -ENOMEM;
682 nents = dma_map_sg(rdev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
683 if (nents != ttm->sg->nents)
684 goto release_sg;
685
686 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
687 gtt->ttm.dma_address, ttm->num_pages);
688
689 return 0;
690
691 release_sg:
692 kfree(ttm->sg);
693
694 release_pages:
695 release_pages(ttm->pages, pinned, 0);
696 return r;
697 #endif
698 }
699
700 static void radeon_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
701 {
702 #ifdef __NetBSD__
703 struct radeon_device *rdev = radeon_get_rdev(ttm->bdev);
704 struct radeon_ttm_tt *gtt = (void *)ttm;
705
706 bus_dmamap_unload(rdev->ddev->dmat, gtt->ttm.dma_address);
707 uvm_vsunlock(gtt->usermm, (void *)(vaddr_t)gtt->userptr,
708 ttm->num_pages << PAGE_SHIFT);
709 #else
710 struct radeon_device *rdev = radeon_get_rdev(ttm->bdev);
711 struct radeon_ttm_tt *gtt = (void *)ttm;
712 struct sg_page_iter sg_iter;
713
714 int write = !(gtt->userflags & RADEON_GEM_USERPTR_READONLY);
715 enum dma_data_direction direction = write ?
716 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
717
718 /* double check that we don't free the table twice */
719 if (!ttm->sg->sgl)
720 return;
721
722 /* free the sg table and pages again */
723 dma_unmap_sg(rdev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
724
725 for_each_sg_page(ttm->sg->sgl, &sg_iter, ttm->sg->nents, 0) {
726 struct page *page = sg_page_iter_page(&sg_iter);
727 if (!(gtt->userflags & RADEON_GEM_USERPTR_READONLY))
728 set_page_dirty(page);
729
730 mark_page_accessed(page);
731 page_cache_release(page);
732 }
733
734 sg_free_table(ttm->sg);
735 #endif
736 }
737
738 static int radeon_ttm_backend_bind(struct ttm_tt *ttm,
739 struct ttm_mem_reg *bo_mem)
740 {
741 struct radeon_ttm_tt *gtt = (void*)ttm;
742 uint32_t flags = RADEON_GART_PAGE_VALID | RADEON_GART_PAGE_READ |
743 RADEON_GART_PAGE_WRITE;
744 int r;
745
746 if (gtt->userptr) {
747 radeon_ttm_tt_pin_userptr(ttm);
748 flags &= ~RADEON_GART_PAGE_WRITE;
749 }
750
751 gtt->offset = (unsigned long)(bo_mem->start << PAGE_SHIFT);
752 if (!ttm->num_pages) {
753 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
754 ttm->num_pages, bo_mem, ttm);
755 }
756 if (ttm->caching_state == tt_cached)
757 flags |= RADEON_GART_PAGE_SNOOP;
758 r = radeon_gart_bind(gtt->rdev, gtt->offset, ttm->num_pages,
759 ttm->pages, gtt->ttm.dma_address, flags);
760 if (r) {
761 DRM_ERROR("failed to bind %lu pages at 0x%08X\n",
762 ttm->num_pages, (unsigned)gtt->offset);
763 return r;
764 }
765 return 0;
766 }
767
768 static int radeon_ttm_backend_unbind(struct ttm_tt *ttm)
769 {
770 struct radeon_ttm_tt *gtt = (void *)ttm;
771
772 radeon_gart_unbind(gtt->rdev, gtt->offset, ttm->num_pages);
773
774 if (gtt->userptr)
775 radeon_ttm_tt_unpin_userptr(ttm);
776
777 return 0;
778 }
779
780 static void radeon_ttm_backend_destroy(struct ttm_tt *ttm)
781 {
782 struct radeon_ttm_tt *gtt = (void *)ttm;
783
784 ttm_dma_tt_fini(>t->ttm);
785 kfree(gtt);
786 }
787
788 static struct ttm_backend_func radeon_backend_func = {
789 .bind = &radeon_ttm_backend_bind,
790 .unbind = &radeon_ttm_backend_unbind,
791 .destroy = &radeon_ttm_backend_destroy,
792 };
793
794 static struct ttm_tt *radeon_ttm_tt_create(struct ttm_bo_device *bdev,
795 unsigned long size, uint32_t page_flags,
796 struct page *dummy_read_page)
797 {
798 struct radeon_device *rdev;
799 struct radeon_ttm_tt *gtt;
800
801 rdev = radeon_get_rdev(bdev);
802 #if IS_ENABLED(CONFIG_AGP)
803 if (rdev->flags & RADEON_IS_AGP) {
804 return ttm_agp_tt_create(bdev, rdev->ddev->agp->bridge,
805 size, page_flags, dummy_read_page);
806 }
807 #endif
808
809 gtt = kzalloc(sizeof(struct radeon_ttm_tt), GFP_KERNEL);
810 if (gtt == NULL) {
811 return NULL;
812 }
813 gtt->ttm.ttm.func = &radeon_backend_func;
814 gtt->rdev = rdev;
815 if (ttm_dma_tt_init(>t->ttm, bdev, size, page_flags, dummy_read_page)) {
816 kfree(gtt);
817 return NULL;
818 }
819 return >t->ttm.ttm;
820 }
821
822 static struct radeon_ttm_tt *radeon_ttm_tt_to_gtt(struct ttm_tt *ttm)
823 {
824 if (!ttm || ttm->func != &radeon_backend_func)
825 return NULL;
826 return (struct radeon_ttm_tt *)ttm;
827 }
828
829 static int radeon_ttm_tt_populate(struct ttm_tt *ttm)
830 {
831 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm);
832 #if !defined(__NetBSD__) || IS_ENABLED(CONFIG_AGP)
833 struct radeon_device *rdev;
834 #endif
835 #ifndef __NetBSD__
836 unsigned i;
837 #endif
838 int r;
839 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
840
841 if (ttm->state != tt_unpopulated)
842 return 0;
843
844 if (gtt && gtt->userptr) {
845 #ifdef __NetBSD__
846 ttm->sg = NULL;
847 #else
848 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
849 if (!ttm->sg)
850 return -ENOMEM;
851 #endif
852
853 ttm->page_flags |= TTM_PAGE_FLAG_SG;
854 ttm->state = tt_unbound;
855 return 0;
856 }
857
858 if (slave && ttm->sg) {
859 #ifdef __NetBSD__
860 r = drm_prime_bus_dmamap_load_sgt(ttm->bdev->dmat,
861 gtt->ttm.dma_address, ttm->sg);
862 if (r)
863 return r;
864 #else
865 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
866 gtt->ttm.dma_address, ttm->num_pages);
867 #endif
868 ttm->state = tt_unbound;
869 return 0;
870 }
871
872 #if !defined(__NetBSD__) || IS_ENABLED(CONFIG_AGP)
873 rdev = radeon_get_rdev(ttm->bdev);
874 #endif
875 #if IS_ENABLED(CONFIG_AGP)
876 if (rdev->flags & RADEON_IS_AGP) {
877 return ttm_agp_tt_populate(ttm);
878 }
879 #endif
880
881 #ifdef __NetBSD__
882 /* XXX errno NetBSD->Linux */
883 return ttm_bus_dma_populate(>t->ttm);
884 #else
885
886 #ifdef CONFIG_SWIOTLB
887 if (swiotlb_nr_tbl()) {
888 return ttm_dma_populate(>t->ttm, rdev->dev);
889 }
890 #endif
891
892 r = ttm_pool_populate(ttm);
893 if (r) {
894 return r;
895 }
896
897 for (i = 0; i < ttm->num_pages; i++) {
898 gtt->ttm.dma_address[i] = pci_map_page(rdev->pdev, ttm->pages[i],
899 0, PAGE_SIZE,
900 PCI_DMA_BIDIRECTIONAL);
901 if (pci_dma_mapping_error(rdev->pdev, gtt->ttm.dma_address[i])) {
902 while (i--) {
903 pci_unmap_page(rdev->pdev, gtt->ttm.dma_address[i],
904 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
905 gtt->ttm.dma_address[i] = 0;
906 }
907 ttm_pool_unpopulate(ttm);
908 return -EFAULT;
909 }
910 }
911 return 0;
912 #endif
913 }
914
915 static void radeon_ttm_tt_unpopulate(struct ttm_tt *ttm)
916 {
917 #if !defined(__NetBSD__) || IS_ENABLED(CONFIG_AGP)
918 struct radeon_device *rdev;
919 #endif
920 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm);
921 #ifndef __NetBSD__
922 unsigned i;
923 #endif
924 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
925
926 #ifdef __NetBSD__
927 if (slave && ttm->sg) {
928 bus_dmamap_unload(ttm->bdev->dmat, gtt->ttm.dma_address);
929 }
930 #endif
931 if (gtt && gtt->userptr) {
932 kfree(ttm->sg);
933 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
934 return;
935 }
936
937 if (slave)
938 return;
939
940 #if !defined(__NetBSD__) || IS_ENABLED(CONFIG_AGP)
941 rdev = radeon_get_rdev(ttm->bdev);
942 #endif
943 #if IS_ENABLED(CONFIG_AGP)
944 if (rdev->flags & RADEON_IS_AGP) {
945 ttm_agp_tt_unpopulate(ttm);
946 return;
947 }
948 #endif
949
950 #ifdef __NetBSD__
951 ttm_bus_dma_unpopulate(>t->ttm);
952 return;
953 #else
954
955 #ifdef CONFIG_SWIOTLB
956 if (swiotlb_nr_tbl()) {
957 ttm_dma_unpopulate(>t->ttm, rdev->dev);
958 return;
959 }
960 #endif
961
962 for (i = 0; i < ttm->num_pages; i++) {
963 if (gtt->ttm.dma_address[i]) {
964 pci_unmap_page(rdev->pdev, gtt->ttm.dma_address[i],
965 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
966 }
967 }
968
969 ttm_pool_unpopulate(ttm);
970 #endif
971 }
972
973 #ifdef __NetBSD__
974 static void radeon_ttm_tt_swapout(struct ttm_tt *ttm)
975 {
976 struct radeon_ttm_tt *gtt = container_of(ttm, struct radeon_ttm_tt,
977 ttm.ttm);
978 struct ttm_dma_tt *ttm_dma = >t->ttm;
979
980 ttm_bus_dma_swapout(ttm_dma);
981 }
982
983 static int radeon_ttm_fault(struct uvm_faultinfo *, vaddr_t,
984 struct vm_page **, int, int, vm_prot_t, int);
985
986 static const struct uvm_pagerops radeon_uvm_ops = {
987 .pgo_reference = &ttm_bo_uvm_reference,
988 .pgo_detach = &ttm_bo_uvm_detach,
989 .pgo_fault = &radeon_ttm_fault,
990 };
991 #endif
992
993 int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
994 uint32_t flags)
995 {
996 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm);
997
998 if (gtt == NULL)
999 return -EINVAL;
1000
1001 gtt->userptr = addr;
1002 #ifdef __NetBSD__
1003 gtt->usermm = curproc->p_vmspace;
1004 #else
1005 gtt->usermm = current->mm;
1006 #endif
1007 gtt->userflags = flags;
1008 return 0;
1009 }
1010
1011 bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm)
1012 {
1013 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm);
1014
1015 if (gtt == NULL)
1016 return false;
1017
1018 return !!gtt->userptr;
1019 }
1020
1021 bool radeon_ttm_tt_is_readonly(struct ttm_tt *ttm)
1022 {
1023 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm);
1024
1025 if (gtt == NULL)
1026 return false;
1027
1028 return !!(gtt->userflags & RADEON_GEM_USERPTR_READONLY);
1029 }
1030
1031 static struct ttm_bo_driver radeon_bo_driver = {
1032 .ttm_tt_create = &radeon_ttm_tt_create,
1033 .ttm_tt_populate = &radeon_ttm_tt_populate,
1034 .ttm_tt_unpopulate = &radeon_ttm_tt_unpopulate,
1035 #ifdef __NetBSD__
1036 .ttm_tt_swapout = &radeon_ttm_tt_swapout,
1037 .ttm_uvm_ops = &radeon_uvm_ops,
1038 #endif
1039 .invalidate_caches = &radeon_invalidate_caches,
1040 .init_mem_type = &radeon_init_mem_type,
1041 .evict_flags = &radeon_evict_flags,
1042 .move = &radeon_bo_move,
1043 .verify_access = &radeon_verify_access,
1044 .move_notify = &radeon_bo_move_notify,
1045 .fault_reserve_notify = &radeon_bo_fault_reserve_notify,
1046 .io_mem_reserve = &radeon_ttm_io_mem_reserve,
1047 .io_mem_free = &radeon_ttm_io_mem_free,
1048 };
1049
1050 int radeon_ttm_init(struct radeon_device *rdev)
1051 {
1052 int r;
1053
1054 r = radeon_ttm_global_init(rdev);
1055 if (r) {
1056 return r;
1057 }
1058 /* No others user of address space so set it to 0 */
1059 r = ttm_bo_device_init(&rdev->mman.bdev,
1060 rdev->mman.bo_global_ref.ref.object,
1061 &radeon_bo_driver,
1062 #ifdef __NetBSD__
1063 rdev->ddev->bst,
1064 rdev->ddev->dmat,
1065 #else
1066 rdev->ddev->anon_inode->i_mapping,
1067 #endif
1068 DRM_FILE_PAGE_OFFSET,
1069 rdev->need_dma32);
1070 if (r) {
1071 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
1072 return r;
1073 }
1074 rdev->mman.initialized = true;
1075 r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_VRAM,
1076 rdev->mc.real_vram_size >> PAGE_SHIFT);
1077 if (r) {
1078 DRM_ERROR("Failed initializing VRAM heap.\n");
1079 return r;
1080 }
1081 /* Change the size here instead of the init above so only lpfn is affected */
1082 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1083
1084 r = radeon_bo_create(rdev, 256 * 1024, PAGE_SIZE, true,
1085 RADEON_GEM_DOMAIN_VRAM, 0, NULL,
1086 NULL, &rdev->stollen_vga_memory);
1087 if (r) {
1088 return r;
1089 }
1090 r = radeon_bo_reserve(rdev->stollen_vga_memory, false);
1091 if (r)
1092 return r;
1093 r = radeon_bo_pin(rdev->stollen_vga_memory, RADEON_GEM_DOMAIN_VRAM, NULL);
1094 radeon_bo_unreserve(rdev->stollen_vga_memory);
1095 if (r) {
1096 radeon_bo_unref(&rdev->stollen_vga_memory);
1097 return r;
1098 }
1099 DRM_INFO("radeon: %uM of VRAM memory ready\n",
1100 (unsigned) (rdev->mc.real_vram_size / (1024 * 1024)));
1101 r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_TT,
1102 rdev->mc.gtt_size >> PAGE_SHIFT);
1103 if (r) {
1104 DRM_ERROR("Failed initializing GTT heap.\n");
1105 return r;
1106 }
1107 DRM_INFO("radeon: %uM of GTT memory ready.\n",
1108 (unsigned)(rdev->mc.gtt_size / (1024 * 1024)));
1109
1110 r = radeon_ttm_debugfs_init(rdev);
1111 if (r) {
1112 DRM_ERROR("Failed to init debugfs\n");
1113 return r;
1114 }
1115 return 0;
1116 }
1117
1118 void radeon_ttm_fini(struct radeon_device *rdev)
1119 {
1120 int r;
1121
1122 if (!rdev->mman.initialized)
1123 return;
1124 radeon_ttm_debugfs_fini(rdev);
1125 if (rdev->stollen_vga_memory) {
1126 r = radeon_bo_reserve(rdev->stollen_vga_memory, false);
1127 if (r == 0) {
1128 radeon_bo_unpin(rdev->stollen_vga_memory);
1129 radeon_bo_unreserve(rdev->stollen_vga_memory);
1130 }
1131 radeon_bo_unref(&rdev->stollen_vga_memory);
1132 }
1133 ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_VRAM);
1134 ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_TT);
1135 ttm_bo_device_release(&rdev->mman.bdev);
1136 radeon_gart_fini(rdev);
1137 radeon_ttm_global_fini(rdev);
1138 rdev->mman.initialized = false;
1139 DRM_INFO("radeon: ttm finalized\n");
1140 }
1141
1142 /* this should only be called at bootup or when userspace
1143 * isn't running */
1144 void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size)
1145 {
1146 struct ttm_mem_type_manager *man;
1147
1148 if (!rdev->mman.initialized)
1149 return;
1150
1151 man = &rdev->mman.bdev.man[TTM_PL_VRAM];
1152 /* this just adjusts TTM size idea, which sets lpfn to the correct value */
1153 man->size = size >> PAGE_SHIFT;
1154 }
1155
1156 #ifdef __NetBSD__
1157
1158 static int
1159 radeon_ttm_fault(struct uvm_faultinfo *ufi, vaddr_t vaddr,
1160 struct vm_page **pps, int npages, int centeridx, vm_prot_t access_type,
1161 int flags)
1162 {
1163 struct uvm_object *const uobj = ufi->entry->object.uvm_obj;
1164 struct ttm_buffer_object *const bo = container_of(uobj,
1165 struct ttm_buffer_object, uvmobj);
1166 struct radeon_device *const rdev = radeon_get_rdev(bo->bdev);
1167 int error;
1168
1169 KASSERT(rdev != NULL);
1170 down_read(&rdev->pm.mclk_lock);
1171 error = ttm_bo_uvm_fault(ufi, vaddr, pps, npages, centeridx,
1172 access_type, flags);
1173 up_read(&rdev->pm.mclk_lock);
1174
1175 return error;
1176 }
1177
1178 int
1179 radeon_mmap_object(struct drm_device *dev, off_t offset, size_t size,
1180 vm_prot_t prot, struct uvm_object **uobjp, voff_t *uoffsetp,
1181 struct file *file)
1182 {
1183 struct radeon_device *rdev = dev->dev_private;
1184
1185 KASSERT(0 == (offset & (PAGE_SIZE - 1)));
1186
1187 if (__predict_false(rdev == NULL)) /* XXX How?? */
1188 return -EINVAL;
1189
1190 if (__predict_false((offset >> PAGE_SHIFT) < DRM_FILE_PAGE_OFFSET))
1191 return -EINVAL;
1192
1193 return ttm_bo_mmap_object(&rdev->mman.bdev, offset, size, prot,
1194 uobjp, uoffsetp, file);
1195 }
1196
1197 #else
1198
1199 static struct vm_operations_struct radeon_ttm_vm_ops;
1200 static const struct vm_operations_struct *ttm_vm_ops = NULL;
1201
1202 static int radeon_ttm_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1203 {
1204 struct ttm_buffer_object *bo;
1205 struct radeon_device *rdev;
1206 int r;
1207
1208 bo = (struct ttm_buffer_object *)vma->vm_private_data;
1209 if (bo == NULL) {
1210 return VM_FAULT_NOPAGE;
1211 }
1212 rdev = radeon_get_rdev(bo->bdev);
1213 down_read(&rdev->pm.mclk_lock);
1214 r = ttm_vm_ops->fault(vma, vmf);
1215 up_read(&rdev->pm.mclk_lock);
1216 return r;
1217 }
1218
1219 int radeon_mmap(struct file *filp, struct vm_area_struct *vma)
1220 {
1221 struct drm_file *file_priv;
1222 struct radeon_device *rdev;
1223 int r;
1224
1225 if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET)) {
1226 return -EINVAL;
1227 }
1228
1229 file_priv = filp->private_data;
1230 rdev = file_priv->minor->dev->dev_private;
1231 if (rdev == NULL) {
1232 return -EINVAL;
1233 }
1234 r = ttm_bo_mmap(filp, vma, &rdev->mman.bdev);
1235 if (unlikely(r != 0)) {
1236 return r;
1237 }
1238 if (unlikely(ttm_vm_ops == NULL)) {
1239 ttm_vm_ops = vma->vm_ops;
1240 radeon_ttm_vm_ops = *ttm_vm_ops;
1241 radeon_ttm_vm_ops.fault = &radeon_ttm_fault;
1242 }
1243 vma->vm_ops = &radeon_ttm_vm_ops;
1244 return 0;
1245 }
1246
1247 #endif /* __NetBSD__ */
1248
1249 #if defined(CONFIG_DEBUG_FS)
1250
1251 static int radeon_mm_dump_table(struct seq_file *m, void *data)
1252 {
1253 struct drm_info_node *node = (struct drm_info_node *)m->private;
1254 unsigned ttm_pl = *(int *)node->info_ent->data;
1255 struct drm_device *dev = node->minor->dev;
1256 struct radeon_device *rdev = dev->dev_private;
1257 struct drm_mm *mm = (struct drm_mm *)rdev->mman.bdev.man[ttm_pl].priv;
1258 int ret;
1259 struct ttm_bo_global *glob = rdev->mman.bdev.glob;
1260
1261 spin_lock(&glob->lru_lock);
1262 ret = drm_mm_dump_table(m, mm);
1263 spin_unlock(&glob->lru_lock);
1264 return ret;
1265 }
1266
1267 static int ttm_pl_vram = TTM_PL_VRAM;
1268 static int ttm_pl_tt = TTM_PL_TT;
1269
1270 static struct drm_info_list radeon_ttm_debugfs_list[] = {
1271 {"radeon_vram_mm", radeon_mm_dump_table, 0, &ttm_pl_vram},
1272 {"radeon_gtt_mm", radeon_mm_dump_table, 0, &ttm_pl_tt},
1273 {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
1274 #ifdef CONFIG_SWIOTLB
1275 {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
1276 #endif
1277 };
1278
1279 static int radeon_ttm_vram_open(struct inode *inode, struct file *filep)
1280 {
1281 struct radeon_device *rdev = inode->i_private;
1282 i_size_write(inode, rdev->mc.mc_vram_size);
1283 filep->private_data = inode->i_private;
1284 return 0;
1285 }
1286
1287 static ssize_t radeon_ttm_vram_read(struct file *f, char __user *buf,
1288 size_t size, loff_t *pos)
1289 {
1290 struct radeon_device *rdev = f->private_data;
1291 ssize_t result = 0;
1292 int r;
1293
1294 if (size & 0x3 || *pos & 0x3)
1295 return -EINVAL;
1296
1297 while (size) {
1298 unsigned long flags;
1299 uint32_t value;
1300
1301 if (*pos >= rdev->mc.mc_vram_size)
1302 return result;
1303
1304 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
1305 WREG32(RADEON_MM_INDEX, ((uint32_t)*pos) | 0x80000000);
1306 if (rdev->family >= CHIP_CEDAR)
1307 WREG32(EVERGREEN_MM_INDEX_HI, *pos >> 31);
1308 value = RREG32(RADEON_MM_DATA);
1309 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
1310
1311 r = put_user(value, (uint32_t *)buf);
1312 if (r)
1313 return r;
1314
1315 result += 4;
1316 buf += 4;
1317 *pos += 4;
1318 size -= 4;
1319 }
1320
1321 return result;
1322 }
1323
1324 static const struct file_operations radeon_ttm_vram_fops = {
1325 .owner = THIS_MODULE,
1326 .open = radeon_ttm_vram_open,
1327 .read = radeon_ttm_vram_read,
1328 .llseek = default_llseek
1329 };
1330
1331 static int radeon_ttm_gtt_open(struct inode *inode, struct file *filep)
1332 {
1333 struct radeon_device *rdev = inode->i_private;
1334 i_size_write(inode, rdev->mc.gtt_size);
1335 filep->private_data = inode->i_private;
1336 return 0;
1337 }
1338
1339 static ssize_t radeon_ttm_gtt_read(struct file *f, char __user *buf,
1340 size_t size, loff_t *pos)
1341 {
1342 struct radeon_device *rdev = f->private_data;
1343 ssize_t result = 0;
1344 int r;
1345
1346 while (size) {
1347 loff_t p = *pos / PAGE_SIZE;
1348 unsigned off = *pos & ~PAGE_MASK;
1349 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
1350 struct page *page;
1351 void *ptr;
1352
1353 if (p >= rdev->gart.num_cpu_pages)
1354 return result;
1355
1356 page = rdev->gart.pages[p];
1357 if (page) {
1358 ptr = kmap(page);
1359 ptr += off;
1360
1361 r = copy_to_user(buf, ptr, cur_size);
1362 kunmap(rdev->gart.pages[p]);
1363 } else
1364 r = clear_user(buf, cur_size);
1365
1366 if (r)
1367 return -EFAULT;
1368
1369 result += cur_size;
1370 buf += cur_size;
1371 *pos += cur_size;
1372 size -= cur_size;
1373 }
1374
1375 return result;
1376 }
1377
1378 static const struct file_operations radeon_ttm_gtt_fops = {
1379 .owner = THIS_MODULE,
1380 .open = radeon_ttm_gtt_open,
1381 .read = radeon_ttm_gtt_read,
1382 .llseek = default_llseek
1383 };
1384
1385 #endif
1386
1387 static int radeon_ttm_debugfs_init(struct radeon_device *rdev)
1388 {
1389 #if defined(CONFIG_DEBUG_FS)
1390 unsigned count;
1391
1392 struct drm_minor *minor = rdev->ddev->primary;
1393 struct dentry *ent, *root = minor->debugfs_root;
1394
1395 ent = debugfs_create_file("radeon_vram", S_IFREG | S_IRUGO, root,
1396 rdev, &radeon_ttm_vram_fops);
1397 if (IS_ERR(ent))
1398 return PTR_ERR(ent);
1399 rdev->mman.vram = ent;
1400
1401 ent = debugfs_create_file("radeon_gtt", S_IFREG | S_IRUGO, root,
1402 rdev, &radeon_ttm_gtt_fops);
1403 if (IS_ERR(ent))
1404 return PTR_ERR(ent);
1405 rdev->mman.gtt = ent;
1406
1407 count = ARRAY_SIZE(radeon_ttm_debugfs_list);
1408
1409 #ifdef CONFIG_SWIOTLB
1410 if (!swiotlb_nr_tbl())
1411 --count;
1412 #endif
1413
1414 return radeon_debugfs_add_files(rdev, radeon_ttm_debugfs_list, count);
1415 #else
1416
1417 return 0;
1418 #endif
1419 }
1420
1421 static void radeon_ttm_debugfs_fini(struct radeon_device *rdev)
1422 {
1423 #if defined(CONFIG_DEBUG_FS)
1424
1425 debugfs_remove(rdev->mman.vram);
1426 rdev->mman.vram = NULL;
1427
1428 debugfs_remove(rdev->mman.gtt);
1429 rdev->mman.gtt = NULL;
1430 #endif
1431 }
1432