radeon_ttm.c revision 1.25 1 /* $NetBSD: radeon_ttm.c,v 1.25 2022/05/21 17:50:21 riastradh Exp $ */
2
3 /*
4 * Copyright 2009 Jerome Glisse.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * The above copyright notice and this permission notice (including the
24 * next paragraph) shall be included in all copies or substantial portions
25 * of the Software.
26 *
27 */
28 /*
29 * Authors:
30 * Jerome Glisse <glisse (at) freedesktop.org>
31 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
32 * Dave Airlie
33 */
34
35 #include <sys/cdefs.h>
36 __KERNEL_RCSID(0, "$NetBSD: radeon_ttm.c,v 1.25 2022/05/21 17:50:21 riastradh Exp $");
37
38 #include <linux/dma-mapping.h>
39 #include <linux/pagemap.h>
40 #include <linux/pci.h>
41 #include <linux/seq_file.h>
42 #include <linux/slab.h>
43 #include <linux/swap.h>
44 #include <linux/swiotlb.h>
45
46 #include <drm/drm_agpsupport.h>
47 #include <drm/drm_debugfs.h>
48 #include <drm/drm_device.h>
49 #include <drm/drm_file.h>
50 #include <drm/drm_prime.h>
51 #include <drm/radeon_drm.h>
52 #include <drm/ttm/ttm_bo_api.h>
53 #include <drm/ttm/ttm_bo_driver.h>
54 #include <drm/ttm/ttm_module.h>
55 #include <drm/ttm/ttm_page_alloc.h>
56 #include <drm/ttm/ttm_placement.h>
57
58 #include "radeon_reg.h"
59 #include "radeon.h"
60
61 #ifdef __NetBSD__
62 #include <uvm/uvm_extern.h>
63 #include <uvm/uvm_fault.h>
64 #include <uvm/uvm_param.h>
65 #include <drm/bus_dma_hacks.h>
66 #endif
67
68 static int radeon_ttm_debugfs_init(struct radeon_device *rdev);
69 static void radeon_ttm_debugfs_fini(struct radeon_device *rdev);
70
71 static struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev)
72 {
73 struct radeon_mman *mman;
74 struct radeon_device *rdev;
75
76 mman = container_of(bdev, struct radeon_mman, bdev);
77 rdev = container_of(mman, struct radeon_device, mman);
78 return rdev;
79 }
80
81 static int radeon_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
82 {
83 return 0;
84 }
85
86 static int radeon_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
87 struct ttm_mem_type_manager *man)
88 {
89 struct radeon_device *rdev;
90
91 rdev = radeon_get_rdev(bdev);
92
93 switch (type) {
94 case TTM_PL_SYSTEM:
95 /* System memory */
96 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
97 man->available_caching = TTM_PL_MASK_CACHING;
98 man->default_caching = TTM_PL_FLAG_CACHED;
99 break;
100 case TTM_PL_TT:
101 man->func = &ttm_bo_manager_func;
102 man->gpu_offset = rdev->mc.gtt_start;
103 man->available_caching = TTM_PL_MASK_CACHING;
104 man->default_caching = TTM_PL_FLAG_CACHED;
105 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
106 #if IS_ENABLED(CONFIG_AGP)
107 if (rdev->flags & RADEON_IS_AGP) {
108 if (!rdev->ddev->agp) {
109 DRM_ERROR("AGP is not enabled for memory type %u\n",
110 (unsigned)type);
111 return -EINVAL;
112 }
113 if (!rdev->ddev->agp->cant_use_aperture)
114 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
115 man->available_caching = TTM_PL_FLAG_UNCACHED |
116 TTM_PL_FLAG_WC;
117 man->default_caching = TTM_PL_FLAG_WC;
118 }
119 #endif
120 break;
121 case TTM_PL_VRAM:
122 /* "On-card" video ram */
123 man->func = &ttm_bo_manager_func;
124 man->gpu_offset = rdev->mc.vram_start;
125 man->flags = TTM_MEMTYPE_FLAG_FIXED |
126 TTM_MEMTYPE_FLAG_MAPPABLE;
127 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
128 man->default_caching = TTM_PL_FLAG_WC;
129 break;
130 default:
131 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
132 return -EINVAL;
133 }
134 return 0;
135 }
136
137 static void radeon_evict_flags(struct ttm_buffer_object *bo,
138 struct ttm_placement *placement)
139 {
140 static const struct ttm_place placements = {
141 .fpfn = 0,
142 .lpfn = 0,
143 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM
144 };
145
146 struct radeon_bo *rbo;
147
148 if (!radeon_ttm_bo_is_radeon_bo(bo)) {
149 placement->placement = &placements;
150 placement->busy_placement = &placements;
151 placement->num_placement = 1;
152 placement->num_busy_placement = 1;
153 return;
154 }
155 rbo = container_of(bo, struct radeon_bo, tbo);
156 switch (bo->mem.mem_type) {
157 case TTM_PL_VRAM:
158 if (rbo->rdev->ring[radeon_copy_ring_index(rbo->rdev)].ready == false)
159 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU);
160 else if (rbo->rdev->mc.visible_vram_size < rbo->rdev->mc.real_vram_size &&
161 bo->mem.start < (rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT)) {
162 unsigned fpfn = rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
163 int i;
164
165 /* Try evicting to the CPU inaccessible part of VRAM
166 * first, but only set GTT as busy placement, so this
167 * BO will be evicted to GTT rather than causing other
168 * BOs to be evicted from VRAM
169 */
170 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM |
171 RADEON_GEM_DOMAIN_GTT);
172 rbo->placement.num_busy_placement = 0;
173 for (i = 0; i < rbo->placement.num_placement; i++) {
174 if (rbo->placements[i].flags & TTM_PL_FLAG_VRAM) {
175 if (rbo->placements[i].fpfn < fpfn)
176 rbo->placements[i].fpfn = fpfn;
177 } else {
178 rbo->placement.busy_placement =
179 &rbo->placements[i];
180 rbo->placement.num_busy_placement = 1;
181 }
182 }
183 } else
184 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT);
185 break;
186 case TTM_PL_TT:
187 default:
188 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU);
189 }
190 *placement = rbo->placement;
191 }
192
193 static int radeon_verify_access(struct ttm_buffer_object *bo, struct file *filp)
194 {
195 struct radeon_bo *rbo = container_of(bo, struct radeon_bo, tbo);
196
197 if (radeon_ttm_tt_has_userptr(bo->ttm))
198 return -EPERM;
199 #ifdef __NetBSD__
200 struct drm_file *drm_file = filp->f_data;
201 return drm_vma_node_verify_access(&rbo->tbo.base.vma_node, drm_file);
202 #else
203 return drm_vma_node_verify_access(&rbo->tbo.base.vma_node,
204 filp->private_data);
205 #endif
206 }
207
208 static void radeon_move_null(struct ttm_buffer_object *bo,
209 struct ttm_mem_reg *new_mem)
210 {
211 struct ttm_mem_reg *old_mem = &bo->mem;
212
213 BUG_ON(old_mem->mm_node != NULL);
214 *old_mem = *new_mem;
215 new_mem->mm_node = NULL;
216 }
217
218 static int radeon_move_blit(struct ttm_buffer_object *bo,
219 bool evict, bool no_wait_gpu,
220 struct ttm_mem_reg *new_mem,
221 struct ttm_mem_reg *old_mem)
222 {
223 struct radeon_device *rdev;
224 uint64_t old_start, new_start;
225 struct radeon_fence *fence;
226 unsigned num_pages;
227 int r, ridx;
228
229 rdev = radeon_get_rdev(bo->bdev);
230 ridx = radeon_copy_ring_index(rdev);
231 old_start = (u64)old_mem->start << PAGE_SHIFT;
232 new_start = (u64)new_mem->start << PAGE_SHIFT;
233
234 switch (old_mem->mem_type) {
235 case TTM_PL_VRAM:
236 old_start += rdev->mc.vram_start;
237 break;
238 case TTM_PL_TT:
239 old_start += rdev->mc.gtt_start;
240 break;
241 default:
242 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
243 return -EINVAL;
244 }
245 switch (new_mem->mem_type) {
246 case TTM_PL_VRAM:
247 new_start += rdev->mc.vram_start;
248 break;
249 case TTM_PL_TT:
250 new_start += rdev->mc.gtt_start;
251 break;
252 default:
253 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
254 return -EINVAL;
255 }
256 if (!rdev->ring[ridx].ready) {
257 DRM_ERROR("Trying to move memory with ring turned off.\n");
258 return -EINVAL;
259 }
260
261 BUILD_BUG_ON((PAGE_SIZE % RADEON_GPU_PAGE_SIZE) != 0);
262
263 num_pages = new_mem->num_pages * (PAGE_SIZE / RADEON_GPU_PAGE_SIZE);
264 fence = radeon_copy(rdev, old_start, new_start, num_pages, bo->base.resv);
265 if (IS_ERR(fence))
266 return PTR_ERR(fence);
267
268 r = ttm_bo_move_accel_cleanup(bo, &fence->base, evict, new_mem);
269 radeon_fence_unref(&fence);
270 return r;
271 }
272
273 static int radeon_move_vram_ram(struct ttm_buffer_object *bo,
274 bool evict, bool interruptible,
275 bool no_wait_gpu,
276 struct ttm_mem_reg *new_mem)
277 {
278 struct ttm_operation_ctx ctx = { interruptible, no_wait_gpu };
279 struct ttm_mem_reg *old_mem = &bo->mem;
280 struct ttm_mem_reg tmp_mem;
281 struct ttm_place placements;
282 struct ttm_placement placement;
283 int r;
284
285 tmp_mem = *new_mem;
286 tmp_mem.mm_node = NULL;
287 placement.num_placement = 1;
288 placement.placement = &placements;
289 placement.num_busy_placement = 1;
290 placement.busy_placement = &placements;
291 placements.fpfn = 0;
292 placements.lpfn = 0;
293 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
294 r = ttm_bo_mem_space(bo, &placement, &tmp_mem, &ctx);
295 if (unlikely(r)) {
296 return r;
297 }
298
299 r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
300 if (unlikely(r)) {
301 goto out_cleanup;
302 }
303
304 r = ttm_tt_bind(bo->ttm, &tmp_mem, &ctx);
305 if (unlikely(r)) {
306 goto out_cleanup;
307 }
308 r = radeon_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem);
309 if (unlikely(r)) {
310 goto out_cleanup;
311 }
312 r = ttm_bo_move_ttm(bo, &ctx, new_mem);
313 out_cleanup:
314 ttm_bo_mem_put(bo, &tmp_mem);
315 return r;
316 }
317
318 static int radeon_move_ram_vram(struct ttm_buffer_object *bo,
319 bool evict, bool interruptible,
320 bool no_wait_gpu,
321 struct ttm_mem_reg *new_mem)
322 {
323 struct ttm_operation_ctx ctx = { interruptible, no_wait_gpu };
324 struct ttm_mem_reg *old_mem = &bo->mem;
325 struct ttm_mem_reg tmp_mem;
326 struct ttm_placement placement;
327 struct ttm_place placements;
328 int r;
329
330 tmp_mem = *new_mem;
331 tmp_mem.mm_node = NULL;
332 placement.num_placement = 1;
333 placement.placement = &placements;
334 placement.num_busy_placement = 1;
335 placement.busy_placement = &placements;
336 placements.fpfn = 0;
337 placements.lpfn = 0;
338 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
339 r = ttm_bo_mem_space(bo, &placement, &tmp_mem, &ctx);
340 if (unlikely(r)) {
341 return r;
342 }
343 r = ttm_bo_move_ttm(bo, &ctx, &tmp_mem);
344 if (unlikely(r)) {
345 goto out_cleanup;
346 }
347 r = radeon_move_blit(bo, true, no_wait_gpu, new_mem, old_mem);
348 if (unlikely(r)) {
349 goto out_cleanup;
350 }
351 out_cleanup:
352 ttm_bo_mem_put(bo, &tmp_mem);
353 return r;
354 }
355
356 static int radeon_bo_move(struct ttm_buffer_object *bo, bool evict,
357 struct ttm_operation_ctx *ctx,
358 struct ttm_mem_reg *new_mem)
359 {
360 struct radeon_device *rdev;
361 struct radeon_bo *rbo;
362 struct ttm_mem_reg *old_mem = &bo->mem;
363 int r;
364
365 r = ttm_bo_wait(bo, ctx->interruptible, ctx->no_wait_gpu);
366 if (r)
367 return r;
368
369 /* Can't move a pinned BO */
370 rbo = container_of(bo, struct radeon_bo, tbo);
371 if (WARN_ON_ONCE(rbo->pin_count > 0))
372 return -EINVAL;
373
374 rdev = radeon_get_rdev(bo->bdev);
375 if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
376 radeon_move_null(bo, new_mem);
377 return 0;
378 }
379 if ((old_mem->mem_type == TTM_PL_TT &&
380 new_mem->mem_type == TTM_PL_SYSTEM) ||
381 (old_mem->mem_type == TTM_PL_SYSTEM &&
382 new_mem->mem_type == TTM_PL_TT)) {
383 /* bind is enough */
384 radeon_move_null(bo, new_mem);
385 return 0;
386 }
387 if (!rdev->ring[radeon_copy_ring_index(rdev)].ready ||
388 rdev->asic->copy.copy == NULL) {
389 /* use memcpy */
390 goto memcpy;
391 }
392
393 if (old_mem->mem_type == TTM_PL_VRAM &&
394 new_mem->mem_type == TTM_PL_SYSTEM) {
395 r = radeon_move_vram_ram(bo, evict, ctx->interruptible,
396 ctx->no_wait_gpu, new_mem);
397 } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
398 new_mem->mem_type == TTM_PL_VRAM) {
399 r = radeon_move_ram_vram(bo, evict, ctx->interruptible,
400 ctx->no_wait_gpu, new_mem);
401 } else {
402 r = radeon_move_blit(bo, evict, ctx->no_wait_gpu,
403 new_mem, old_mem);
404 }
405
406 if (r) {
407 memcpy:
408 r = ttm_bo_move_memcpy(bo, ctx, new_mem);
409 if (r) {
410 return r;
411 }
412 }
413
414 /* update statistics */
415 atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &rdev->num_bytes_moved);
416 return 0;
417 }
418
419 static int radeon_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
420 {
421 struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
422 struct radeon_device *rdev = radeon_get_rdev(bdev);
423
424 mem->bus.addr = NULL;
425 mem->bus.offset = 0;
426 mem->bus.size = mem->num_pages << PAGE_SHIFT;
427 mem->bus.base = 0;
428 mem->bus.is_iomem = false;
429 if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
430 return -EINVAL;
431 switch (mem->mem_type) {
432 case TTM_PL_SYSTEM:
433 /* system memory */
434 return 0;
435 case TTM_PL_TT:
436 #if IS_ENABLED(CONFIG_AGP)
437 if (rdev->flags & RADEON_IS_AGP) {
438 /* RADEON_IS_AGP is set only if AGP is active */
439 mem->bus.offset = mem->start << PAGE_SHIFT;
440 mem->bus.base = rdev->mc.agp_base;
441 mem->bus.is_iomem = !rdev->ddev->agp->cant_use_aperture;
442 KASSERTMSG((mem->bus.base & (PAGE_SIZE - 1)) == 0,
443 "agp aperture is not page-aligned: %" PRIx64 "",
444 (uint64_t)mem->bus.base);
445 KASSERT((mem->bus.offset & (PAGE_SIZE - 1)) == 0);
446 }
447 #endif
448 break;
449 case TTM_PL_VRAM:
450 mem->bus.offset = mem->start << PAGE_SHIFT;
451 /* check if it's visible */
452 if ((mem->bus.offset + mem->bus.size) > rdev->mc.visible_vram_size)
453 return -EINVAL;
454 mem->bus.base = rdev->mc.aper_base;
455 mem->bus.is_iomem = true;
456 #ifdef __alpha__
457 /*
458 * Alpha: use bus.addr to hold the ioremap() return,
459 * so we can modify bus.base below.
460 */
461 if (mem->placement & TTM_PL_FLAG_WC)
462 mem->bus.addr =
463 ioremap_wc(mem->bus.base + mem->bus.offset,
464 mem->bus.size);
465 else
466 mem->bus.addr =
467 ioremap(mem->bus.base + mem->bus.offset,
468 mem->bus.size);
469 if (!mem->bus.addr)
470 return -ENOMEM;
471
472 /*
473 * Alpha: Use just the bus offset plus
474 * the hose/domain memory base for bus.base.
475 * It then can be used to build PTEs for VRAM
476 * access, as done in ttm_bo_vm_fault().
477 */
478 mem->bus.base = (mem->bus.base & 0x0ffffffffUL) +
479 rdev->ddev->hose->dense_mem_base;
480 #endif
481 KASSERTMSG((mem->bus.base & (PAGE_SIZE - 1)) == 0,
482 "mc aperture is not page-aligned: %" PRIx64 "",
483 (uint64_t)mem->bus.base);
484 KASSERT((mem->bus.offset & (PAGE_SIZE - 1)) == 0);
485 break;
486 default:
487 return -EINVAL;
488 }
489 return 0;
490 }
491
492 static void radeon_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
493 {
494 }
495
496 /*
497 * TTM backend functions.
498 */
499 struct radeon_ttm_tt {
500 struct ttm_dma_tt ttm;
501 struct radeon_device *rdev;
502 u64 offset;
503
504 uint64_t userptr;
505 #ifdef __NetBSD__
506 struct vmspace *usermm;
507 #else
508 struct mm_struct *usermm;
509 #endif
510 uint32_t userflags;
511 };
512
513 /* prepare the sg table with the user pages */
514 static int radeon_ttm_tt_pin_userptr(struct ttm_tt *ttm)
515 {
516 struct radeon_device *rdev = radeon_get_rdev(ttm->bdev);
517 struct radeon_ttm_tt *gtt = (void *)ttm;
518 #ifndef __NetBSD__
519 unsigned pinned = 0, nents;
520 #endif
521 int r;
522
523 int write = !(gtt->userflags & RADEON_GEM_USERPTR_READONLY);
524 #ifndef __NetBSD__
525 enum dma_data_direction direction = write ?
526 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
527 #endif
528
529 #ifdef __NetBSD__
530 if (curproc->p_vmspace != gtt->usermm)
531 return -EPERM;
532 #else
533 if (current->mm != gtt->usermm)
534 return -EPERM;
535 #endif
536
537 if (gtt->userflags & RADEON_GEM_USERPTR_ANONONLY) {
538 /* check that we only pin down anonymous memory
539 to prevent problems with writeback */
540 unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE;
541 #ifdef __NetBSD__
542 /* XXX ??? TOCTOU, anyone? */
543 /* XXX should do range_test */
544 struct vm_map_entry *entry;
545 bool ok;
546 vm_map_lock_read(>t->usermm->vm_map);
547 ok = uvm_map_lookup_entry(>t->usermm->vm_map,
548 (vaddr_t)gtt->userptr, &entry);
549 if (ok)
550 ok = !UVM_ET_ISOBJ(entry) && end <= entry->end;
551 vm_map_unlock_read(>t->usermm->vm_map);
552 if (!ok)
553 return -EPERM;
554 #else
555 struct vm_area_struct *vma;
556 vma = find_vma(gtt->usermm, gtt->userptr);
557 if (!vma || vma->vm_file || vma->vm_end < end)
558 return -EPERM;
559 #endif
560 }
561
562 #ifdef __NetBSD__
563 struct iovec iov = {
564 .iov_base = (void *)(vaddr_t)gtt->userptr,
565 .iov_len = ttm->num_pages << PAGE_SHIFT,
566 };
567 struct uio uio = {
568 .uio_iov = &iov,
569 .uio_iovcnt = 1,
570 .uio_offset = 0,
571 .uio_resid = ttm->num_pages << PAGE_SHIFT,
572 .uio_rw = (write ? UIO_READ : UIO_WRITE), /* XXX ??? */
573 .uio_vmspace = gtt->usermm,
574 };
575 unsigned long i;
576
577 /* Wire the relevant part of the user's address space. */
578 /* XXX What happens if user does munmap? */
579 /* XXX errno NetBSD->Linux */
580 r = -uvm_vslock(gtt->usermm, (void *)(vaddr_t)gtt->userptr,
581 ttm->num_pages << PAGE_SHIFT,
582 (write ? VM_PROT_WRITE : VM_PROT_READ)); /* XXX ??? */
583 if (r)
584 goto fail0;
585
586 /* Load it up for DMA. */
587 /* XXX errno NetBSD->Linux */
588 r = -bus_dmamap_load_uio(rdev->ddev->dmat, gtt->ttm.dma_address, &uio,
589 BUS_DMA_WAITOK);
590 if (r)
591 goto fail1;
592
593 /* Get each of the pages as ttm requests. */
594 for (i = 0; i < ttm->num_pages; i++) {
595 vaddr_t va = (vaddr_t)gtt->userptr + (i << PAGE_SHIFT);
596 paddr_t pa;
597 struct vm_page *vmp;
598
599 if (!pmap_extract(gtt->usermm->vm_map.pmap, va, &pa)) {
600 r = -EFAULT;
601 goto fail2;
602 }
603 vmp = PHYS_TO_VM_PAGE(pa);
604 ttm->pages[i] = container_of(vmp, struct page, p_vmp);
605 }
606
607 /* Success! */
608 return 0;
609
610 fail2: while (i --> 0)
611 ttm->pages[i] = NULL; /* paranoia */
612 bus_dmamap_unload(rdev->ddev->dmat, gtt->ttm.dma_address);
613 fail1: uvm_vsunlock(gtt->usermm, (void *)(vaddr_t)gtt->userptr,
614 ttm->num_pages << PAGE_SHIFT);
615 fail0: return r;
616 #else
617 do {
618 unsigned num_pages = ttm->num_pages - pinned;
619 uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE;
620 struct page **pages = ttm->pages + pinned;
621
622 r = get_user_pages(userptr, num_pages, write ? FOLL_WRITE : 0,
623 pages, NULL);
624 if (r < 0)
625 goto release_pages;
626
627 pinned += r;
628
629 } while (pinned < ttm->num_pages);
630
631 r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
632 ttm->num_pages << PAGE_SHIFT,
633 GFP_KERNEL);
634 if (r)
635 goto release_sg;
636
637 r = -ENOMEM;
638 nents = dma_map_sg(rdev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
639 if (nents != ttm->sg->nents)
640 goto release_sg;
641
642 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
643 gtt->ttm.dma_address, ttm->num_pages);
644
645 return 0;
646
647 release_sg:
648 kfree(ttm->sg);
649
650 release_pages:
651 release_pages(ttm->pages, pinned);
652 return r;
653 #endif
654 }
655
656 static void radeon_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
657 {
658 #ifdef __NetBSD__
659 struct radeon_device *rdev = radeon_get_rdev(ttm->bdev);
660 struct radeon_ttm_tt *gtt = (void *)ttm;
661
662 bus_dmamap_unload(rdev->ddev->dmat, gtt->ttm.dma_address);
663 uvm_vsunlock(gtt->usermm, (void *)(vaddr_t)gtt->userptr,
664 ttm->num_pages << PAGE_SHIFT);
665 #else
666 struct radeon_device *rdev = radeon_get_rdev(ttm->bdev);
667 struct radeon_ttm_tt *gtt = (void *)ttm;
668 struct sg_page_iter sg_iter;
669
670 int write = !(gtt->userflags & RADEON_GEM_USERPTR_READONLY);
671 enum dma_data_direction direction = write ?
672 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
673
674 /* double check that we don't free the table twice */
675 if (!ttm->sg->sgl)
676 return;
677
678 /* free the sg table and pages again */
679 dma_unmap_sg(rdev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
680
681 for_each_sg_page(ttm->sg->sgl, &sg_iter, ttm->sg->nents, 0) {
682 struct page *page = sg_page_iter_page(&sg_iter);
683 if (!(gtt->userflags & RADEON_GEM_USERPTR_READONLY))
684 set_page_dirty(page);
685
686 mark_page_accessed(page);
687 put_page(page);
688 }
689
690 sg_free_table(ttm->sg);
691 #endif
692 }
693
694 static int radeon_ttm_backend_bind(struct ttm_tt *ttm,
695 struct ttm_mem_reg *bo_mem)
696 {
697 struct radeon_ttm_tt *gtt = (void*)ttm;
698 uint32_t flags = RADEON_GART_PAGE_VALID | RADEON_GART_PAGE_READ |
699 RADEON_GART_PAGE_WRITE;
700 int r;
701
702 if (gtt->userptr) {
703 radeon_ttm_tt_pin_userptr(ttm);
704 flags &= ~RADEON_GART_PAGE_WRITE;
705 }
706
707 gtt->offset = (unsigned long)(bo_mem->start << PAGE_SHIFT);
708 if (!ttm->num_pages) {
709 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
710 ttm->num_pages, bo_mem, ttm);
711 }
712 if (ttm->caching_state == tt_cached)
713 flags |= RADEON_GART_PAGE_SNOOP;
714 r = radeon_gart_bind(gtt->rdev, gtt->offset, ttm->num_pages,
715 ttm->pages, gtt->ttm.dma_address, flags);
716 if (r) {
717 DRM_ERROR("failed to bind %lu pages at 0x%08X\n",
718 ttm->num_pages, (unsigned)gtt->offset);
719 return r;
720 }
721 return 0;
722 }
723
724 static int radeon_ttm_backend_unbind(struct ttm_tt *ttm)
725 {
726 struct radeon_ttm_tt *gtt = (void *)ttm;
727
728 radeon_gart_unbind(gtt->rdev, gtt->offset, ttm->num_pages);
729
730 if (gtt->userptr)
731 radeon_ttm_tt_unpin_userptr(ttm);
732
733 return 0;
734 }
735
736 static void radeon_ttm_backend_destroy(struct ttm_tt *ttm)
737 {
738 struct radeon_ttm_tt *gtt = (void *)ttm;
739
740 ttm_dma_tt_fini(>t->ttm);
741 kfree(gtt);
742 }
743
744 static struct ttm_backend_func radeon_backend_func = {
745 .bind = &radeon_ttm_backend_bind,
746 .unbind = &radeon_ttm_backend_unbind,
747 .destroy = &radeon_ttm_backend_destroy,
748 };
749
750 static struct ttm_tt *radeon_ttm_tt_create(struct ttm_buffer_object *bo,
751 uint32_t page_flags)
752 {
753 struct radeon_device *rdev;
754 struct radeon_ttm_tt *gtt;
755
756 rdev = radeon_get_rdev(bo->bdev);
757 #if IS_ENABLED(CONFIG_AGP)
758 if (rdev->flags & RADEON_IS_AGP) {
759 return ttm_agp_tt_create(bo, rdev->ddev->agp->bridge,
760 page_flags);
761 }
762 #endif
763
764 gtt = kzalloc(sizeof(struct radeon_ttm_tt), GFP_KERNEL);
765 if (gtt == NULL) {
766 return NULL;
767 }
768 gtt->ttm.ttm.func = &radeon_backend_func;
769 gtt->rdev = rdev;
770 if (ttm_dma_tt_init(>t->ttm, bo, page_flags)) {
771 kfree(gtt);
772 return NULL;
773 }
774 return >t->ttm.ttm;
775 }
776
777 static struct radeon_ttm_tt *radeon_ttm_tt_to_gtt(struct ttm_tt *ttm)
778 {
779 if (!ttm || ttm->func != &radeon_backend_func)
780 return NULL;
781 return (struct radeon_ttm_tt *)ttm;
782 }
783
784 static int radeon_ttm_tt_populate(struct ttm_tt *ttm,
785 struct ttm_operation_ctx *ctx)
786 {
787 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm);
788 #if !defined(__NetBSD__) || IS_ENABLED(CONFIG_AGP)
789 struct radeon_device *rdev;
790 #endif
791 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
792
793 if (gtt && gtt->userptr) {
794 #ifdef __NetBSD__
795 ttm->sg = NULL;
796 #else
797 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
798 if (!ttm->sg)
799 return -ENOMEM;
800 #endif
801
802 ttm->page_flags |= TTM_PAGE_FLAG_SG;
803 ttm->state = tt_unbound;
804 return 0;
805 }
806
807 if (slave && ttm->sg) {
808 #ifdef __NetBSD__
809 int r = drm_prime_bus_dmamap_load_sgt(ttm->bdev->dmat,
810 gtt->ttm.dma_address, ttm->sg);
811 if (r)
812 return r;
813 #else
814 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
815 gtt->ttm.dma_address, ttm->num_pages);
816 #endif
817 ttm->state = tt_unbound;
818 return 0;
819 }
820
821 #if !defined(__NetBSD__) || IS_ENABLED(CONFIG_AGP)
822 rdev = radeon_get_rdev(ttm->bdev);
823 #endif
824 #if IS_ENABLED(CONFIG_AGP)
825 if (rdev->flags & RADEON_IS_AGP) {
826 return ttm_agp_tt_populate(ttm, ctx);
827 }
828 #endif
829
830 #ifdef __NetBSD__
831 /* XXX errno NetBSD->Linux */
832 return ttm_bus_dma_populate(>t->ttm);
833 #else
834
835 #ifdef CONFIG_SWIOTLB
836 if (rdev->need_swiotlb && swiotlb_nr_tbl()) {
837 return ttm_dma_populate(>t->ttm, rdev->dev, ctx);
838 }
839 #endif
840
841 return ttm_populate_and_map_pages(rdev->dev, >t->ttm, ctx);
842 #endif
843 }
844
845 static void radeon_ttm_tt_unpopulate(struct ttm_tt *ttm)
846 {
847 #if !defined(__NetBSD__) || IS_ENABLED(CONFIG_AGP)
848 struct radeon_device *rdev;
849 #endif
850 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm);
851 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
852
853 #ifdef __NetBSD__
854 if (slave && ttm->sg) {
855 bus_dmamap_unload(ttm->bdev->dmat, gtt->ttm.dma_address);
856 }
857 #endif
858 if (gtt && gtt->userptr) {
859 kfree(ttm->sg);
860 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
861 return;
862 }
863
864 if (slave)
865 return;
866
867 #if !defined(__NetBSD__) || IS_ENABLED(CONFIG_AGP)
868 rdev = radeon_get_rdev(ttm->bdev);
869 #endif
870 #if IS_ENABLED(CONFIG_AGP)
871 if (rdev->flags & RADEON_IS_AGP) {
872 ttm_agp_tt_unpopulate(ttm);
873 return;
874 }
875 #endif
876
877 #ifdef __NetBSD__
878 ttm_bus_dma_unpopulate(>t->ttm);
879 return;
880 #else
881
882 #ifdef CONFIG_SWIOTLB
883 if (rdev->need_swiotlb && swiotlb_nr_tbl()) {
884 ttm_dma_unpopulate(>t->ttm, rdev->dev);
885 return;
886 }
887 #endif
888
889 ttm_unmap_and_unpopulate_pages(rdev->dev, >t->ttm);
890 #endif
891 }
892
893 #ifdef __NetBSD__
894 static void radeon_ttm_tt_swapout(struct ttm_tt *ttm)
895 {
896 struct radeon_ttm_tt *gtt = container_of(ttm, struct radeon_ttm_tt,
897 ttm.ttm);
898 struct ttm_dma_tt *ttm_dma = >t->ttm;
899
900 ttm_bus_dma_swapout(ttm_dma);
901 }
902
903 static int radeon_ttm_fault(struct uvm_faultinfo *, vaddr_t,
904 struct vm_page **, int, int, vm_prot_t, int);
905
906 static const struct uvm_pagerops radeon_uvm_ops = {
907 .pgo_reference = &ttm_bo_uvm_reference,
908 .pgo_detach = &ttm_bo_uvm_detach,
909 .pgo_fault = &radeon_ttm_fault,
910 };
911 #endif
912
913 int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
914 uint32_t flags)
915 {
916 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm);
917
918 if (gtt == NULL)
919 return -EINVAL;
920
921 gtt->userptr = addr;
922 #ifdef __NetBSD__
923 gtt->usermm = curproc->p_vmspace;
924 #else
925 gtt->usermm = current->mm;
926 #endif
927 gtt->userflags = flags;
928 return 0;
929 }
930
931 bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm)
932 {
933 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm);
934
935 if (gtt == NULL)
936 return false;
937
938 return !!gtt->userptr;
939 }
940
941 bool radeon_ttm_tt_is_readonly(struct ttm_tt *ttm)
942 {
943 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm);
944
945 if (gtt == NULL)
946 return false;
947
948 return !!(gtt->userflags & RADEON_GEM_USERPTR_READONLY);
949 }
950
951 static struct ttm_bo_driver radeon_bo_driver = {
952 .ttm_tt_create = &radeon_ttm_tt_create,
953 .ttm_tt_populate = &radeon_ttm_tt_populate,
954 .ttm_tt_unpopulate = &radeon_ttm_tt_unpopulate,
955 #ifdef __NetBSD__
956 .ttm_tt_swapout = &radeon_ttm_tt_swapout,
957 .ttm_uvm_ops = &radeon_uvm_ops,
958 #endif
959 .invalidate_caches = &radeon_invalidate_caches,
960 .init_mem_type = &radeon_init_mem_type,
961 .eviction_valuable = ttm_bo_eviction_valuable,
962 .evict_flags = &radeon_evict_flags,
963 .move = &radeon_bo_move,
964 .verify_access = &radeon_verify_access,
965 .move_notify = &radeon_bo_move_notify,
966 .fault_reserve_notify = &radeon_bo_fault_reserve_notify,
967 .io_mem_reserve = &radeon_ttm_io_mem_reserve,
968 .io_mem_free = &radeon_ttm_io_mem_free,
969 };
970
971 int radeon_ttm_init(struct radeon_device *rdev)
972 {
973 int r;
974
975 /* No others user of address space so set it to 0 */
976 r = ttm_bo_device_init(&rdev->mman.bdev,
977 &radeon_bo_driver,
978 #ifdef __NetBSD__
979 rdev->ddev->bst,
980 rdev->ddev->dmat,
981 #else
982 rdev->ddev->anon_inode->i_mapping,
983 #endif
984 rdev->ddev->vma_offset_manager,
985 dma_addressing_limited(pci_dev_dev(rdev->pdev)));
986 if (r) {
987 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
988 return r;
989 }
990 rdev->mman.initialized = true;
991 r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_VRAM,
992 rdev->mc.real_vram_size >> PAGE_SHIFT);
993 if (r) {
994 DRM_ERROR("Failed initializing VRAM heap.\n");
995 return r;
996 }
997 /* Change the size here instead of the init above so only lpfn is affected */
998 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
999
1000 r = radeon_bo_create(rdev, 256 * 1024, PAGE_SIZE, true,
1001 RADEON_GEM_DOMAIN_VRAM, 0, NULL,
1002 NULL, &rdev->stolen_vga_memory);
1003 if (r) {
1004 return r;
1005 }
1006 r = radeon_bo_reserve(rdev->stolen_vga_memory, false);
1007 if (r)
1008 return r;
1009 r = radeon_bo_pin(rdev->stolen_vga_memory, RADEON_GEM_DOMAIN_VRAM, NULL);
1010 radeon_bo_unreserve(rdev->stolen_vga_memory);
1011 if (r) {
1012 radeon_bo_unref(&rdev->stolen_vga_memory);
1013 return r;
1014 }
1015 DRM_INFO("radeon: %uM of VRAM memory ready\n",
1016 (unsigned) (rdev->mc.real_vram_size / (1024 * 1024)));
1017 r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_TT,
1018 rdev->mc.gtt_size >> PAGE_SHIFT);
1019 if (r) {
1020 DRM_ERROR("Failed initializing GTT heap.\n");
1021 return r;
1022 }
1023 DRM_INFO("radeon: %uM of GTT memory ready.\n",
1024 (unsigned)(rdev->mc.gtt_size / (1024 * 1024)));
1025
1026 r = radeon_ttm_debugfs_init(rdev);
1027 if (r) {
1028 DRM_ERROR("Failed to init debugfs\n");
1029 return r;
1030 }
1031 return 0;
1032 }
1033
1034 void radeon_ttm_fini(struct radeon_device *rdev)
1035 {
1036 int r;
1037
1038 if (!rdev->mman.initialized)
1039 return;
1040 radeon_ttm_debugfs_fini(rdev);
1041 if (rdev->stolen_vga_memory) {
1042 r = radeon_bo_reserve(rdev->stolen_vga_memory, false);
1043 if (r == 0) {
1044 radeon_bo_unpin(rdev->stolen_vga_memory);
1045 radeon_bo_unreserve(rdev->stolen_vga_memory);
1046 }
1047 radeon_bo_unref(&rdev->stolen_vga_memory);
1048 }
1049 ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_VRAM);
1050 ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_TT);
1051 ttm_bo_device_release(&rdev->mman.bdev);
1052 radeon_gart_fini(rdev);
1053 rdev->mman.initialized = false;
1054 DRM_INFO("radeon: ttm finalized\n");
1055 }
1056
1057 /* this should only be called at bootup or when userspace
1058 * isn't running */
1059 void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size)
1060 {
1061 struct ttm_mem_type_manager *man;
1062
1063 if (!rdev->mman.initialized)
1064 return;
1065
1066 man = &rdev->mman.bdev.man[TTM_PL_VRAM];
1067 /* this just adjusts TTM size idea, which sets lpfn to the correct value */
1068 man->size = size >> PAGE_SHIFT;
1069 }
1070
1071 #ifdef __NetBSD__
1072
1073 static int
1074 radeon_ttm_fault(struct uvm_faultinfo *ufi, vaddr_t vaddr,
1075 struct vm_page **pps, int npages, int centeridx, vm_prot_t access_type,
1076 int flags)
1077 {
1078 struct uvm_object *const uobj = ufi->entry->object.uvm_obj;
1079 struct ttm_buffer_object *const bo = container_of(uobj,
1080 struct ttm_buffer_object, uvmobj);
1081 struct radeon_device *const rdev = radeon_get_rdev(bo->bdev);
1082 int error;
1083
1084 KASSERT(rdev != NULL);
1085 down_read(&rdev->pm.mclk_lock);
1086 error = ttm_bo_uvm_fault(ufi, vaddr, pps, npages, centeridx,
1087 access_type, flags);
1088 up_read(&rdev->pm.mclk_lock);
1089
1090 return error;
1091 }
1092
1093 int
1094 radeon_mmap_object(struct drm_device *dev, off_t offset, size_t size,
1095 vm_prot_t prot, struct uvm_object **uobjp, voff_t *uoffsetp,
1096 struct file *file)
1097 {
1098 struct radeon_device *rdev = dev->dev_private;
1099
1100 KASSERT(0 == (offset & (PAGE_SIZE - 1)));
1101
1102 if (__predict_false(rdev == NULL)) /* XXX How?? */
1103 return -EINVAL;
1104
1105 return ttm_bo_mmap_object(&rdev->mman.bdev, offset, size, prot,
1106 uobjp, uoffsetp, file);
1107 }
1108
1109 #else
1110
1111 static vm_fault_t radeon_ttm_fault(struct vm_fault *vmf)
1112 {
1113 struct ttm_buffer_object *bo;
1114 struct radeon_device *rdev;
1115 vm_fault_t ret;
1116
1117 bo = (struct ttm_buffer_object *)vmf->vma->vm_private_data;
1118 if (bo == NULL)
1119 return VM_FAULT_NOPAGE;
1120
1121 rdev = radeon_get_rdev(bo->bdev);
1122 down_read(&rdev->pm.mclk_lock);
1123 ret = ttm_bo_vm_fault(vmf);
1124 up_read(&rdev->pm.mclk_lock);
1125 return ret;
1126 }
1127
1128 static struct vm_operations_struct radeon_ttm_vm_ops = {
1129 .fault = radeon_ttm_fault,
1130 .open = ttm_bo_vm_open,
1131 .close = ttm_bo_vm_close,
1132 .access = ttm_bo_vm_access
1133 };
1134
1135 int radeon_mmap(struct file *filp, struct vm_area_struct *vma)
1136 {
1137 int r;
1138 struct drm_file *file_priv = filp->private_data;
1139 struct radeon_device *rdev = file_priv->minor->dev->dev_private;
1140
1141 if (rdev == NULL)
1142 return -EINVAL;
1143
1144 r = ttm_bo_mmap(filp, vma, &rdev->mman.bdev);
1145 if (unlikely(r != 0))
1146 return r;
1147
1148 vma->vm_ops = &radeon_ttm_vm_ops;
1149 return 0;
1150 }
1151
1152 #endif /* __NetBSD__ */
1153
1154 #if defined(CONFIG_DEBUG_FS)
1155
1156 static int radeon_mm_dump_table(struct seq_file *m, void *data)
1157 {
1158 struct drm_info_node *node = (struct drm_info_node *)m->private;
1159 unsigned ttm_pl = *(int*)node->info_ent->data;
1160 struct drm_device *dev = node->minor->dev;
1161 struct radeon_device *rdev = dev->dev_private;
1162 struct ttm_mem_type_manager *man = &rdev->mman.bdev.man[ttm_pl];
1163 struct drm_printer p = drm_seq_file_printer(m);
1164
1165 man->func->debug(man, &p);
1166 return 0;
1167 }
1168
1169
1170 static int ttm_pl_vram = TTM_PL_VRAM;
1171 static int ttm_pl_tt = TTM_PL_TT;
1172
1173 static struct drm_info_list radeon_ttm_debugfs_list[] = {
1174 {"radeon_vram_mm", radeon_mm_dump_table, 0, &ttm_pl_vram},
1175 {"radeon_gtt_mm", radeon_mm_dump_table, 0, &ttm_pl_tt},
1176 {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
1177 #ifdef CONFIG_SWIOTLB
1178 {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
1179 #endif
1180 };
1181
1182 static int radeon_ttm_vram_open(struct inode *inode, struct file *filep)
1183 {
1184 struct radeon_device *rdev = inode->i_private;
1185 i_size_write(inode, rdev->mc.mc_vram_size);
1186 filep->private_data = inode->i_private;
1187 return 0;
1188 }
1189
1190 static ssize_t radeon_ttm_vram_read(struct file *f, char __user *buf,
1191 size_t size, loff_t *pos)
1192 {
1193 struct radeon_device *rdev = f->private_data;
1194 ssize_t result = 0;
1195 int r;
1196
1197 if (size & 0x3 || *pos & 0x3)
1198 return -EINVAL;
1199
1200 while (size) {
1201 unsigned long flags;
1202 uint32_t value;
1203
1204 if (*pos >= rdev->mc.mc_vram_size)
1205 return result;
1206
1207 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
1208 WREG32(RADEON_MM_INDEX, ((uint32_t)*pos) | 0x80000000);
1209 if (rdev->family >= CHIP_CEDAR)
1210 WREG32(EVERGREEN_MM_INDEX_HI, *pos >> 31);
1211 value = RREG32(RADEON_MM_DATA);
1212 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
1213
1214 r = put_user(value, (uint32_t *)buf);
1215 if (r)
1216 return r;
1217
1218 result += 4;
1219 buf += 4;
1220 *pos += 4;
1221 size -= 4;
1222 }
1223
1224 return result;
1225 }
1226
1227 static const struct file_operations radeon_ttm_vram_fops = {
1228 .owner = THIS_MODULE,
1229 .open = radeon_ttm_vram_open,
1230 .read = radeon_ttm_vram_read,
1231 .llseek = default_llseek
1232 };
1233
1234 static int radeon_ttm_gtt_open(struct inode *inode, struct file *filep)
1235 {
1236 struct radeon_device *rdev = inode->i_private;
1237 i_size_write(inode, rdev->mc.gtt_size);
1238 filep->private_data = inode->i_private;
1239 return 0;
1240 }
1241
1242 static ssize_t radeon_ttm_gtt_read(struct file *f, char __user *buf,
1243 size_t size, loff_t *pos)
1244 {
1245 struct radeon_device *rdev = f->private_data;
1246 ssize_t result = 0;
1247 int r;
1248
1249 while (size) {
1250 loff_t p = *pos / PAGE_SIZE;
1251 unsigned off = *pos & ~PAGE_MASK;
1252 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
1253 struct page *page;
1254 void *ptr;
1255
1256 if (p >= rdev->gart.num_cpu_pages)
1257 return result;
1258
1259 page = rdev->gart.pages[p];
1260 if (page) {
1261 ptr = kmap(page);
1262 ptr += off;
1263
1264 r = copy_to_user(buf, ptr, cur_size);
1265 kunmap(rdev->gart.pages[p]);
1266 } else
1267 r = clear_user(buf, cur_size);
1268
1269 if (r)
1270 return -EFAULT;
1271
1272 result += cur_size;
1273 buf += cur_size;
1274 *pos += cur_size;
1275 size -= cur_size;
1276 }
1277
1278 return result;
1279 }
1280
1281 static const struct file_operations radeon_ttm_gtt_fops = {
1282 .owner = THIS_MODULE,
1283 .open = radeon_ttm_gtt_open,
1284 .read = radeon_ttm_gtt_read,
1285 .llseek = default_llseek
1286 };
1287
1288 #endif
1289
1290 static int radeon_ttm_debugfs_init(struct radeon_device *rdev)
1291 {
1292 #if defined(CONFIG_DEBUG_FS)
1293 unsigned count;
1294
1295 struct drm_minor *minor = rdev->ddev->primary;
1296 struct dentry *root = minor->debugfs_root;
1297
1298 rdev->mman.vram = debugfs_create_file("radeon_vram", S_IFREG | S_IRUGO,
1299 root, rdev,
1300 &radeon_ttm_vram_fops);
1301
1302 rdev->mman.gtt = debugfs_create_file("radeon_gtt", S_IFREG | S_IRUGO,
1303 root, rdev, &radeon_ttm_gtt_fops);
1304
1305 count = ARRAY_SIZE(radeon_ttm_debugfs_list);
1306
1307 #ifdef CONFIG_SWIOTLB
1308 if (!(rdev->need_swiotlb && swiotlb_nr_tbl()))
1309 --count;
1310 #endif
1311
1312 return radeon_debugfs_add_files(rdev, radeon_ttm_debugfs_list, count);
1313 #else
1314
1315 return 0;
1316 #endif
1317 }
1318
1319 static void radeon_ttm_debugfs_fini(struct radeon_device *rdev)
1320 {
1321 #if defined(CONFIG_DEBUG_FS)
1322
1323 debugfs_remove(rdev->mman.vram);
1324 rdev->mman.vram = NULL;
1325
1326 debugfs_remove(rdev->mman.gtt);
1327 rdev->mman.gtt = NULL;
1328 #endif
1329 }
1330