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radeon_ttm.c revision 1.5.2.2
      1 /*
      2  * Copyright 2009 Jerome Glisse.
      3  * All Rights Reserved.
      4  *
      5  * Permission is hereby granted, free of charge, to any person obtaining a
      6  * copy of this software and associated documentation files (the
      7  * "Software"), to deal in the Software without restriction, including
      8  * without limitation the rights to use, copy, modify, merge, publish,
      9  * distribute, sub license, and/or sell copies of the Software, and to
     10  * permit persons to whom the Software is furnished to do so, subject to
     11  * the following conditions:
     12  *
     13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
     16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
     17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
     18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
     19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
     20  *
     21  * The above copyright notice and this permission notice (including the
     22  * next paragraph) shall be included in all copies or substantial portions
     23  * of the Software.
     24  *
     25  */
     26 /*
     27  * Authors:
     28  *    Jerome Glisse <glisse (at) freedesktop.org>
     29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
     30  *    Dave Airlie
     31  */
     32 #include <ttm/ttm_bo_api.h>
     33 #include <ttm/ttm_bo_driver.h>
     34 #include <ttm/ttm_placement.h>
     35 #include <ttm/ttm_module.h>
     36 #include <ttm/ttm_page_alloc.h>
     37 #include <drm/drmP.h>
     38 #include <drm/radeon_drm.h>
     39 #include <linux/seq_file.h>
     40 #include <linux/slab.h>
     41 #include <linux/swiotlb.h>
     42 #include <linux/debugfs.h>
     43 #include "radeon_reg.h"
     44 #include "radeon.h"
     45 
     46 #ifdef __NetBSD__
     47 #include <uvm/uvm_extern.h>
     48 #include <uvm/uvm_fault.h>
     49 #include <uvm/uvm_param.h>
     50 #include <drm/bus_dma_hacks.h>
     51 #endif
     52 
     53 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
     54 
     55 static int radeon_ttm_debugfs_init(struct radeon_device *rdev);
     56 static void radeon_ttm_debugfs_fini(struct radeon_device *rdev);
     57 
     58 static struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev)
     59 {
     60 	struct radeon_mman *mman;
     61 	struct radeon_device *rdev;
     62 
     63 	mman = container_of(bdev, struct radeon_mman, bdev);
     64 	rdev = container_of(mman, struct radeon_device, mman);
     65 	return rdev;
     66 }
     67 
     68 
     69 /*
     70  * Global memory.
     71  */
     72 static int radeon_ttm_mem_global_init(struct drm_global_reference *ref)
     73 {
     74 	return ttm_mem_global_init(ref->object);
     75 }
     76 
     77 static void radeon_ttm_mem_global_release(struct drm_global_reference *ref)
     78 {
     79 	ttm_mem_global_release(ref->object);
     80 }
     81 
     82 static int radeon_ttm_global_init(struct radeon_device *rdev)
     83 {
     84 	struct drm_global_reference *global_ref;
     85 	int r;
     86 
     87 	rdev->mman.mem_global_referenced = false;
     88 	global_ref = &rdev->mman.mem_global_ref;
     89 	global_ref->global_type = DRM_GLOBAL_TTM_MEM;
     90 	global_ref->size = sizeof(struct ttm_mem_global);
     91 	global_ref->init = &radeon_ttm_mem_global_init;
     92 	global_ref->release = &radeon_ttm_mem_global_release;
     93 	r = drm_global_item_ref(global_ref);
     94 	if (r != 0) {
     95 		DRM_ERROR("Failed setting up TTM memory accounting "
     96 			  "subsystem.\n");
     97 		return r;
     98 	}
     99 
    100 	rdev->mman.bo_global_ref.mem_glob =
    101 		rdev->mman.mem_global_ref.object;
    102 	global_ref = &rdev->mman.bo_global_ref.ref;
    103 	global_ref->global_type = DRM_GLOBAL_TTM_BO;
    104 	global_ref->size = sizeof(struct ttm_bo_global);
    105 	global_ref->init = &ttm_bo_global_init;
    106 	global_ref->release = &ttm_bo_global_release;
    107 	r = drm_global_item_ref(global_ref);
    108 	if (r != 0) {
    109 		DRM_ERROR("Failed setting up TTM BO subsystem.\n");
    110 		drm_global_item_unref(&rdev->mman.mem_global_ref);
    111 		return r;
    112 	}
    113 
    114 	rdev->mman.mem_global_referenced = true;
    115 	return 0;
    116 }
    117 
    118 static void radeon_ttm_global_fini(struct radeon_device *rdev)
    119 {
    120 	if (rdev->mman.mem_global_referenced) {
    121 		drm_global_item_unref(&rdev->mman.bo_global_ref.ref);
    122 		drm_global_item_unref(&rdev->mman.mem_global_ref);
    123 		rdev->mman.mem_global_referenced = false;
    124 	}
    125 }
    126 
    127 static int radeon_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
    128 {
    129 	return 0;
    130 }
    131 
    132 static int radeon_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
    133 				struct ttm_mem_type_manager *man)
    134 {
    135 	struct radeon_device *rdev;
    136 
    137 	rdev = radeon_get_rdev(bdev);
    138 
    139 	switch (type) {
    140 	case TTM_PL_SYSTEM:
    141 		/* System memory */
    142 		man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
    143 		man->available_caching = TTM_PL_MASK_CACHING;
    144 		man->default_caching = TTM_PL_FLAG_CACHED;
    145 		break;
    146 	case TTM_PL_TT:
    147 		man->func = &ttm_bo_manager_func;
    148 		man->gpu_offset = rdev->mc.gtt_start;
    149 		man->available_caching = TTM_PL_MASK_CACHING;
    150 		man->default_caching = TTM_PL_FLAG_CACHED;
    151 		man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
    152 #if __OS_HAS_AGP
    153 		if (rdev->flags & RADEON_IS_AGP) {
    154 			if (!rdev->ddev->agp) {
    155 				DRM_ERROR("AGP is not enabled for memory type %u\n",
    156 					  (unsigned)type);
    157 				return -EINVAL;
    158 			}
    159 			if (!rdev->ddev->agp->cant_use_aperture)
    160 				man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
    161 			man->available_caching = TTM_PL_FLAG_UNCACHED |
    162 						 TTM_PL_FLAG_WC;
    163 			man->default_caching = TTM_PL_FLAG_WC;
    164 		}
    165 #endif
    166 		break;
    167 	case TTM_PL_VRAM:
    168 		/* "On-card" video ram */
    169 		man->func = &ttm_bo_manager_func;
    170 		man->gpu_offset = rdev->mc.vram_start;
    171 		man->flags = TTM_MEMTYPE_FLAG_FIXED |
    172 			     TTM_MEMTYPE_FLAG_MAPPABLE;
    173 		man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
    174 		man->default_caching = TTM_PL_FLAG_WC;
    175 		break;
    176 	default:
    177 		DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
    178 		return -EINVAL;
    179 	}
    180 	return 0;
    181 }
    182 
    183 static void radeon_evict_flags(struct ttm_buffer_object *bo,
    184 				struct ttm_placement *placement)
    185 {
    186 	struct radeon_bo *rbo;
    187 	static u32 placements = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
    188 
    189 	if (!radeon_ttm_bo_is_radeon_bo(bo)) {
    190 		placement->fpfn = 0;
    191 		placement->lpfn = 0;
    192 		placement->placement = &placements;
    193 		placement->busy_placement = &placements;
    194 		placement->num_placement = 1;
    195 		placement->num_busy_placement = 1;
    196 		return;
    197 	}
    198 	rbo = container_of(bo, struct radeon_bo, tbo);
    199 	switch (bo->mem.mem_type) {
    200 	case TTM_PL_VRAM:
    201 		if (rbo->rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready == false)
    202 			radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU);
    203 		else
    204 			radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT);
    205 		break;
    206 	case TTM_PL_TT:
    207 	default:
    208 		radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU);
    209 	}
    210 	*placement = rbo->placement;
    211 }
    212 
    213 static int radeon_verify_access(struct ttm_buffer_object *bo, struct file *filp)
    214 {
    215 	struct radeon_bo *rbo = container_of(bo, struct radeon_bo, tbo);
    216 
    217 	return drm_vma_node_verify_access(&rbo->gem_base.vma_node, filp);
    218 }
    219 
    220 static void radeon_move_null(struct ttm_buffer_object *bo,
    221 			     struct ttm_mem_reg *new_mem)
    222 {
    223 	struct ttm_mem_reg *old_mem = &bo->mem;
    224 
    225 	BUG_ON(old_mem->mm_node != NULL);
    226 	*old_mem = *new_mem;
    227 	new_mem->mm_node = NULL;
    228 }
    229 
    230 static int radeon_move_blit(struct ttm_buffer_object *bo,
    231 			bool evict, bool no_wait_gpu,
    232 			struct ttm_mem_reg *new_mem,
    233 			struct ttm_mem_reg *old_mem)
    234 {
    235 	struct radeon_device *rdev;
    236 	uint64_t old_start, new_start;
    237 	struct radeon_fence *fence;
    238 	int r, ridx;
    239 
    240 	rdev = radeon_get_rdev(bo->bdev);
    241 	ridx = radeon_copy_ring_index(rdev);
    242 	old_start = old_mem->start << PAGE_SHIFT;
    243 	new_start = new_mem->start << PAGE_SHIFT;
    244 
    245 	switch (old_mem->mem_type) {
    246 	case TTM_PL_VRAM:
    247 		old_start += rdev->mc.vram_start;
    248 		break;
    249 	case TTM_PL_TT:
    250 		old_start += rdev->mc.gtt_start;
    251 		break;
    252 	default:
    253 		DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
    254 		return -EINVAL;
    255 	}
    256 	switch (new_mem->mem_type) {
    257 	case TTM_PL_VRAM:
    258 		new_start += rdev->mc.vram_start;
    259 		break;
    260 	case TTM_PL_TT:
    261 		new_start += rdev->mc.gtt_start;
    262 		break;
    263 	default:
    264 		DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
    265 		return -EINVAL;
    266 	}
    267 	if (!rdev->ring[ridx].ready) {
    268 		DRM_ERROR("Trying to move memory with ring turned off.\n");
    269 		return -EINVAL;
    270 	}
    271 
    272 	BUILD_BUG_ON((PAGE_SIZE % RADEON_GPU_PAGE_SIZE) != 0);
    273 
    274 	/* sync other rings */
    275 	fence = bo->sync_obj;
    276 	r = radeon_copy(rdev, old_start, new_start,
    277 			new_mem->num_pages * (PAGE_SIZE / RADEON_GPU_PAGE_SIZE), /* GPU pages */
    278 			&fence);
    279 	/* FIXME: handle copy error */
    280 	r = ttm_bo_move_accel_cleanup(bo, (void *)fence,
    281 				      evict, no_wait_gpu, new_mem);
    282 	radeon_fence_unref(&fence);
    283 	return r;
    284 }
    285 
    286 static int radeon_move_vram_ram(struct ttm_buffer_object *bo,
    287 				bool evict, bool interruptible,
    288 				bool no_wait_gpu,
    289 				struct ttm_mem_reg *new_mem)
    290 {
    291 	struct radeon_device *rdev __unused;
    292 	struct ttm_mem_reg *old_mem = &bo->mem;
    293 	struct ttm_mem_reg tmp_mem;
    294 	u32 placements;
    295 	struct ttm_placement placement;
    296 	int r;
    297 
    298 	rdev = radeon_get_rdev(bo->bdev);
    299 	tmp_mem = *new_mem;
    300 	tmp_mem.mm_node = NULL;
    301 	placement.fpfn = 0;
    302 	placement.lpfn = 0;
    303 	placement.num_placement = 1;
    304 	placement.placement = &placements;
    305 	placement.num_busy_placement = 1;
    306 	placement.busy_placement = &placements;
    307 	placements = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
    308 	r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
    309 			     interruptible, no_wait_gpu);
    310 	if (unlikely(r)) {
    311 		return r;
    312 	}
    313 
    314 	r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
    315 	if (unlikely(r)) {
    316 		goto out_cleanup;
    317 	}
    318 
    319 	r = ttm_tt_bind(bo->ttm, &tmp_mem);
    320 	if (unlikely(r)) {
    321 		goto out_cleanup;
    322 	}
    323 	r = radeon_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem);
    324 	if (unlikely(r)) {
    325 		goto out_cleanup;
    326 	}
    327 	r = ttm_bo_move_ttm(bo, true, no_wait_gpu, new_mem);
    328 out_cleanup:
    329 	ttm_bo_mem_put(bo, &tmp_mem);
    330 	return r;
    331 }
    332 
    333 static int radeon_move_ram_vram(struct ttm_buffer_object *bo,
    334 				bool evict, bool interruptible,
    335 				bool no_wait_gpu,
    336 				struct ttm_mem_reg *new_mem)
    337 {
    338 	struct radeon_device *rdev __unused;
    339 	struct ttm_mem_reg *old_mem = &bo->mem;
    340 	struct ttm_mem_reg tmp_mem;
    341 	struct ttm_placement placement;
    342 	u32 placements;
    343 	int r;
    344 
    345 	rdev = radeon_get_rdev(bo->bdev);
    346 	tmp_mem = *new_mem;
    347 	tmp_mem.mm_node = NULL;
    348 	placement.fpfn = 0;
    349 	placement.lpfn = 0;
    350 	placement.num_placement = 1;
    351 	placement.placement = &placements;
    352 	placement.num_busy_placement = 1;
    353 	placement.busy_placement = &placements;
    354 	placements = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
    355 	r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
    356 			     interruptible, no_wait_gpu);
    357 	if (unlikely(r)) {
    358 		return r;
    359 	}
    360 	r = ttm_bo_move_ttm(bo, true, no_wait_gpu, &tmp_mem);
    361 	if (unlikely(r)) {
    362 		goto out_cleanup;
    363 	}
    364 	r = radeon_move_blit(bo, true, no_wait_gpu, new_mem, old_mem);
    365 	if (unlikely(r)) {
    366 		goto out_cleanup;
    367 	}
    368 out_cleanup:
    369 	ttm_bo_mem_put(bo, &tmp_mem);
    370 	return r;
    371 }
    372 
    373 static int radeon_bo_move(struct ttm_buffer_object *bo,
    374 			bool evict, bool interruptible,
    375 			bool no_wait_gpu,
    376 			struct ttm_mem_reg *new_mem)
    377 {
    378 	struct radeon_device *rdev;
    379 	struct ttm_mem_reg *old_mem = &bo->mem;
    380 	int r;
    381 
    382 	rdev = radeon_get_rdev(bo->bdev);
    383 	if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
    384 		radeon_move_null(bo, new_mem);
    385 		return 0;
    386 	}
    387 	if ((old_mem->mem_type == TTM_PL_TT &&
    388 	     new_mem->mem_type == TTM_PL_SYSTEM) ||
    389 	    (old_mem->mem_type == TTM_PL_SYSTEM &&
    390 	     new_mem->mem_type == TTM_PL_TT)) {
    391 		/* bind is enough */
    392 		radeon_move_null(bo, new_mem);
    393 		return 0;
    394 	}
    395 	if (!rdev->ring[radeon_copy_ring_index(rdev)].ready ||
    396 	    rdev->asic->copy.copy == NULL) {
    397 		/* use memcpy */
    398 		goto memcpy;
    399 	}
    400 
    401 	if (old_mem->mem_type == TTM_PL_VRAM &&
    402 	    new_mem->mem_type == TTM_PL_SYSTEM) {
    403 		r = radeon_move_vram_ram(bo, evict, interruptible,
    404 					no_wait_gpu, new_mem);
    405 	} else if (old_mem->mem_type == TTM_PL_SYSTEM &&
    406 		   new_mem->mem_type == TTM_PL_VRAM) {
    407 		r = radeon_move_ram_vram(bo, evict, interruptible,
    408 					    no_wait_gpu, new_mem);
    409 	} else {
    410 		r = radeon_move_blit(bo, evict, no_wait_gpu, new_mem, old_mem);
    411 	}
    412 
    413 	if (r) {
    414 memcpy:
    415 		r = ttm_bo_move_memcpy(bo, evict, no_wait_gpu, new_mem);
    416 		if (r) {
    417 			return r;
    418 		}
    419 	}
    420 
    421 	/* update statistics */
    422 	atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &rdev->num_bytes_moved);
    423 	return 0;
    424 }
    425 
    426 static int radeon_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
    427 {
    428 	struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
    429 	struct radeon_device *rdev = radeon_get_rdev(bdev);
    430 
    431 	mem->bus.addr = NULL;
    432 	mem->bus.offset = 0;
    433 	mem->bus.size = mem->num_pages << PAGE_SHIFT;
    434 	mem->bus.base = 0;
    435 	mem->bus.is_iomem = false;
    436 	if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
    437 		return -EINVAL;
    438 	switch (mem->mem_type) {
    439 	case TTM_PL_SYSTEM:
    440 		/* system memory */
    441 		return 0;
    442 	case TTM_PL_TT:
    443 #if __OS_HAS_AGP
    444 		if (rdev->flags & RADEON_IS_AGP) {
    445 			/* RADEON_IS_AGP is set only if AGP is active */
    446 			mem->bus.offset = mem->start << PAGE_SHIFT;
    447 			mem->bus.base = rdev->mc.agp_base;
    448 			mem->bus.is_iomem = !rdev->ddev->agp->cant_use_aperture;
    449 		}
    450 #endif
    451 		break;
    452 	case TTM_PL_VRAM:
    453 		mem->bus.offset = mem->start << PAGE_SHIFT;
    454 		/* check if it's visible */
    455 		if ((mem->bus.offset + mem->bus.size) > rdev->mc.visible_vram_size)
    456 			return -EINVAL;
    457 		mem->bus.base = rdev->mc.aper_base;
    458 		mem->bus.is_iomem = true;
    459 #ifdef __alpha__
    460 		/*
    461 		 * Alpha: use bus.addr to hold the ioremap() return,
    462 		 * so we can modify bus.base below.
    463 		 */
    464 		if (mem->placement & TTM_PL_FLAG_WC)
    465 			mem->bus.addr =
    466 				ioremap_wc(mem->bus.base + mem->bus.offset,
    467 					   mem->bus.size);
    468 		else
    469 			mem->bus.addr =
    470 				ioremap_nocache(mem->bus.base + mem->bus.offset,
    471 						mem->bus.size);
    472 
    473 		/*
    474 		 * Alpha: Use just the bus offset plus
    475 		 * the hose/domain memory base for bus.base.
    476 		 * It then can be used to build PTEs for VRAM
    477 		 * access, as done in ttm_bo_vm_fault().
    478 		 */
    479 		mem->bus.base = (mem->bus.base & 0x0ffffffffUL) +
    480 			rdev->ddev->hose->dense_mem_base;
    481 #endif
    482 		break;
    483 	default:
    484 		return -EINVAL;
    485 	}
    486 	return 0;
    487 }
    488 
    489 static void radeon_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
    490 {
    491 }
    492 
    493 static int radeon_sync_obj_wait(void *sync_obj, bool lazy, bool interruptible)
    494 {
    495 	return radeon_fence_wait((struct radeon_fence *)sync_obj, interruptible);
    496 }
    497 
    498 static int radeon_sync_obj_flush(void *sync_obj)
    499 {
    500 	return 0;
    501 }
    502 
    503 static void radeon_sync_obj_unref(void **sync_obj)
    504 {
    505 	radeon_fence_unref((struct radeon_fence **)sync_obj);
    506 }
    507 
    508 static void *radeon_sync_obj_ref(void *sync_obj)
    509 {
    510 	return radeon_fence_ref((struct radeon_fence *)sync_obj);
    511 }
    512 
    513 static bool radeon_sync_obj_signaled(void *sync_obj)
    514 {
    515 	return radeon_fence_signaled((struct radeon_fence *)sync_obj);
    516 }
    517 
    518 /*
    519  * TTM backend functions.
    520  */
    521 struct radeon_ttm_tt {
    522 	struct ttm_dma_tt		ttm;
    523 	struct radeon_device		*rdev;
    524 	u64				offset;
    525 };
    526 
    527 static int radeon_ttm_backend_bind(struct ttm_tt *ttm,
    528 				   struct ttm_mem_reg *bo_mem)
    529 {
    530 	struct radeon_ttm_tt *gtt = (void*)ttm;
    531 	int r;
    532 
    533 	gtt->offset = (unsigned long)(bo_mem->start << PAGE_SHIFT);
    534 	if (!ttm->num_pages) {
    535 		WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
    536 		     ttm->num_pages, bo_mem, ttm);
    537 	}
    538 	r = radeon_gart_bind(gtt->rdev, gtt->offset,
    539 			     ttm->num_pages, ttm->pages, gtt->ttm.dma_address);
    540 	if (r) {
    541 		DRM_ERROR("failed to bind %lu pages at 0x%08X\n",
    542 			  ttm->num_pages, (unsigned)gtt->offset);
    543 		return r;
    544 	}
    545 	return 0;
    546 }
    547 
    548 static int radeon_ttm_backend_unbind(struct ttm_tt *ttm)
    549 {
    550 	struct radeon_ttm_tt *gtt = (void *)ttm;
    551 
    552 	radeon_gart_unbind(gtt->rdev, gtt->offset, ttm->num_pages);
    553 	return 0;
    554 }
    555 
    556 static void radeon_ttm_backend_destroy(struct ttm_tt *ttm)
    557 {
    558 	struct radeon_ttm_tt *gtt = (void *)ttm;
    559 
    560 	ttm_dma_tt_fini(&gtt->ttm);
    561 	kfree(gtt);
    562 }
    563 
    564 static struct ttm_backend_func radeon_backend_func = {
    565 	.bind = &radeon_ttm_backend_bind,
    566 	.unbind = &radeon_ttm_backend_unbind,
    567 	.destroy = &radeon_ttm_backend_destroy,
    568 };
    569 
    570 static struct ttm_tt *radeon_ttm_tt_create(struct ttm_bo_device *bdev,
    571 				    unsigned long size, uint32_t page_flags,
    572 				    struct page *dummy_read_page)
    573 {
    574 	struct radeon_device *rdev;
    575 	struct radeon_ttm_tt *gtt;
    576 
    577 	rdev = radeon_get_rdev(bdev);
    578 #if __OS_HAS_AGP
    579 	if (rdev->flags & RADEON_IS_AGP) {
    580 		return ttm_agp_tt_create(bdev, rdev->ddev->agp->bridge,
    581 					 size, page_flags, dummy_read_page);
    582 	}
    583 #endif
    584 
    585 	gtt = kzalloc(sizeof(struct radeon_ttm_tt), GFP_KERNEL);
    586 	if (gtt == NULL) {
    587 		return NULL;
    588 	}
    589 	gtt->ttm.ttm.func = &radeon_backend_func;
    590 	gtt->rdev = rdev;
    591 	if (ttm_dma_tt_init(&gtt->ttm, bdev, size, page_flags, dummy_read_page)) {
    592 		kfree(gtt);
    593 		return NULL;
    594 	}
    595 	return &gtt->ttm.ttm;
    596 }
    597 
    598 static int radeon_ttm_tt_populate(struct ttm_tt *ttm)
    599 {
    600 	struct radeon_device *rdev;
    601 	struct radeon_ttm_tt *gtt = (void *)ttm;
    602 #ifndef __NetBSD__
    603 	unsigned i;
    604 	int r;
    605 #endif
    606 	bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
    607 
    608 	if (ttm->state != tt_unpopulated)
    609 		return 0;
    610 
    611 	if (slave && ttm->sg) {
    612 #ifdef __NetBSD__		/* XXX drm prime */
    613 		return -EINVAL;
    614 #else
    615 		drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
    616 						 gtt->ttm.dma_address, ttm->num_pages);
    617 		ttm->state = tt_unbound;
    618 		return 0;
    619 #endif
    620 	}
    621 
    622 	rdev = radeon_get_rdev(ttm->bdev);
    623 #if __OS_HAS_AGP
    624 	if (rdev->flags & RADEON_IS_AGP) {
    625 		return ttm_agp_tt_populate(ttm);
    626 	}
    627 #endif
    628 
    629 #ifdef __NetBSD__
    630 	/* XXX errno NetBSD->Linux */
    631 	return ttm_bus_dma_populate(&gtt->ttm);
    632 #else
    633 
    634 #ifdef CONFIG_SWIOTLB
    635 	if (swiotlb_nr_tbl()) {
    636 		return ttm_dma_populate(&gtt->ttm, rdev->dev);
    637 	}
    638 #endif
    639 
    640 	r = ttm_pool_populate(ttm);
    641 	if (r) {
    642 		return r;
    643 	}
    644 
    645 	for (i = 0; i < ttm->num_pages; i++) {
    646 		gtt->ttm.dma_address[i] = pci_map_page(rdev->pdev, ttm->pages[i],
    647 						       0, PAGE_SIZE,
    648 						       PCI_DMA_BIDIRECTIONAL);
    649 		if (pci_dma_mapping_error(rdev->pdev, gtt->ttm.dma_address[i])) {
    650 			while (--i) {
    651 				pci_unmap_page(rdev->pdev, gtt->ttm.dma_address[i],
    652 					       PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
    653 				gtt->ttm.dma_address[i] = 0;
    654 			}
    655 			ttm_pool_unpopulate(ttm);
    656 			return -EFAULT;
    657 		}
    658 	}
    659 	return 0;
    660 #endif
    661 }
    662 
    663 static void radeon_ttm_tt_unpopulate(struct ttm_tt *ttm)
    664 {
    665 	struct radeon_device *rdev;
    666 	struct radeon_ttm_tt *gtt = (void *)ttm;
    667 #ifndef __NetBSD__
    668 	unsigned i;
    669 #endif
    670 	bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
    671 
    672 	if (slave)
    673 		return;
    674 
    675 	rdev = radeon_get_rdev(ttm->bdev);
    676 #if __OS_HAS_AGP
    677 	if (rdev->flags & RADEON_IS_AGP) {
    678 		ttm_agp_tt_unpopulate(ttm);
    679 		return;
    680 	}
    681 #endif
    682 
    683 #ifdef __NetBSD__
    684 	ttm_bus_dma_unpopulate(&gtt->ttm);
    685 	return;
    686 #else
    687 
    688 #ifdef CONFIG_SWIOTLB
    689 	if (swiotlb_nr_tbl()) {
    690 		ttm_dma_unpopulate(&gtt->ttm, rdev->dev);
    691 		return;
    692 	}
    693 #endif
    694 
    695 	for (i = 0; i < ttm->num_pages; i++) {
    696 		if (gtt->ttm.dma_address[i]) {
    697 			pci_unmap_page(rdev->pdev, gtt->ttm.dma_address[i],
    698 				       PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
    699 		}
    700 	}
    701 
    702 	ttm_pool_unpopulate(ttm);
    703 #endif
    704 }
    705 
    706 #ifdef __NetBSD__
    707 static int	radeon_ttm_fault(struct uvm_faultinfo *, vaddr_t,
    708 		    struct vm_page **, int, int, vm_prot_t, int);
    709 
    710 static const struct uvm_pagerops radeon_uvm_ops = {
    711 	.pgo_reference = &ttm_bo_uvm_reference,
    712 	.pgo_detach = &ttm_bo_uvm_detach,
    713 	.pgo_fault = &radeon_ttm_fault,
    714 };
    715 #endif
    716 
    717 static struct ttm_bo_driver radeon_bo_driver = {
    718 	.ttm_tt_create = &radeon_ttm_tt_create,
    719 	.ttm_tt_populate = &radeon_ttm_tt_populate,
    720 	.ttm_tt_unpopulate = &radeon_ttm_tt_unpopulate,
    721 #ifdef __NetBSD__
    722 	.ttm_uvm_ops = &radeon_uvm_ops,
    723 #endif
    724 	.invalidate_caches = &radeon_invalidate_caches,
    725 	.init_mem_type = &radeon_init_mem_type,
    726 	.evict_flags = &radeon_evict_flags,
    727 	.move = &radeon_bo_move,
    728 	.verify_access = &radeon_verify_access,
    729 	.sync_obj_signaled = &radeon_sync_obj_signaled,
    730 	.sync_obj_wait = &radeon_sync_obj_wait,
    731 	.sync_obj_flush = &radeon_sync_obj_flush,
    732 	.sync_obj_unref = &radeon_sync_obj_unref,
    733 	.sync_obj_ref = &radeon_sync_obj_ref,
    734 	.move_notify = &radeon_bo_move_notify,
    735 	.fault_reserve_notify = &radeon_bo_fault_reserve_notify,
    736 	.io_mem_reserve = &radeon_ttm_io_mem_reserve,
    737 	.io_mem_free = &radeon_ttm_io_mem_free,
    738 };
    739 
    740 int radeon_ttm_init(struct radeon_device *rdev)
    741 {
    742 	int r;
    743 
    744 	r = radeon_ttm_global_init(rdev);
    745 	if (r) {
    746 		return r;
    747 	}
    748 	/* No others user of address space so set it to 0 */
    749 	r = ttm_bo_device_init(&rdev->mman.bdev,
    750 			       rdev->mman.bo_global_ref.ref.object,
    751 			       &radeon_bo_driver,
    752 #ifdef __NetBSD__
    753 			       rdev->ddev->bst,
    754 			       rdev->ddev->dmat,
    755 #else
    756 			       rdev->ddev->anon_inode->i_mapping,
    757 #endif
    758 			       DRM_FILE_PAGE_OFFSET,
    759 			       rdev->need_dma32);
    760 	if (r) {
    761 		DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
    762 		return r;
    763 	}
    764 	rdev->mman.initialized = true;
    765 	r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_VRAM,
    766 				rdev->mc.real_vram_size >> PAGE_SHIFT);
    767 	if (r) {
    768 		DRM_ERROR("Failed initializing VRAM heap.\n");
    769 		return r;
    770 	}
    771 	/* Change the size here instead of the init above so only lpfn is affected */
    772 	radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
    773 
    774 	r = radeon_bo_create(rdev, 256 * 1024, PAGE_SIZE, true,
    775 			     RADEON_GEM_DOMAIN_VRAM,
    776 			     NULL, &rdev->stollen_vga_memory);
    777 	if (r) {
    778 		return r;
    779 	}
    780 	r = radeon_bo_reserve(rdev->stollen_vga_memory, false);
    781 	if (r)
    782 		return r;
    783 	r = radeon_bo_pin(rdev->stollen_vga_memory, RADEON_GEM_DOMAIN_VRAM, NULL);
    784 	radeon_bo_unreserve(rdev->stollen_vga_memory);
    785 	if (r) {
    786 		radeon_bo_unref(&rdev->stollen_vga_memory);
    787 		return r;
    788 	}
    789 	DRM_INFO("radeon: %uM of VRAM memory ready\n",
    790 		 (unsigned) (rdev->mc.real_vram_size / (1024 * 1024)));
    791 	r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_TT,
    792 				rdev->mc.gtt_size >> PAGE_SHIFT);
    793 	if (r) {
    794 		DRM_ERROR("Failed initializing GTT heap.\n");
    795 		return r;
    796 	}
    797 	DRM_INFO("radeon: %uM of GTT memory ready.\n",
    798 		 (unsigned)(rdev->mc.gtt_size / (1024 * 1024)));
    799 
    800 	r = radeon_ttm_debugfs_init(rdev);
    801 	if (r) {
    802 		DRM_ERROR("Failed to init debugfs\n");
    803 		return r;
    804 	}
    805 	return 0;
    806 }
    807 
    808 void radeon_ttm_fini(struct radeon_device *rdev)
    809 {
    810 	int r;
    811 
    812 	if (!rdev->mman.initialized)
    813 		return;
    814 	radeon_ttm_debugfs_fini(rdev);
    815 	if (rdev->stollen_vga_memory) {
    816 		r = radeon_bo_reserve(rdev->stollen_vga_memory, false);
    817 		if (r == 0) {
    818 			radeon_bo_unpin(rdev->stollen_vga_memory);
    819 			radeon_bo_unreserve(rdev->stollen_vga_memory);
    820 		}
    821 		radeon_bo_unref(&rdev->stollen_vga_memory);
    822 	}
    823 	ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_VRAM);
    824 	ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_TT);
    825 	ttm_bo_device_release(&rdev->mman.bdev);
    826 	radeon_gart_fini(rdev);
    827 	radeon_ttm_global_fini(rdev);
    828 	rdev->mman.initialized = false;
    829 	DRM_INFO("radeon: ttm finalized\n");
    830 }
    831 
    832 /* this should only be called at bootup or when userspace
    833  * isn't running */
    834 void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size)
    835 {
    836 	struct ttm_mem_type_manager *man;
    837 
    838 	if (!rdev->mman.initialized)
    839 		return;
    840 
    841 	man = &rdev->mman.bdev.man[TTM_PL_VRAM];
    842 	/* this just adjusts TTM size idea, which sets lpfn to the correct value */
    843 	man->size = size >> PAGE_SHIFT;
    844 }
    845 
    846 #ifdef __NetBSD__
    847 
    848 static int
    849 radeon_ttm_fault(struct uvm_faultinfo *ufi, vaddr_t vaddr,
    850     struct vm_page **pps, int npages, int centeridx, vm_prot_t access_type,
    851     int flags)
    852 {
    853 	struct uvm_object *const uobj = ufi->entry->object.uvm_obj;
    854 	struct ttm_buffer_object *const bo = container_of(uobj,
    855 	    struct ttm_buffer_object, uvmobj);
    856 	struct radeon_device *const rdev = radeon_get_rdev(bo->bdev);
    857 	int error;
    858 
    859 	KASSERT(rdev != NULL);
    860 	down_read(&rdev->pm.mclk_lock);
    861 	error = ttm_bo_uvm_fault(ufi, vaddr, pps, npages, centeridx,
    862 	    access_type, flags);
    863 	up_read(&rdev->pm.mclk_lock);
    864 
    865 	return error;
    866 }
    867 
    868 int
    869 radeon_mmap_object(struct drm_device *dev, off_t offset, size_t size,
    870     vm_prot_t prot, struct uvm_object **uobjp, voff_t *uoffsetp,
    871     struct file *file)
    872 {
    873 	struct radeon_device *rdev = dev->dev_private;
    874 
    875 	KASSERT(0 == (offset & (PAGE_SIZE - 1)));
    876 
    877 	if (__predict_false(rdev == NULL))	/* XXX How?? */
    878 		return -EINVAL;
    879 
    880 	if (__predict_false((offset >> PAGE_SHIFT) < DRM_FILE_PAGE_OFFSET))
    881 		return drm_mmap_object(dev, offset, size, prot, uobjp,
    882 		    uoffsetp, file);
    883 	else
    884 		return ttm_bo_mmap_object(&rdev->mman.bdev, offset, size, prot,
    885 		    uobjp, uoffsetp, file);
    886 }
    887 
    888 #else
    889 
    890 static struct vm_operations_struct radeon_ttm_vm_ops;
    891 static const struct vm_operations_struct *ttm_vm_ops = NULL;
    892 
    893 static int radeon_ttm_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
    894 {
    895 	struct ttm_buffer_object *bo;
    896 	struct radeon_device *rdev;
    897 	int r;
    898 
    899 	bo = (struct ttm_buffer_object *)vma->vm_private_data;
    900 	if (bo == NULL) {
    901 		return VM_FAULT_NOPAGE;
    902 	}
    903 	rdev = radeon_get_rdev(bo->bdev);
    904 	down_read(&rdev->pm.mclk_lock);
    905 	r = ttm_vm_ops->fault(vma, vmf);
    906 	up_read(&rdev->pm.mclk_lock);
    907 	return r;
    908 }
    909 
    910 int radeon_mmap(struct file *filp, struct vm_area_struct *vma)
    911 {
    912 	struct drm_file *file_priv;
    913 	struct radeon_device *rdev;
    914 	int r;
    915 
    916 	if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET)) {
    917 		return drm_mmap(filp, vma);
    918 	}
    919 
    920 	file_priv = filp->private_data;
    921 	rdev = file_priv->minor->dev->dev_private;
    922 	if (rdev == NULL) {
    923 		return -EINVAL;
    924 	}
    925 	r = ttm_bo_mmap(filp, vma, &rdev->mman.bdev);
    926 	if (unlikely(r != 0)) {
    927 		return r;
    928 	}
    929 	if (unlikely(ttm_vm_ops == NULL)) {
    930 		ttm_vm_ops = vma->vm_ops;
    931 		radeon_ttm_vm_ops = *ttm_vm_ops;
    932 		radeon_ttm_vm_ops.fault = &radeon_ttm_fault;
    933 	}
    934 	vma->vm_ops = &radeon_ttm_vm_ops;
    935 	return 0;
    936 }
    937 
    938 #endif	/* __NetBSD__ */
    939 
    940 #if defined(CONFIG_DEBUG_FS)
    941 
    942 static int radeon_mm_dump_table(struct seq_file *m, void *data)
    943 {
    944 	struct drm_info_node *node = (struct drm_info_node *)m->private;
    945 	unsigned ttm_pl = *(int *)node->info_ent->data;
    946 	struct drm_device *dev = node->minor->dev;
    947 	struct radeon_device *rdev = dev->dev_private;
    948 	struct drm_mm *mm = (struct drm_mm *)rdev->mman.bdev.man[ttm_pl].priv;
    949 	int ret;
    950 	struct ttm_bo_global *glob = rdev->mman.bdev.glob;
    951 
    952 	spin_lock(&glob->lru_lock);
    953 	ret = drm_mm_dump_table(m, mm);
    954 	spin_unlock(&glob->lru_lock);
    955 	return ret;
    956 }
    957 
    958 static int ttm_pl_vram = TTM_PL_VRAM;
    959 static int ttm_pl_tt = TTM_PL_TT;
    960 
    961 static struct drm_info_list radeon_ttm_debugfs_list[] = {
    962 	{"radeon_vram_mm", radeon_mm_dump_table, 0, &ttm_pl_vram},
    963 	{"radeon_gtt_mm", radeon_mm_dump_table, 0, &ttm_pl_tt},
    964 	{"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
    965 #ifdef CONFIG_SWIOTLB
    966 	{"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
    967 #endif
    968 };
    969 
    970 static int radeon_ttm_vram_open(struct inode *inode, struct file *filep)
    971 {
    972 	struct radeon_device *rdev = inode->i_private;
    973 	i_size_write(inode, rdev->mc.mc_vram_size);
    974 	filep->private_data = inode->i_private;
    975 	return 0;
    976 }
    977 
    978 static ssize_t radeon_ttm_vram_read(struct file *f, char __user *buf,
    979 				    size_t size, loff_t *pos)
    980 {
    981 	struct radeon_device *rdev = f->private_data;
    982 	ssize_t result = 0;
    983 	int r;
    984 
    985 	if (size & 0x3 || *pos & 0x3)
    986 		return -EINVAL;
    987 
    988 	while (size) {
    989 		unsigned long flags;
    990 		uint32_t value;
    991 
    992 		if (*pos >= rdev->mc.mc_vram_size)
    993 			return result;
    994 
    995 		spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
    996 		WREG32(RADEON_MM_INDEX, ((uint32_t)*pos) | 0x80000000);
    997 		if (rdev->family >= CHIP_CEDAR)
    998 			WREG32(EVERGREEN_MM_INDEX_HI, *pos >> 31);
    999 		value = RREG32(RADEON_MM_DATA);
   1000 		spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
   1001 
   1002 		r = put_user(value, (uint32_t *)buf);
   1003 		if (r)
   1004 			return r;
   1005 
   1006 		result += 4;
   1007 		buf += 4;
   1008 		*pos += 4;
   1009 		size -= 4;
   1010 	}
   1011 
   1012 	return result;
   1013 }
   1014 
   1015 static const struct file_operations radeon_ttm_vram_fops = {
   1016 	.owner = THIS_MODULE,
   1017 	.open = radeon_ttm_vram_open,
   1018 	.read = radeon_ttm_vram_read,
   1019 	.llseek = default_llseek
   1020 };
   1021 
   1022 static int radeon_ttm_gtt_open(struct inode *inode, struct file *filep)
   1023 {
   1024 	struct radeon_device *rdev = inode->i_private;
   1025 	i_size_write(inode, rdev->mc.gtt_size);
   1026 	filep->private_data = inode->i_private;
   1027 	return 0;
   1028 }
   1029 
   1030 static ssize_t radeon_ttm_gtt_read(struct file *f, char __user *buf,
   1031 				   size_t size, loff_t *pos)
   1032 {
   1033 	struct radeon_device *rdev = f->private_data;
   1034 	ssize_t result = 0;
   1035 	int r;
   1036 
   1037 	while (size) {
   1038 		loff_t p = *pos / PAGE_SIZE;
   1039 		unsigned off = *pos & ~PAGE_MASK;
   1040 		size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
   1041 		struct page *page;
   1042 		void *ptr;
   1043 
   1044 		if (p >= rdev->gart.num_cpu_pages)
   1045 			return result;
   1046 
   1047 		page = rdev->gart.pages[p];
   1048 		if (page) {
   1049 			ptr = kmap(page);
   1050 			ptr += off;
   1051 
   1052 			r = copy_to_user(buf, ptr, cur_size);
   1053 			kunmap(rdev->gart.pages[p]);
   1054 		} else
   1055 			r = clear_user(buf, cur_size);
   1056 
   1057 		if (r)
   1058 			return -EFAULT;
   1059 
   1060 		result += cur_size;
   1061 		buf += cur_size;
   1062 		*pos += cur_size;
   1063 		size -= cur_size;
   1064 	}
   1065 
   1066 	return result;
   1067 }
   1068 
   1069 static const struct file_operations radeon_ttm_gtt_fops = {
   1070 	.owner = THIS_MODULE,
   1071 	.open = radeon_ttm_gtt_open,
   1072 	.read = radeon_ttm_gtt_read,
   1073 	.llseek = default_llseek
   1074 };
   1075 
   1076 #endif
   1077 
   1078 static int radeon_ttm_debugfs_init(struct radeon_device *rdev)
   1079 {
   1080 #if defined(CONFIG_DEBUG_FS)
   1081 	unsigned count;
   1082 
   1083 	struct drm_minor *minor = rdev->ddev->primary;
   1084 	struct dentry *ent, *root = minor->debugfs_root;
   1085 
   1086 	ent = debugfs_create_file("radeon_vram", S_IFREG | S_IRUGO, root,
   1087 				  rdev, &radeon_ttm_vram_fops);
   1088 	if (IS_ERR(ent))
   1089 		return PTR_ERR(ent);
   1090 	rdev->mman.vram = ent;
   1091 
   1092 	ent = debugfs_create_file("radeon_gtt", S_IFREG | S_IRUGO, root,
   1093 				  rdev, &radeon_ttm_gtt_fops);
   1094 	if (IS_ERR(ent))
   1095 		return PTR_ERR(ent);
   1096 	rdev->mman.gtt = ent;
   1097 
   1098 	count = ARRAY_SIZE(radeon_ttm_debugfs_list);
   1099 
   1100 #ifdef CONFIG_SWIOTLB
   1101 	if (!swiotlb_nr_tbl())
   1102 		--count;
   1103 #endif
   1104 
   1105 	return radeon_debugfs_add_files(rdev, radeon_ttm_debugfs_list, count);
   1106 #else
   1107 
   1108 	return 0;
   1109 #endif
   1110 }
   1111 
   1112 static void radeon_ttm_debugfs_fini(struct radeon_device *rdev)
   1113 {
   1114 #if defined(CONFIG_DEBUG_FS)
   1115 
   1116 	debugfs_remove(rdev->mman.vram);
   1117 	rdev->mman.vram = NULL;
   1118 
   1119 	debugfs_remove(rdev->mman.gtt);
   1120 	rdev->mman.gtt = NULL;
   1121 #endif
   1122 }
   1123