radeon_ttm.c revision 1.9.18.1 1 /* $NetBSD: radeon_ttm.c,v 1.9.18.1 2019/06/10 22:08:27 christos Exp $ */
2
3 /*
4 * Copyright 2009 Jerome Glisse.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * The above copyright notice and this permission notice (including the
24 * next paragraph) shall be included in all copies or substantial portions
25 * of the Software.
26 *
27 */
28 /*
29 * Authors:
30 * Jerome Glisse <glisse (at) freedesktop.org>
31 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
32 * Dave Airlie
33 */
34 #include <sys/cdefs.h>
35 __KERNEL_RCSID(0, "$NetBSD: radeon_ttm.c,v 1.9.18.1 2019/06/10 22:08:27 christos Exp $");
36
37 #include <ttm/ttm_bo_api.h>
38 #include <ttm/ttm_bo_driver.h>
39 #include <ttm/ttm_placement.h>
40 #include <ttm/ttm_module.h>
41 #include <ttm/ttm_page_alloc.h>
42 #include <drm/drmP.h>
43 #include <drm/radeon_drm.h>
44 #include <linux/seq_file.h>
45 #include <linux/slab.h>
46 #include <linux/swiotlb.h>
47 #include <linux/swap.h>
48 #include <linux/pagemap.h>
49 #include <linux/debugfs.h>
50 #include "radeon_reg.h"
51 #include "radeon.h"
52
53 #ifdef __NetBSD__
54 #include <uvm/uvm_extern.h>
55 #include <uvm/uvm_fault.h>
56 #include <uvm/uvm_param.h>
57 #include <drm/bus_dma_hacks.h>
58 #endif
59
60 #ifdef _LP64
61 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
62 #else
63 #define DRM_FILE_PAGE_OFFSET (0xa0000000UL >> PAGE_SHIFT)
64 #endif
65
66 static int radeon_ttm_debugfs_init(struct radeon_device *rdev);
67 static void radeon_ttm_debugfs_fini(struct radeon_device *rdev);
68
69 static struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev)
70 {
71 struct radeon_mman *mman;
72 struct radeon_device *rdev;
73
74 mman = container_of(bdev, struct radeon_mman, bdev);
75 rdev = container_of(mman, struct radeon_device, mman);
76 return rdev;
77 }
78
79
80 /*
81 * Global memory.
82 */
83 static int radeon_ttm_mem_global_init(struct drm_global_reference *ref)
84 {
85 return ttm_mem_global_init(ref->object);
86 }
87
88 static void radeon_ttm_mem_global_release(struct drm_global_reference *ref)
89 {
90 ttm_mem_global_release(ref->object);
91 }
92
93 static int radeon_ttm_global_init(struct radeon_device *rdev)
94 {
95 struct drm_global_reference *global_ref;
96 int r;
97
98 rdev->mman.mem_global_referenced = false;
99 global_ref = &rdev->mman.mem_global_ref;
100 global_ref->global_type = DRM_GLOBAL_TTM_MEM;
101 global_ref->size = sizeof(struct ttm_mem_global);
102 global_ref->init = &radeon_ttm_mem_global_init;
103 global_ref->release = &radeon_ttm_mem_global_release;
104 r = drm_global_item_ref(global_ref);
105 if (r != 0) {
106 DRM_ERROR("Failed setting up TTM memory accounting "
107 "subsystem.\n");
108 return r;
109 }
110
111 rdev->mman.bo_global_ref.mem_glob =
112 rdev->mman.mem_global_ref.object;
113 global_ref = &rdev->mman.bo_global_ref.ref;
114 global_ref->global_type = DRM_GLOBAL_TTM_BO;
115 global_ref->size = sizeof(struct ttm_bo_global);
116 global_ref->init = &ttm_bo_global_init;
117 global_ref->release = &ttm_bo_global_release;
118 r = drm_global_item_ref(global_ref);
119 if (r != 0) {
120 DRM_ERROR("Failed setting up TTM BO subsystem.\n");
121 drm_global_item_unref(&rdev->mman.mem_global_ref);
122 return r;
123 }
124
125 rdev->mman.mem_global_referenced = true;
126 return 0;
127 }
128
129 static void radeon_ttm_global_fini(struct radeon_device *rdev)
130 {
131 if (rdev->mman.mem_global_referenced) {
132 drm_global_item_unref(&rdev->mman.bo_global_ref.ref);
133 drm_global_item_unref(&rdev->mman.mem_global_ref);
134 rdev->mman.mem_global_referenced = false;
135 }
136 }
137
138 static int radeon_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
139 {
140 return 0;
141 }
142
143 static int radeon_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
144 struct ttm_mem_type_manager *man)
145 {
146 struct radeon_device *rdev;
147
148 rdev = radeon_get_rdev(bdev);
149
150 switch (type) {
151 case TTM_PL_SYSTEM:
152 /* System memory */
153 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
154 man->available_caching = TTM_PL_MASK_CACHING;
155 man->default_caching = TTM_PL_FLAG_CACHED;
156 break;
157 case TTM_PL_TT:
158 man->func = &ttm_bo_manager_func;
159 man->gpu_offset = rdev->mc.gtt_start;
160 man->available_caching = TTM_PL_MASK_CACHING;
161 man->default_caching = TTM_PL_FLAG_CACHED;
162 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
163 #if IS_ENABLED(CONFIG_AGP)
164 if (rdev->flags & RADEON_IS_AGP) {
165 if (!rdev->ddev->agp) {
166 DRM_ERROR("AGP is not enabled for memory type %u\n",
167 (unsigned)type);
168 return -EINVAL;
169 }
170 if (!rdev->ddev->agp->cant_use_aperture)
171 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
172 man->available_caching = TTM_PL_FLAG_UNCACHED |
173 TTM_PL_FLAG_WC;
174 man->default_caching = TTM_PL_FLAG_WC;
175 }
176 #endif
177 break;
178 case TTM_PL_VRAM:
179 /* "On-card" video ram */
180 man->func = &ttm_bo_manager_func;
181 man->gpu_offset = rdev->mc.vram_start;
182 man->flags = TTM_MEMTYPE_FLAG_FIXED |
183 TTM_MEMTYPE_FLAG_MAPPABLE;
184 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
185 man->default_caching = TTM_PL_FLAG_WC;
186 break;
187 default:
188 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
189 return -EINVAL;
190 }
191 return 0;
192 }
193
194 static void radeon_evict_flags(struct ttm_buffer_object *bo,
195 struct ttm_placement *placement)
196 {
197 static struct ttm_place placements = {
198 .fpfn = 0,
199 .lpfn = 0,
200 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM
201 };
202
203 struct radeon_bo *rbo;
204
205 if (!radeon_ttm_bo_is_radeon_bo(bo)) {
206 placement->placement = &placements;
207 placement->busy_placement = &placements;
208 placement->num_placement = 1;
209 placement->num_busy_placement = 1;
210 return;
211 }
212 rbo = container_of(bo, struct radeon_bo, tbo);
213 switch (bo->mem.mem_type) {
214 case TTM_PL_VRAM:
215 if (rbo->rdev->ring[radeon_copy_ring_index(rbo->rdev)].ready == false)
216 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU);
217 else if (rbo->rdev->mc.visible_vram_size < rbo->rdev->mc.real_vram_size &&
218 bo->mem.start < (rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT)) {
219 unsigned fpfn = rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
220 int i;
221
222 /* Try evicting to the CPU inaccessible part of VRAM
223 * first, but only set GTT as busy placement, so this
224 * BO will be evicted to GTT rather than causing other
225 * BOs to be evicted from VRAM
226 */
227 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM |
228 RADEON_GEM_DOMAIN_GTT);
229 rbo->placement.num_busy_placement = 0;
230 for (i = 0; i < rbo->placement.num_placement; i++) {
231 if (rbo->placements[i].flags & TTM_PL_FLAG_VRAM) {
232 if (rbo->placements[i].fpfn < fpfn)
233 rbo->placements[i].fpfn = fpfn;
234 } else {
235 rbo->placement.busy_placement =
236 &rbo->placements[i];
237 rbo->placement.num_busy_placement = 1;
238 }
239 }
240 } else
241 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT);
242 break;
243 case TTM_PL_TT:
244 default:
245 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU);
246 }
247 *placement = rbo->placement;
248 }
249
250 static int radeon_verify_access(struct ttm_buffer_object *bo, struct file *filp)
251 {
252 struct radeon_bo *rbo = container_of(bo, struct radeon_bo, tbo);
253
254 if (radeon_ttm_tt_has_userptr(bo->ttm))
255 return -EPERM;
256 return drm_vma_node_verify_access(&rbo->gem_base.vma_node, filp);
257 }
258
259 static void radeon_move_null(struct ttm_buffer_object *bo,
260 struct ttm_mem_reg *new_mem)
261 {
262 struct ttm_mem_reg *old_mem = &bo->mem;
263
264 BUG_ON(old_mem->mm_node != NULL);
265 *old_mem = *new_mem;
266 new_mem->mm_node = NULL;
267 }
268
269 static int radeon_move_blit(struct ttm_buffer_object *bo,
270 bool evict, bool no_wait_gpu,
271 struct ttm_mem_reg *new_mem,
272 struct ttm_mem_reg *old_mem)
273 {
274 struct radeon_device *rdev;
275 uint64_t old_start, new_start;
276 struct radeon_fence *fence;
277 unsigned num_pages;
278 int r, ridx;
279
280 rdev = radeon_get_rdev(bo->bdev);
281 ridx = radeon_copy_ring_index(rdev);
282 old_start = (u64)old_mem->start << PAGE_SHIFT;
283 new_start = (u64)new_mem->start << PAGE_SHIFT;
284
285 switch (old_mem->mem_type) {
286 case TTM_PL_VRAM:
287 old_start += rdev->mc.vram_start;
288 break;
289 case TTM_PL_TT:
290 old_start += rdev->mc.gtt_start;
291 break;
292 default:
293 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
294 return -EINVAL;
295 }
296 switch (new_mem->mem_type) {
297 case TTM_PL_VRAM:
298 new_start += rdev->mc.vram_start;
299 break;
300 case TTM_PL_TT:
301 new_start += rdev->mc.gtt_start;
302 break;
303 default:
304 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
305 return -EINVAL;
306 }
307 if (!rdev->ring[ridx].ready) {
308 DRM_ERROR("Trying to move memory with ring turned off.\n");
309 return -EINVAL;
310 }
311
312 BUILD_BUG_ON((PAGE_SIZE % RADEON_GPU_PAGE_SIZE) != 0);
313
314 num_pages = new_mem->num_pages * (PAGE_SIZE / RADEON_GPU_PAGE_SIZE);
315 fence = radeon_copy(rdev, old_start, new_start, num_pages, bo->resv);
316 if (IS_ERR(fence))
317 return PTR_ERR(fence);
318
319 r = ttm_bo_move_accel_cleanup(bo, &fence->base,
320 evict, no_wait_gpu, new_mem);
321 radeon_fence_unref(&fence);
322 return r;
323 }
324
325 static int radeon_move_vram_ram(struct ttm_buffer_object *bo,
326 bool evict, bool interruptible,
327 bool no_wait_gpu,
328 struct ttm_mem_reg *new_mem)
329 {
330 struct radeon_device *rdev __unused;
331 struct ttm_mem_reg *old_mem = &bo->mem;
332 struct ttm_mem_reg tmp_mem;
333 struct ttm_place placements;
334 struct ttm_placement placement;
335 int r;
336
337 rdev = radeon_get_rdev(bo->bdev);
338 tmp_mem = *new_mem;
339 tmp_mem.mm_node = NULL;
340 placement.num_placement = 1;
341 placement.placement = &placements;
342 placement.num_busy_placement = 1;
343 placement.busy_placement = &placements;
344 placements.fpfn = 0;
345 placements.lpfn = 0;
346 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
347 r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
348 interruptible, no_wait_gpu);
349 if (unlikely(r)) {
350 return r;
351 }
352
353 r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
354 if (unlikely(r)) {
355 goto out_cleanup;
356 }
357
358 r = ttm_tt_bind(bo->ttm, &tmp_mem);
359 if (unlikely(r)) {
360 goto out_cleanup;
361 }
362 r = radeon_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem);
363 if (unlikely(r)) {
364 goto out_cleanup;
365 }
366 r = ttm_bo_move_ttm(bo, true, no_wait_gpu, new_mem);
367 out_cleanup:
368 ttm_bo_mem_put(bo, &tmp_mem);
369 return r;
370 }
371
372 static int radeon_move_ram_vram(struct ttm_buffer_object *bo,
373 bool evict, bool interruptible,
374 bool no_wait_gpu,
375 struct ttm_mem_reg *new_mem)
376 {
377 struct radeon_device *rdev __unused;
378 struct ttm_mem_reg *old_mem = &bo->mem;
379 struct ttm_mem_reg tmp_mem;
380 struct ttm_placement placement;
381 struct ttm_place placements;
382 int r;
383
384 rdev = radeon_get_rdev(bo->bdev);
385 tmp_mem = *new_mem;
386 tmp_mem.mm_node = NULL;
387 placement.num_placement = 1;
388 placement.placement = &placements;
389 placement.num_busy_placement = 1;
390 placement.busy_placement = &placements;
391 placements.fpfn = 0;
392 placements.lpfn = 0;
393 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
394 r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
395 interruptible, no_wait_gpu);
396 if (unlikely(r)) {
397 return r;
398 }
399 r = ttm_bo_move_ttm(bo, true, no_wait_gpu, &tmp_mem);
400 if (unlikely(r)) {
401 goto out_cleanup;
402 }
403 r = radeon_move_blit(bo, true, no_wait_gpu, new_mem, old_mem);
404 if (unlikely(r)) {
405 goto out_cleanup;
406 }
407 out_cleanup:
408 ttm_bo_mem_put(bo, &tmp_mem);
409 return r;
410 }
411
412 static int radeon_bo_move(struct ttm_buffer_object *bo,
413 bool evict, bool interruptible,
414 bool no_wait_gpu,
415 struct ttm_mem_reg *new_mem)
416 {
417 struct radeon_device *rdev;
418 struct ttm_mem_reg *old_mem = &bo->mem;
419 int r;
420
421 rdev = radeon_get_rdev(bo->bdev);
422 if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
423 radeon_move_null(bo, new_mem);
424 return 0;
425 }
426 if ((old_mem->mem_type == TTM_PL_TT &&
427 new_mem->mem_type == TTM_PL_SYSTEM) ||
428 (old_mem->mem_type == TTM_PL_SYSTEM &&
429 new_mem->mem_type == TTM_PL_TT)) {
430 /* bind is enough */
431 radeon_move_null(bo, new_mem);
432 return 0;
433 }
434 if (!rdev->ring[radeon_copy_ring_index(rdev)].ready ||
435 rdev->asic->copy.copy == NULL) {
436 /* use memcpy */
437 goto memcpy;
438 }
439
440 if (old_mem->mem_type == TTM_PL_VRAM &&
441 new_mem->mem_type == TTM_PL_SYSTEM) {
442 r = radeon_move_vram_ram(bo, evict, interruptible,
443 no_wait_gpu, new_mem);
444 } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
445 new_mem->mem_type == TTM_PL_VRAM) {
446 r = radeon_move_ram_vram(bo, evict, interruptible,
447 no_wait_gpu, new_mem);
448 } else {
449 r = radeon_move_blit(bo, evict, no_wait_gpu, new_mem, old_mem);
450 }
451
452 if (r) {
453 memcpy:
454 r = ttm_bo_move_memcpy(bo, evict, no_wait_gpu, new_mem);
455 if (r) {
456 return r;
457 }
458 }
459
460 /* update statistics */
461 atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &rdev->num_bytes_moved);
462 return 0;
463 }
464
465 static int radeon_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
466 {
467 struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
468 struct radeon_device *rdev = radeon_get_rdev(bdev);
469
470 mem->bus.addr = NULL;
471 mem->bus.offset = 0;
472 mem->bus.size = mem->num_pages << PAGE_SHIFT;
473 mem->bus.base = 0;
474 mem->bus.is_iomem = false;
475 if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
476 return -EINVAL;
477 switch (mem->mem_type) {
478 case TTM_PL_SYSTEM:
479 /* system memory */
480 return 0;
481 case TTM_PL_TT:
482 #if IS_ENABLED(CONFIG_AGP)
483 if (rdev->flags & RADEON_IS_AGP) {
484 /* RADEON_IS_AGP is set only if AGP is active */
485 mem->bus.offset = mem->start << PAGE_SHIFT;
486 mem->bus.base = rdev->mc.agp_base;
487 mem->bus.is_iomem = !rdev->ddev->agp->cant_use_aperture;
488 KASSERTMSG((mem->bus.base & (PAGE_SIZE - 1)) == 0,
489 "agp aperture is not page-aligned: %lx",
490 mem->bus.base);
491 KASSERT((mem->bus.offset & (PAGE_SIZE - 1)) == 0);
492 }
493 #endif
494 break;
495 case TTM_PL_VRAM:
496 mem->bus.offset = mem->start << PAGE_SHIFT;
497 /* check if it's visible */
498 if ((mem->bus.offset + mem->bus.size) > rdev->mc.visible_vram_size)
499 return -EINVAL;
500 mem->bus.base = rdev->mc.aper_base;
501 mem->bus.is_iomem = true;
502 #ifdef __alpha__
503 /*
504 * Alpha: use bus.addr to hold the ioremap() return,
505 * so we can modify bus.base below.
506 */
507 if (mem->placement & TTM_PL_FLAG_WC)
508 mem->bus.addr =
509 ioremap_wc(mem->bus.base + mem->bus.offset,
510 mem->bus.size);
511 else
512 mem->bus.addr =
513 ioremap_nocache(mem->bus.base + mem->bus.offset,
514 mem->bus.size);
515
516 /*
517 * Alpha: Use just the bus offset plus
518 * the hose/domain memory base for bus.base.
519 * It then can be used to build PTEs for VRAM
520 * access, as done in ttm_bo_vm_fault().
521 */
522 mem->bus.base = (mem->bus.base & 0x0ffffffffUL) +
523 rdev->ddev->hose->dense_mem_base;
524 #endif
525 KASSERTMSG((mem->bus.base & (PAGE_SIZE - 1)) == 0,
526 "mc aperture is not page-aligned: %lx",
527 mem->bus.base);
528 KASSERT((mem->bus.offset & (PAGE_SIZE - 1)) == 0);
529 break;
530 default:
531 return -EINVAL;
532 }
533 return 0;
534 }
535
536 static void radeon_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
537 {
538 }
539
540 /*
541 * TTM backend functions.
542 */
543 struct radeon_ttm_tt {
544 struct ttm_dma_tt ttm;
545 struct radeon_device *rdev;
546 u64 offset;
547
548 uint64_t userptr;
549 struct mm_struct *usermm;
550 uint32_t userflags;
551 };
552
553 /* prepare the sg table with the user pages */
554 static int radeon_ttm_tt_pin_userptr(struct ttm_tt *ttm)
555 {
556 #ifdef __NetBSD__
557 panic("we don't handle user pointers round these parts");
558 #else
559 struct radeon_device *rdev = radeon_get_rdev(ttm->bdev);
560 struct radeon_ttm_tt *gtt = (void *)ttm;
561 unsigned pinned = 0, nents;
562 int r;
563
564 int write = !(gtt->userflags & RADEON_GEM_USERPTR_READONLY);
565 enum dma_data_direction direction = write ?
566 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
567
568 if (current->mm != gtt->usermm)
569 return -EPERM;
570
571 if (gtt->userflags & RADEON_GEM_USERPTR_ANONONLY) {
572 /* check that we only pin down anonymous memory
573 to prevent problems with writeback */
574 unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE;
575 struct vm_area_struct *vma;
576 vma = find_vma(gtt->usermm, gtt->userptr);
577 if (!vma || vma->vm_file || vma->vm_end < end)
578 return -EPERM;
579 }
580
581 do {
582 unsigned num_pages = ttm->num_pages - pinned;
583 uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE;
584 struct page **pages = ttm->pages + pinned;
585
586 r = get_user_pages(current, current->mm, userptr, num_pages,
587 write, 0, pages, NULL);
588 if (r < 0)
589 goto release_pages;
590
591 pinned += r;
592
593 } while (pinned < ttm->num_pages);
594
595 r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
596 ttm->num_pages << PAGE_SHIFT,
597 GFP_KERNEL);
598 if (r)
599 goto release_sg;
600
601 r = -ENOMEM;
602 nents = dma_map_sg(rdev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
603 if (nents != ttm->sg->nents)
604 goto release_sg;
605
606 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
607 gtt->ttm.dma_address, ttm->num_pages);
608
609 return 0;
610
611 release_sg:
612 kfree(ttm->sg);
613
614 release_pages:
615 release_pages(ttm->pages, pinned, 0);
616 return r;
617 #endif
618 }
619
620 static void radeon_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
621 {
622 #ifdef __NetBSD__
623 panic("some varmint pinned a userptr to my hat");
624 #else
625 struct radeon_device *rdev = radeon_get_rdev(ttm->bdev);
626 struct radeon_ttm_tt *gtt = (void *)ttm;
627 struct sg_page_iter sg_iter;
628
629 int write = !(gtt->userflags & RADEON_GEM_USERPTR_READONLY);
630 enum dma_data_direction direction = write ?
631 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
632
633 /* double check that we don't free the table twice */
634 if (!ttm->sg->sgl)
635 return;
636
637 /* free the sg table and pages again */
638 dma_unmap_sg(rdev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
639
640 for_each_sg_page(ttm->sg->sgl, &sg_iter, ttm->sg->nents, 0) {
641 struct page *page = sg_page_iter_page(&sg_iter);
642 if (!(gtt->userflags & RADEON_GEM_USERPTR_READONLY))
643 set_page_dirty(page);
644
645 mark_page_accessed(page);
646 page_cache_release(page);
647 }
648
649 sg_free_table(ttm->sg);
650 #endif
651 }
652
653 static int radeon_ttm_backend_bind(struct ttm_tt *ttm,
654 struct ttm_mem_reg *bo_mem)
655 {
656 struct radeon_ttm_tt *gtt = (void*)ttm;
657 uint32_t flags = RADEON_GART_PAGE_VALID | RADEON_GART_PAGE_READ |
658 RADEON_GART_PAGE_WRITE;
659 int r;
660
661 if (gtt->userptr) {
662 radeon_ttm_tt_pin_userptr(ttm);
663 flags &= ~RADEON_GART_PAGE_WRITE;
664 }
665
666 gtt->offset = (unsigned long)(bo_mem->start << PAGE_SHIFT);
667 if (!ttm->num_pages) {
668 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
669 ttm->num_pages, bo_mem, ttm);
670 }
671 if (ttm->caching_state == tt_cached)
672 flags |= RADEON_GART_PAGE_SNOOP;
673 r = radeon_gart_bind(gtt->rdev, gtt->offset, ttm->num_pages,
674 ttm->pages, gtt->ttm.dma_address, flags);
675 if (r) {
676 DRM_ERROR("failed to bind %lu pages at 0x%08X\n",
677 ttm->num_pages, (unsigned)gtt->offset);
678 return r;
679 }
680 return 0;
681 }
682
683 static int radeon_ttm_backend_unbind(struct ttm_tt *ttm)
684 {
685 struct radeon_ttm_tt *gtt = (void *)ttm;
686
687 radeon_gart_unbind(gtt->rdev, gtt->offset, ttm->num_pages);
688
689 if (gtt->userptr)
690 radeon_ttm_tt_unpin_userptr(ttm);
691
692 return 0;
693 }
694
695 static void radeon_ttm_backend_destroy(struct ttm_tt *ttm)
696 {
697 struct radeon_ttm_tt *gtt = (void *)ttm;
698
699 ttm_dma_tt_fini(>t->ttm);
700 kfree(gtt);
701 }
702
703 static struct ttm_backend_func radeon_backend_func = {
704 .bind = &radeon_ttm_backend_bind,
705 .unbind = &radeon_ttm_backend_unbind,
706 .destroy = &radeon_ttm_backend_destroy,
707 };
708
709 static struct ttm_tt *radeon_ttm_tt_create(struct ttm_bo_device *bdev,
710 unsigned long size, uint32_t page_flags,
711 struct page *dummy_read_page)
712 {
713 struct radeon_device *rdev;
714 struct radeon_ttm_tt *gtt;
715
716 rdev = radeon_get_rdev(bdev);
717 #if IS_ENABLED(CONFIG_AGP)
718 if (rdev->flags & RADEON_IS_AGP) {
719 return ttm_agp_tt_create(bdev, rdev->ddev->agp->bridge,
720 size, page_flags, dummy_read_page);
721 }
722 #endif
723
724 gtt = kzalloc(sizeof(struct radeon_ttm_tt), GFP_KERNEL);
725 if (gtt == NULL) {
726 return NULL;
727 }
728 gtt->ttm.ttm.func = &radeon_backend_func;
729 gtt->rdev = rdev;
730 if (ttm_dma_tt_init(>t->ttm, bdev, size, page_flags, dummy_read_page)) {
731 kfree(gtt);
732 return NULL;
733 }
734 return >t->ttm.ttm;
735 }
736
737 static struct radeon_ttm_tt *radeon_ttm_tt_to_gtt(struct ttm_tt *ttm)
738 {
739 if (!ttm || ttm->func != &radeon_backend_func)
740 return NULL;
741 return (struct radeon_ttm_tt *)ttm;
742 }
743
744 static int radeon_ttm_tt_populate(struct ttm_tt *ttm)
745 {
746 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm);
747 #if !defined(__NetBSD__) || IS_ENABLED(CONFIG_AGP)
748 struct radeon_device *rdev;
749 #endif
750 #ifndef __NetBSD__
751 unsigned i;
752 #endif
753 int r;
754 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
755
756 if (ttm->state != tt_unpopulated)
757 return 0;
758
759 if (gtt && gtt->userptr) {
760 #ifdef __NetBSD__
761 panic("don't point at users, it's not polite");
762 #else
763 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
764 if (!ttm->sg)
765 return -ENOMEM;
766
767 ttm->page_flags |= TTM_PAGE_FLAG_SG;
768 ttm->state = tt_unbound;
769 #endif
770 return 0;
771 }
772
773 if (slave && ttm->sg) {
774 #ifdef __NetBSD__
775 r = drm_prime_bus_dmamap_load_sgt(ttm->bdev->dmat,
776 gtt->ttm.dma_address, ttm->sg);
777 if (r)
778 return r;
779 #else
780 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
781 gtt->ttm.dma_address, ttm->num_pages);
782 #endif
783 ttm->state = tt_unbound;
784 return 0;
785 }
786
787 #if !defined(__NetBSD__) || IS_ENABLED(CONFIG_AGP)
788 rdev = radeon_get_rdev(ttm->bdev);
789 #endif
790 #if IS_ENABLED(CONFIG_AGP)
791 if (rdev->flags & RADEON_IS_AGP) {
792 return ttm_agp_tt_populate(ttm);
793 }
794 #endif
795
796 #ifdef __NetBSD__
797 /* XXX errno NetBSD->Linux */
798 return ttm_bus_dma_populate(>t->ttm);
799 #else
800
801 #ifdef CONFIG_SWIOTLB
802 if (swiotlb_nr_tbl()) {
803 return ttm_dma_populate(>t->ttm, rdev->dev);
804 }
805 #endif
806
807 r = ttm_pool_populate(ttm);
808 if (r) {
809 return r;
810 }
811
812 for (i = 0; i < ttm->num_pages; i++) {
813 gtt->ttm.dma_address[i] = pci_map_page(rdev->pdev, ttm->pages[i],
814 0, PAGE_SIZE,
815 PCI_DMA_BIDIRECTIONAL);
816 if (pci_dma_mapping_error(rdev->pdev, gtt->ttm.dma_address[i])) {
817 while (i--) {
818 pci_unmap_page(rdev->pdev, gtt->ttm.dma_address[i],
819 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
820 gtt->ttm.dma_address[i] = 0;
821 }
822 ttm_pool_unpopulate(ttm);
823 return -EFAULT;
824 }
825 }
826 return 0;
827 #endif
828 }
829
830 static void radeon_ttm_tt_unpopulate(struct ttm_tt *ttm)
831 {
832 #if !defined(__NetBSD__) || IS_ENABLED(CONFIG_AGP)
833 struct radeon_device *rdev;
834 #endif
835 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm);
836 #ifndef __NetBSD__
837 unsigned i;
838 #endif
839 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
840
841 if (gtt && gtt->userptr) {
842 kfree(ttm->sg);
843 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
844 return;
845 }
846
847 if (slave)
848 return;
849
850 #if !defined(__NetBSD__) || IS_ENABLED(CONFIG_AGP)
851 rdev = radeon_get_rdev(ttm->bdev);
852 #endif
853 #if IS_ENABLED(CONFIG_AGP)
854 if (rdev->flags & RADEON_IS_AGP) {
855 ttm_agp_tt_unpopulate(ttm);
856 return;
857 }
858 #endif
859
860 #ifdef __NetBSD__
861 ttm_bus_dma_unpopulate(>t->ttm);
862 return;
863 #else
864
865 #ifdef CONFIG_SWIOTLB
866 if (swiotlb_nr_tbl()) {
867 ttm_dma_unpopulate(>t->ttm, rdev->dev);
868 return;
869 }
870 #endif
871
872 for (i = 0; i < ttm->num_pages; i++) {
873 if (gtt->ttm.dma_address[i]) {
874 pci_unmap_page(rdev->pdev, gtt->ttm.dma_address[i],
875 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
876 }
877 }
878
879 ttm_pool_unpopulate(ttm);
880 #endif
881 }
882
883 #ifdef __NetBSD__
884 static void radeon_ttm_tt_swapout(struct ttm_tt *ttm)
885 {
886 struct radeon_ttm_tt *gtt = container_of(ttm, struct radeon_ttm_tt,
887 ttm.ttm);
888 struct ttm_dma_tt *ttm_dma = >t->ttm;
889
890 ttm_bus_dma_swapout(ttm_dma);
891 }
892
893 static int radeon_ttm_fault(struct uvm_faultinfo *, vaddr_t,
894 struct vm_page **, int, int, vm_prot_t, int);
895
896 static const struct uvm_pagerops radeon_uvm_ops = {
897 .pgo_reference = &ttm_bo_uvm_reference,
898 .pgo_detach = &ttm_bo_uvm_detach,
899 .pgo_fault = &radeon_ttm_fault,
900 };
901 #endif
902
903 int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
904 uint32_t flags)
905 {
906 #ifdef __NetBSD__
907 /*
908 * XXX Too painful to contemplate for now. If you add this,
909 * make sure to update radeon_cs.c radeon_cs_parser_relocs
910 * (need_mmap_lock), and anything else using
911 * radeon_ttm_tt_has_userptr.
912 */
913 return -ENODEV;
914 #else
915 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm);
916
917 if (gtt == NULL)
918 return -EINVAL;
919
920 gtt->userptr = addr;
921 gtt->usermm = current->mm;
922 gtt->userflags = flags;
923 return 0;
924 #endif
925 }
926
927 bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm)
928 {
929 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm);
930
931 if (gtt == NULL)
932 return false;
933
934 return !!gtt->userptr;
935 }
936
937 bool radeon_ttm_tt_is_readonly(struct ttm_tt *ttm)
938 {
939 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm);
940
941 if (gtt == NULL)
942 return false;
943
944 return !!(gtt->userflags & RADEON_GEM_USERPTR_READONLY);
945 }
946
947 static struct ttm_bo_driver radeon_bo_driver = {
948 .ttm_tt_create = &radeon_ttm_tt_create,
949 .ttm_tt_populate = &radeon_ttm_tt_populate,
950 .ttm_tt_unpopulate = &radeon_ttm_tt_unpopulate,
951 #ifdef __NetBSD__
952 .ttm_tt_swapout = &radeon_ttm_tt_swapout,
953 .ttm_uvm_ops = &radeon_uvm_ops,
954 #endif
955 .invalidate_caches = &radeon_invalidate_caches,
956 .init_mem_type = &radeon_init_mem_type,
957 .evict_flags = &radeon_evict_flags,
958 .move = &radeon_bo_move,
959 .verify_access = &radeon_verify_access,
960 .move_notify = &radeon_bo_move_notify,
961 .fault_reserve_notify = &radeon_bo_fault_reserve_notify,
962 .io_mem_reserve = &radeon_ttm_io_mem_reserve,
963 .io_mem_free = &radeon_ttm_io_mem_free,
964 };
965
966 int radeon_ttm_init(struct radeon_device *rdev)
967 {
968 int r;
969
970 r = radeon_ttm_global_init(rdev);
971 if (r) {
972 return r;
973 }
974 /* No others user of address space so set it to 0 */
975 r = ttm_bo_device_init(&rdev->mman.bdev,
976 rdev->mman.bo_global_ref.ref.object,
977 &radeon_bo_driver,
978 #ifdef __NetBSD__
979 rdev->ddev->bst,
980 rdev->ddev->dmat,
981 #else
982 rdev->ddev->anon_inode->i_mapping,
983 #endif
984 DRM_FILE_PAGE_OFFSET,
985 rdev->need_dma32);
986 if (r) {
987 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
988 return r;
989 }
990 rdev->mman.initialized = true;
991 r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_VRAM,
992 rdev->mc.real_vram_size >> PAGE_SHIFT);
993 if (r) {
994 DRM_ERROR("Failed initializing VRAM heap.\n");
995 return r;
996 }
997 /* Change the size here instead of the init above so only lpfn is affected */
998 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
999
1000 r = radeon_bo_create(rdev, 256 * 1024, PAGE_SIZE, true,
1001 RADEON_GEM_DOMAIN_VRAM, 0, NULL,
1002 NULL, &rdev->stollen_vga_memory);
1003 if (r) {
1004 return r;
1005 }
1006 r = radeon_bo_reserve(rdev->stollen_vga_memory, false);
1007 if (r)
1008 return r;
1009 r = radeon_bo_pin(rdev->stollen_vga_memory, RADEON_GEM_DOMAIN_VRAM, NULL);
1010 radeon_bo_unreserve(rdev->stollen_vga_memory);
1011 if (r) {
1012 radeon_bo_unref(&rdev->stollen_vga_memory);
1013 return r;
1014 }
1015 DRM_INFO("radeon: %uM of VRAM memory ready\n",
1016 (unsigned) (rdev->mc.real_vram_size / (1024 * 1024)));
1017 r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_TT,
1018 rdev->mc.gtt_size >> PAGE_SHIFT);
1019 if (r) {
1020 DRM_ERROR("Failed initializing GTT heap.\n");
1021 return r;
1022 }
1023 DRM_INFO("radeon: %uM of GTT memory ready.\n",
1024 (unsigned)(rdev->mc.gtt_size / (1024 * 1024)));
1025
1026 r = radeon_ttm_debugfs_init(rdev);
1027 if (r) {
1028 DRM_ERROR("Failed to init debugfs\n");
1029 return r;
1030 }
1031 return 0;
1032 }
1033
1034 void radeon_ttm_fini(struct radeon_device *rdev)
1035 {
1036 int r;
1037
1038 if (!rdev->mman.initialized)
1039 return;
1040 radeon_ttm_debugfs_fini(rdev);
1041 if (rdev->stollen_vga_memory) {
1042 r = radeon_bo_reserve(rdev->stollen_vga_memory, false);
1043 if (r == 0) {
1044 radeon_bo_unpin(rdev->stollen_vga_memory);
1045 radeon_bo_unreserve(rdev->stollen_vga_memory);
1046 }
1047 radeon_bo_unref(&rdev->stollen_vga_memory);
1048 }
1049 ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_VRAM);
1050 ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_TT);
1051 ttm_bo_device_release(&rdev->mman.bdev);
1052 radeon_gart_fini(rdev);
1053 radeon_ttm_global_fini(rdev);
1054 rdev->mman.initialized = false;
1055 DRM_INFO("radeon: ttm finalized\n");
1056 }
1057
1058 /* this should only be called at bootup or when userspace
1059 * isn't running */
1060 void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size)
1061 {
1062 struct ttm_mem_type_manager *man;
1063
1064 if (!rdev->mman.initialized)
1065 return;
1066
1067 man = &rdev->mman.bdev.man[TTM_PL_VRAM];
1068 /* this just adjusts TTM size idea, which sets lpfn to the correct value */
1069 man->size = size >> PAGE_SHIFT;
1070 }
1071
1072 #ifdef __NetBSD__
1073
1074 static int
1075 radeon_ttm_fault(struct uvm_faultinfo *ufi, vaddr_t vaddr,
1076 struct vm_page **pps, int npages, int centeridx, vm_prot_t access_type,
1077 int flags)
1078 {
1079 struct uvm_object *const uobj = ufi->entry->object.uvm_obj;
1080 struct ttm_buffer_object *const bo = container_of(uobj,
1081 struct ttm_buffer_object, uvmobj);
1082 struct radeon_device *const rdev = radeon_get_rdev(bo->bdev);
1083 int error;
1084
1085 KASSERT(rdev != NULL);
1086 down_read(&rdev->pm.mclk_lock);
1087 error = ttm_bo_uvm_fault(ufi, vaddr, pps, npages, centeridx,
1088 access_type, flags);
1089 up_read(&rdev->pm.mclk_lock);
1090
1091 return error;
1092 }
1093
1094 int
1095 radeon_mmap_object(struct drm_device *dev, off_t offset, size_t size,
1096 vm_prot_t prot, struct uvm_object **uobjp, voff_t *uoffsetp,
1097 struct file *file)
1098 {
1099 struct radeon_device *rdev = dev->dev_private;
1100
1101 KASSERT(0 == (offset & (PAGE_SIZE - 1)));
1102
1103 if (__predict_false(rdev == NULL)) /* XXX How?? */
1104 return -EINVAL;
1105
1106 if (__predict_false((offset >> PAGE_SHIFT) < DRM_FILE_PAGE_OFFSET))
1107 return -EINVAL;
1108
1109 return ttm_bo_mmap_object(&rdev->mman.bdev, offset, size, prot,
1110 uobjp, uoffsetp, file);
1111 }
1112
1113 #else
1114
1115 static struct vm_operations_struct radeon_ttm_vm_ops;
1116 static const struct vm_operations_struct *ttm_vm_ops = NULL;
1117
1118 static int radeon_ttm_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1119 {
1120 struct ttm_buffer_object *bo;
1121 struct radeon_device *rdev;
1122 int r;
1123
1124 bo = (struct ttm_buffer_object *)vma->vm_private_data;
1125 if (bo == NULL) {
1126 return VM_FAULT_NOPAGE;
1127 }
1128 rdev = radeon_get_rdev(bo->bdev);
1129 down_read(&rdev->pm.mclk_lock);
1130 r = ttm_vm_ops->fault(vma, vmf);
1131 up_read(&rdev->pm.mclk_lock);
1132 return r;
1133 }
1134
1135 int radeon_mmap(struct file *filp, struct vm_area_struct *vma)
1136 {
1137 struct drm_file *file_priv;
1138 struct radeon_device *rdev;
1139 int r;
1140
1141 if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET)) {
1142 return -EINVAL;
1143 }
1144
1145 file_priv = filp->private_data;
1146 rdev = file_priv->minor->dev->dev_private;
1147 if (rdev == NULL) {
1148 return -EINVAL;
1149 }
1150 r = ttm_bo_mmap(filp, vma, &rdev->mman.bdev);
1151 if (unlikely(r != 0)) {
1152 return r;
1153 }
1154 if (unlikely(ttm_vm_ops == NULL)) {
1155 ttm_vm_ops = vma->vm_ops;
1156 radeon_ttm_vm_ops = *ttm_vm_ops;
1157 radeon_ttm_vm_ops.fault = &radeon_ttm_fault;
1158 }
1159 vma->vm_ops = &radeon_ttm_vm_ops;
1160 return 0;
1161 }
1162
1163 #endif /* __NetBSD__ */
1164
1165 #if defined(CONFIG_DEBUG_FS)
1166
1167 static int radeon_mm_dump_table(struct seq_file *m, void *data)
1168 {
1169 struct drm_info_node *node = (struct drm_info_node *)m->private;
1170 unsigned ttm_pl = *(int *)node->info_ent->data;
1171 struct drm_device *dev = node->minor->dev;
1172 struct radeon_device *rdev = dev->dev_private;
1173 struct drm_mm *mm = (struct drm_mm *)rdev->mman.bdev.man[ttm_pl].priv;
1174 int ret;
1175 struct ttm_bo_global *glob = rdev->mman.bdev.glob;
1176
1177 spin_lock(&glob->lru_lock);
1178 ret = drm_mm_dump_table(m, mm);
1179 spin_unlock(&glob->lru_lock);
1180 return ret;
1181 }
1182
1183 static int ttm_pl_vram = TTM_PL_VRAM;
1184 static int ttm_pl_tt = TTM_PL_TT;
1185
1186 static struct drm_info_list radeon_ttm_debugfs_list[] = {
1187 {"radeon_vram_mm", radeon_mm_dump_table, 0, &ttm_pl_vram},
1188 {"radeon_gtt_mm", radeon_mm_dump_table, 0, &ttm_pl_tt},
1189 {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
1190 #ifdef CONFIG_SWIOTLB
1191 {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
1192 #endif
1193 };
1194
1195 static int radeon_ttm_vram_open(struct inode *inode, struct file *filep)
1196 {
1197 struct radeon_device *rdev = inode->i_private;
1198 i_size_write(inode, rdev->mc.mc_vram_size);
1199 filep->private_data = inode->i_private;
1200 return 0;
1201 }
1202
1203 static ssize_t radeon_ttm_vram_read(struct file *f, char __user *buf,
1204 size_t size, loff_t *pos)
1205 {
1206 struct radeon_device *rdev = f->private_data;
1207 ssize_t result = 0;
1208 int r;
1209
1210 if (size & 0x3 || *pos & 0x3)
1211 return -EINVAL;
1212
1213 while (size) {
1214 unsigned long flags;
1215 uint32_t value;
1216
1217 if (*pos >= rdev->mc.mc_vram_size)
1218 return result;
1219
1220 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
1221 WREG32(RADEON_MM_INDEX, ((uint32_t)*pos) | 0x80000000);
1222 if (rdev->family >= CHIP_CEDAR)
1223 WREG32(EVERGREEN_MM_INDEX_HI, *pos >> 31);
1224 value = RREG32(RADEON_MM_DATA);
1225 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
1226
1227 r = put_user(value, (uint32_t *)buf);
1228 if (r)
1229 return r;
1230
1231 result += 4;
1232 buf += 4;
1233 *pos += 4;
1234 size -= 4;
1235 }
1236
1237 return result;
1238 }
1239
1240 static const struct file_operations radeon_ttm_vram_fops = {
1241 .owner = THIS_MODULE,
1242 .open = radeon_ttm_vram_open,
1243 .read = radeon_ttm_vram_read,
1244 .llseek = default_llseek
1245 };
1246
1247 static int radeon_ttm_gtt_open(struct inode *inode, struct file *filep)
1248 {
1249 struct radeon_device *rdev = inode->i_private;
1250 i_size_write(inode, rdev->mc.gtt_size);
1251 filep->private_data = inode->i_private;
1252 return 0;
1253 }
1254
1255 static ssize_t radeon_ttm_gtt_read(struct file *f, char __user *buf,
1256 size_t size, loff_t *pos)
1257 {
1258 struct radeon_device *rdev = f->private_data;
1259 ssize_t result = 0;
1260 int r;
1261
1262 while (size) {
1263 loff_t p = *pos / PAGE_SIZE;
1264 unsigned off = *pos & ~PAGE_MASK;
1265 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
1266 struct page *page;
1267 void *ptr;
1268
1269 if (p >= rdev->gart.num_cpu_pages)
1270 return result;
1271
1272 page = rdev->gart.pages[p];
1273 if (page) {
1274 ptr = kmap(page);
1275 ptr += off;
1276
1277 r = copy_to_user(buf, ptr, cur_size);
1278 kunmap(rdev->gart.pages[p]);
1279 } else
1280 r = clear_user(buf, cur_size);
1281
1282 if (r)
1283 return -EFAULT;
1284
1285 result += cur_size;
1286 buf += cur_size;
1287 *pos += cur_size;
1288 size -= cur_size;
1289 }
1290
1291 return result;
1292 }
1293
1294 static const struct file_operations radeon_ttm_gtt_fops = {
1295 .owner = THIS_MODULE,
1296 .open = radeon_ttm_gtt_open,
1297 .read = radeon_ttm_gtt_read,
1298 .llseek = default_llseek
1299 };
1300
1301 #endif
1302
1303 static int radeon_ttm_debugfs_init(struct radeon_device *rdev)
1304 {
1305 #if defined(CONFIG_DEBUG_FS)
1306 unsigned count;
1307
1308 struct drm_minor *minor = rdev->ddev->primary;
1309 struct dentry *ent, *root = minor->debugfs_root;
1310
1311 ent = debugfs_create_file("radeon_vram", S_IFREG | S_IRUGO, root,
1312 rdev, &radeon_ttm_vram_fops);
1313 if (IS_ERR(ent))
1314 return PTR_ERR(ent);
1315 rdev->mman.vram = ent;
1316
1317 ent = debugfs_create_file("radeon_gtt", S_IFREG | S_IRUGO, root,
1318 rdev, &radeon_ttm_gtt_fops);
1319 if (IS_ERR(ent))
1320 return PTR_ERR(ent);
1321 rdev->mman.gtt = ent;
1322
1323 count = ARRAY_SIZE(radeon_ttm_debugfs_list);
1324
1325 #ifdef CONFIG_SWIOTLB
1326 if (!swiotlb_nr_tbl())
1327 --count;
1328 #endif
1329
1330 return radeon_debugfs_add_files(rdev, radeon_ttm_debugfs_list, count);
1331 #else
1332
1333 return 0;
1334 #endif
1335 }
1336
1337 static void radeon_ttm_debugfs_fini(struct radeon_device *rdev)
1338 {
1339 #if defined(CONFIG_DEBUG_FS)
1340
1341 debugfs_remove(rdev->mman.vram);
1342 rdev->mman.vram = NULL;
1343
1344 debugfs_remove(rdev->mman.gtt);
1345 rdev->mman.gtt = NULL;
1346 #endif
1347 }
1348