radeon_uvd.c revision 1.1.1.2
1 /* $NetBSD: radeon_uvd.c,v 1.1.1.2 2018/08/27 01:34:59 riastradh Exp $ */ 2 3 /* 4 * Copyright 2011 Advanced Micro Devices, Inc. 5 * All Rights Reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the 9 * "Software"), to deal in the Software without restriction, including 10 * without limitation the rights to use, copy, modify, merge, publish, 11 * distribute, sub license, and/or sell copies of the Software, and to 12 * permit persons to whom the Software is furnished to do so, subject to 13 * the following conditions: 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * The above copyright notice and this permission notice (including the 24 * next paragraph) shall be included in all copies or substantial portions 25 * of the Software. 26 * 27 */ 28 /* 29 * Authors: 30 * Christian Knig <deathsimple (at) vodafone.de> 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: radeon_uvd.c,v 1.1.1.2 2018/08/27 01:34:59 riastradh Exp $"); 35 36 #include <linux/firmware.h> 37 #include <linux/module.h> 38 #include <drm/drmP.h> 39 #include <drm/drm.h> 40 41 #include "radeon.h" 42 #include "r600d.h" 43 44 /* 1 second timeout */ 45 #define UVD_IDLE_TIMEOUT_MS 1000 46 47 /* Firmware Names */ 48 #define FIRMWARE_R600 "radeon/R600_uvd.bin" 49 #define FIRMWARE_RS780 "radeon/RS780_uvd.bin" 50 #define FIRMWARE_RV770 "radeon/RV770_uvd.bin" 51 #define FIRMWARE_RV710 "radeon/RV710_uvd.bin" 52 #define FIRMWARE_CYPRESS "radeon/CYPRESS_uvd.bin" 53 #define FIRMWARE_SUMO "radeon/SUMO_uvd.bin" 54 #define FIRMWARE_TAHITI "radeon/TAHITI_uvd.bin" 55 #define FIRMWARE_BONAIRE "radeon/BONAIRE_uvd.bin" 56 57 MODULE_FIRMWARE(FIRMWARE_R600); 58 MODULE_FIRMWARE(FIRMWARE_RS780); 59 MODULE_FIRMWARE(FIRMWARE_RV770); 60 MODULE_FIRMWARE(FIRMWARE_RV710); 61 MODULE_FIRMWARE(FIRMWARE_CYPRESS); 62 MODULE_FIRMWARE(FIRMWARE_SUMO); 63 MODULE_FIRMWARE(FIRMWARE_TAHITI); 64 MODULE_FIRMWARE(FIRMWARE_BONAIRE); 65 66 static void radeon_uvd_idle_work_handler(struct work_struct *work); 67 68 int radeon_uvd_init(struct radeon_device *rdev) 69 { 70 unsigned long bo_size; 71 const char *fw_name; 72 int i, r; 73 74 INIT_DELAYED_WORK(&rdev->uvd.idle_work, radeon_uvd_idle_work_handler); 75 76 switch (rdev->family) { 77 case CHIP_RV610: 78 case CHIP_RV630: 79 case CHIP_RV670: 80 case CHIP_RV620: 81 case CHIP_RV635: 82 fw_name = FIRMWARE_R600; 83 break; 84 85 case CHIP_RS780: 86 case CHIP_RS880: 87 fw_name = FIRMWARE_RS780; 88 break; 89 90 case CHIP_RV770: 91 fw_name = FIRMWARE_RV770; 92 break; 93 94 case CHIP_RV710: 95 case CHIP_RV730: 96 case CHIP_RV740: 97 fw_name = FIRMWARE_RV710; 98 break; 99 100 case CHIP_CYPRESS: 101 case CHIP_HEMLOCK: 102 case CHIP_JUNIPER: 103 case CHIP_REDWOOD: 104 case CHIP_CEDAR: 105 fw_name = FIRMWARE_CYPRESS; 106 break; 107 108 case CHIP_SUMO: 109 case CHIP_SUMO2: 110 case CHIP_PALM: 111 case CHIP_CAYMAN: 112 case CHIP_BARTS: 113 case CHIP_TURKS: 114 case CHIP_CAICOS: 115 fw_name = FIRMWARE_SUMO; 116 break; 117 118 case CHIP_TAHITI: 119 case CHIP_VERDE: 120 case CHIP_PITCAIRN: 121 case CHIP_ARUBA: 122 case CHIP_OLAND: 123 fw_name = FIRMWARE_TAHITI; 124 break; 125 126 case CHIP_BONAIRE: 127 case CHIP_KABINI: 128 case CHIP_KAVERI: 129 case CHIP_HAWAII: 130 case CHIP_MULLINS: 131 fw_name = FIRMWARE_BONAIRE; 132 break; 133 134 default: 135 return -EINVAL; 136 } 137 138 r = request_firmware(&rdev->uvd_fw, fw_name, rdev->dev); 139 if (r) { 140 dev_err(rdev->dev, "radeon_uvd: Can't load firmware \"%s\"\n", 141 fw_name); 142 return r; 143 } 144 145 bo_size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->size + 8) + 146 RADEON_UVD_STACK_SIZE + RADEON_UVD_HEAP_SIZE + 147 RADEON_GPU_PAGE_SIZE; 148 r = radeon_bo_create(rdev, bo_size, PAGE_SIZE, true, 149 RADEON_GEM_DOMAIN_VRAM, 0, NULL, 150 NULL, &rdev->uvd.vcpu_bo); 151 if (r) { 152 dev_err(rdev->dev, "(%d) failed to allocate UVD bo\n", r); 153 return r; 154 } 155 156 r = radeon_bo_reserve(rdev->uvd.vcpu_bo, false); 157 if (r) { 158 radeon_bo_unref(&rdev->uvd.vcpu_bo); 159 dev_err(rdev->dev, "(%d) failed to reserve UVD bo\n", r); 160 return r; 161 } 162 163 r = radeon_bo_pin(rdev->uvd.vcpu_bo, RADEON_GEM_DOMAIN_VRAM, 164 &rdev->uvd.gpu_addr); 165 if (r) { 166 radeon_bo_unreserve(rdev->uvd.vcpu_bo); 167 radeon_bo_unref(&rdev->uvd.vcpu_bo); 168 dev_err(rdev->dev, "(%d) UVD bo pin failed\n", r); 169 return r; 170 } 171 172 r = radeon_bo_kmap(rdev->uvd.vcpu_bo, &rdev->uvd.cpu_addr); 173 if (r) { 174 dev_err(rdev->dev, "(%d) UVD map failed\n", r); 175 return r; 176 } 177 178 radeon_bo_unreserve(rdev->uvd.vcpu_bo); 179 180 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) { 181 atomic_set(&rdev->uvd.handles[i], 0); 182 rdev->uvd.filp[i] = NULL; 183 rdev->uvd.img_size[i] = 0; 184 } 185 186 return 0; 187 } 188 189 void radeon_uvd_fini(struct radeon_device *rdev) 190 { 191 int r; 192 193 if (rdev->uvd.vcpu_bo == NULL) 194 return; 195 196 r = radeon_bo_reserve(rdev->uvd.vcpu_bo, false); 197 if (!r) { 198 radeon_bo_kunmap(rdev->uvd.vcpu_bo); 199 radeon_bo_unpin(rdev->uvd.vcpu_bo); 200 radeon_bo_unreserve(rdev->uvd.vcpu_bo); 201 } 202 203 radeon_bo_unref(&rdev->uvd.vcpu_bo); 204 205 radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX]); 206 207 release_firmware(rdev->uvd_fw); 208 } 209 210 int radeon_uvd_suspend(struct radeon_device *rdev) 211 { 212 int i, r; 213 214 if (rdev->uvd.vcpu_bo == NULL) 215 return 0; 216 217 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) { 218 uint32_t handle = atomic_read(&rdev->uvd.handles[i]); 219 if (handle != 0) { 220 struct radeon_fence *fence; 221 222 radeon_uvd_note_usage(rdev); 223 224 r = radeon_uvd_get_destroy_msg(rdev, 225 R600_RING_TYPE_UVD_INDEX, handle, &fence); 226 if (r) { 227 DRM_ERROR("Error destroying UVD (%d)!\n", r); 228 continue; 229 } 230 231 radeon_fence_wait(fence, false); 232 radeon_fence_unref(&fence); 233 234 rdev->uvd.filp[i] = NULL; 235 atomic_set(&rdev->uvd.handles[i], 0); 236 } 237 } 238 239 return 0; 240 } 241 242 int radeon_uvd_resume(struct radeon_device *rdev) 243 { 244 unsigned size; 245 void *ptr; 246 247 if (rdev->uvd.vcpu_bo == NULL) 248 return -EINVAL; 249 250 memcpy(rdev->uvd.cpu_addr, rdev->uvd_fw->data, rdev->uvd_fw->size); 251 252 size = radeon_bo_size(rdev->uvd.vcpu_bo); 253 size -= rdev->uvd_fw->size; 254 255 ptr = rdev->uvd.cpu_addr; 256 ptr += rdev->uvd_fw->size; 257 258 memset(ptr, 0, size); 259 260 return 0; 261 } 262 263 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo, 264 uint32_t allowed_domains) 265 { 266 int i; 267 268 for (i = 0; i < rbo->placement.num_placement; ++i) { 269 rbo->placements[i].fpfn = 0 >> PAGE_SHIFT; 270 rbo->placements[i].lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT; 271 } 272 273 /* If it must be in VRAM it must be in the first segment as well */ 274 if (allowed_domains == RADEON_GEM_DOMAIN_VRAM) 275 return; 276 277 /* abort if we already have more than one placement */ 278 if (rbo->placement.num_placement > 1) 279 return; 280 281 /* add another 256MB segment */ 282 rbo->placements[1] = rbo->placements[0]; 283 rbo->placements[1].fpfn += (256 * 1024 * 1024) >> PAGE_SHIFT; 284 rbo->placements[1].lpfn += (256 * 1024 * 1024) >> PAGE_SHIFT; 285 rbo->placement.num_placement++; 286 rbo->placement.num_busy_placement++; 287 } 288 289 void radeon_uvd_free_handles(struct radeon_device *rdev, struct drm_file *filp) 290 { 291 int i, r; 292 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) { 293 uint32_t handle = atomic_read(&rdev->uvd.handles[i]); 294 if (handle != 0 && rdev->uvd.filp[i] == filp) { 295 struct radeon_fence *fence; 296 297 radeon_uvd_note_usage(rdev); 298 299 r = radeon_uvd_get_destroy_msg(rdev, 300 R600_RING_TYPE_UVD_INDEX, handle, &fence); 301 if (r) { 302 DRM_ERROR("Error destroying UVD (%d)!\n", r); 303 continue; 304 } 305 306 radeon_fence_wait(fence, false); 307 radeon_fence_unref(&fence); 308 309 rdev->uvd.filp[i] = NULL; 310 atomic_set(&rdev->uvd.handles[i], 0); 311 } 312 } 313 } 314 315 static int radeon_uvd_cs_msg_decode(uint32_t *msg, unsigned buf_sizes[]) 316 { 317 unsigned stream_type = msg[4]; 318 unsigned width = msg[6]; 319 unsigned height = msg[7]; 320 unsigned dpb_size = msg[9]; 321 unsigned pitch = msg[28]; 322 323 unsigned width_in_mb = width / 16; 324 unsigned height_in_mb = ALIGN(height / 16, 2); 325 326 unsigned image_size, tmp, min_dpb_size; 327 328 image_size = width * height; 329 image_size += image_size / 2; 330 image_size = ALIGN(image_size, 1024); 331 332 switch (stream_type) { 333 case 0: /* H264 */ 334 335 /* reference picture buffer */ 336 min_dpb_size = image_size * 17; 337 338 /* macroblock context buffer */ 339 min_dpb_size += width_in_mb * height_in_mb * 17 * 192; 340 341 /* IT surface buffer */ 342 min_dpb_size += width_in_mb * height_in_mb * 32; 343 break; 344 345 case 1: /* VC1 */ 346 347 /* reference picture buffer */ 348 min_dpb_size = image_size * 3; 349 350 /* CONTEXT_BUFFER */ 351 min_dpb_size += width_in_mb * height_in_mb * 128; 352 353 /* IT surface buffer */ 354 min_dpb_size += width_in_mb * 64; 355 356 /* DB surface buffer */ 357 min_dpb_size += width_in_mb * 128; 358 359 /* BP */ 360 tmp = max(width_in_mb, height_in_mb); 361 min_dpb_size += ALIGN(tmp * 7 * 16, 64); 362 break; 363 364 case 3: /* MPEG2 */ 365 366 /* reference picture buffer */ 367 min_dpb_size = image_size * 3; 368 break; 369 370 case 4: /* MPEG4 */ 371 372 /* reference picture buffer */ 373 min_dpb_size = image_size * 3; 374 375 /* CM */ 376 min_dpb_size += width_in_mb * height_in_mb * 64; 377 378 /* IT surface buffer */ 379 min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64); 380 break; 381 382 default: 383 DRM_ERROR("UVD codec not handled %d!\n", stream_type); 384 return -EINVAL; 385 } 386 387 if (width > pitch) { 388 DRM_ERROR("Invalid UVD decoding target pitch!\n"); 389 return -EINVAL; 390 } 391 392 if (dpb_size < min_dpb_size) { 393 DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n", 394 dpb_size, min_dpb_size); 395 return -EINVAL; 396 } 397 398 buf_sizes[0x1] = dpb_size; 399 buf_sizes[0x2] = image_size; 400 return 0; 401 } 402 403 static int radeon_uvd_validate_codec(struct radeon_cs_parser *p, 404 unsigned stream_type) 405 { 406 switch (stream_type) { 407 case 0: /* H264 */ 408 case 1: /* VC1 */ 409 /* always supported */ 410 return 0; 411 412 case 3: /* MPEG2 */ 413 case 4: /* MPEG4 */ 414 /* only since UVD 3 */ 415 if (p->rdev->family >= CHIP_PALM) 416 return 0; 417 418 /* fall through */ 419 default: 420 DRM_ERROR("UVD codec not supported by hardware %d!\n", 421 stream_type); 422 return -EINVAL; 423 } 424 } 425 426 static int radeon_uvd_cs_msg(struct radeon_cs_parser *p, struct radeon_bo *bo, 427 unsigned offset, unsigned buf_sizes[]) 428 { 429 int32_t *msg, msg_type, handle; 430 unsigned img_size = 0; 431 struct fence *f; 432 void *ptr; 433 434 int i, r; 435 436 if (offset & 0x3F) { 437 DRM_ERROR("UVD messages must be 64 byte aligned!\n"); 438 return -EINVAL; 439 } 440 441 f = reservation_object_get_excl(bo->tbo.resv); 442 if (f) { 443 r = radeon_fence_wait((struct radeon_fence *)f, false); 444 if (r) { 445 DRM_ERROR("Failed waiting for UVD message (%d)!\n", r); 446 return r; 447 } 448 } 449 450 r = radeon_bo_kmap(bo, &ptr); 451 if (r) { 452 DRM_ERROR("Failed mapping the UVD message (%d)!\n", r); 453 return r; 454 } 455 456 msg = ptr + offset; 457 458 msg_type = msg[1]; 459 handle = msg[2]; 460 461 if (handle == 0) { 462 DRM_ERROR("Invalid UVD handle!\n"); 463 return -EINVAL; 464 } 465 466 switch (msg_type) { 467 case 0: 468 /* it's a create msg, calc image size (width * height) */ 469 img_size = msg[7] * msg[8]; 470 471 r = radeon_uvd_validate_codec(p, msg[4]); 472 radeon_bo_kunmap(bo); 473 if (r) 474 return r; 475 476 /* try to alloc a new handle */ 477 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) { 478 if (atomic_read(&p->rdev->uvd.handles[i]) == handle) { 479 DRM_ERROR("Handle 0x%x already in use!\n", handle); 480 return -EINVAL; 481 } 482 483 if (!atomic_cmpxchg(&p->rdev->uvd.handles[i], 0, handle)) { 484 p->rdev->uvd.filp[i] = p->filp; 485 p->rdev->uvd.img_size[i] = img_size; 486 return 0; 487 } 488 } 489 490 DRM_ERROR("No more free UVD handles!\n"); 491 return -EINVAL; 492 493 case 1: 494 /* it's a decode msg, validate codec and calc buffer sizes */ 495 r = radeon_uvd_validate_codec(p, msg[4]); 496 if (!r) 497 r = radeon_uvd_cs_msg_decode(msg, buf_sizes); 498 radeon_bo_kunmap(bo); 499 if (r) 500 return r; 501 502 /* validate the handle */ 503 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) { 504 if (atomic_read(&p->rdev->uvd.handles[i]) == handle) { 505 if (p->rdev->uvd.filp[i] != p->filp) { 506 DRM_ERROR("UVD handle collision detected!\n"); 507 return -EINVAL; 508 } 509 return 0; 510 } 511 } 512 513 DRM_ERROR("Invalid UVD handle 0x%x!\n", handle); 514 return -ENOENT; 515 516 case 2: 517 /* it's a destroy msg, free the handle */ 518 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) 519 atomic_cmpxchg(&p->rdev->uvd.handles[i], handle, 0); 520 radeon_bo_kunmap(bo); 521 return 0; 522 523 default: 524 525 DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type); 526 return -EINVAL; 527 } 528 529 BUG(); 530 return -EINVAL; 531 } 532 533 static int radeon_uvd_cs_reloc(struct radeon_cs_parser *p, 534 int data0, int data1, 535 unsigned buf_sizes[], bool *has_msg_cmd) 536 { 537 struct radeon_cs_chunk *relocs_chunk; 538 struct radeon_bo_list *reloc; 539 unsigned idx, cmd, offset; 540 uint64_t start, end; 541 int r; 542 543 relocs_chunk = p->chunk_relocs; 544 offset = radeon_get_ib_value(p, data0); 545 idx = radeon_get_ib_value(p, data1); 546 if (idx >= relocs_chunk->length_dw) { 547 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n", 548 idx, relocs_chunk->length_dw); 549 return -EINVAL; 550 } 551 552 reloc = &p->relocs[(idx / 4)]; 553 start = reloc->gpu_offset; 554 end = start + radeon_bo_size(reloc->robj); 555 start += offset; 556 557 p->ib.ptr[data0] = start & 0xFFFFFFFF; 558 p->ib.ptr[data1] = start >> 32; 559 560 cmd = radeon_get_ib_value(p, p->idx) >> 1; 561 562 if (cmd < 0x4) { 563 if (end <= start) { 564 DRM_ERROR("invalid reloc offset %X!\n", offset); 565 return -EINVAL; 566 } 567 if ((end - start) < buf_sizes[cmd]) { 568 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd, 569 (unsigned)(end - start), buf_sizes[cmd]); 570 return -EINVAL; 571 } 572 573 } else if (cmd != 0x100) { 574 DRM_ERROR("invalid UVD command %X!\n", cmd); 575 return -EINVAL; 576 } 577 578 if ((start >> 28) != ((end - 1) >> 28)) { 579 DRM_ERROR("reloc %LX-%LX crossing 256MB boundary!\n", 580 start, end); 581 return -EINVAL; 582 } 583 584 /* TODO: is this still necessary on NI+ ? */ 585 if ((cmd == 0 || cmd == 0x3) && 586 (start >> 28) != (p->rdev->uvd.gpu_addr >> 28)) { 587 DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n", 588 start, end); 589 return -EINVAL; 590 } 591 592 if (cmd == 0) { 593 if (*has_msg_cmd) { 594 DRM_ERROR("More than one message in a UVD-IB!\n"); 595 return -EINVAL; 596 } 597 *has_msg_cmd = true; 598 r = radeon_uvd_cs_msg(p, reloc->robj, offset, buf_sizes); 599 if (r) 600 return r; 601 } else if (!*has_msg_cmd) { 602 DRM_ERROR("Message needed before other commands are send!\n"); 603 return -EINVAL; 604 } 605 606 return 0; 607 } 608 609 static int radeon_uvd_cs_reg(struct radeon_cs_parser *p, 610 struct radeon_cs_packet *pkt, 611 int *data0, int *data1, 612 unsigned buf_sizes[], 613 bool *has_msg_cmd) 614 { 615 int i, r; 616 617 p->idx++; 618 for (i = 0; i <= pkt->count; ++i) { 619 switch (pkt->reg + i*4) { 620 case UVD_GPCOM_VCPU_DATA0: 621 *data0 = p->idx; 622 break; 623 case UVD_GPCOM_VCPU_DATA1: 624 *data1 = p->idx; 625 break; 626 case UVD_GPCOM_VCPU_CMD: 627 r = radeon_uvd_cs_reloc(p, *data0, *data1, 628 buf_sizes, has_msg_cmd); 629 if (r) 630 return r; 631 break; 632 case UVD_ENGINE_CNTL: 633 break; 634 default: 635 DRM_ERROR("Invalid reg 0x%X!\n", 636 pkt->reg + i*4); 637 return -EINVAL; 638 } 639 p->idx++; 640 } 641 return 0; 642 } 643 644 int radeon_uvd_cs_parse(struct radeon_cs_parser *p) 645 { 646 struct radeon_cs_packet pkt; 647 int r, data0 = 0, data1 = 0; 648 649 /* does the IB has a msg command */ 650 bool has_msg_cmd = false; 651 652 /* minimum buffer sizes */ 653 unsigned buf_sizes[] = { 654 [0x00000000] = 2048, 655 [0x00000001] = 32 * 1024 * 1024, 656 [0x00000002] = 2048 * 1152 * 3, 657 [0x00000003] = 2048, 658 }; 659 660 if (p->chunk_ib->length_dw % 16) { 661 DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n", 662 p->chunk_ib->length_dw); 663 return -EINVAL; 664 } 665 666 if (p->chunk_relocs == NULL) { 667 DRM_ERROR("No relocation chunk !\n"); 668 return -EINVAL; 669 } 670 671 672 do { 673 r = radeon_cs_packet_parse(p, &pkt, p->idx); 674 if (r) 675 return r; 676 switch (pkt.type) { 677 case RADEON_PACKET_TYPE0: 678 r = radeon_uvd_cs_reg(p, &pkt, &data0, &data1, 679 buf_sizes, &has_msg_cmd); 680 if (r) 681 return r; 682 break; 683 case RADEON_PACKET_TYPE2: 684 p->idx += pkt.count + 2; 685 break; 686 default: 687 DRM_ERROR("Unknown packet type %d !\n", pkt.type); 688 return -EINVAL; 689 } 690 } while (p->idx < p->chunk_ib->length_dw); 691 692 if (!has_msg_cmd) { 693 DRM_ERROR("UVD-IBs need a msg command!\n"); 694 return -EINVAL; 695 } 696 697 return 0; 698 } 699 700 static int radeon_uvd_send_msg(struct radeon_device *rdev, 701 int ring, uint64_t addr, 702 struct radeon_fence **fence) 703 { 704 struct radeon_ib ib; 705 int i, r; 706 707 r = radeon_ib_get(rdev, ring, &ib, NULL, 64); 708 if (r) 709 return r; 710 711 ib.ptr[0] = PACKET0(UVD_GPCOM_VCPU_DATA0, 0); 712 ib.ptr[1] = addr; 713 ib.ptr[2] = PACKET0(UVD_GPCOM_VCPU_DATA1, 0); 714 ib.ptr[3] = addr >> 32; 715 ib.ptr[4] = PACKET0(UVD_GPCOM_VCPU_CMD, 0); 716 ib.ptr[5] = 0; 717 for (i = 6; i < 16; ++i) 718 ib.ptr[i] = PACKET2(0); 719 ib.length_dw = 16; 720 721 r = radeon_ib_schedule(rdev, &ib, NULL, false); 722 723 if (fence) 724 *fence = radeon_fence_ref(ib.fence); 725 726 radeon_ib_free(rdev, &ib); 727 return r; 728 } 729 730 /* multiple fence commands without any stream commands in between can 731 crash the vcpu so just try to emmit a dummy create/destroy msg to 732 avoid this */ 733 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring, 734 uint32_t handle, struct radeon_fence **fence) 735 { 736 /* we use the last page of the vcpu bo for the UVD message */ 737 uint64_t offs = radeon_bo_size(rdev->uvd.vcpu_bo) - 738 RADEON_GPU_PAGE_SIZE; 739 740 uint32_t *msg = rdev->uvd.cpu_addr + offs; 741 uint64_t addr = rdev->uvd.gpu_addr + offs; 742 743 int r, i; 744 745 r = radeon_bo_reserve(rdev->uvd.vcpu_bo, true); 746 if (r) 747 return r; 748 749 /* stitch together an UVD create msg */ 750 msg[0] = cpu_to_le32(0x00000de4); 751 msg[1] = cpu_to_le32(0x00000000); 752 msg[2] = cpu_to_le32(handle); 753 msg[3] = cpu_to_le32(0x00000000); 754 msg[4] = cpu_to_le32(0x00000000); 755 msg[5] = cpu_to_le32(0x00000000); 756 msg[6] = cpu_to_le32(0x00000000); 757 msg[7] = cpu_to_le32(0x00000780); 758 msg[8] = cpu_to_le32(0x00000440); 759 msg[9] = cpu_to_le32(0x00000000); 760 msg[10] = cpu_to_le32(0x01b37000); 761 for (i = 11; i < 1024; ++i) 762 msg[i] = cpu_to_le32(0x0); 763 764 r = radeon_uvd_send_msg(rdev, ring, addr, fence); 765 radeon_bo_unreserve(rdev->uvd.vcpu_bo); 766 return r; 767 } 768 769 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring, 770 uint32_t handle, struct radeon_fence **fence) 771 { 772 /* we use the last page of the vcpu bo for the UVD message */ 773 uint64_t offs = radeon_bo_size(rdev->uvd.vcpu_bo) - 774 RADEON_GPU_PAGE_SIZE; 775 776 uint32_t *msg = rdev->uvd.cpu_addr + offs; 777 uint64_t addr = rdev->uvd.gpu_addr + offs; 778 779 int r, i; 780 781 r = radeon_bo_reserve(rdev->uvd.vcpu_bo, true); 782 if (r) 783 return r; 784 785 /* stitch together an UVD destroy msg */ 786 msg[0] = cpu_to_le32(0x00000de4); 787 msg[1] = cpu_to_le32(0x00000002); 788 msg[2] = cpu_to_le32(handle); 789 msg[3] = cpu_to_le32(0x00000000); 790 for (i = 4; i < 1024; ++i) 791 msg[i] = cpu_to_le32(0x0); 792 793 r = radeon_uvd_send_msg(rdev, ring, addr, fence); 794 radeon_bo_unreserve(rdev->uvd.vcpu_bo); 795 return r; 796 } 797 798 /** 799 * radeon_uvd_count_handles - count number of open streams 800 * 801 * @rdev: radeon_device pointer 802 * @sd: number of SD streams 803 * @hd: number of HD streams 804 * 805 * Count the number of open SD/HD streams as a hint for power mangement 806 */ 807 static void radeon_uvd_count_handles(struct radeon_device *rdev, 808 unsigned *sd, unsigned *hd) 809 { 810 unsigned i; 811 812 *sd = 0; 813 *hd = 0; 814 815 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) { 816 if (!atomic_read(&rdev->uvd.handles[i])) 817 continue; 818 819 if (rdev->uvd.img_size[i] >= 720*576) 820 ++(*hd); 821 else 822 ++(*sd); 823 } 824 } 825 826 static void radeon_uvd_idle_work_handler(struct work_struct *work) 827 { 828 struct radeon_device *rdev = 829 container_of(work, struct radeon_device, uvd.idle_work.work); 830 831 if (radeon_fence_count_emitted(rdev, R600_RING_TYPE_UVD_INDEX) == 0) { 832 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { 833 radeon_uvd_count_handles(rdev, &rdev->pm.dpm.sd, 834 &rdev->pm.dpm.hd); 835 radeon_dpm_enable_uvd(rdev, false); 836 } else { 837 radeon_set_uvd_clocks(rdev, 0, 0); 838 } 839 } else { 840 schedule_delayed_work(&rdev->uvd.idle_work, 841 msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS)); 842 } 843 } 844 845 void radeon_uvd_note_usage(struct radeon_device *rdev) 846 { 847 bool streams_changed = false; 848 bool set_clocks = !cancel_delayed_work_sync(&rdev->uvd.idle_work); 849 set_clocks &= schedule_delayed_work(&rdev->uvd.idle_work, 850 msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS)); 851 852 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { 853 unsigned hd = 0, sd = 0; 854 radeon_uvd_count_handles(rdev, &sd, &hd); 855 if ((rdev->pm.dpm.sd != sd) || 856 (rdev->pm.dpm.hd != hd)) { 857 rdev->pm.dpm.sd = sd; 858 rdev->pm.dpm.hd = hd; 859 /* disable this for now */ 860 /*streams_changed = true;*/ 861 } 862 } 863 864 if (set_clocks || streams_changed) { 865 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { 866 radeon_dpm_enable_uvd(rdev, true); 867 } else { 868 radeon_set_uvd_clocks(rdev, 53300, 40000); 869 } 870 } 871 } 872 873 static unsigned radeon_uvd_calc_upll_post_div(unsigned vco_freq, 874 unsigned target_freq, 875 unsigned pd_min, 876 unsigned pd_even) 877 { 878 unsigned post_div = vco_freq / target_freq; 879 880 /* adjust to post divider minimum value */ 881 if (post_div < pd_min) 882 post_div = pd_min; 883 884 /* we alway need a frequency less than or equal the target */ 885 if ((vco_freq / post_div) > target_freq) 886 post_div += 1; 887 888 /* post dividers above a certain value must be even */ 889 if (post_div > pd_even && post_div % 2) 890 post_div += 1; 891 892 return post_div; 893 } 894 895 /** 896 * radeon_uvd_calc_upll_dividers - calc UPLL clock dividers 897 * 898 * @rdev: radeon_device pointer 899 * @vclk: wanted VCLK 900 * @dclk: wanted DCLK 901 * @vco_min: minimum VCO frequency 902 * @vco_max: maximum VCO frequency 903 * @fb_factor: factor to multiply vco freq with 904 * @fb_mask: limit and bitmask for feedback divider 905 * @pd_min: post divider minimum 906 * @pd_max: post divider maximum 907 * @pd_even: post divider must be even above this value 908 * @optimal_fb_div: resulting feedback divider 909 * @optimal_vclk_div: resulting vclk post divider 910 * @optimal_dclk_div: resulting dclk post divider 911 * 912 * Calculate dividers for UVDs UPLL (R6xx-SI, except APUs). 913 * Returns zero on success -EINVAL on error. 914 */ 915 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev, 916 unsigned vclk, unsigned dclk, 917 unsigned vco_min, unsigned vco_max, 918 unsigned fb_factor, unsigned fb_mask, 919 unsigned pd_min, unsigned pd_max, 920 unsigned pd_even, 921 unsigned *optimal_fb_div, 922 unsigned *optimal_vclk_div, 923 unsigned *optimal_dclk_div) 924 { 925 unsigned vco_freq, ref_freq = rdev->clock.spll.reference_freq; 926 927 /* start off with something large */ 928 unsigned optimal_score = ~0; 929 930 /* loop through vco from low to high */ 931 vco_min = max(max(vco_min, vclk), dclk); 932 for (vco_freq = vco_min; vco_freq <= vco_max; vco_freq += 100) { 933 934 uint64_t fb_div = (uint64_t)vco_freq * fb_factor; 935 unsigned vclk_div, dclk_div, score; 936 937 do_div(fb_div, ref_freq); 938 939 /* fb div out of range ? */ 940 if (fb_div > fb_mask) 941 break; /* it can oly get worse */ 942 943 fb_div &= fb_mask; 944 945 /* calc vclk divider with current vco freq */ 946 vclk_div = radeon_uvd_calc_upll_post_div(vco_freq, vclk, 947 pd_min, pd_even); 948 if (vclk_div > pd_max) 949 break; /* vco is too big, it has to stop */ 950 951 /* calc dclk divider with current vco freq */ 952 dclk_div = radeon_uvd_calc_upll_post_div(vco_freq, dclk, 953 pd_min, pd_even); 954 if (dclk_div > pd_max) 955 break; /* vco is too big, it has to stop */ 956 957 /* calc score with current vco freq */ 958 score = vclk - (vco_freq / vclk_div) + dclk - (vco_freq / dclk_div); 959 960 /* determine if this vco setting is better than current optimal settings */ 961 if (score < optimal_score) { 962 *optimal_fb_div = fb_div; 963 *optimal_vclk_div = vclk_div; 964 *optimal_dclk_div = dclk_div; 965 optimal_score = score; 966 if (optimal_score == 0) 967 break; /* it can't get better than this */ 968 } 969 } 970 971 /* did we found a valid setup ? */ 972 if (optimal_score == ~0) 973 return -EINVAL; 974 975 return 0; 976 } 977 978 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev, 979 unsigned cg_upll_func_cntl) 980 { 981 unsigned i; 982 983 /* make sure UPLL_CTLREQ is deasserted */ 984 WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK); 985 986 mdelay(10); 987 988 /* assert UPLL_CTLREQ */ 989 WREG32_P(cg_upll_func_cntl, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK); 990 991 /* wait for CTLACK and CTLACK2 to get asserted */ 992 for (i = 0; i < 100; ++i) { 993 uint32_t mask = UPLL_CTLACK_MASK | UPLL_CTLACK2_MASK; 994 if ((RREG32(cg_upll_func_cntl) & mask) == mask) 995 break; 996 mdelay(10); 997 } 998 999 /* deassert UPLL_CTLREQ */ 1000 WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK); 1001 1002 if (i == 100) { 1003 DRM_ERROR("Timeout setting UVD clocks!\n"); 1004 return -ETIMEDOUT; 1005 } 1006 1007 return 0; 1008 } 1009
Indexes created Sun Oct 26 21:10:03 GMT 2025