radeon_uvd.c revision 1.1.1.3
1 /* $NetBSD: radeon_uvd.c,v 1.1.1.3 2021/12/18 20:15:52 riastradh Exp $ */ 2 3 /* 4 * Copyright 2011 Advanced Micro Devices, Inc. 5 * All Rights Reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the 9 * "Software"), to deal in the Software without restriction, including 10 * without limitation the rights to use, copy, modify, merge, publish, 11 * distribute, sub license, and/or sell copies of the Software, and to 12 * permit persons to whom the Software is furnished to do so, subject to 13 * the following conditions: 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * The above copyright notice and this permission notice (including the 24 * next paragraph) shall be included in all copies or substantial portions 25 * of the Software. 26 * 27 */ 28 /* 29 * Authors: 30 * Christian Knig <deathsimple (at) vodafone.de> 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: radeon_uvd.c,v 1.1.1.3 2021/12/18 20:15:52 riastradh Exp $"); 35 36 #include <linux/firmware.h> 37 #include <linux/module.h> 38 39 #include <drm/drm.h> 40 41 #include "radeon.h" 42 #include "radeon_ucode.h" 43 #include "r600d.h" 44 45 /* 1 second timeout */ 46 #define UVD_IDLE_TIMEOUT_MS 1000 47 48 /* Firmware Names */ 49 #define FIRMWARE_R600 "radeon/R600_uvd.bin" 50 #define FIRMWARE_RS780 "radeon/RS780_uvd.bin" 51 #define FIRMWARE_RV770 "radeon/RV770_uvd.bin" 52 #define FIRMWARE_RV710 "radeon/RV710_uvd.bin" 53 #define FIRMWARE_CYPRESS "radeon/CYPRESS_uvd.bin" 54 #define FIRMWARE_SUMO "radeon/SUMO_uvd.bin" 55 #define FIRMWARE_TAHITI "radeon/TAHITI_uvd.bin" 56 #define FIRMWARE_BONAIRE_LEGACY "radeon/BONAIRE_uvd.bin" 57 #define FIRMWARE_BONAIRE "radeon/bonaire_uvd.bin" 58 59 MODULE_FIRMWARE(FIRMWARE_R600); 60 MODULE_FIRMWARE(FIRMWARE_RS780); 61 MODULE_FIRMWARE(FIRMWARE_RV770); 62 MODULE_FIRMWARE(FIRMWARE_RV710); 63 MODULE_FIRMWARE(FIRMWARE_CYPRESS); 64 MODULE_FIRMWARE(FIRMWARE_SUMO); 65 MODULE_FIRMWARE(FIRMWARE_TAHITI); 66 MODULE_FIRMWARE(FIRMWARE_BONAIRE_LEGACY); 67 MODULE_FIRMWARE(FIRMWARE_BONAIRE); 68 69 static void radeon_uvd_idle_work_handler(struct work_struct *work); 70 71 int radeon_uvd_init(struct radeon_device *rdev) 72 { 73 unsigned long bo_size; 74 const char *fw_name = NULL, *legacy_fw_name = NULL; 75 int i, r; 76 77 INIT_DELAYED_WORK(&rdev->uvd.idle_work, radeon_uvd_idle_work_handler); 78 79 switch (rdev->family) { 80 case CHIP_RV610: 81 case CHIP_RV630: 82 case CHIP_RV670: 83 case CHIP_RV620: 84 case CHIP_RV635: 85 legacy_fw_name = FIRMWARE_R600; 86 break; 87 88 case CHIP_RS780: 89 case CHIP_RS880: 90 legacy_fw_name = FIRMWARE_RS780; 91 break; 92 93 case CHIP_RV770: 94 legacy_fw_name = FIRMWARE_RV770; 95 break; 96 97 case CHIP_RV710: 98 case CHIP_RV730: 99 case CHIP_RV740: 100 legacy_fw_name = FIRMWARE_RV710; 101 break; 102 103 case CHIP_CYPRESS: 104 case CHIP_HEMLOCK: 105 case CHIP_JUNIPER: 106 case CHIP_REDWOOD: 107 case CHIP_CEDAR: 108 legacy_fw_name = FIRMWARE_CYPRESS; 109 break; 110 111 case CHIP_SUMO: 112 case CHIP_SUMO2: 113 case CHIP_PALM: 114 case CHIP_CAYMAN: 115 case CHIP_BARTS: 116 case CHIP_TURKS: 117 case CHIP_CAICOS: 118 legacy_fw_name = FIRMWARE_SUMO; 119 break; 120 121 case CHIP_TAHITI: 122 case CHIP_VERDE: 123 case CHIP_PITCAIRN: 124 case CHIP_ARUBA: 125 case CHIP_OLAND: 126 legacy_fw_name = FIRMWARE_TAHITI; 127 break; 128 129 case CHIP_BONAIRE: 130 case CHIP_KABINI: 131 case CHIP_KAVERI: 132 case CHIP_HAWAII: 133 case CHIP_MULLINS: 134 legacy_fw_name = FIRMWARE_BONAIRE_LEGACY; 135 fw_name = FIRMWARE_BONAIRE; 136 break; 137 138 default: 139 return -EINVAL; 140 } 141 142 rdev->uvd.fw_header_present = false; 143 rdev->uvd.max_handles = RADEON_DEFAULT_UVD_HANDLES; 144 if (fw_name) { 145 /* Let's try to load the newer firmware first */ 146 r = request_firmware(&rdev->uvd_fw, fw_name, rdev->dev); 147 if (r) { 148 dev_err(rdev->dev, "radeon_uvd: Can't load firmware \"%s\"\n", 149 fw_name); 150 } else { 151 struct common_firmware_header *hdr = (void *)rdev->uvd_fw->data; 152 unsigned version_major, version_minor, family_id; 153 154 r = radeon_ucode_validate(rdev->uvd_fw); 155 if (r) 156 return r; 157 158 rdev->uvd.fw_header_present = true; 159 160 family_id = le32_to_cpu(hdr->ucode_version) & 0xff; 161 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff; 162 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff; 163 DRM_INFO("Found UVD firmware Version: %hu.%hu Family ID: %hu\n", 164 version_major, version_minor, family_id); 165 166 /* 167 * Limit the number of UVD handles depending on 168 * microcode major and minor versions. 169 */ 170 if ((version_major >= 0x01) && (version_minor >= 0x37)) 171 rdev->uvd.max_handles = RADEON_MAX_UVD_HANDLES; 172 } 173 } 174 175 /* 176 * In case there is only legacy firmware, or we encounter an error 177 * while loading the new firmware, we fall back to loading the legacy 178 * firmware now. 179 */ 180 if (!fw_name || r) { 181 r = request_firmware(&rdev->uvd_fw, legacy_fw_name, rdev->dev); 182 if (r) { 183 dev_err(rdev->dev, "radeon_uvd: Can't load firmware \"%s\"\n", 184 legacy_fw_name); 185 return r; 186 } 187 } 188 189 bo_size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->size + 8) + 190 RADEON_UVD_STACK_SIZE + RADEON_UVD_HEAP_SIZE + 191 RADEON_UVD_SESSION_SIZE * rdev->uvd.max_handles; 192 r = radeon_bo_create(rdev, bo_size, PAGE_SIZE, true, 193 RADEON_GEM_DOMAIN_VRAM, 0, NULL, 194 NULL, &rdev->uvd.vcpu_bo); 195 if (r) { 196 dev_err(rdev->dev, "(%d) failed to allocate UVD bo\n", r); 197 return r; 198 } 199 200 r = radeon_bo_reserve(rdev->uvd.vcpu_bo, false); 201 if (r) { 202 radeon_bo_unref(&rdev->uvd.vcpu_bo); 203 dev_err(rdev->dev, "(%d) failed to reserve UVD bo\n", r); 204 return r; 205 } 206 207 r = radeon_bo_pin(rdev->uvd.vcpu_bo, RADEON_GEM_DOMAIN_VRAM, 208 &rdev->uvd.gpu_addr); 209 if (r) { 210 radeon_bo_unreserve(rdev->uvd.vcpu_bo); 211 radeon_bo_unref(&rdev->uvd.vcpu_bo); 212 dev_err(rdev->dev, "(%d) UVD bo pin failed\n", r); 213 return r; 214 } 215 216 r = radeon_bo_kmap(rdev->uvd.vcpu_bo, &rdev->uvd.cpu_addr); 217 if (r) { 218 dev_err(rdev->dev, "(%d) UVD map failed\n", r); 219 return r; 220 } 221 222 radeon_bo_unreserve(rdev->uvd.vcpu_bo); 223 224 for (i = 0; i < rdev->uvd.max_handles; ++i) { 225 atomic_set(&rdev->uvd.handles[i], 0); 226 rdev->uvd.filp[i] = NULL; 227 rdev->uvd.img_size[i] = 0; 228 } 229 230 return 0; 231 } 232 233 void radeon_uvd_fini(struct radeon_device *rdev) 234 { 235 int r; 236 237 if (rdev->uvd.vcpu_bo == NULL) 238 return; 239 240 r = radeon_bo_reserve(rdev->uvd.vcpu_bo, false); 241 if (!r) { 242 radeon_bo_kunmap(rdev->uvd.vcpu_bo); 243 radeon_bo_unpin(rdev->uvd.vcpu_bo); 244 radeon_bo_unreserve(rdev->uvd.vcpu_bo); 245 } 246 247 radeon_bo_unref(&rdev->uvd.vcpu_bo); 248 249 radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX]); 250 251 release_firmware(rdev->uvd_fw); 252 } 253 254 int radeon_uvd_suspend(struct radeon_device *rdev) 255 { 256 int i, r; 257 258 if (rdev->uvd.vcpu_bo == NULL) 259 return 0; 260 261 for (i = 0; i < rdev->uvd.max_handles; ++i) { 262 uint32_t handle = atomic_read(&rdev->uvd.handles[i]); 263 if (handle != 0) { 264 struct radeon_fence *fence; 265 266 radeon_uvd_note_usage(rdev); 267 268 r = radeon_uvd_get_destroy_msg(rdev, 269 R600_RING_TYPE_UVD_INDEX, handle, &fence); 270 if (r) { 271 DRM_ERROR("Error destroying UVD (%d)!\n", r); 272 continue; 273 } 274 275 radeon_fence_wait(fence, false); 276 radeon_fence_unref(&fence); 277 278 rdev->uvd.filp[i] = NULL; 279 atomic_set(&rdev->uvd.handles[i], 0); 280 } 281 } 282 283 return 0; 284 } 285 286 int radeon_uvd_resume(struct radeon_device *rdev) 287 { 288 unsigned size; 289 void *ptr; 290 291 if (rdev->uvd.vcpu_bo == NULL) 292 return -EINVAL; 293 294 memcpy(rdev->uvd.cpu_addr, rdev->uvd_fw->data, rdev->uvd_fw->size); 295 296 size = radeon_bo_size(rdev->uvd.vcpu_bo); 297 size -= rdev->uvd_fw->size; 298 299 ptr = rdev->uvd.cpu_addr; 300 ptr += rdev->uvd_fw->size; 301 302 memset(ptr, 0, size); 303 304 return 0; 305 } 306 307 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo, 308 uint32_t allowed_domains) 309 { 310 int i; 311 312 for (i = 0; i < rbo->placement.num_placement; ++i) { 313 rbo->placements[i].fpfn = 0 >> PAGE_SHIFT; 314 rbo->placements[i].lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT; 315 } 316 317 /* If it must be in VRAM it must be in the first segment as well */ 318 if (allowed_domains == RADEON_GEM_DOMAIN_VRAM) 319 return; 320 321 /* abort if we already have more than one placement */ 322 if (rbo->placement.num_placement > 1) 323 return; 324 325 /* add another 256MB segment */ 326 rbo->placements[1] = rbo->placements[0]; 327 rbo->placements[1].fpfn += (256 * 1024 * 1024) >> PAGE_SHIFT; 328 rbo->placements[1].lpfn += (256 * 1024 * 1024) >> PAGE_SHIFT; 329 rbo->placement.num_placement++; 330 rbo->placement.num_busy_placement++; 331 } 332 333 void radeon_uvd_free_handles(struct radeon_device *rdev, struct drm_file *filp) 334 { 335 int i, r; 336 for (i = 0; i < rdev->uvd.max_handles; ++i) { 337 uint32_t handle = atomic_read(&rdev->uvd.handles[i]); 338 if (handle != 0 && rdev->uvd.filp[i] == filp) { 339 struct radeon_fence *fence; 340 341 radeon_uvd_note_usage(rdev); 342 343 r = radeon_uvd_get_destroy_msg(rdev, 344 R600_RING_TYPE_UVD_INDEX, handle, &fence); 345 if (r) { 346 DRM_ERROR("Error destroying UVD (%d)!\n", r); 347 continue; 348 } 349 350 radeon_fence_wait(fence, false); 351 radeon_fence_unref(&fence); 352 353 rdev->uvd.filp[i] = NULL; 354 atomic_set(&rdev->uvd.handles[i], 0); 355 } 356 } 357 } 358 359 static int radeon_uvd_cs_msg_decode(uint32_t *msg, unsigned buf_sizes[]) 360 { 361 unsigned stream_type = msg[4]; 362 unsigned width = msg[6]; 363 unsigned height = msg[7]; 364 unsigned dpb_size = msg[9]; 365 unsigned pitch = msg[28]; 366 367 unsigned width_in_mb = width / 16; 368 unsigned height_in_mb = ALIGN(height / 16, 2); 369 370 unsigned image_size, tmp, min_dpb_size; 371 372 image_size = width * height; 373 image_size += image_size / 2; 374 image_size = ALIGN(image_size, 1024); 375 376 switch (stream_type) { 377 case 0: /* H264 */ 378 379 /* reference picture buffer */ 380 min_dpb_size = image_size * 17; 381 382 /* macroblock context buffer */ 383 min_dpb_size += width_in_mb * height_in_mb * 17 * 192; 384 385 /* IT surface buffer */ 386 min_dpb_size += width_in_mb * height_in_mb * 32; 387 break; 388 389 case 1: /* VC1 */ 390 391 /* reference picture buffer */ 392 min_dpb_size = image_size * 3; 393 394 /* CONTEXT_BUFFER */ 395 min_dpb_size += width_in_mb * height_in_mb * 128; 396 397 /* IT surface buffer */ 398 min_dpb_size += width_in_mb * 64; 399 400 /* DB surface buffer */ 401 min_dpb_size += width_in_mb * 128; 402 403 /* BP */ 404 tmp = max(width_in_mb, height_in_mb); 405 min_dpb_size += ALIGN(tmp * 7 * 16, 64); 406 break; 407 408 case 3: /* MPEG2 */ 409 410 /* reference picture buffer */ 411 min_dpb_size = image_size * 3; 412 break; 413 414 case 4: /* MPEG4 */ 415 416 /* reference picture buffer */ 417 min_dpb_size = image_size * 3; 418 419 /* CM */ 420 min_dpb_size += width_in_mb * height_in_mb * 64; 421 422 /* IT surface buffer */ 423 min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64); 424 break; 425 426 default: 427 DRM_ERROR("UVD codec not handled %d!\n", stream_type); 428 return -EINVAL; 429 } 430 431 if (width > pitch) { 432 DRM_ERROR("Invalid UVD decoding target pitch!\n"); 433 return -EINVAL; 434 } 435 436 if (dpb_size < min_dpb_size) { 437 DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n", 438 dpb_size, min_dpb_size); 439 return -EINVAL; 440 } 441 442 buf_sizes[0x1] = dpb_size; 443 buf_sizes[0x2] = image_size; 444 return 0; 445 } 446 447 static int radeon_uvd_validate_codec(struct radeon_cs_parser *p, 448 unsigned stream_type) 449 { 450 switch (stream_type) { 451 case 0: /* H264 */ 452 case 1: /* VC1 */ 453 /* always supported */ 454 return 0; 455 456 case 3: /* MPEG2 */ 457 case 4: /* MPEG4 */ 458 /* only since UVD 3 */ 459 if (p->rdev->family >= CHIP_PALM) 460 return 0; 461 462 /* fall through */ 463 default: 464 DRM_ERROR("UVD codec not supported by hardware %d!\n", 465 stream_type); 466 return -EINVAL; 467 } 468 } 469 470 static int radeon_uvd_cs_msg(struct radeon_cs_parser *p, struct radeon_bo *bo, 471 unsigned offset, unsigned buf_sizes[]) 472 { 473 int32_t *msg, msg_type, handle; 474 unsigned img_size = 0; 475 struct dma_fence *f; 476 void *ptr; 477 478 int i, r; 479 480 if (offset & 0x3F) { 481 DRM_ERROR("UVD messages must be 64 byte aligned!\n"); 482 return -EINVAL; 483 } 484 485 f = dma_resv_get_excl(bo->tbo.base.resv); 486 if (f) { 487 r = radeon_fence_wait((struct radeon_fence *)f, false); 488 if (r) { 489 DRM_ERROR("Failed waiting for UVD message (%d)!\n", r); 490 return r; 491 } 492 } 493 494 r = radeon_bo_kmap(bo, &ptr); 495 if (r) { 496 DRM_ERROR("Failed mapping the UVD message (%d)!\n", r); 497 return r; 498 } 499 500 msg = ptr + offset; 501 502 msg_type = msg[1]; 503 handle = msg[2]; 504 505 if (handle == 0) { 506 DRM_ERROR("Invalid UVD handle!\n"); 507 return -EINVAL; 508 } 509 510 switch (msg_type) { 511 case 0: 512 /* it's a create msg, calc image size (width * height) */ 513 img_size = msg[7] * msg[8]; 514 515 r = radeon_uvd_validate_codec(p, msg[4]); 516 radeon_bo_kunmap(bo); 517 if (r) 518 return r; 519 520 /* try to alloc a new handle */ 521 for (i = 0; i < p->rdev->uvd.max_handles; ++i) { 522 if (atomic_read(&p->rdev->uvd.handles[i]) == handle) { 523 DRM_ERROR("Handle 0x%x already in use!\n", handle); 524 return -EINVAL; 525 } 526 527 if (!atomic_cmpxchg(&p->rdev->uvd.handles[i], 0, handle)) { 528 p->rdev->uvd.filp[i] = p->filp; 529 p->rdev->uvd.img_size[i] = img_size; 530 return 0; 531 } 532 } 533 534 DRM_ERROR("No more free UVD handles!\n"); 535 return -EINVAL; 536 537 case 1: 538 /* it's a decode msg, validate codec and calc buffer sizes */ 539 r = radeon_uvd_validate_codec(p, msg[4]); 540 if (!r) 541 r = radeon_uvd_cs_msg_decode(msg, buf_sizes); 542 radeon_bo_kunmap(bo); 543 if (r) 544 return r; 545 546 /* validate the handle */ 547 for (i = 0; i < p->rdev->uvd.max_handles; ++i) { 548 if (atomic_read(&p->rdev->uvd.handles[i]) == handle) { 549 if (p->rdev->uvd.filp[i] != p->filp) { 550 DRM_ERROR("UVD handle collision detected!\n"); 551 return -EINVAL; 552 } 553 return 0; 554 } 555 } 556 557 DRM_ERROR("Invalid UVD handle 0x%x!\n", handle); 558 return -ENOENT; 559 560 case 2: 561 /* it's a destroy msg, free the handle */ 562 for (i = 0; i < p->rdev->uvd.max_handles; ++i) 563 atomic_cmpxchg(&p->rdev->uvd.handles[i], handle, 0); 564 radeon_bo_kunmap(bo); 565 return 0; 566 567 default: 568 569 DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type); 570 return -EINVAL; 571 } 572 573 BUG(); 574 return -EINVAL; 575 } 576 577 static int radeon_uvd_cs_reloc(struct radeon_cs_parser *p, 578 int data0, int data1, 579 unsigned buf_sizes[], bool *has_msg_cmd) 580 { 581 struct radeon_cs_chunk *relocs_chunk; 582 struct radeon_bo_list *reloc; 583 unsigned idx, cmd, offset; 584 uint64_t start, end; 585 int r; 586 587 relocs_chunk = p->chunk_relocs; 588 offset = radeon_get_ib_value(p, data0); 589 idx = radeon_get_ib_value(p, data1); 590 if (idx >= relocs_chunk->length_dw) { 591 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n", 592 idx, relocs_chunk->length_dw); 593 return -EINVAL; 594 } 595 596 reloc = &p->relocs[(idx / 4)]; 597 start = reloc->gpu_offset; 598 end = start + radeon_bo_size(reloc->robj); 599 start += offset; 600 601 p->ib.ptr[data0] = start & 0xFFFFFFFF; 602 p->ib.ptr[data1] = start >> 32; 603 604 cmd = radeon_get_ib_value(p, p->idx) >> 1; 605 606 if (cmd < 0x4) { 607 if (end <= start) { 608 DRM_ERROR("invalid reloc offset %X!\n", offset); 609 return -EINVAL; 610 } 611 if ((end - start) < buf_sizes[cmd]) { 612 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd, 613 (unsigned)(end - start), buf_sizes[cmd]); 614 return -EINVAL; 615 } 616 617 } else if (cmd != 0x100) { 618 DRM_ERROR("invalid UVD command %X!\n", cmd); 619 return -EINVAL; 620 } 621 622 if ((start >> 28) != ((end - 1) >> 28)) { 623 DRM_ERROR("reloc %LX-%LX crossing 256MB boundary!\n", 624 start, end); 625 return -EINVAL; 626 } 627 628 /* TODO: is this still necessary on NI+ ? */ 629 if ((cmd == 0 || cmd == 0x3) && 630 (start >> 28) != (p->rdev->uvd.gpu_addr >> 28)) { 631 DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n", 632 start, end); 633 return -EINVAL; 634 } 635 636 if (cmd == 0) { 637 if (*has_msg_cmd) { 638 DRM_ERROR("More than one message in a UVD-IB!\n"); 639 return -EINVAL; 640 } 641 *has_msg_cmd = true; 642 r = radeon_uvd_cs_msg(p, reloc->robj, offset, buf_sizes); 643 if (r) 644 return r; 645 } else if (!*has_msg_cmd) { 646 DRM_ERROR("Message needed before other commands are send!\n"); 647 return -EINVAL; 648 } 649 650 return 0; 651 } 652 653 static int radeon_uvd_cs_reg(struct radeon_cs_parser *p, 654 struct radeon_cs_packet *pkt, 655 int *data0, int *data1, 656 unsigned buf_sizes[], 657 bool *has_msg_cmd) 658 { 659 int i, r; 660 661 p->idx++; 662 for (i = 0; i <= pkt->count; ++i) { 663 switch (pkt->reg + i*4) { 664 case UVD_GPCOM_VCPU_DATA0: 665 *data0 = p->idx; 666 break; 667 case UVD_GPCOM_VCPU_DATA1: 668 *data1 = p->idx; 669 break; 670 case UVD_GPCOM_VCPU_CMD: 671 r = radeon_uvd_cs_reloc(p, *data0, *data1, 672 buf_sizes, has_msg_cmd); 673 if (r) 674 return r; 675 break; 676 case UVD_ENGINE_CNTL: 677 case UVD_NO_OP: 678 break; 679 default: 680 DRM_ERROR("Invalid reg 0x%X!\n", 681 pkt->reg + i*4); 682 return -EINVAL; 683 } 684 p->idx++; 685 } 686 return 0; 687 } 688 689 int radeon_uvd_cs_parse(struct radeon_cs_parser *p) 690 { 691 struct radeon_cs_packet pkt; 692 int r, data0 = 0, data1 = 0; 693 694 /* does the IB has a msg command */ 695 bool has_msg_cmd = false; 696 697 /* minimum buffer sizes */ 698 unsigned buf_sizes[] = { 699 [0x00000000] = 2048, 700 [0x00000001] = 32 * 1024 * 1024, 701 [0x00000002] = 2048 * 1152 * 3, 702 [0x00000003] = 2048, 703 }; 704 705 if (p->chunk_ib->length_dw % 16) { 706 DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n", 707 p->chunk_ib->length_dw); 708 return -EINVAL; 709 } 710 711 if (p->chunk_relocs == NULL) { 712 DRM_ERROR("No relocation chunk !\n"); 713 return -EINVAL; 714 } 715 716 717 do { 718 r = radeon_cs_packet_parse(p, &pkt, p->idx); 719 if (r) 720 return r; 721 switch (pkt.type) { 722 case RADEON_PACKET_TYPE0: 723 r = radeon_uvd_cs_reg(p, &pkt, &data0, &data1, 724 buf_sizes, &has_msg_cmd); 725 if (r) 726 return r; 727 break; 728 case RADEON_PACKET_TYPE2: 729 p->idx += pkt.count + 2; 730 break; 731 default: 732 DRM_ERROR("Unknown packet type %d !\n", pkt.type); 733 return -EINVAL; 734 } 735 } while (p->idx < p->chunk_ib->length_dw); 736 737 if (!has_msg_cmd) { 738 DRM_ERROR("UVD-IBs need a msg command!\n"); 739 return -EINVAL; 740 } 741 742 return 0; 743 } 744 745 static int radeon_uvd_send_msg(struct radeon_device *rdev, 746 int ring, uint64_t addr, 747 struct radeon_fence **fence) 748 { 749 struct radeon_ib ib; 750 int i, r; 751 752 r = radeon_ib_get(rdev, ring, &ib, NULL, 64); 753 if (r) 754 return r; 755 756 ib.ptr[0] = PACKET0(UVD_GPCOM_VCPU_DATA0, 0); 757 ib.ptr[1] = addr; 758 ib.ptr[2] = PACKET0(UVD_GPCOM_VCPU_DATA1, 0); 759 ib.ptr[3] = addr >> 32; 760 ib.ptr[4] = PACKET0(UVD_GPCOM_VCPU_CMD, 0); 761 ib.ptr[5] = 0; 762 for (i = 6; i < 16; i += 2) { 763 ib.ptr[i] = PACKET0(UVD_NO_OP, 0); 764 ib.ptr[i+1] = 0; 765 } 766 ib.length_dw = 16; 767 768 r = radeon_ib_schedule(rdev, &ib, NULL, false); 769 770 if (fence) 771 *fence = radeon_fence_ref(ib.fence); 772 773 radeon_ib_free(rdev, &ib); 774 return r; 775 } 776 777 /* 778 * multiple fence commands without any stream commands in between can 779 * crash the vcpu so just try to emmit a dummy create/destroy msg to 780 * avoid this 781 */ 782 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring, 783 uint32_t handle, struct radeon_fence **fence) 784 { 785 /* we use the last page of the vcpu bo for the UVD message */ 786 uint64_t offs = radeon_bo_size(rdev->uvd.vcpu_bo) - 787 RADEON_GPU_PAGE_SIZE; 788 789 uint32_t *msg = rdev->uvd.cpu_addr + offs; 790 uint64_t addr = rdev->uvd.gpu_addr + offs; 791 792 int r, i; 793 794 r = radeon_bo_reserve(rdev->uvd.vcpu_bo, true); 795 if (r) 796 return r; 797 798 /* stitch together an UVD create msg */ 799 msg[0] = cpu_to_le32(0x00000de4); 800 msg[1] = cpu_to_le32(0x00000000); 801 msg[2] = cpu_to_le32(handle); 802 msg[3] = cpu_to_le32(0x00000000); 803 msg[4] = cpu_to_le32(0x00000000); 804 msg[5] = cpu_to_le32(0x00000000); 805 msg[6] = cpu_to_le32(0x00000000); 806 msg[7] = cpu_to_le32(0x00000780); 807 msg[8] = cpu_to_le32(0x00000440); 808 msg[9] = cpu_to_le32(0x00000000); 809 msg[10] = cpu_to_le32(0x01b37000); 810 for (i = 11; i < 1024; ++i) 811 msg[i] = cpu_to_le32(0x0); 812 813 r = radeon_uvd_send_msg(rdev, ring, addr, fence); 814 radeon_bo_unreserve(rdev->uvd.vcpu_bo); 815 return r; 816 } 817 818 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring, 819 uint32_t handle, struct radeon_fence **fence) 820 { 821 /* we use the last page of the vcpu bo for the UVD message */ 822 uint64_t offs = radeon_bo_size(rdev->uvd.vcpu_bo) - 823 RADEON_GPU_PAGE_SIZE; 824 825 uint32_t *msg = rdev->uvd.cpu_addr + offs; 826 uint64_t addr = rdev->uvd.gpu_addr + offs; 827 828 int r, i; 829 830 r = radeon_bo_reserve(rdev->uvd.vcpu_bo, true); 831 if (r) 832 return r; 833 834 /* stitch together an UVD destroy msg */ 835 msg[0] = cpu_to_le32(0x00000de4); 836 msg[1] = cpu_to_le32(0x00000002); 837 msg[2] = cpu_to_le32(handle); 838 msg[3] = cpu_to_le32(0x00000000); 839 for (i = 4; i < 1024; ++i) 840 msg[i] = cpu_to_le32(0x0); 841 842 r = radeon_uvd_send_msg(rdev, ring, addr, fence); 843 radeon_bo_unreserve(rdev->uvd.vcpu_bo); 844 return r; 845 } 846 847 /** 848 * radeon_uvd_count_handles - count number of open streams 849 * 850 * @rdev: radeon_device pointer 851 * @sd: number of SD streams 852 * @hd: number of HD streams 853 * 854 * Count the number of open SD/HD streams as a hint for power mangement 855 */ 856 static void radeon_uvd_count_handles(struct radeon_device *rdev, 857 unsigned *sd, unsigned *hd) 858 { 859 unsigned i; 860 861 *sd = 0; 862 *hd = 0; 863 864 for (i = 0; i < rdev->uvd.max_handles; ++i) { 865 if (!atomic_read(&rdev->uvd.handles[i])) 866 continue; 867 868 if (rdev->uvd.img_size[i] >= 720*576) 869 ++(*hd); 870 else 871 ++(*sd); 872 } 873 } 874 875 static void radeon_uvd_idle_work_handler(struct work_struct *work) 876 { 877 struct radeon_device *rdev = 878 container_of(work, struct radeon_device, uvd.idle_work.work); 879 880 if (radeon_fence_count_emitted(rdev, R600_RING_TYPE_UVD_INDEX) == 0) { 881 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { 882 radeon_uvd_count_handles(rdev, &rdev->pm.dpm.sd, 883 &rdev->pm.dpm.hd); 884 radeon_dpm_enable_uvd(rdev, false); 885 } else { 886 radeon_set_uvd_clocks(rdev, 0, 0); 887 } 888 } else { 889 schedule_delayed_work(&rdev->uvd.idle_work, 890 msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS)); 891 } 892 } 893 894 void radeon_uvd_note_usage(struct radeon_device *rdev) 895 { 896 bool streams_changed = false; 897 bool set_clocks = !cancel_delayed_work_sync(&rdev->uvd.idle_work); 898 set_clocks &= schedule_delayed_work(&rdev->uvd.idle_work, 899 msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS)); 900 901 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { 902 unsigned hd = 0, sd = 0; 903 radeon_uvd_count_handles(rdev, &sd, &hd); 904 if ((rdev->pm.dpm.sd != sd) || 905 (rdev->pm.dpm.hd != hd)) { 906 rdev->pm.dpm.sd = sd; 907 rdev->pm.dpm.hd = hd; 908 /* disable this for now */ 909 /*streams_changed = true;*/ 910 } 911 } 912 913 if (set_clocks || streams_changed) { 914 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { 915 radeon_dpm_enable_uvd(rdev, true); 916 } else { 917 radeon_set_uvd_clocks(rdev, 53300, 40000); 918 } 919 } 920 } 921 922 static unsigned radeon_uvd_calc_upll_post_div(unsigned vco_freq, 923 unsigned target_freq, 924 unsigned pd_min, 925 unsigned pd_even) 926 { 927 unsigned post_div = vco_freq / target_freq; 928 929 /* adjust to post divider minimum value */ 930 if (post_div < pd_min) 931 post_div = pd_min; 932 933 /* we alway need a frequency less than or equal the target */ 934 if ((vco_freq / post_div) > target_freq) 935 post_div += 1; 936 937 /* post dividers above a certain value must be even */ 938 if (post_div > pd_even && post_div % 2) 939 post_div += 1; 940 941 return post_div; 942 } 943 944 /** 945 * radeon_uvd_calc_upll_dividers - calc UPLL clock dividers 946 * 947 * @rdev: radeon_device pointer 948 * @vclk: wanted VCLK 949 * @dclk: wanted DCLK 950 * @vco_min: minimum VCO frequency 951 * @vco_max: maximum VCO frequency 952 * @fb_factor: factor to multiply vco freq with 953 * @fb_mask: limit and bitmask for feedback divider 954 * @pd_min: post divider minimum 955 * @pd_max: post divider maximum 956 * @pd_even: post divider must be even above this value 957 * @optimal_fb_div: resulting feedback divider 958 * @optimal_vclk_div: resulting vclk post divider 959 * @optimal_dclk_div: resulting dclk post divider 960 * 961 * Calculate dividers for UVDs UPLL (R6xx-SI, except APUs). 962 * Returns zero on success -EINVAL on error. 963 */ 964 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev, 965 unsigned vclk, unsigned dclk, 966 unsigned vco_min, unsigned vco_max, 967 unsigned fb_factor, unsigned fb_mask, 968 unsigned pd_min, unsigned pd_max, 969 unsigned pd_even, 970 unsigned *optimal_fb_div, 971 unsigned *optimal_vclk_div, 972 unsigned *optimal_dclk_div) 973 { 974 unsigned vco_freq, ref_freq = rdev->clock.spll.reference_freq; 975 976 /* start off with something large */ 977 unsigned optimal_score = ~0; 978 979 /* loop through vco from low to high */ 980 vco_min = max(max(vco_min, vclk), dclk); 981 for (vco_freq = vco_min; vco_freq <= vco_max; vco_freq += 100) { 982 983 uint64_t fb_div = (uint64_t)vco_freq * fb_factor; 984 unsigned vclk_div, dclk_div, score; 985 986 do_div(fb_div, ref_freq); 987 988 /* fb div out of range ? */ 989 if (fb_div > fb_mask) 990 break; /* it can oly get worse */ 991 992 fb_div &= fb_mask; 993 994 /* calc vclk divider with current vco freq */ 995 vclk_div = radeon_uvd_calc_upll_post_div(vco_freq, vclk, 996 pd_min, pd_even); 997 if (vclk_div > pd_max) 998 break; /* vco is too big, it has to stop */ 999 1000 /* calc dclk divider with current vco freq */ 1001 dclk_div = radeon_uvd_calc_upll_post_div(vco_freq, dclk, 1002 pd_min, pd_even); 1003 if (dclk_div > pd_max) 1004 break; /* vco is too big, it has to stop */ 1005 1006 /* calc score with current vco freq */ 1007 score = vclk - (vco_freq / vclk_div) + dclk - (vco_freq / dclk_div); 1008 1009 /* determine if this vco setting is better than current optimal settings */ 1010 if (score < optimal_score) { 1011 *optimal_fb_div = fb_div; 1012 *optimal_vclk_div = vclk_div; 1013 *optimal_dclk_div = dclk_div; 1014 optimal_score = score; 1015 if (optimal_score == 0) 1016 break; /* it can't get better than this */ 1017 } 1018 } 1019 1020 /* did we found a valid setup ? */ 1021 if (optimal_score == ~0) 1022 return -EINVAL; 1023 1024 return 0; 1025 } 1026 1027 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev, 1028 unsigned cg_upll_func_cntl) 1029 { 1030 unsigned i; 1031 1032 /* make sure UPLL_CTLREQ is deasserted */ 1033 WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK); 1034 1035 mdelay(10); 1036 1037 /* assert UPLL_CTLREQ */ 1038 WREG32_P(cg_upll_func_cntl, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK); 1039 1040 /* wait for CTLACK and CTLACK2 to get asserted */ 1041 for (i = 0; i < 100; ++i) { 1042 uint32_t mask = UPLL_CTLACK_MASK | UPLL_CTLACK2_MASK; 1043 if ((RREG32(cg_upll_func_cntl) & mask) == mask) 1044 break; 1045 mdelay(10); 1046 } 1047 1048 /* deassert UPLL_CTLREQ */ 1049 WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK); 1050 1051 if (i == 100) { 1052 DRM_ERROR("Timeout setting UVD clocks!\n"); 1053 return -ETIMEDOUT; 1054 } 1055 1056 return 0; 1057 } 1058
Indexes created Mon Oct 27 08:10:08 GMT 2025