radeon_uvd.c revision 1.2.32.2
1 /* $NetBSD: radeon_uvd.c,v 1.2.32.2 2020/04/08 14:08:26 martin Exp $ */ 2 3 /* 4 * Copyright 2011 Advanced Micro Devices, Inc. 5 * All Rights Reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the 9 * "Software"), to deal in the Software without restriction, including 10 * without limitation the rights to use, copy, modify, merge, publish, 11 * distribute, sub license, and/or sell copies of the Software, and to 12 * permit persons to whom the Software is furnished to do so, subject to 13 * the following conditions: 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * The above copyright notice and this permission notice (including the 24 * next paragraph) shall be included in all copies or substantial portions 25 * of the Software. 26 * 27 */ 28 /* 29 * Authors: 30 * Christian Knig <deathsimple (at) vodafone.de> 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: radeon_uvd.c,v 1.2.32.2 2020/04/08 14:08:26 martin Exp $"); 35 36 #include <linux/firmware.h> 37 #include <linux/module.h> 38 #include <drm/drmP.h> 39 #include <drm/drm.h> 40 41 #include "radeon.h" 42 #include "r600d.h" 43 44 #include <linux/nbsd-namespace.h> 45 46 /* 1 second timeout */ 47 #define UVD_IDLE_TIMEOUT_MS 1000 48 49 /* Firmware Names */ 50 #define FIRMWARE_R600 "radeon/R600_uvd.bin" 51 #define FIRMWARE_RS780 "radeon/RS780_uvd.bin" 52 #define FIRMWARE_RV770 "radeon/RV770_uvd.bin" 53 #define FIRMWARE_RV710 "radeon/RV710_uvd.bin" 54 #define FIRMWARE_CYPRESS "radeon/CYPRESS_uvd.bin" 55 #define FIRMWARE_SUMO "radeon/SUMO_uvd.bin" 56 #define FIRMWARE_TAHITI "radeon/TAHITI_uvd.bin" 57 #define FIRMWARE_BONAIRE "radeon/BONAIRE_uvd.bin" 58 59 MODULE_FIRMWARE(FIRMWARE_R600); 60 MODULE_FIRMWARE(FIRMWARE_RS780); 61 MODULE_FIRMWARE(FIRMWARE_RV770); 62 MODULE_FIRMWARE(FIRMWARE_RV710); 63 MODULE_FIRMWARE(FIRMWARE_CYPRESS); 64 MODULE_FIRMWARE(FIRMWARE_SUMO); 65 MODULE_FIRMWARE(FIRMWARE_TAHITI); 66 MODULE_FIRMWARE(FIRMWARE_BONAIRE); 67 68 static void radeon_uvd_idle_work_handler(struct work_struct *work); 69 70 int radeon_uvd_init(struct radeon_device *rdev) 71 { 72 unsigned long bo_size; 73 const char *fw_name; 74 int i, r; 75 76 INIT_DELAYED_WORK(&rdev->uvd.idle_work, radeon_uvd_idle_work_handler); 77 78 switch (rdev->family) { 79 case CHIP_RV610: 80 case CHIP_RV630: 81 case CHIP_RV670: 82 case CHIP_RV620: 83 case CHIP_RV635: 84 fw_name = FIRMWARE_R600; 85 break; 86 87 case CHIP_RS780: 88 case CHIP_RS880: 89 fw_name = FIRMWARE_RS780; 90 break; 91 92 case CHIP_RV770: 93 fw_name = FIRMWARE_RV770; 94 break; 95 96 case CHIP_RV710: 97 case CHIP_RV730: 98 case CHIP_RV740: 99 fw_name = FIRMWARE_RV710; 100 break; 101 102 case CHIP_CYPRESS: 103 case CHIP_HEMLOCK: 104 case CHIP_JUNIPER: 105 case CHIP_REDWOOD: 106 case CHIP_CEDAR: 107 fw_name = FIRMWARE_CYPRESS; 108 break; 109 110 case CHIP_SUMO: 111 case CHIP_SUMO2: 112 case CHIP_PALM: 113 case CHIP_CAYMAN: 114 case CHIP_BARTS: 115 case CHIP_TURKS: 116 case CHIP_CAICOS: 117 fw_name = FIRMWARE_SUMO; 118 break; 119 120 case CHIP_TAHITI: 121 case CHIP_VERDE: 122 case CHIP_PITCAIRN: 123 case CHIP_ARUBA: 124 case CHIP_OLAND: 125 fw_name = FIRMWARE_TAHITI; 126 break; 127 128 case CHIP_BONAIRE: 129 case CHIP_KABINI: 130 case CHIP_KAVERI: 131 case CHIP_HAWAII: 132 case CHIP_MULLINS: 133 fw_name = FIRMWARE_BONAIRE; 134 break; 135 136 default: 137 return -EINVAL; 138 } 139 140 r = request_firmware(&rdev->uvd_fw, fw_name, rdev->dev); 141 if (r) { 142 dev_err(rdev->dev, "radeon_uvd: Can't load firmware \"%s\"\n", 143 fw_name); 144 return r; 145 } 146 147 bo_size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->size + 8) + 148 RADEON_UVD_STACK_SIZE + RADEON_UVD_HEAP_SIZE + 149 RADEON_GPU_PAGE_SIZE; 150 r = radeon_bo_create(rdev, bo_size, PAGE_SIZE, true, 151 RADEON_GEM_DOMAIN_VRAM, 0, NULL, 152 NULL, &rdev->uvd.vcpu_bo); 153 if (r) { 154 dev_err(rdev->dev, "(%d) failed to allocate UVD bo\n", r); 155 return r; 156 } 157 158 r = radeon_bo_reserve(rdev->uvd.vcpu_bo, false); 159 if (r) { 160 radeon_bo_unref(&rdev->uvd.vcpu_bo); 161 dev_err(rdev->dev, "(%d) failed to reserve UVD bo\n", r); 162 return r; 163 } 164 165 r = radeon_bo_pin(rdev->uvd.vcpu_bo, RADEON_GEM_DOMAIN_VRAM, 166 &rdev->uvd.gpu_addr); 167 if (r) { 168 radeon_bo_unreserve(rdev->uvd.vcpu_bo); 169 radeon_bo_unref(&rdev->uvd.vcpu_bo); 170 dev_err(rdev->dev, "(%d) UVD bo pin failed\n", r); 171 return r; 172 } 173 174 r = radeon_bo_kmap(rdev->uvd.vcpu_bo, &rdev->uvd.cpu_addr); 175 if (r) { 176 dev_err(rdev->dev, "(%d) UVD map failed\n", r); 177 return r; 178 } 179 180 radeon_bo_unreserve(rdev->uvd.vcpu_bo); 181 182 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) { 183 atomic_set(&rdev->uvd.handles[i], 0); 184 rdev->uvd.filp[i] = NULL; 185 rdev->uvd.img_size[i] = 0; 186 } 187 188 return 0; 189 } 190 191 void radeon_uvd_fini(struct radeon_device *rdev) 192 { 193 int r; 194 195 if (rdev->uvd.vcpu_bo == NULL) 196 return; 197 198 r = radeon_bo_reserve(rdev->uvd.vcpu_bo, false); 199 if (!r) { 200 radeon_bo_kunmap(rdev->uvd.vcpu_bo); 201 radeon_bo_unpin(rdev->uvd.vcpu_bo); 202 radeon_bo_unreserve(rdev->uvd.vcpu_bo); 203 } 204 205 radeon_bo_unref(&rdev->uvd.vcpu_bo); 206 207 radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX]); 208 209 release_firmware(rdev->uvd_fw); 210 } 211 212 int radeon_uvd_suspend(struct radeon_device *rdev) 213 { 214 int i, r; 215 216 if (rdev->uvd.vcpu_bo == NULL) 217 return 0; 218 219 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) { 220 uint32_t handle = atomic_read(&rdev->uvd.handles[i]); 221 if (handle != 0) { 222 struct radeon_fence *fence; 223 224 radeon_uvd_note_usage(rdev); 225 226 r = radeon_uvd_get_destroy_msg(rdev, 227 R600_RING_TYPE_UVD_INDEX, handle, &fence); 228 if (r) { 229 DRM_ERROR("Error destroying UVD (%d)!\n", r); 230 continue; 231 } 232 233 radeon_fence_wait(fence, false); 234 radeon_fence_unref(&fence); 235 236 rdev->uvd.filp[i] = NULL; 237 atomic_set(&rdev->uvd.handles[i], 0); 238 } 239 } 240 241 return 0; 242 } 243 244 int radeon_uvd_resume(struct radeon_device *rdev) 245 { 246 unsigned size; 247 void *ptr; 248 249 if (rdev->uvd.vcpu_bo == NULL) 250 return -EINVAL; 251 252 memcpy(rdev->uvd.cpu_addr, rdev->uvd_fw->data, rdev->uvd_fw->size); 253 254 size = radeon_bo_size(rdev->uvd.vcpu_bo); 255 size -= rdev->uvd_fw->size; 256 257 ptr = rdev->uvd.cpu_addr; 258 ptr += rdev->uvd_fw->size; 259 260 memset(ptr, 0, size); 261 262 return 0; 263 } 264 265 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo, 266 uint32_t allowed_domains) 267 { 268 int i; 269 270 for (i = 0; i < rbo->placement.num_placement; ++i) { 271 rbo->placements[i].fpfn = 0 >> PAGE_SHIFT; 272 rbo->placements[i].lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT; 273 } 274 275 /* If it must be in VRAM it must be in the first segment as well */ 276 if (allowed_domains == RADEON_GEM_DOMAIN_VRAM) 277 return; 278 279 /* abort if we already have more than one placement */ 280 if (rbo->placement.num_placement > 1) 281 return; 282 283 /* add another 256MB segment */ 284 rbo->placements[1] = rbo->placements[0]; 285 rbo->placements[1].fpfn += (256 * 1024 * 1024) >> PAGE_SHIFT; 286 rbo->placements[1].lpfn += (256 * 1024 * 1024) >> PAGE_SHIFT; 287 rbo->placement.num_placement++; 288 rbo->placement.num_busy_placement++; 289 } 290 291 void radeon_uvd_free_handles(struct radeon_device *rdev, struct drm_file *filp) 292 { 293 int i, r; 294 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) { 295 uint32_t handle = atomic_read(&rdev->uvd.handles[i]); 296 if (handle != 0 && rdev->uvd.filp[i] == filp) { 297 struct radeon_fence *fence; 298 299 radeon_uvd_note_usage(rdev); 300 301 r = radeon_uvd_get_destroy_msg(rdev, 302 R600_RING_TYPE_UVD_INDEX, handle, &fence); 303 if (r) { 304 DRM_ERROR("Error destroying UVD (%d)!\n", r); 305 continue; 306 } 307 308 radeon_fence_wait(fence, false); 309 radeon_fence_unref(&fence); 310 311 rdev->uvd.filp[i] = NULL; 312 atomic_set(&rdev->uvd.handles[i], 0); 313 } 314 } 315 } 316 317 static int radeon_uvd_cs_msg_decode(uint32_t *msg, unsigned buf_sizes[]) 318 { 319 unsigned stream_type = msg[4]; 320 unsigned width = msg[6]; 321 unsigned height = msg[7]; 322 unsigned dpb_size = msg[9]; 323 unsigned pitch = msg[28]; 324 325 unsigned width_in_mb = width / 16; 326 unsigned height_in_mb = ALIGN(height / 16, 2); 327 328 unsigned image_size, tmp, min_dpb_size; 329 330 image_size = width * height; 331 image_size += image_size / 2; 332 image_size = ALIGN(image_size, 1024); 333 334 switch (stream_type) { 335 case 0: /* H264 */ 336 337 /* reference picture buffer */ 338 min_dpb_size = image_size * 17; 339 340 /* macroblock context buffer */ 341 min_dpb_size += width_in_mb * height_in_mb * 17 * 192; 342 343 /* IT surface buffer */ 344 min_dpb_size += width_in_mb * height_in_mb * 32; 345 break; 346 347 case 1: /* VC1 */ 348 349 /* reference picture buffer */ 350 min_dpb_size = image_size * 3; 351 352 /* CONTEXT_BUFFER */ 353 min_dpb_size += width_in_mb * height_in_mb * 128; 354 355 /* IT surface buffer */ 356 min_dpb_size += width_in_mb * 64; 357 358 /* DB surface buffer */ 359 min_dpb_size += width_in_mb * 128; 360 361 /* BP */ 362 tmp = max(width_in_mb, height_in_mb); 363 min_dpb_size += ALIGN(tmp * 7 * 16, 64); 364 break; 365 366 case 3: /* MPEG2 */ 367 368 /* reference picture buffer */ 369 min_dpb_size = image_size * 3; 370 break; 371 372 case 4: /* MPEG4 */ 373 374 /* reference picture buffer */ 375 min_dpb_size = image_size * 3; 376 377 /* CM */ 378 min_dpb_size += width_in_mb * height_in_mb * 64; 379 380 /* IT surface buffer */ 381 min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64); 382 break; 383 384 default: 385 DRM_ERROR("UVD codec not handled %d!\n", stream_type); 386 return -EINVAL; 387 } 388 389 if (width > pitch) { 390 DRM_ERROR("Invalid UVD decoding target pitch!\n"); 391 return -EINVAL; 392 } 393 394 if (dpb_size < min_dpb_size) { 395 DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n", 396 dpb_size, min_dpb_size); 397 return -EINVAL; 398 } 399 400 buf_sizes[0x1] = dpb_size; 401 buf_sizes[0x2] = image_size; 402 return 0; 403 } 404 405 static int radeon_uvd_validate_codec(struct radeon_cs_parser *p, 406 unsigned stream_type) 407 { 408 switch (stream_type) { 409 case 0: /* H264 */ 410 case 1: /* VC1 */ 411 /* always supported */ 412 return 0; 413 414 case 3: /* MPEG2 */ 415 case 4: /* MPEG4 */ 416 /* only since UVD 3 */ 417 if (p->rdev->family >= CHIP_PALM) 418 return 0; 419 420 /* fall through */ 421 default: 422 DRM_ERROR("UVD codec not supported by hardware %d!\n", 423 stream_type); 424 return -EINVAL; 425 } 426 } 427 428 static int radeon_uvd_cs_msg(struct radeon_cs_parser *p, struct radeon_bo *bo, 429 unsigned offset, unsigned buf_sizes[]) 430 { 431 int32_t *msg, msg_type, handle; 432 unsigned img_size = 0; 433 struct fence *f; 434 void *ptr; 435 436 int i, r; 437 438 if (offset & 0x3F) { 439 DRM_ERROR("UVD messages must be 64 byte aligned!\n"); 440 return -EINVAL; 441 } 442 443 f = reservation_object_get_excl(bo->tbo.resv); 444 if (f) { 445 r = radeon_fence_wait((struct radeon_fence *)f, false); 446 if (r) { 447 DRM_ERROR("Failed waiting for UVD message (%d)!\n", r); 448 return r; 449 } 450 } 451 452 r = radeon_bo_kmap(bo, &ptr); 453 if (r) { 454 DRM_ERROR("Failed mapping the UVD message (%d)!\n", r); 455 return r; 456 } 457 458 msg = ptr + offset; 459 460 msg_type = msg[1]; 461 handle = msg[2]; 462 463 if (handle == 0) { 464 DRM_ERROR("Invalid UVD handle!\n"); 465 return -EINVAL; 466 } 467 468 switch (msg_type) { 469 case 0: 470 /* it's a create msg, calc image size (width * height) */ 471 img_size = msg[7] * msg[8]; 472 473 r = radeon_uvd_validate_codec(p, msg[4]); 474 radeon_bo_kunmap(bo); 475 if (r) 476 return r; 477 478 /* try to alloc a new handle */ 479 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) { 480 if (atomic_read(&p->rdev->uvd.handles[i]) == handle) { 481 DRM_ERROR("Handle 0x%x already in use!\n", handle); 482 return -EINVAL; 483 } 484 485 if (!atomic_cmpxchg(&p->rdev->uvd.handles[i], 0, handle)) { 486 p->rdev->uvd.filp[i] = p->filp; 487 p->rdev->uvd.img_size[i] = img_size; 488 return 0; 489 } 490 } 491 492 DRM_ERROR("No more free UVD handles!\n"); 493 return -EINVAL; 494 495 case 1: 496 /* it's a decode msg, validate codec and calc buffer sizes */ 497 r = radeon_uvd_validate_codec(p, msg[4]); 498 if (!r) 499 r = radeon_uvd_cs_msg_decode(msg, buf_sizes); 500 radeon_bo_kunmap(bo); 501 if (r) 502 return r; 503 504 /* validate the handle */ 505 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) { 506 if (atomic_read(&p->rdev->uvd.handles[i]) == handle) { 507 if (p->rdev->uvd.filp[i] != p->filp) { 508 DRM_ERROR("UVD handle collision detected!\n"); 509 return -EINVAL; 510 } 511 return 0; 512 } 513 } 514 515 DRM_ERROR("Invalid UVD handle 0x%x!\n", handle); 516 return -ENOENT; 517 518 case 2: 519 /* it's a destroy msg, free the handle */ 520 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) 521 atomic_cmpxchg(&p->rdev->uvd.handles[i], handle, 0); 522 radeon_bo_kunmap(bo); 523 return 0; 524 525 default: 526 527 DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type); 528 return -EINVAL; 529 } 530 531 BUG(); 532 return -EINVAL; 533 } 534 535 static int radeon_uvd_cs_reloc(struct radeon_cs_parser *p, 536 int data0, int data1, 537 unsigned buf_sizes[], bool *has_msg_cmd) 538 { 539 struct radeon_cs_chunk *relocs_chunk; 540 struct radeon_bo_list *reloc; 541 unsigned idx, cmd, offset; 542 uint64_t start, end; 543 int r; 544 545 relocs_chunk = p->chunk_relocs; 546 offset = radeon_get_ib_value(p, data0); 547 idx = radeon_get_ib_value(p, data1); 548 if (idx >= relocs_chunk->length_dw) { 549 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n", 550 idx, relocs_chunk->length_dw); 551 return -EINVAL; 552 } 553 554 reloc = &p->relocs[(idx / 4)]; 555 start = reloc->gpu_offset; 556 end = start + radeon_bo_size(reloc->robj); 557 start += offset; 558 559 p->ib.ptr[data0] = start & 0xFFFFFFFF; 560 p->ib.ptr[data1] = start >> 32; 561 562 cmd = radeon_get_ib_value(p, p->idx) >> 1; 563 564 if (cmd < 0x4) { 565 if (end <= start) { 566 DRM_ERROR("invalid reloc offset %X!\n", offset); 567 return -EINVAL; 568 } 569 if ((end - start) < buf_sizes[cmd]) { 570 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd, 571 (unsigned)(end - start), buf_sizes[cmd]); 572 return -EINVAL; 573 } 574 575 } else if (cmd != 0x100) { 576 DRM_ERROR("invalid UVD command %X!\n", cmd); 577 return -EINVAL; 578 } 579 580 if ((start >> 28) != ((end - 1) >> 28)) { 581 DRM_ERROR("reloc %"PRIX64"-%"PRIX64" crossing 256MB boundary!\n", 582 start, end); 583 return -EINVAL; 584 } 585 586 /* TODO: is this still necessary on NI+ ? */ 587 if ((cmd == 0 || cmd == 0x3) && 588 (start >> 28) != (p->rdev->uvd.gpu_addr >> 28)) { 589 DRM_ERROR("msg/fb buffer %"PRIX64"-%"PRIX64" out of 256MB segment!\n", 590 start, end); 591 return -EINVAL; 592 } 593 594 if (cmd == 0) { 595 if (*has_msg_cmd) { 596 DRM_ERROR("More than one message in a UVD-IB!\n"); 597 return -EINVAL; 598 } 599 *has_msg_cmd = true; 600 r = radeon_uvd_cs_msg(p, reloc->robj, offset, buf_sizes); 601 if (r) 602 return r; 603 } else if (!*has_msg_cmd) { 604 DRM_ERROR("Message needed before other commands are send!\n"); 605 return -EINVAL; 606 } 607 608 return 0; 609 } 610 611 static int radeon_uvd_cs_reg(struct radeon_cs_parser *p, 612 struct radeon_cs_packet *pkt, 613 int *data0, int *data1, 614 unsigned buf_sizes[], 615 bool *has_msg_cmd) 616 { 617 int i, r; 618 619 p->idx++; 620 for (i = 0; i <= pkt->count; ++i) { 621 switch (pkt->reg + i*4) { 622 case UVD_GPCOM_VCPU_DATA0: 623 *data0 = p->idx; 624 break; 625 case UVD_GPCOM_VCPU_DATA1: 626 *data1 = p->idx; 627 break; 628 case UVD_GPCOM_VCPU_CMD: 629 r = radeon_uvd_cs_reloc(p, *data0, *data1, 630 buf_sizes, has_msg_cmd); 631 if (r) 632 return r; 633 break; 634 case UVD_ENGINE_CNTL: 635 break; 636 default: 637 DRM_ERROR("Invalid reg 0x%X!\n", 638 pkt->reg + i*4); 639 return -EINVAL; 640 } 641 p->idx++; 642 } 643 return 0; 644 } 645 646 int radeon_uvd_cs_parse(struct radeon_cs_parser *p) 647 { 648 struct radeon_cs_packet pkt; 649 int r, data0 = 0, data1 = 0; 650 651 /* does the IB has a msg command */ 652 bool has_msg_cmd = false; 653 654 /* minimum buffer sizes */ 655 unsigned buf_sizes[] = { 656 [0x00000000] = 2048, 657 [0x00000001] = 32 * 1024 * 1024, 658 [0x00000002] = 2048 * 1152 * 3, 659 [0x00000003] = 2048, 660 }; 661 662 if (p->chunk_ib->length_dw % 16) { 663 DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n", 664 p->chunk_ib->length_dw); 665 return -EINVAL; 666 } 667 668 if (p->chunk_relocs == NULL) { 669 DRM_ERROR("No relocation chunk !\n"); 670 return -EINVAL; 671 } 672 673 674 do { 675 r = radeon_cs_packet_parse(p, &pkt, p->idx); 676 if (r) 677 return r; 678 switch (pkt.type) { 679 case RADEON_PACKET_TYPE0: 680 r = radeon_uvd_cs_reg(p, &pkt, &data0, &data1, 681 buf_sizes, &has_msg_cmd); 682 if (r) 683 return r; 684 break; 685 case RADEON_PACKET_TYPE2: 686 p->idx += pkt.count + 2; 687 break; 688 default: 689 DRM_ERROR("Unknown packet type %d !\n", pkt.type); 690 return -EINVAL; 691 } 692 } while (p->idx < p->chunk_ib->length_dw); 693 694 if (!has_msg_cmd) { 695 DRM_ERROR("UVD-IBs need a msg command!\n"); 696 return -EINVAL; 697 } 698 699 return 0; 700 } 701 702 static int radeon_uvd_send_msg(struct radeon_device *rdev, 703 int ring, uint64_t addr, 704 struct radeon_fence **fence) 705 { 706 struct radeon_ib ib; 707 int i, r; 708 709 r = radeon_ib_get(rdev, ring, &ib, NULL, 64); 710 if (r) 711 return r; 712 713 ib.ptr[0] = PACKET0(UVD_GPCOM_VCPU_DATA0, 0); 714 ib.ptr[1] = addr; 715 ib.ptr[2] = PACKET0(UVD_GPCOM_VCPU_DATA1, 0); 716 ib.ptr[3] = addr >> 32; 717 ib.ptr[4] = PACKET0(UVD_GPCOM_VCPU_CMD, 0); 718 ib.ptr[5] = 0; 719 for (i = 6; i < 16; ++i) 720 ib.ptr[i] = PACKET2(0); 721 ib.length_dw = 16; 722 723 r = radeon_ib_schedule(rdev, &ib, NULL, false); 724 725 if (fence) 726 *fence = radeon_fence_ref(ib.fence); 727 728 radeon_ib_free(rdev, &ib); 729 return r; 730 } 731 732 /* multiple fence commands without any stream commands in between can 733 crash the vcpu so just try to emmit a dummy create/destroy msg to 734 avoid this */ 735 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring, 736 uint32_t handle, struct radeon_fence **fence) 737 { 738 /* we use the last page of the vcpu bo for the UVD message */ 739 uint64_t offs = radeon_bo_size(rdev->uvd.vcpu_bo) - 740 RADEON_GPU_PAGE_SIZE; 741 742 uint32_t *msg = rdev->uvd.cpu_addr + offs; 743 uint64_t addr = rdev->uvd.gpu_addr + offs; 744 745 int r, i; 746 747 r = radeon_bo_reserve(rdev->uvd.vcpu_bo, true); 748 if (r) 749 return r; 750 751 /* stitch together an UVD create msg */ 752 msg[0] = cpu_to_le32(0x00000de4); 753 msg[1] = cpu_to_le32(0x00000000); 754 msg[2] = cpu_to_le32(handle); 755 msg[3] = cpu_to_le32(0x00000000); 756 msg[4] = cpu_to_le32(0x00000000); 757 msg[5] = cpu_to_le32(0x00000000); 758 msg[6] = cpu_to_le32(0x00000000); 759 msg[7] = cpu_to_le32(0x00000780); 760 msg[8] = cpu_to_le32(0x00000440); 761 msg[9] = cpu_to_le32(0x00000000); 762 msg[10] = cpu_to_le32(0x01b37000); 763 for (i = 11; i < 1024; ++i) 764 msg[i] = cpu_to_le32(0x0); 765 766 r = radeon_uvd_send_msg(rdev, ring, addr, fence); 767 radeon_bo_unreserve(rdev->uvd.vcpu_bo); 768 return r; 769 } 770 771 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring, 772 uint32_t handle, struct radeon_fence **fence) 773 { 774 /* we use the last page of the vcpu bo for the UVD message */ 775 uint64_t offs = radeon_bo_size(rdev->uvd.vcpu_bo) - 776 RADEON_GPU_PAGE_SIZE; 777 778 uint32_t *msg = rdev->uvd.cpu_addr + offs; 779 uint64_t addr = rdev->uvd.gpu_addr + offs; 780 781 int r, i; 782 783 r = radeon_bo_reserve(rdev->uvd.vcpu_bo, true); 784 if (r) 785 return r; 786 787 /* stitch together an UVD destroy msg */ 788 msg[0] = cpu_to_le32(0x00000de4); 789 msg[1] = cpu_to_le32(0x00000002); 790 msg[2] = cpu_to_le32(handle); 791 msg[3] = cpu_to_le32(0x00000000); 792 for (i = 4; i < 1024; ++i) 793 msg[i] = cpu_to_le32(0x0); 794 795 r = radeon_uvd_send_msg(rdev, ring, addr, fence); 796 radeon_bo_unreserve(rdev->uvd.vcpu_bo); 797 return r; 798 } 799 800 /** 801 * radeon_uvd_count_handles - count number of open streams 802 * 803 * @rdev: radeon_device pointer 804 * @sd: number of SD streams 805 * @hd: number of HD streams 806 * 807 * Count the number of open SD/HD streams as a hint for power mangement 808 */ 809 static void radeon_uvd_count_handles(struct radeon_device *rdev, 810 unsigned *sd, unsigned *hd) 811 { 812 unsigned i; 813 814 *sd = 0; 815 *hd = 0; 816 817 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) { 818 if (!atomic_read(&rdev->uvd.handles[i])) 819 continue; 820 821 if (rdev->uvd.img_size[i] >= 720*576) 822 ++(*hd); 823 else 824 ++(*sd); 825 } 826 } 827 828 static void radeon_uvd_idle_work_handler(struct work_struct *work) 829 { 830 struct radeon_device *rdev = 831 container_of(work, struct radeon_device, uvd.idle_work.work); 832 833 if (radeon_fence_count_emitted(rdev, R600_RING_TYPE_UVD_INDEX) == 0) { 834 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { 835 radeon_uvd_count_handles(rdev, &rdev->pm.dpm.sd, 836 &rdev->pm.dpm.hd); 837 radeon_dpm_enable_uvd(rdev, false); 838 } else { 839 radeon_set_uvd_clocks(rdev, 0, 0); 840 } 841 } else { 842 schedule_delayed_work(&rdev->uvd.idle_work, 843 msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS)); 844 } 845 } 846 847 void radeon_uvd_note_usage(struct radeon_device *rdev) 848 { 849 bool streams_changed = false; 850 bool set_clocks = !cancel_delayed_work_sync(&rdev->uvd.idle_work); 851 set_clocks &= schedule_delayed_work(&rdev->uvd.idle_work, 852 msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS)); 853 854 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { 855 unsigned hd = 0, sd = 0; 856 radeon_uvd_count_handles(rdev, &sd, &hd); 857 if ((rdev->pm.dpm.sd != sd) || 858 (rdev->pm.dpm.hd != hd)) { 859 rdev->pm.dpm.sd = sd; 860 rdev->pm.dpm.hd = hd; 861 /* disable this for now */ 862 /*streams_changed = true;*/ 863 } 864 } 865 866 if (set_clocks || streams_changed) { 867 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { 868 radeon_dpm_enable_uvd(rdev, true); 869 } else { 870 radeon_set_uvd_clocks(rdev, 53300, 40000); 871 } 872 } 873 } 874 875 static unsigned radeon_uvd_calc_upll_post_div(unsigned vco_freq, 876 unsigned target_freq, 877 unsigned pd_min, 878 unsigned pd_even) 879 { 880 unsigned post_div = vco_freq / target_freq; 881 882 /* adjust to post divider minimum value */ 883 if (post_div < pd_min) 884 post_div = pd_min; 885 886 /* we alway need a frequency less than or equal the target */ 887 if ((vco_freq / post_div) > target_freq) 888 post_div += 1; 889 890 /* post dividers above a certain value must be even */ 891 if (post_div > pd_even && post_div % 2) 892 post_div += 1; 893 894 return post_div; 895 } 896 897 /** 898 * radeon_uvd_calc_upll_dividers - calc UPLL clock dividers 899 * 900 * @rdev: radeon_device pointer 901 * @vclk: wanted VCLK 902 * @dclk: wanted DCLK 903 * @vco_min: minimum VCO frequency 904 * @vco_max: maximum VCO frequency 905 * @fb_factor: factor to multiply vco freq with 906 * @fb_mask: limit and bitmask for feedback divider 907 * @pd_min: post divider minimum 908 * @pd_max: post divider maximum 909 * @pd_even: post divider must be even above this value 910 * @optimal_fb_div: resulting feedback divider 911 * @optimal_vclk_div: resulting vclk post divider 912 * @optimal_dclk_div: resulting dclk post divider 913 * 914 * Calculate dividers for UVDs UPLL (R6xx-SI, except APUs). 915 * Returns zero on success -EINVAL on error. 916 */ 917 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev, 918 unsigned vclk, unsigned dclk, 919 unsigned vco_min, unsigned vco_max, 920 unsigned fb_factor, unsigned fb_mask, 921 unsigned pd_min, unsigned pd_max, 922 unsigned pd_even, 923 unsigned *optimal_fb_div, 924 unsigned *optimal_vclk_div, 925 unsigned *optimal_dclk_div) 926 { 927 unsigned vco_freq, ref_freq = rdev->clock.spll.reference_freq; 928 929 /* start off with something large */ 930 unsigned optimal_score = ~0; 931 932 /* loop through vco from low to high */ 933 vco_min = max(max(vco_min, vclk), dclk); 934 for (vco_freq = vco_min; vco_freq <= vco_max; vco_freq += 100) { 935 936 uint64_t fb_div = (uint64_t)vco_freq * fb_factor; 937 unsigned vclk_div, dclk_div, score; 938 939 do_div(fb_div, ref_freq); 940 941 /* fb div out of range ? */ 942 if (fb_div > fb_mask) 943 break; /* it can oly get worse */ 944 945 fb_div &= fb_mask; 946 947 /* calc vclk divider with current vco freq */ 948 vclk_div = radeon_uvd_calc_upll_post_div(vco_freq, vclk, 949 pd_min, pd_even); 950 if (vclk_div > pd_max) 951 break; /* vco is too big, it has to stop */ 952 953 /* calc dclk divider with current vco freq */ 954 dclk_div = radeon_uvd_calc_upll_post_div(vco_freq, dclk, 955 pd_min, pd_even); 956 if (dclk_div > pd_max) 957 break; /* vco is too big, it has to stop */ 958 959 /* calc score with current vco freq */ 960 score = vclk - (vco_freq / vclk_div) + dclk - (vco_freq / dclk_div); 961 962 /* determine if this vco setting is better than current optimal settings */ 963 if (score < optimal_score) { 964 *optimal_fb_div = fb_div; 965 *optimal_vclk_div = vclk_div; 966 *optimal_dclk_div = dclk_div; 967 optimal_score = score; 968 if (optimal_score == 0) 969 break; /* it can't get better than this */ 970 } 971 } 972 973 /* did we found a valid setup ? */ 974 if (optimal_score == ~0) 975 return -EINVAL; 976 977 return 0; 978 } 979 980 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev, 981 unsigned cg_upll_func_cntl) 982 { 983 unsigned i; 984 985 /* make sure UPLL_CTLREQ is deasserted */ 986 WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK); 987 988 mdelay(10); 989 990 /* assert UPLL_CTLREQ */ 991 WREG32_P(cg_upll_func_cntl, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK); 992 993 /* wait for CTLACK and CTLACK2 to get asserted */ 994 for (i = 0; i < 100; ++i) { 995 uint32_t mask = UPLL_CTLACK_MASK | UPLL_CTLACK2_MASK; 996 if ((RREG32(cg_upll_func_cntl) & mask) == mask) 997 break; 998 mdelay(10); 999 } 1000 1001 /* deassert UPLL_CTLREQ */ 1002 WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK); 1003 1004 if (i == 100) { 1005 DRM_ERROR("Timeout setting UVD clocks!\n"); 1006 return -ETIMEDOUT; 1007 } 1008 1009 return 0; 1010 } 1011
Indexes created Sun Oct 26 21:10:03 GMT 2025