1 1.1 riastrad r600 0x9400 2 1.1 riastrad 0x000287A0 R7xx_CB_SHADER_CONTROL 3 1.1 riastrad 0x00028230 R7xx_PA_SC_EDGERULE 4 1.1 riastrad 0x000286C8 R7xx_SPI_THREAD_GROUPING 5 1.1 riastrad 0x00008D8C R7xx_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ 6 1.1 riastrad 0x00008490 CP_STRMOUT_CNTL 7 1.1 riastrad 0x000085F0 CP_COHER_CNTL 8 1.1 riastrad 0x000085F4 CP_COHER_SIZE 9 1.1 riastrad 0x000088C4 VGT_CACHE_INVALIDATION 10 1.1 riastrad 0x00028A50 VGT_ENHANCE 11 1.1 riastrad 0x000088CC VGT_ES_PER_GS 12 1.1 riastrad 0x00028A2C VGT_GROUP_DECR 13 1.1 riastrad 0x00028A28 VGT_GROUP_FIRST_DECR 14 1.1 riastrad 0x00028A24 VGT_GROUP_PRIM_TYPE 15 1.1 riastrad 0x00028A30 VGT_GROUP_VECT_0_CNTL 16 1.1 riastrad 0x00028A38 VGT_GROUP_VECT_0_FMT_CNTL 17 1.1 riastrad 0x00028A34 VGT_GROUP_VECT_1_CNTL 18 1.1 riastrad 0x00028A3C VGT_GROUP_VECT_1_FMT_CNTL 19 1.1 riastrad 0x00028A40 VGT_GS_MODE 20 1.1 riastrad 0x00028A6C VGT_GS_OUT_PRIM_TYPE 21 1.1 riastrad 0x00028B38 VGT_GS_MAX_VERT_OUT 22 1.1 riastrad 0x000088C8 VGT_GS_PER_ES 23 1.1 riastrad 0x000088E8 VGT_GS_PER_VS 24 1.1 riastrad 0x000088D4 VGT_GS_VERTEX_REUSE 25 1.1 riastrad 0x00028A14 VGT_HOS_CNTL 26 1.1 riastrad 0x00028A18 VGT_HOS_MAX_TESS_LEVEL 27 1.1 riastrad 0x00028A1C VGT_HOS_MIN_TESS_LEVEL 28 1.1 riastrad 0x00028A20 VGT_HOS_REUSE_DEPTH 29 1.1 riastrad 0x0000895C VGT_INDEX_TYPE 30 1.1 riastrad 0x00028408 VGT_INDX_OFFSET 31 1.1 riastrad 0x00028AA0 VGT_INSTANCE_STEP_RATE_0 32 1.1 riastrad 0x00028AA4 VGT_INSTANCE_STEP_RATE_1 33 1.1 riastrad 0x00028400 VGT_MAX_VTX_INDX 34 1.1 riastrad 0x00028404 VGT_MIN_VTX_INDX 35 1.1 riastrad 0x00028A94 VGT_MULTI_PRIM_IB_RESET_EN 36 1.1 riastrad 0x0002840C VGT_MULTI_PRIM_IB_RESET_INDX 37 1.1 riastrad 0x00008970 VGT_NUM_INDICES 38 1.1 riastrad 0x00008974 VGT_NUM_INSTANCES 39 1.1 riastrad 0x00028A10 VGT_OUTPUT_PATH_CNTL 40 1.1 riastrad 0x00028A84 VGT_PRIMITIVEID_EN 41 1.1 riastrad 0x00008958 VGT_PRIMITIVE_TYPE 42 1.1 riastrad 0x00028AB4 VGT_REUSE_OFF 43 1.1 riastrad 0x00028AB8 VGT_VTX_CNT_EN 44 1.1 riastrad 0x000088B0 VGT_VTX_VECT_EJECT_REG 45 1.1 riastrad 0x00028AD4 VGT_STRMOUT_VTX_STRIDE_0 46 1.1 riastrad 0x00028AE4 VGT_STRMOUT_VTX_STRIDE_1 47 1.1 riastrad 0x00028AF4 VGT_STRMOUT_VTX_STRIDE_2 48 1.1 riastrad 0x00028B04 VGT_STRMOUT_VTX_STRIDE_3 49 1.1 riastrad 0x00028B28 VGT_STRMOUT_DRAW_OPAQUE_OFFSET 50 1.1 riastrad 0x00028B2C VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE 51 1.1 riastrad 0x00028B30 VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE 52 1.1 riastrad 0x00028810 PA_CL_CLIP_CNTL 53 1.1 riastrad 0x00008A14 PA_CL_ENHANCE 54 1.1 riastrad 0x00028C14 PA_CL_GB_HORZ_CLIP_ADJ 55 1.1 riastrad 0x00028C18 PA_CL_GB_HORZ_DISC_ADJ 56 1.1 riastrad 0x00028C0C PA_CL_GB_VERT_CLIP_ADJ 57 1.1 riastrad 0x00028C10 PA_CL_GB_VERT_DISC_ADJ 58 1.1 riastrad 0x00028820 PA_CL_NANINF_CNTL 59 1.1 riastrad 0x00028E1C PA_CL_POINT_CULL_RAD 60 1.1 riastrad 0x00028E18 PA_CL_POINT_SIZE 61 1.1 riastrad 0x00028E10 PA_CL_POINT_X_RAD 62 1.1 riastrad 0x00028E14 PA_CL_POINT_Y_RAD 63 1.1 riastrad 0x00028E2C PA_CL_UCP_0_W 64 1.1 riastrad 0x00028E3C PA_CL_UCP_1_W 65 1.1 riastrad 0x00028E4C PA_CL_UCP_2_W 66 1.1 riastrad 0x00028E5C PA_CL_UCP_3_W 67 1.1 riastrad 0x00028E6C PA_CL_UCP_4_W 68 1.1 riastrad 0x00028E7C PA_CL_UCP_5_W 69 1.1 riastrad 0x00028E20 PA_CL_UCP_0_X 70 1.1 riastrad 0x00028E30 PA_CL_UCP_1_X 71 1.1 riastrad 0x00028E40 PA_CL_UCP_2_X 72 1.1 riastrad 0x00028E50 PA_CL_UCP_3_X 73 1.1 riastrad 0x00028E60 PA_CL_UCP_4_X 74 1.1 riastrad 0x00028E70 PA_CL_UCP_5_X 75 1.1 riastrad 0x00028E24 PA_CL_UCP_0_Y 76 1.1 riastrad 0x00028E34 PA_CL_UCP_1_Y 77 1.1 riastrad 0x00028E44 PA_CL_UCP_2_Y 78 1.1 riastrad 0x00028E54 PA_CL_UCP_3_Y 79 1.1 riastrad 0x00028E64 PA_CL_UCP_4_Y 80 1.1 riastrad 0x00028E74 PA_CL_UCP_5_Y 81 1.1 riastrad 0x00028E28 PA_CL_UCP_0_Z 82 1.1 riastrad 0x00028E38 PA_CL_UCP_1_Z 83 1.1 riastrad 0x00028E48 PA_CL_UCP_2_Z 84 1.1 riastrad 0x00028E58 PA_CL_UCP_3_Z 85 1.1 riastrad 0x00028E68 PA_CL_UCP_4_Z 86 1.1 riastrad 0x00028E78 PA_CL_UCP_5_Z 87 1.1 riastrad 0x00028440 PA_CL_VPORT_XOFFSET_0 88 1.1 riastrad 0x00028458 PA_CL_VPORT_XOFFSET_1 89 1.1 riastrad 0x00028470 PA_CL_VPORT_XOFFSET_2 90 1.1 riastrad 0x00028488 PA_CL_VPORT_XOFFSET_3 91 1.1 riastrad 0x000284A0 PA_CL_VPORT_XOFFSET_4 92 1.1 riastrad 0x000284B8 PA_CL_VPORT_XOFFSET_5 93 1.1 riastrad 0x000284D0 PA_CL_VPORT_XOFFSET_6 94 1.1 riastrad 0x000284E8 PA_CL_VPORT_XOFFSET_7 95 1.1 riastrad 0x00028500 PA_CL_VPORT_XOFFSET_8 96 1.1 riastrad 0x00028518 PA_CL_VPORT_XOFFSET_9 97 1.1 riastrad 0x00028530 PA_CL_VPORT_XOFFSET_10 98 1.1 riastrad 0x00028548 PA_CL_VPORT_XOFFSET_11 99 1.1 riastrad 0x00028560 PA_CL_VPORT_XOFFSET_12 100 1.1 riastrad 0x00028578 PA_CL_VPORT_XOFFSET_13 101 1.1 riastrad 0x00028590 PA_CL_VPORT_XOFFSET_14 102 1.1 riastrad 0x000285A8 PA_CL_VPORT_XOFFSET_15 103 1.1 riastrad 0x0002843C PA_CL_VPORT_XSCALE_0 104 1.1 riastrad 0x00028454 PA_CL_VPORT_XSCALE_1 105 1.1 riastrad 0x0002846C PA_CL_VPORT_XSCALE_2 106 1.1 riastrad 0x00028484 PA_CL_VPORT_XSCALE_3 107 1.1 riastrad 0x0002849C PA_CL_VPORT_XSCALE_4 108 1.1 riastrad 0x000284B4 PA_CL_VPORT_XSCALE_5 109 1.1 riastrad 0x000284CC PA_CL_VPORT_XSCALE_6 110 1.1 riastrad 0x000284E4 PA_CL_VPORT_XSCALE_7 111 1.1 riastrad 0x000284FC PA_CL_VPORT_XSCALE_8 112 1.1 riastrad 0x00028514 PA_CL_VPORT_XSCALE_9 113 1.1 riastrad 0x0002852C PA_CL_VPORT_XSCALE_10 114 1.1 riastrad 0x00028544 PA_CL_VPORT_XSCALE_11 115 1.1 riastrad 0x0002855C PA_CL_VPORT_XSCALE_12 116 1.1 riastrad 0x00028574 PA_CL_VPORT_XSCALE_13 117 1.1 riastrad 0x0002858C PA_CL_VPORT_XSCALE_14 118 1.1 riastrad 0x000285A4 PA_CL_VPORT_XSCALE_15 119 1.1 riastrad 0x00028448 PA_CL_VPORT_YOFFSET_0 120 1.1 riastrad 0x00028460 PA_CL_VPORT_YOFFSET_1 121 1.1 riastrad 0x00028478 PA_CL_VPORT_YOFFSET_2 122 1.1 riastrad 0x00028490 PA_CL_VPORT_YOFFSET_3 123 1.1 riastrad 0x000284A8 PA_CL_VPORT_YOFFSET_4 124 1.1 riastrad 0x000284C0 PA_CL_VPORT_YOFFSET_5 125 1.1 riastrad 0x000284D8 PA_CL_VPORT_YOFFSET_6 126 1.1 riastrad 0x000284F0 PA_CL_VPORT_YOFFSET_7 127 1.1 riastrad 0x00028508 PA_CL_VPORT_YOFFSET_8 128 1.1 riastrad 0x00028520 PA_CL_VPORT_YOFFSET_9 129 1.1 riastrad 0x00028538 PA_CL_VPORT_YOFFSET_10 130 1.1 riastrad 0x00028550 PA_CL_VPORT_YOFFSET_11 131 1.1 riastrad 0x00028568 PA_CL_VPORT_YOFFSET_12 132 1.1 riastrad 0x00028580 PA_CL_VPORT_YOFFSET_13 133 1.1 riastrad 0x00028598 PA_CL_VPORT_YOFFSET_14 134 1.1 riastrad 0x000285B0 PA_CL_VPORT_YOFFSET_15 135 1.1 riastrad 0x00028444 PA_CL_VPORT_YSCALE_0 136 1.1 riastrad 0x0002845C PA_CL_VPORT_YSCALE_1 137 1.1 riastrad 0x00028474 PA_CL_VPORT_YSCALE_2 138 1.1 riastrad 0x0002848C PA_CL_VPORT_YSCALE_3 139 1.1 riastrad 0x000284A4 PA_CL_VPORT_YSCALE_4 140 1.1 riastrad 0x000284BC PA_CL_VPORT_YSCALE_5 141 1.1 riastrad 0x000284D4 PA_CL_VPORT_YSCALE_6 142 1.1 riastrad 0x000284EC PA_CL_VPORT_YSCALE_7 143 1.1 riastrad 0x00028504 PA_CL_VPORT_YSCALE_8 144 1.1 riastrad 0x0002851C PA_CL_VPORT_YSCALE_9 145 1.1 riastrad 0x00028534 PA_CL_VPORT_YSCALE_10 146 1.1 riastrad 0x0002854C PA_CL_VPORT_YSCALE_11 147 1.1 riastrad 0x00028564 PA_CL_VPORT_YSCALE_12 148 1.1 riastrad 0x0002857C PA_CL_VPORT_YSCALE_13 149 1.1 riastrad 0x00028594 PA_CL_VPORT_YSCALE_14 150 1.1 riastrad 0x000285AC PA_CL_VPORT_YSCALE_15 151 1.1 riastrad 0x00028450 PA_CL_VPORT_ZOFFSET_0 152 1.1 riastrad 0x00028468 PA_CL_VPORT_ZOFFSET_1 153 1.1 riastrad 0x00028480 PA_CL_VPORT_ZOFFSET_2 154 1.1 riastrad 0x00028498 PA_CL_VPORT_ZOFFSET_3 155 1.1 riastrad 0x000284B0 PA_CL_VPORT_ZOFFSET_4 156 1.1 riastrad 0x000284C8 PA_CL_VPORT_ZOFFSET_5 157 1.1 riastrad 0x000284E0 PA_CL_VPORT_ZOFFSET_6 158 1.1 riastrad 0x000284F8 PA_CL_VPORT_ZOFFSET_7 159 1.1 riastrad 0x00028510 PA_CL_VPORT_ZOFFSET_8 160 1.1 riastrad 0x00028528 PA_CL_VPORT_ZOFFSET_9 161 1.1 riastrad 0x00028540 PA_CL_VPORT_ZOFFSET_10 162 1.1 riastrad 0x00028558 PA_CL_VPORT_ZOFFSET_11 163 1.1 riastrad 0x00028570 PA_CL_VPORT_ZOFFSET_12 164 1.1 riastrad 0x00028588 PA_CL_VPORT_ZOFFSET_13 165 1.1 riastrad 0x000285A0 PA_CL_VPORT_ZOFFSET_14 166 1.1 riastrad 0x000285B8 PA_CL_VPORT_ZOFFSET_15 167 1.1 riastrad 0x0002844C PA_CL_VPORT_ZSCALE_0 168 1.1 riastrad 0x00028464 PA_CL_VPORT_ZSCALE_1 169 1.1 riastrad 0x0002847C PA_CL_VPORT_ZSCALE_2 170 1.1 riastrad 0x00028494 PA_CL_VPORT_ZSCALE_3 171 1.1 riastrad 0x000284AC PA_CL_VPORT_ZSCALE_4 172 1.1 riastrad 0x000284C4 PA_CL_VPORT_ZSCALE_5 173 1.1 riastrad 0x000284DC PA_CL_VPORT_ZSCALE_6 174 1.1 riastrad 0x000284F4 PA_CL_VPORT_ZSCALE_7 175 1.1 riastrad 0x0002850C PA_CL_VPORT_ZSCALE_8 176 1.1 riastrad 0x00028524 PA_CL_VPORT_ZSCALE_9 177 1.1 riastrad 0x0002853C PA_CL_VPORT_ZSCALE_10 178 1.1 riastrad 0x00028554 PA_CL_VPORT_ZSCALE_11 179 1.1 riastrad 0x0002856C PA_CL_VPORT_ZSCALE_12 180 1.1 riastrad 0x00028584 PA_CL_VPORT_ZSCALE_13 181 1.1 riastrad 0x0002859C PA_CL_VPORT_ZSCALE_14 182 1.1 riastrad 0x000285B4 PA_CL_VPORT_ZSCALE_15 183 1.1 riastrad 0x0002881C PA_CL_VS_OUT_CNTL 184 1.1 riastrad 0x00028818 PA_CL_VTE_CNTL 185 1.1 riastrad 0x00028C48 PA_SC_AA_MASK 186 1.1 riastrad 0x00008B40 PA_SC_AA_SAMPLE_LOCS_2S 187 1.1 riastrad 0x00008B44 PA_SC_AA_SAMPLE_LOCS_4S 188 1.1 riastrad 0x00008B48 PA_SC_AA_SAMPLE_LOCS_8S_WD0 189 1.1 riastrad 0x00008B4C PA_SC_AA_SAMPLE_LOCS_8S_WD1 190 1.1 riastrad 0x00028C20 PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX 191 1.1 riastrad 0x00028C1C PA_SC_AA_SAMPLE_LOCS_MCTX 192 1.1 riastrad 0x00028214 PA_SC_CLIPRECT_0_BR 193 1.1 riastrad 0x0002821C PA_SC_CLIPRECT_1_BR 194 1.1 riastrad 0x00028224 PA_SC_CLIPRECT_2_BR 195 1.1 riastrad 0x0002822C PA_SC_CLIPRECT_3_BR 196 1.1 riastrad 0x00028210 PA_SC_CLIPRECT_0_TL 197 1.1 riastrad 0x00028218 PA_SC_CLIPRECT_1_TL 198 1.1 riastrad 0x00028220 PA_SC_CLIPRECT_2_TL 199 1.1 riastrad 0x00028228 PA_SC_CLIPRECT_3_TL 200 1.1 riastrad 0x0002820C PA_SC_CLIPRECT_RULE 201 1.1 riastrad 0x00008BF0 PA_SC_ENHANCE 202 1.1 riastrad 0x00028244 PA_SC_GENERIC_SCISSOR_BR 203 1.1 riastrad 0x00028240 PA_SC_GENERIC_SCISSOR_TL 204 1.1 riastrad 0x00028C00 PA_SC_LINE_CNTL 205 1.1 riastrad 0x00028A0C PA_SC_LINE_STIPPLE 206 1.1 riastrad 0x00008B10 PA_SC_LINE_STIPPLE_STATE 207 1.1 riastrad 0x00028A4C PA_SC_MODE_CNTL 208 1.1 riastrad 0x00028A48 PA_SC_MPASS_PS_CNTL 209 1.1 riastrad 0x00008B20 PA_SC_MULTI_CHIP_CNTL 210 1.1 riastrad 0x00028034 PA_SC_SCREEN_SCISSOR_BR 211 1.1 riastrad 0x00028030 PA_SC_SCREEN_SCISSOR_TL 212 1.1 riastrad 0x00028254 PA_SC_VPORT_SCISSOR_0_BR 213 1.1 riastrad 0x0002825C PA_SC_VPORT_SCISSOR_1_BR 214 1.1 riastrad 0x00028264 PA_SC_VPORT_SCISSOR_2_BR 215 1.1 riastrad 0x0002826C PA_SC_VPORT_SCISSOR_3_BR 216 1.1 riastrad 0x00028274 PA_SC_VPORT_SCISSOR_4_BR 217 1.1 riastrad 0x0002827C PA_SC_VPORT_SCISSOR_5_BR 218 1.1 riastrad 0x00028284 PA_SC_VPORT_SCISSOR_6_BR 219 1.1 riastrad 0x0002828C PA_SC_VPORT_SCISSOR_7_BR 220 1.1 riastrad 0x00028294 PA_SC_VPORT_SCISSOR_8_BR 221 1.1 riastrad 0x0002829C PA_SC_VPORT_SCISSOR_9_BR 222 1.1 riastrad 0x000282A4 PA_SC_VPORT_SCISSOR_10_BR 223 1.1 riastrad 0x000282AC PA_SC_VPORT_SCISSOR_11_BR 224 1.1 riastrad 0x000282B4 PA_SC_VPORT_SCISSOR_12_BR 225 1.1 riastrad 0x000282BC PA_SC_VPORT_SCISSOR_13_BR 226 1.1 riastrad 0x000282C4 PA_SC_VPORT_SCISSOR_14_BR 227 1.1 riastrad 0x000282CC PA_SC_VPORT_SCISSOR_15_BR 228 1.1 riastrad 0x00028250 PA_SC_VPORT_SCISSOR_0_TL 229 1.1 riastrad 0x00028258 PA_SC_VPORT_SCISSOR_1_TL 230 1.1 riastrad 0x00028260 PA_SC_VPORT_SCISSOR_2_TL 231 1.1 riastrad 0x00028268 PA_SC_VPORT_SCISSOR_3_TL 232 1.1 riastrad 0x00028270 PA_SC_VPORT_SCISSOR_4_TL 233 1.1 riastrad 0x00028278 PA_SC_VPORT_SCISSOR_5_TL 234 1.1 riastrad 0x00028280 PA_SC_VPORT_SCISSOR_6_TL 235 1.1 riastrad 0x00028288 PA_SC_VPORT_SCISSOR_7_TL 236 1.1 riastrad 0x00028290 PA_SC_VPORT_SCISSOR_8_TL 237 1.1 riastrad 0x00028298 PA_SC_VPORT_SCISSOR_9_TL 238 1.1 riastrad 0x000282A0 PA_SC_VPORT_SCISSOR_10_TL 239 1.1 riastrad 0x000282A8 PA_SC_VPORT_SCISSOR_11_TL 240 1.1 riastrad 0x000282B0 PA_SC_VPORT_SCISSOR_12_TL 241 1.1 riastrad 0x000282B8 PA_SC_VPORT_SCISSOR_13_TL 242 1.1 riastrad 0x000282C0 PA_SC_VPORT_SCISSOR_14_TL 243 1.1 riastrad 0x000282C8 PA_SC_VPORT_SCISSOR_15_TL 244 1.1 riastrad 0x000282D4 PA_SC_VPORT_ZMAX_0 245 1.1 riastrad 0x000282DC PA_SC_VPORT_ZMAX_1 246 1.1 riastrad 0x000282E4 PA_SC_VPORT_ZMAX_2 247 1.1 riastrad 0x000282EC PA_SC_VPORT_ZMAX_3 248 1.1 riastrad 0x000282F4 PA_SC_VPORT_ZMAX_4 249 1.1 riastrad 0x000282FC PA_SC_VPORT_ZMAX_5 250 1.1 riastrad 0x00028304 PA_SC_VPORT_ZMAX_6 251 1.1 riastrad 0x0002830C PA_SC_VPORT_ZMAX_7 252 1.1 riastrad 0x00028314 PA_SC_VPORT_ZMAX_8 253 1.1 riastrad 0x0002831C PA_SC_VPORT_ZMAX_9 254 1.1 riastrad 0x00028324 PA_SC_VPORT_ZMAX_10 255 1.1 riastrad 0x0002832C PA_SC_VPORT_ZMAX_11 256 1.1 riastrad 0x00028334 PA_SC_VPORT_ZMAX_12 257 1.1 riastrad 0x0002833C PA_SC_VPORT_ZMAX_13 258 1.1 riastrad 0x00028344 PA_SC_VPORT_ZMAX_14 259 1.1 riastrad 0x0002834C PA_SC_VPORT_ZMAX_15 260 1.1 riastrad 0x000282D0 PA_SC_VPORT_ZMIN_0 261 1.1 riastrad 0x000282D8 PA_SC_VPORT_ZMIN_1 262 1.1 riastrad 0x000282E0 PA_SC_VPORT_ZMIN_2 263 1.1 riastrad 0x000282E8 PA_SC_VPORT_ZMIN_3 264 1.1 riastrad 0x000282F0 PA_SC_VPORT_ZMIN_4 265 1.1 riastrad 0x000282F8 PA_SC_VPORT_ZMIN_5 266 1.1 riastrad 0x00028300 PA_SC_VPORT_ZMIN_6 267 1.1 riastrad 0x00028308 PA_SC_VPORT_ZMIN_7 268 1.1 riastrad 0x00028310 PA_SC_VPORT_ZMIN_8 269 1.1 riastrad 0x00028318 PA_SC_VPORT_ZMIN_9 270 1.1 riastrad 0x00028320 PA_SC_VPORT_ZMIN_10 271 1.1 riastrad 0x00028328 PA_SC_VPORT_ZMIN_11 272 1.1 riastrad 0x00028330 PA_SC_VPORT_ZMIN_12 273 1.1 riastrad 0x00028338 PA_SC_VPORT_ZMIN_13 274 1.1 riastrad 0x00028340 PA_SC_VPORT_ZMIN_14 275 1.1 riastrad 0x00028348 PA_SC_VPORT_ZMIN_15 276 1.1 riastrad 0x00028200 PA_SC_WINDOW_OFFSET 277 1.1 riastrad 0x00028208 PA_SC_WINDOW_SCISSOR_BR 278 1.1 riastrad 0x00028204 PA_SC_WINDOW_SCISSOR_TL 279 1.1 riastrad 0x00028A08 PA_SU_LINE_CNTL 280 1.1 riastrad 0x00028A04 PA_SU_POINT_MINMAX 281 1.1 riastrad 0x00028A00 PA_SU_POINT_SIZE 282 1.1 riastrad 0x00028E0C PA_SU_POLY_OFFSET_BACK_OFFSET 283 1.1 riastrad 0x00028E08 PA_SU_POLY_OFFSET_BACK_SCALE 284 1.1 riastrad 0x00028DFC PA_SU_POLY_OFFSET_CLAMP 285 1.1 riastrad 0x00028DF8 PA_SU_POLY_OFFSET_DB_FMT_CNTL 286 1.1 riastrad 0x00028E04 PA_SU_POLY_OFFSET_FRONT_OFFSET 287 1.1 riastrad 0x00028E00 PA_SU_POLY_OFFSET_FRONT_SCALE 288 1.1 riastrad 0x00028814 PA_SU_SC_MODE_CNTL 289 1.1 riastrad 0x00028C08 PA_SU_VTX_CNTL 290 1.1 riastrad 0x00008C04 SQ_GPR_RESOURCE_MGMT_1 291 1.1 riastrad 0x00008C08 SQ_GPR_RESOURCE_MGMT_2 292 1.1 riastrad 0x00008C10 SQ_STACK_RESOURCE_MGMT_1 293 1.1 riastrad 0x00008C14 SQ_STACK_RESOURCE_MGMT_2 294 1.1 riastrad 0x00008C0C SQ_THREAD_RESOURCE_MGMT 295 1.1 riastrad 0x00028380 SQ_VTX_SEMANTIC_0 296 1.1 riastrad 0x00028384 SQ_VTX_SEMANTIC_1 297 1.1 riastrad 0x00028388 SQ_VTX_SEMANTIC_2 298 1.1 riastrad 0x0002838C SQ_VTX_SEMANTIC_3 299 1.1 riastrad 0x00028390 SQ_VTX_SEMANTIC_4 300 1.1 riastrad 0x00028394 SQ_VTX_SEMANTIC_5 301 1.1 riastrad 0x00028398 SQ_VTX_SEMANTIC_6 302 1.1 riastrad 0x0002839C SQ_VTX_SEMANTIC_7 303 1.1 riastrad 0x000283A0 SQ_VTX_SEMANTIC_8 304 1.1 riastrad 0x000283A4 SQ_VTX_SEMANTIC_9 305 1.1 riastrad 0x000283A8 SQ_VTX_SEMANTIC_10 306 1.1 riastrad 0x000283AC SQ_VTX_SEMANTIC_11 307 1.1 riastrad 0x000283B0 SQ_VTX_SEMANTIC_12 308 1.1 riastrad 0x000283B4 SQ_VTX_SEMANTIC_13 309 1.1 riastrad 0x000283B8 SQ_VTX_SEMANTIC_14 310 1.1 riastrad 0x000283BC SQ_VTX_SEMANTIC_15 311 1.1 riastrad 0x000283C0 SQ_VTX_SEMANTIC_16 312 1.1 riastrad 0x000283C4 SQ_VTX_SEMANTIC_17 313 1.1 riastrad 0x000283C8 SQ_VTX_SEMANTIC_18 314 1.1 riastrad 0x000283CC SQ_VTX_SEMANTIC_19 315 1.1 riastrad 0x000283D0 SQ_VTX_SEMANTIC_20 316 1.1 riastrad 0x000283D4 SQ_VTX_SEMANTIC_21 317 1.1 riastrad 0x000283D8 SQ_VTX_SEMANTIC_22 318 1.1 riastrad 0x000283DC SQ_VTX_SEMANTIC_23 319 1.1 riastrad 0x000283E0 SQ_VTX_SEMANTIC_24 320 1.1 riastrad 0x000283E4 SQ_VTX_SEMANTIC_25 321 1.1 riastrad 0x000283E8 SQ_VTX_SEMANTIC_26 322 1.1 riastrad 0x000283EC SQ_VTX_SEMANTIC_27 323 1.1 riastrad 0x000283F0 SQ_VTX_SEMANTIC_28 324 1.1 riastrad 0x000283F4 SQ_VTX_SEMANTIC_29 325 1.1 riastrad 0x000283F8 SQ_VTX_SEMANTIC_30 326 1.1 riastrad 0x000283FC SQ_VTX_SEMANTIC_31 327 1.1 riastrad 0x000288E0 SQ_VTX_SEMANTIC_CLEAR 328 1.1 riastrad 0x0003CFF4 SQ_VTX_START_INST_LOC 329 1.1 riastrad 0x000281C0 SQ_ALU_CONST_BUFFER_SIZE_GS_0 330 1.1 riastrad 0x000281C4 SQ_ALU_CONST_BUFFER_SIZE_GS_1 331 1.1 riastrad 0x000281C8 SQ_ALU_CONST_BUFFER_SIZE_GS_2 332 1.1 riastrad 0x000281CC SQ_ALU_CONST_BUFFER_SIZE_GS_3 333 1.1 riastrad 0x000281D0 SQ_ALU_CONST_BUFFER_SIZE_GS_4 334 1.1 riastrad 0x000281D4 SQ_ALU_CONST_BUFFER_SIZE_GS_5 335 1.1 riastrad 0x000281D8 SQ_ALU_CONST_BUFFER_SIZE_GS_6 336 1.1 riastrad 0x000281DC SQ_ALU_CONST_BUFFER_SIZE_GS_7 337 1.1 riastrad 0x000281E0 SQ_ALU_CONST_BUFFER_SIZE_GS_8 338 1.1 riastrad 0x000281E4 SQ_ALU_CONST_BUFFER_SIZE_GS_9 339 1.1 riastrad 0x000281E8 SQ_ALU_CONST_BUFFER_SIZE_GS_10 340 1.1 riastrad 0x000281EC SQ_ALU_CONST_BUFFER_SIZE_GS_11 341 1.1 riastrad 0x000281F0 SQ_ALU_CONST_BUFFER_SIZE_GS_12 342 1.1 riastrad 0x000281F4 SQ_ALU_CONST_BUFFER_SIZE_GS_13 343 1.1 riastrad 0x000281F8 SQ_ALU_CONST_BUFFER_SIZE_GS_14 344 1.1 riastrad 0x000281FC SQ_ALU_CONST_BUFFER_SIZE_GS_15 345 1.1 riastrad 0x00028140 SQ_ALU_CONST_BUFFER_SIZE_PS_0 346 1.1 riastrad 0x00028144 SQ_ALU_CONST_BUFFER_SIZE_PS_1 347 1.1 riastrad 0x00028148 SQ_ALU_CONST_BUFFER_SIZE_PS_2 348 1.1 riastrad 0x0002814C SQ_ALU_CONST_BUFFER_SIZE_PS_3 349 1.1 riastrad 0x00028150 SQ_ALU_CONST_BUFFER_SIZE_PS_4 350 1.1 riastrad 0x00028154 SQ_ALU_CONST_BUFFER_SIZE_PS_5 351 1.1 riastrad 0x00028158 SQ_ALU_CONST_BUFFER_SIZE_PS_6 352 1.1 riastrad 0x0002815C SQ_ALU_CONST_BUFFER_SIZE_PS_7 353 1.1 riastrad 0x00028160 SQ_ALU_CONST_BUFFER_SIZE_PS_8 354 1.1 riastrad 0x00028164 SQ_ALU_CONST_BUFFER_SIZE_PS_9 355 1.1 riastrad 0x00028168 SQ_ALU_CONST_BUFFER_SIZE_PS_10 356 1.1 riastrad 0x0002816C SQ_ALU_CONST_BUFFER_SIZE_PS_11 357 1.1 riastrad 0x00028170 SQ_ALU_CONST_BUFFER_SIZE_PS_12 358 1.1 riastrad 0x00028174 SQ_ALU_CONST_BUFFER_SIZE_PS_13 359 1.1 riastrad 0x00028178 SQ_ALU_CONST_BUFFER_SIZE_PS_14 360 1.1 riastrad 0x0002817C SQ_ALU_CONST_BUFFER_SIZE_PS_15 361 1.1 riastrad 0x00028180 SQ_ALU_CONST_BUFFER_SIZE_VS_0 362 1.1 riastrad 0x00028184 SQ_ALU_CONST_BUFFER_SIZE_VS_1 363 1.1 riastrad 0x00028188 SQ_ALU_CONST_BUFFER_SIZE_VS_2 364 1.1 riastrad 0x0002818C SQ_ALU_CONST_BUFFER_SIZE_VS_3 365 1.1 riastrad 0x00028190 SQ_ALU_CONST_BUFFER_SIZE_VS_4 366 1.1 riastrad 0x00028194 SQ_ALU_CONST_BUFFER_SIZE_VS_5 367 1.1 riastrad 0x00028198 SQ_ALU_CONST_BUFFER_SIZE_VS_6 368 1.1 riastrad 0x0002819C SQ_ALU_CONST_BUFFER_SIZE_VS_7 369 1.1 riastrad 0x000281A0 SQ_ALU_CONST_BUFFER_SIZE_VS_8 370 1.1 riastrad 0x000281A4 SQ_ALU_CONST_BUFFER_SIZE_VS_9 371 1.1 riastrad 0x000281A8 SQ_ALU_CONST_BUFFER_SIZE_VS_10 372 1.1 riastrad 0x000281AC SQ_ALU_CONST_BUFFER_SIZE_VS_11 373 1.1 riastrad 0x000281B0 SQ_ALU_CONST_BUFFER_SIZE_VS_12 374 1.1 riastrad 0x000281B4 SQ_ALU_CONST_BUFFER_SIZE_VS_13 375 1.1 riastrad 0x000281B8 SQ_ALU_CONST_BUFFER_SIZE_VS_14 376 1.1 riastrad 0x000281BC SQ_ALU_CONST_BUFFER_SIZE_VS_15 377 1.1 riastrad 0x000288D8 SQ_PGM_CF_OFFSET_ES 378 1.1 riastrad 0x000288DC SQ_PGM_CF_OFFSET_FS 379 1.1 riastrad 0x000288D4 SQ_PGM_CF_OFFSET_GS 380 1.1 riastrad 0x000288CC SQ_PGM_CF_OFFSET_PS 381 1.1 riastrad 0x000288D0 SQ_PGM_CF_OFFSET_VS 382 1.1 riastrad 0x00028854 SQ_PGM_EXPORTS_PS 383 1.1 riastrad 0x00028890 SQ_PGM_RESOURCES_ES 384 1.1 riastrad 0x000288A4 SQ_PGM_RESOURCES_FS 385 1.1 riastrad 0x0002887C SQ_PGM_RESOURCES_GS 386 1.1 riastrad 0x00028850 SQ_PGM_RESOURCES_PS 387 1.1 riastrad 0x00028868 SQ_PGM_RESOURCES_VS 388 1.1 riastrad 0x00009100 SPI_CONFIG_CNTL 389 1.1 riastrad 0x0000913C SPI_CONFIG_CNTL_1 390 1.1 riastrad 0x000286DC SPI_FOG_CNTL 391 1.1 riastrad 0x000286E4 SPI_FOG_FUNC_BIAS 392 1.1 riastrad 0x000286E0 SPI_FOG_FUNC_SCALE 393 1.1 riastrad 0x000286D8 SPI_INPUT_Z 394 1.1 riastrad 0x000286D4 SPI_INTERP_CONTROL_0 395 1.1 riastrad 0x00028644 SPI_PS_INPUT_CNTL_0 396 1.1 riastrad 0x00028648 SPI_PS_INPUT_CNTL_1 397 1.1 riastrad 0x0002864C SPI_PS_INPUT_CNTL_2 398 1.1 riastrad 0x00028650 SPI_PS_INPUT_CNTL_3 399 1.1 riastrad 0x00028654 SPI_PS_INPUT_CNTL_4 400 1.1 riastrad 0x00028658 SPI_PS_INPUT_CNTL_5 401 1.1 riastrad 0x0002865C SPI_PS_INPUT_CNTL_6 402 1.1 riastrad 0x00028660 SPI_PS_INPUT_CNTL_7 403 1.1 riastrad 0x00028664 SPI_PS_INPUT_CNTL_8 404 1.1 riastrad 0x00028668 SPI_PS_INPUT_CNTL_9 405 1.1 riastrad 0x0002866C SPI_PS_INPUT_CNTL_10 406 1.1 riastrad 0x00028670 SPI_PS_INPUT_CNTL_11 407 1.1 riastrad 0x00028674 SPI_PS_INPUT_CNTL_12 408 1.1 riastrad 0x00028678 SPI_PS_INPUT_CNTL_13 409 1.1 riastrad 0x0002867C SPI_PS_INPUT_CNTL_14 410 1.1 riastrad 0x00028680 SPI_PS_INPUT_CNTL_15 411 1.1 riastrad 0x00028684 SPI_PS_INPUT_CNTL_16 412 1.1 riastrad 0x00028688 SPI_PS_INPUT_CNTL_17 413 1.1 riastrad 0x0002868C SPI_PS_INPUT_CNTL_18 414 1.1 riastrad 0x00028690 SPI_PS_INPUT_CNTL_19 415 1.1 riastrad 0x00028694 SPI_PS_INPUT_CNTL_20 416 1.1 riastrad 0x00028698 SPI_PS_INPUT_CNTL_21 417 1.1 riastrad 0x0002869C SPI_PS_INPUT_CNTL_22 418 1.1 riastrad 0x000286A0 SPI_PS_INPUT_CNTL_23 419 1.1 riastrad 0x000286A4 SPI_PS_INPUT_CNTL_24 420 1.1 riastrad 0x000286A8 SPI_PS_INPUT_CNTL_25 421 1.1 riastrad 0x000286AC SPI_PS_INPUT_CNTL_26 422 1.1 riastrad 0x000286B0 SPI_PS_INPUT_CNTL_27 423 1.1 riastrad 0x000286B4 SPI_PS_INPUT_CNTL_28 424 1.1 riastrad 0x000286B8 SPI_PS_INPUT_CNTL_29 425 1.1 riastrad 0x000286BC SPI_PS_INPUT_CNTL_30 426 1.1 riastrad 0x000286C0 SPI_PS_INPUT_CNTL_31 427 1.1 riastrad 0x000286CC SPI_PS_IN_CONTROL_0 428 1.1 riastrad 0x000286D0 SPI_PS_IN_CONTROL_1 429 1.1 riastrad 0x000286C4 SPI_VS_OUT_CONFIG 430 1.1 riastrad 0x00028614 SPI_VS_OUT_ID_0 431 1.1 riastrad 0x00028618 SPI_VS_OUT_ID_1 432 1.1 riastrad 0x0002861C SPI_VS_OUT_ID_2 433 1.1 riastrad 0x00028620 SPI_VS_OUT_ID_3 434 1.1 riastrad 0x00028624 SPI_VS_OUT_ID_4 435 1.1 riastrad 0x00028628 SPI_VS_OUT_ID_5 436 1.1 riastrad 0x0002862C SPI_VS_OUT_ID_6 437 1.1 riastrad 0x00028630 SPI_VS_OUT_ID_7 438 1.1 riastrad 0x00028634 SPI_VS_OUT_ID_8 439 1.1 riastrad 0x00028638 SPI_VS_OUT_ID_9 440 1.1 riastrad 0x00028438 SX_ALPHA_REF 441 1.1 riastrad 0x00028410 SX_ALPHA_TEST_CONTROL 442 1.1 riastrad 0x00028354 SX_SURFACE_SYNC 443 1.1 riastrad 0x00009014 SX_MEMORY_EXPORT_SIZE 444 1.1 riastrad 0x00009604 TC_INVALIDATE 445 1.1 riastrad 0x00009400 TD_FILTER4 446 1.1 riastrad 0x00009404 TD_FILTER4_1 447 1.1 riastrad 0x00009408 TD_FILTER4_2 448 1.1 riastrad 0x0000940C TD_FILTER4_3 449 1.1 riastrad 0x00009410 TD_FILTER4_4 450 1.1 riastrad 0x00009414 TD_FILTER4_5 451 1.1 riastrad 0x00009418 TD_FILTER4_6 452 1.1 riastrad 0x0000941C TD_FILTER4_7 453 1.1 riastrad 0x00009420 TD_FILTER4_8 454 1.1 riastrad 0x00009424 TD_FILTER4_9 455 1.1 riastrad 0x00009428 TD_FILTER4_10 456 1.1 riastrad 0x0000942C TD_FILTER4_11 457 1.1 riastrad 0x00009430 TD_FILTER4_12 458 1.1 riastrad 0x00009434 TD_FILTER4_13 459 1.1 riastrad 0x00009438 TD_FILTER4_14 460 1.1 riastrad 0x0000943C TD_FILTER4_15 461 1.1 riastrad 0x00009440 TD_FILTER4_16 462 1.1 riastrad 0x00009444 TD_FILTER4_17 463 1.1 riastrad 0x00009448 TD_FILTER4_18 464 1.1 riastrad 0x0000944C TD_FILTER4_19 465 1.1 riastrad 0x00009450 TD_FILTER4_20 466 1.1 riastrad 0x00009454 TD_FILTER4_21 467 1.1 riastrad 0x00009458 TD_FILTER4_22 468 1.1 riastrad 0x0000945C TD_FILTER4_23 469 1.1 riastrad 0x00009460 TD_FILTER4_24 470 1.1 riastrad 0x00009464 TD_FILTER4_25 471 1.1 riastrad 0x00009468 TD_FILTER4_26 472 1.1 riastrad 0x0000946C TD_FILTER4_27 473 1.1 riastrad 0x00009470 TD_FILTER4_28 474 1.1 riastrad 0x00009474 TD_FILTER4_29 475 1.1 riastrad 0x00009478 TD_FILTER4_30 476 1.1 riastrad 0x0000947C TD_FILTER4_31 477 1.1 riastrad 0x00009480 TD_FILTER4_32 478 1.1 riastrad 0x00009484 TD_FILTER4_33 479 1.1 riastrad 0x00009488 TD_FILTER4_34 480 1.1 riastrad 0x0000948C TD_FILTER4_35 481 1.1 riastrad 0x0000A80C TD_GS_SAMPLER0_BORDER_ALPHA 482 1.1 riastrad 0x0000A81C TD_GS_SAMPLER1_BORDER_ALPHA 483 1.1 riastrad 0x0000A82C TD_GS_SAMPLER2_BORDER_ALPHA 484 1.1 riastrad 0x0000A83C TD_GS_SAMPLER3_BORDER_ALPHA 485 1.1 riastrad 0x0000A84C TD_GS_SAMPLER4_BORDER_ALPHA 486 1.1 riastrad 0x0000A85C TD_GS_SAMPLER5_BORDER_ALPHA 487 1.1 riastrad 0x0000A86C TD_GS_SAMPLER6_BORDER_ALPHA 488 1.1 riastrad 0x0000A87C TD_GS_SAMPLER7_BORDER_ALPHA 489 1.1 riastrad 0x0000A88C TD_GS_SAMPLER8_BORDER_ALPHA 490 1.1 riastrad 0x0000A89C TD_GS_SAMPLER9_BORDER_ALPHA 491 1.1 riastrad 0x0000A8AC TD_GS_SAMPLER10_BORDER_ALPHA 492 1.1 riastrad 0x0000A8BC TD_GS_SAMPLER11_BORDER_ALPHA 493 1.1 riastrad 0x0000A8CC TD_GS_SAMPLER12_BORDER_ALPHA 494 1.1 riastrad 0x0000A8DC TD_GS_SAMPLER13_BORDER_ALPHA 495 1.1 riastrad 0x0000A8EC TD_GS_SAMPLER14_BORDER_ALPHA 496 1.1 riastrad 0x0000A8FC TD_GS_SAMPLER15_BORDER_ALPHA 497 1.1 riastrad 0x0000A90C TD_GS_SAMPLER16_BORDER_ALPHA 498 1.1 riastrad 0x0000A91C TD_GS_SAMPLER17_BORDER_ALPHA 499 1.1 riastrad 0x0000A808 TD_GS_SAMPLER0_BORDER_BLUE 500 1.1 riastrad 0x0000A818 TD_GS_SAMPLER1_BORDER_BLUE 501 1.1 riastrad 0x0000A828 TD_GS_SAMPLER2_BORDER_BLUE 502 1.1 riastrad 0x0000A838 TD_GS_SAMPLER3_BORDER_BLUE 503 1.1 riastrad 0x0000A848 TD_GS_SAMPLER4_BORDER_BLUE 504 1.1 riastrad 0x0000A858 TD_GS_SAMPLER5_BORDER_BLUE 505 1.1 riastrad 0x0000A868 TD_GS_SAMPLER6_BORDER_BLUE 506 1.1 riastrad 0x0000A878 TD_GS_SAMPLER7_BORDER_BLUE 507 1.1 riastrad 0x0000A888 TD_GS_SAMPLER8_BORDER_BLUE 508 1.1 riastrad 0x0000A898 TD_GS_SAMPLER9_BORDER_BLUE 509 1.1 riastrad 0x0000A8A8 TD_GS_SAMPLER10_BORDER_BLUE 510 1.1 riastrad 0x0000A8B8 TD_GS_SAMPLER11_BORDER_BLUE 511 1.1 riastrad 0x0000A8C8 TD_GS_SAMPLER12_BORDER_BLUE 512 1.1 riastrad 0x0000A8D8 TD_GS_SAMPLER13_BORDER_BLUE 513 1.1 riastrad 0x0000A8E8 TD_GS_SAMPLER14_BORDER_BLUE 514 1.1 riastrad 0x0000A8F8 TD_GS_SAMPLER15_BORDER_BLUE 515 1.1 riastrad 0x0000A908 TD_GS_SAMPLER16_BORDER_BLUE 516 1.1 riastrad 0x0000A918 TD_GS_SAMPLER17_BORDER_BLUE 517 1.1 riastrad 0x0000A804 TD_GS_SAMPLER0_BORDER_GREEN 518 1.1 riastrad 0x0000A814 TD_GS_SAMPLER1_BORDER_GREEN 519 1.1 riastrad 0x0000A824 TD_GS_SAMPLER2_BORDER_GREEN 520 1.1 riastrad 0x0000A834 TD_GS_SAMPLER3_BORDER_GREEN 521 1.1 riastrad 0x0000A844 TD_GS_SAMPLER4_BORDER_GREEN 522 1.1 riastrad 0x0000A854 TD_GS_SAMPLER5_BORDER_GREEN 523 1.1 riastrad 0x0000A864 TD_GS_SAMPLER6_BORDER_GREEN 524 1.1 riastrad 0x0000A874 TD_GS_SAMPLER7_BORDER_GREEN 525 1.1 riastrad 0x0000A884 TD_GS_SAMPLER8_BORDER_GREEN 526 1.1 riastrad 0x0000A894 TD_GS_SAMPLER9_BORDER_GREEN 527 1.1 riastrad 0x0000A8A4 TD_GS_SAMPLER10_BORDER_GREEN 528 1.1 riastrad 0x0000A8B4 TD_GS_SAMPLER11_BORDER_GREEN 529 1.1 riastrad 0x0000A8C4 TD_GS_SAMPLER12_BORDER_GREEN 530 1.1 riastrad 0x0000A8D4 TD_GS_SAMPLER13_BORDER_GREEN 531 1.1 riastrad 0x0000A8E4 TD_GS_SAMPLER14_BORDER_GREEN 532 1.1 riastrad 0x0000A8F4 TD_GS_SAMPLER15_BORDER_GREEN 533 1.1 riastrad 0x0000A904 TD_GS_SAMPLER16_BORDER_GREEN 534 1.1 riastrad 0x0000A914 TD_GS_SAMPLER17_BORDER_GREEN 535 1.1 riastrad 0x0000A800 TD_GS_SAMPLER0_BORDER_RED 536 1.1 riastrad 0x0000A810 TD_GS_SAMPLER1_BORDER_RED 537 1.1 riastrad 0x0000A820 TD_GS_SAMPLER2_BORDER_RED 538 1.1 riastrad 0x0000A830 TD_GS_SAMPLER3_BORDER_RED 539 1.1 riastrad 0x0000A840 TD_GS_SAMPLER4_BORDER_RED 540 1.1 riastrad 0x0000A850 TD_GS_SAMPLER5_BORDER_RED 541 1.1 riastrad 0x0000A860 TD_GS_SAMPLER6_BORDER_RED 542 1.1 riastrad 0x0000A870 TD_GS_SAMPLER7_BORDER_RED 543 1.1 riastrad 0x0000A880 TD_GS_SAMPLER8_BORDER_RED 544 1.1 riastrad 0x0000A890 TD_GS_SAMPLER9_BORDER_RED 545 1.1 riastrad 0x0000A8A0 TD_GS_SAMPLER10_BORDER_RED 546 1.1 riastrad 0x0000A8B0 TD_GS_SAMPLER11_BORDER_RED 547 1.1 riastrad 0x0000A8C0 TD_GS_SAMPLER12_BORDER_RED 548 1.1 riastrad 0x0000A8D0 TD_GS_SAMPLER13_BORDER_RED 549 1.1 riastrad 0x0000A8E0 TD_GS_SAMPLER14_BORDER_RED 550 1.1 riastrad 0x0000A8F0 TD_GS_SAMPLER15_BORDER_RED 551 1.1 riastrad 0x0000A900 TD_GS_SAMPLER16_BORDER_RED 552 1.1 riastrad 0x0000A910 TD_GS_SAMPLER17_BORDER_RED 553 1.1 riastrad 0x0000A40C TD_PS_SAMPLER0_BORDER_ALPHA 554 1.1 riastrad 0x0000A41C TD_PS_SAMPLER1_BORDER_ALPHA 555 1.1 riastrad 0x0000A42C TD_PS_SAMPLER2_BORDER_ALPHA 556 1.1 riastrad 0x0000A43C TD_PS_SAMPLER3_BORDER_ALPHA 557 1.1 riastrad 0x0000A44C TD_PS_SAMPLER4_BORDER_ALPHA 558 1.1 riastrad 0x0000A45C TD_PS_SAMPLER5_BORDER_ALPHA 559 1.1 riastrad 0x0000A46C TD_PS_SAMPLER6_BORDER_ALPHA 560 1.1 riastrad 0x0000A47C TD_PS_SAMPLER7_BORDER_ALPHA 561 1.1 riastrad 0x0000A48C TD_PS_SAMPLER8_BORDER_ALPHA 562 1.1 riastrad 0x0000A49C TD_PS_SAMPLER9_BORDER_ALPHA 563 1.1 riastrad 0x0000A4AC TD_PS_SAMPLER10_BORDER_ALPHA 564 1.1 riastrad 0x0000A4BC TD_PS_SAMPLER11_BORDER_ALPHA 565 1.1 riastrad 0x0000A4CC TD_PS_SAMPLER12_BORDER_ALPHA 566 1.1 riastrad 0x0000A4DC TD_PS_SAMPLER13_BORDER_ALPHA 567 1.1 riastrad 0x0000A4EC TD_PS_SAMPLER14_BORDER_ALPHA 568 1.1 riastrad 0x0000A4FC TD_PS_SAMPLER15_BORDER_ALPHA 569 1.1 riastrad 0x0000A50C TD_PS_SAMPLER16_BORDER_ALPHA 570 1.1 riastrad 0x0000A51C TD_PS_SAMPLER17_BORDER_ALPHA 571 1.1 riastrad 0x0000A408 TD_PS_SAMPLER0_BORDER_BLUE 572 1.1 riastrad 0x0000A418 TD_PS_SAMPLER1_BORDER_BLUE 573 1.1 riastrad 0x0000A428 TD_PS_SAMPLER2_BORDER_BLUE 574 1.1 riastrad 0x0000A438 TD_PS_SAMPLER3_BORDER_BLUE 575 1.1 riastrad 0x0000A448 TD_PS_SAMPLER4_BORDER_BLUE 576 1.1 riastrad 0x0000A458 TD_PS_SAMPLER5_BORDER_BLUE 577 1.1 riastrad 0x0000A468 TD_PS_SAMPLER6_BORDER_BLUE 578 1.1 riastrad 0x0000A478 TD_PS_SAMPLER7_BORDER_BLUE 579 1.1 riastrad 0x0000A488 TD_PS_SAMPLER8_BORDER_BLUE 580 1.1 riastrad 0x0000A498 TD_PS_SAMPLER9_BORDER_BLUE 581 1.1 riastrad 0x0000A4A8 TD_PS_SAMPLER10_BORDER_BLUE 582 1.1 riastrad 0x0000A4B8 TD_PS_SAMPLER11_BORDER_BLUE 583 1.1 riastrad 0x0000A4C8 TD_PS_SAMPLER12_BORDER_BLUE 584 1.1 riastrad 0x0000A4D8 TD_PS_SAMPLER13_BORDER_BLUE 585 1.1 riastrad 0x0000A4E8 TD_PS_SAMPLER14_BORDER_BLUE 586 1.1 riastrad 0x0000A4F8 TD_PS_SAMPLER15_BORDER_BLUE 587 1.1 riastrad 0x0000A508 TD_PS_SAMPLER16_BORDER_BLUE 588 1.1 riastrad 0x0000A518 TD_PS_SAMPLER17_BORDER_BLUE 589 1.1 riastrad 0x0000A404 TD_PS_SAMPLER0_BORDER_GREEN 590 1.1 riastrad 0x0000A414 TD_PS_SAMPLER1_BORDER_GREEN 591 1.1 riastrad 0x0000A424 TD_PS_SAMPLER2_BORDER_GREEN 592 1.1 riastrad 0x0000A434 TD_PS_SAMPLER3_BORDER_GREEN 593 1.1 riastrad 0x0000A444 TD_PS_SAMPLER4_BORDER_GREEN 594 1.1 riastrad 0x0000A454 TD_PS_SAMPLER5_BORDER_GREEN 595 1.1 riastrad 0x0000A464 TD_PS_SAMPLER6_BORDER_GREEN 596 1.1 riastrad 0x0000A474 TD_PS_SAMPLER7_BORDER_GREEN 597 1.1 riastrad 0x0000A484 TD_PS_SAMPLER8_BORDER_GREEN 598 1.1 riastrad 0x0000A494 TD_PS_SAMPLER9_BORDER_GREEN 599 1.1 riastrad 0x0000A4A4 TD_PS_SAMPLER10_BORDER_GREEN 600 1.1 riastrad 0x0000A4B4 TD_PS_SAMPLER11_BORDER_GREEN 601 1.1 riastrad 0x0000A4C4 TD_PS_SAMPLER12_BORDER_GREEN 602 1.1 riastrad 0x0000A4D4 TD_PS_SAMPLER13_BORDER_GREEN 603 1.1 riastrad 0x0000A4E4 TD_PS_SAMPLER14_BORDER_GREEN 604 1.1 riastrad 0x0000A4F4 TD_PS_SAMPLER15_BORDER_GREEN 605 1.1 riastrad 0x0000A504 TD_PS_SAMPLER16_BORDER_GREEN 606 1.1 riastrad 0x0000A514 TD_PS_SAMPLER17_BORDER_GREEN 607 1.1 riastrad 0x0000A400 TD_PS_SAMPLER0_BORDER_RED 608 1.1 riastrad 0x0000A410 TD_PS_SAMPLER1_BORDER_RED 609 1.1 riastrad 0x0000A420 TD_PS_SAMPLER2_BORDER_RED 610 1.1 riastrad 0x0000A430 TD_PS_SAMPLER3_BORDER_RED 611 1.1 riastrad 0x0000A440 TD_PS_SAMPLER4_BORDER_RED 612 1.1 riastrad 0x0000A450 TD_PS_SAMPLER5_BORDER_RED 613 1.1 riastrad 0x0000A460 TD_PS_SAMPLER6_BORDER_RED 614 1.1 riastrad 0x0000A470 TD_PS_SAMPLER7_BORDER_RED 615 1.1 riastrad 0x0000A480 TD_PS_SAMPLER8_BORDER_RED 616 1.1 riastrad 0x0000A490 TD_PS_SAMPLER9_BORDER_RED 617 1.1 riastrad 0x0000A4A0 TD_PS_SAMPLER10_BORDER_RED 618 1.1 riastrad 0x0000A4B0 TD_PS_SAMPLER11_BORDER_RED 619 1.1 riastrad 0x0000A4C0 TD_PS_SAMPLER12_BORDER_RED 620 1.1 riastrad 0x0000A4D0 TD_PS_SAMPLER13_BORDER_RED 621 1.1 riastrad 0x0000A4E0 TD_PS_SAMPLER14_BORDER_RED 622 1.1 riastrad 0x0000A4F0 TD_PS_SAMPLER15_BORDER_RED 623 1.1 riastrad 0x0000A500 TD_PS_SAMPLER16_BORDER_RED 624 1.1 riastrad 0x0000A510 TD_PS_SAMPLER17_BORDER_RED 625 1.1 riastrad 0x0000AA00 TD_PS_SAMPLER0_CLEARTYPE_KERNEL 626 1.1 riastrad 0x0000AA04 TD_PS_SAMPLER1_CLEARTYPE_KERNEL 627 1.1 riastrad 0x0000AA08 TD_PS_SAMPLER2_CLEARTYPE_KERNEL 628 1.1 riastrad 0x0000AA0C TD_PS_SAMPLER3_CLEARTYPE_KERNEL 629 1.1 riastrad 0x0000AA10 TD_PS_SAMPLER4_CLEARTYPE_KERNEL 630 1.1 riastrad 0x0000AA14 TD_PS_SAMPLER5_CLEARTYPE_KERNEL 631 1.1 riastrad 0x0000AA18 TD_PS_SAMPLER6_CLEARTYPE_KERNEL 632 1.1 riastrad 0x0000AA1C TD_PS_SAMPLER7_CLEARTYPE_KERNEL 633 1.1 riastrad 0x0000AA20 TD_PS_SAMPLER8_CLEARTYPE_KERNEL 634 1.1 riastrad 0x0000AA24 TD_PS_SAMPLER9_CLEARTYPE_KERNEL 635 1.1 riastrad 0x0000AA28 TD_PS_SAMPLER10_CLEARTYPE_KERNEL 636 1.1 riastrad 0x0000AA2C TD_PS_SAMPLER11_CLEARTYPE_KERNEL 637 1.1 riastrad 0x0000AA30 TD_PS_SAMPLER12_CLEARTYPE_KERNEL 638 1.1 riastrad 0x0000AA34 TD_PS_SAMPLER13_CLEARTYPE_KERNEL 639 1.1 riastrad 0x0000AA38 TD_PS_SAMPLER14_CLEARTYPE_KERNEL 640 1.1 riastrad 0x0000AA3C TD_PS_SAMPLER15_CLEARTYPE_KERNEL 641 1.1 riastrad 0x0000AA40 TD_PS_SAMPLER16_CLEARTYPE_KERNEL 642 1.1 riastrad 0x0000AA44 TD_PS_SAMPLER17_CLEARTYPE_KERNEL 643 1.1 riastrad 0x0000A60C TD_VS_SAMPLER0_BORDER_ALPHA 644 1.1 riastrad 0x0000A61C TD_VS_SAMPLER1_BORDER_ALPHA 645 1.1 riastrad 0x0000A62C TD_VS_SAMPLER2_BORDER_ALPHA 646 1.1 riastrad 0x0000A63C TD_VS_SAMPLER3_BORDER_ALPHA 647 1.1 riastrad 0x0000A64C TD_VS_SAMPLER4_BORDER_ALPHA 648 1.1 riastrad 0x0000A65C TD_VS_SAMPLER5_BORDER_ALPHA 649 1.1 riastrad 0x0000A66C TD_VS_SAMPLER6_BORDER_ALPHA 650 1.1 riastrad 0x0000A67C TD_VS_SAMPLER7_BORDER_ALPHA 651 1.1 riastrad 0x0000A68C TD_VS_SAMPLER8_BORDER_ALPHA 652 1.1 riastrad 0x0000A69C TD_VS_SAMPLER9_BORDER_ALPHA 653 1.1 riastrad 0x0000A6AC TD_VS_SAMPLER10_BORDER_ALPHA 654 1.1 riastrad 0x0000A6BC TD_VS_SAMPLER11_BORDER_ALPHA 655 1.1 riastrad 0x0000A6CC TD_VS_SAMPLER12_BORDER_ALPHA 656 1.1 riastrad 0x0000A6DC TD_VS_SAMPLER13_BORDER_ALPHA 657 1.1 riastrad 0x0000A6EC TD_VS_SAMPLER14_BORDER_ALPHA 658 1.1 riastrad 0x0000A6FC TD_VS_SAMPLER15_BORDER_ALPHA 659 1.1 riastrad 0x0000A70C TD_VS_SAMPLER16_BORDER_ALPHA 660 1.1 riastrad 0x0000A71C TD_VS_SAMPLER17_BORDER_ALPHA 661 1.1 riastrad 0x0000A608 TD_VS_SAMPLER0_BORDER_BLUE 662 1.1 riastrad 0x0000A618 TD_VS_SAMPLER1_BORDER_BLUE 663 1.1 riastrad 0x0000A628 TD_VS_SAMPLER2_BORDER_BLUE 664 1.1 riastrad 0x0000A638 TD_VS_SAMPLER3_BORDER_BLUE 665 1.1 riastrad 0x0000A648 TD_VS_SAMPLER4_BORDER_BLUE 666 1.1 riastrad 0x0000A658 TD_VS_SAMPLER5_BORDER_BLUE 667 1.1 riastrad 0x0000A668 TD_VS_SAMPLER6_BORDER_BLUE 668 1.1 riastrad 0x0000A678 TD_VS_SAMPLER7_BORDER_BLUE 669 1.1 riastrad 0x0000A688 TD_VS_SAMPLER8_BORDER_BLUE 670 1.1 riastrad 0x0000A698 TD_VS_SAMPLER9_BORDER_BLUE 671 1.1 riastrad 0x0000A6A8 TD_VS_SAMPLER10_BORDER_BLUE 672 1.1 riastrad 0x0000A6B8 TD_VS_SAMPLER11_BORDER_BLUE 673 1.1 riastrad 0x0000A6C8 TD_VS_SAMPLER12_BORDER_BLUE 674 1.1 riastrad 0x0000A6D8 TD_VS_SAMPLER13_BORDER_BLUE 675 1.1 riastrad 0x0000A6E8 TD_VS_SAMPLER14_BORDER_BLUE 676 1.1 riastrad 0x0000A6F8 TD_VS_SAMPLER15_BORDER_BLUE 677 1.1 riastrad 0x0000A708 TD_VS_SAMPLER16_BORDER_BLUE 678 1.1 riastrad 0x0000A718 TD_VS_SAMPLER17_BORDER_BLUE 679 1.1 riastrad 0x0000A604 TD_VS_SAMPLER0_BORDER_GREEN 680 1.1 riastrad 0x0000A614 TD_VS_SAMPLER1_BORDER_GREEN 681 1.1 riastrad 0x0000A624 TD_VS_SAMPLER2_BORDER_GREEN 682 1.1 riastrad 0x0000A634 TD_VS_SAMPLER3_BORDER_GREEN 683 1.1 riastrad 0x0000A644 TD_VS_SAMPLER4_BORDER_GREEN 684 1.1 riastrad 0x0000A654 TD_VS_SAMPLER5_BORDER_GREEN 685 1.1 riastrad 0x0000A664 TD_VS_SAMPLER6_BORDER_GREEN 686 1.1 riastrad 0x0000A674 TD_VS_SAMPLER7_BORDER_GREEN 687 1.1 riastrad 0x0000A684 TD_VS_SAMPLER8_BORDER_GREEN 688 1.1 riastrad 0x0000A694 TD_VS_SAMPLER9_BORDER_GREEN 689 1.1 riastrad 0x0000A6A4 TD_VS_SAMPLER10_BORDER_GREEN 690 1.1 riastrad 0x0000A6B4 TD_VS_SAMPLER11_BORDER_GREEN 691 1.1 riastrad 0x0000A6C4 TD_VS_SAMPLER12_BORDER_GREEN 692 1.1 riastrad 0x0000A6D4 TD_VS_SAMPLER13_BORDER_GREEN 693 1.1 riastrad 0x0000A6E4 TD_VS_SAMPLER14_BORDER_GREEN 694 1.1 riastrad 0x0000A6F4 TD_VS_SAMPLER15_BORDER_GREEN 695 1.1 riastrad 0x0000A704 TD_VS_SAMPLER16_BORDER_GREEN 696 1.1 riastrad 0x0000A714 TD_VS_SAMPLER17_BORDER_GREEN 697 1.1 riastrad 0x0000A600 TD_VS_SAMPLER0_BORDER_RED 698 1.1 riastrad 0x0000A610 TD_VS_SAMPLER1_BORDER_RED 699 1.1 riastrad 0x0000A620 TD_VS_SAMPLER2_BORDER_RED 700 1.1 riastrad 0x0000A630 TD_VS_SAMPLER3_BORDER_RED 701 1.1 riastrad 0x0000A640 TD_VS_SAMPLER4_BORDER_RED 702 1.1 riastrad 0x0000A650 TD_VS_SAMPLER5_BORDER_RED 703 1.1 riastrad 0x0000A660 TD_VS_SAMPLER6_BORDER_RED 704 1.1 riastrad 0x0000A670 TD_VS_SAMPLER7_BORDER_RED 705 1.1 riastrad 0x0000A680 TD_VS_SAMPLER8_BORDER_RED 706 1.1 riastrad 0x0000A690 TD_VS_SAMPLER9_BORDER_RED 707 1.1 riastrad 0x0000A6A0 TD_VS_SAMPLER10_BORDER_RED 708 1.1 riastrad 0x0000A6B0 TD_VS_SAMPLER11_BORDER_RED 709 1.1 riastrad 0x0000A6C0 TD_VS_SAMPLER12_BORDER_RED 710 1.1 riastrad 0x0000A6D0 TD_VS_SAMPLER13_BORDER_RED 711 1.1 riastrad 0x0000A6E0 TD_VS_SAMPLER14_BORDER_RED 712 1.1 riastrad 0x0000A6F0 TD_VS_SAMPLER15_BORDER_RED 713 1.1 riastrad 0x0000A700 TD_VS_SAMPLER16_BORDER_RED 714 1.1 riastrad 0x0000A710 TD_VS_SAMPLER17_BORDER_RED 715 1.1 riastrad 0x00009508 TA_CNTL_AUX 716 1.1 riastrad 0x0002802C DB_DEPTH_CLEAR 717 1.1 riastrad 0x00028D34 DB_PREFETCH_LIMIT 718 1.1 riastrad 0x00028D30 DB_PRELOAD_CONTROL 719 1.1 riastrad 0x00028D0C DB_RENDER_CONTROL 720 1.1 riastrad 0x00028D10 DB_RENDER_OVERRIDE 721 1.1 riastrad 0x0002880C DB_SHADER_CONTROL 722 1.1 riastrad 0x00028D28 DB_SRESULTS_COMPARE_STATE0 723 1.1 riastrad 0x00028D2C DB_SRESULTS_COMPARE_STATE1 724 1.1 riastrad 0x00028430 DB_STENCILREFMASK 725 1.1 riastrad 0x00028434 DB_STENCILREFMASK_BF 726 1.1 riastrad 0x00028028 DB_STENCIL_CLEAR 727 1.1 riastrad 0x00028780 CB_BLEND0_CONTROL 728 1.1 riastrad 0x00028784 CB_BLEND1_CONTROL 729 1.1 riastrad 0x00028788 CB_BLEND2_CONTROL 730 1.1 riastrad 0x0002878C CB_BLEND3_CONTROL 731 1.1 riastrad 0x00028790 CB_BLEND4_CONTROL 732 1.1 riastrad 0x00028794 CB_BLEND5_CONTROL 733 1.1 riastrad 0x00028798 CB_BLEND6_CONTROL 734 1.1 riastrad 0x0002879C CB_BLEND7_CONTROL 735 1.1 riastrad 0x00028804 CB_BLEND_CONTROL 736 1.1 riastrad 0x00028420 CB_BLEND_ALPHA 737 1.1 riastrad 0x0002841C CB_BLEND_BLUE 738 1.1 riastrad 0x00028418 CB_BLEND_GREEN 739 1.1 riastrad 0x00028414 CB_BLEND_RED 740 1.1 riastrad 0x0002812C CB_CLEAR_ALPHA 741 1.1 riastrad 0x00028128 CB_CLEAR_BLUE 742 1.1 riastrad 0x00028124 CB_CLEAR_GREEN 743 1.1 riastrad 0x00028120 CB_CLEAR_RED 744 1.1 riastrad 0x00028C30 CB_CLRCMP_CONTROL 745 1.1 riastrad 0x00028C38 CB_CLRCMP_DST 746 1.1 riastrad 0x00028C3C CB_CLRCMP_MSK 747 1.1 riastrad 0x00028C34 CB_CLRCMP_SRC 748 1.1 riastrad 0x0002842C CB_FOG_BLUE 749 1.1 riastrad 0x00028428 CB_FOG_GREEN 750 1.1 riastrad 0x00028424 CB_FOG_RED 751 1.1 riastrad 0x00008040 WAIT_UNTIL 752 1.1 riastrad 0x00009714 VC_ENHANCE 753 1.1 riastrad 0x00009830 DB_DEBUG 754 1.1 riastrad 0x00009838 DB_WATERMARKS 755 1.1 riastrad 0x00028D44 DB_ALPHA_TO_MASK 756 1.1 riastrad 0x00009700 VC_CNTL 757
Indexes created Tue Sep 30 11:09:46 GMT 2025