Home | History | Annotate | Line # | Download | only in radeon
rv6xx_dpm.h revision 1.1.1.1.30.1 
      1 /*	$NetBSD: rv6xx_dpm.h,v 1.1.1.1.30.1 2018/09/06 06:56:33 pgoyette Exp $	*/
      2 
      3 /*
      4  * Copyright 2011 Advanced Micro Devices, Inc.
      5  *
      6  * Permission is hereby granted, free of charge, to any person obtaining a
      7  * copy of this software and associated documentation files (the "Software"),
      8  * to deal in the Software without restriction, including without limitation
      9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
     10  * and/or sell copies of the Software, and to permit persons to whom the
     11  * Software is furnished to do so, subject to the following conditions:
     12  *
     13  * The above copyright notice and this permission notice shall be included in
     14  * all copies or substantial portions of the Software.
     15  *
     16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     22  * OTHER DEALINGS IN THE SOFTWARE.
     23  *
     24  * Authors: Alex Deucher
     25  */
     26 
     27 #ifndef __RV6XX_DPM_H__
     28 #define __RV6XX_DPM_H__
     29 
     30 #include "r600_dpm.h"
     31 
     32 /* Represents a single SCLK step. */
     33 struct rv6xx_sclk_stepping
     34 {
     35     u32 vco_frequency;
     36     u32 post_divider;
     37 };
     38 
     39 struct rv6xx_pm_hw_state {
     40 	u32 sclks[R600_PM_NUMBER_OF_ACTIVITY_LEVELS];
     41 	u32 mclks[R600_PM_NUMBER_OF_MCLKS];
     42 	u16 vddc[R600_PM_NUMBER_OF_VOLTAGE_LEVELS];
     43 	bool backbias[R600_PM_NUMBER_OF_VOLTAGE_LEVELS];
     44 	bool pcie_gen2[R600_PM_NUMBER_OF_ACTIVITY_LEVELS];
     45 	u8 high_sclk_index;
     46 	u8 medium_sclk_index;
     47 	u8 low_sclk_index;
     48 	u8 high_mclk_index;
     49 	u8 medium_mclk_index;
     50 	u8 low_mclk_index;
     51 	u8 high_vddc_index;
     52 	u8 medium_vddc_index;
     53 	u8 low_vddc_index;
     54 	u8 rp[R600_PM_NUMBER_OF_ACTIVITY_LEVELS];
     55 	u8 lp[R600_PM_NUMBER_OF_ACTIVITY_LEVELS];
     56 };
     57 
     58 struct rv6xx_power_info {
     59 	/* flags */
     60 	bool voltage_control;
     61 	bool sclk_ss;
     62 	bool mclk_ss;
     63 	bool dynamic_ss;
     64 	bool dynamic_pcie_gen2;
     65 	bool thermal_protection;
     66 	bool display_gap;
     67 	bool gfx_clock_gating;
     68 	/* clk values */
     69 	u32 fb_div_scale;
     70 	u32 spll_ref_div;
     71 	u32 mpll_ref_div;
     72 	u32 bsu;
     73 	u32 bsp;
     74 	/* */
     75 	u32 active_auto_throttle_sources;
     76 	/* current power state */
     77 	u32 restricted_levels;
     78 	struct rv6xx_pm_hw_state hw;
     79 };
     80 
     81 struct rv6xx_pl {
     82 	u32 sclk;
     83 	u32 mclk;
     84 	u16 vddc;
     85 	u32 flags;
     86 };
     87 
     88 struct rv6xx_ps {
     89 	struct rv6xx_pl high;
     90 	struct rv6xx_pl medium;
     91 	struct rv6xx_pl low;
     92 };
     93 
     94 #define RV6XX_DEFAULT_VCLK_FREQ  40000 /* 10 khz */
     95 #define RV6XX_DEFAULT_DCLK_FREQ  30000 /* 10 khz */
     96 
     97 #endif
     98