rv770_dpm.h revision 1.2
1 /* $NetBSD: rv770_dpm.h,v 1.2 2018/08/27 04:58:36 riastradh Exp $ */ 2 3 /* 4 * Copyright 2011 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 #ifndef __RV770_DPM_H__ 26 #define __RV770_DPM_H__ 27 28 #include "rv770_smc.h" 29 30 struct rv770_clock_registers { 31 u32 cg_spll_func_cntl; 32 u32 cg_spll_func_cntl_2; 33 u32 cg_spll_func_cntl_3; 34 u32 cg_spll_spread_spectrum; 35 u32 cg_spll_spread_spectrum_2; 36 u32 mpll_ad_func_cntl; 37 u32 mpll_ad_func_cntl_2; 38 u32 mpll_dq_func_cntl; 39 u32 mpll_dq_func_cntl_2; 40 u32 mclk_pwrmgt_cntl; 41 u32 dll_cntl; 42 u32 mpll_ss1; 43 u32 mpll_ss2; 44 }; 45 46 struct rv730_clock_registers { 47 u32 cg_spll_func_cntl; 48 u32 cg_spll_func_cntl_2; 49 u32 cg_spll_func_cntl_3; 50 u32 cg_spll_spread_spectrum; 51 u32 cg_spll_spread_spectrum_2; 52 u32 mclk_pwrmgt_cntl; 53 u32 dll_cntl; 54 u32 mpll_func_cntl; 55 u32 mpll_func_cntl2; 56 u32 mpll_func_cntl3; 57 u32 mpll_ss; 58 u32 mpll_ss2; 59 }; 60 61 union r7xx_clock_registers { 62 struct rv770_clock_registers rv770; 63 struct rv730_clock_registers rv730; 64 }; 65 66 struct vddc_table_entry { 67 u16 vddc; 68 u8 vddc_index; 69 u8 high_smio; 70 u32 low_smio; 71 }; 72 73 #define MAX_NO_OF_MVDD_VALUES 2 74 #define MAX_NO_VREG_STEPS 32 75 76 struct rv7xx_power_info { 77 /* flags */ 78 bool mem_gddr5; 79 bool pcie_gen2; 80 bool dynamic_pcie_gen2; 81 bool acpi_pcie_gen2; 82 bool boot_in_gen2; 83 bool voltage_control; /* vddc */ 84 bool mvdd_control; 85 bool sclk_ss; 86 bool mclk_ss; 87 bool dynamic_ss; 88 bool gfx_clock_gating; 89 bool mg_clock_gating; 90 bool mgcgtssm; 91 bool power_gating; 92 bool thermal_protection; 93 bool display_gap; 94 bool dcodt; 95 bool ulps; 96 /* registers */ 97 union r7xx_clock_registers clk_regs; 98 u32 s0_vid_lower_smio_cntl; 99 /* voltage */ 100 u32 vddc_mask_low; 101 u32 mvdd_mask_low; 102 u32 mvdd_split_frequency; 103 u32 mvdd_low_smio[MAX_NO_OF_MVDD_VALUES]; 104 u16 max_vddc; 105 u16 max_vddc_in_table; 106 u16 min_vddc_in_table; 107 struct vddc_table_entry vddc_table[MAX_NO_VREG_STEPS]; 108 u8 valid_vddc_entries; 109 /* dc odt */ 110 u32 mclk_odt_threshold; 111 u8 odt_value_0[2]; 112 u8 odt_value_1[2]; 113 /* stored values */ 114 u32 boot_sclk; 115 u16 acpi_vddc; 116 u32 ref_div; 117 u32 active_auto_throttle_sources; 118 u32 mclk_stutter_mode_threshold; 119 u32 mclk_strobe_mode_threshold; 120 u32 mclk_edc_enable_threshold; 121 u32 bsp; 122 u32 bsu; 123 u32 pbsp; 124 u32 pbsu; 125 u32 dsp; 126 u32 psp; 127 u32 asi; 128 u32 pasi; 129 u32 vrc; 130 u32 restricted_levels; 131 u32 rlp; 132 u32 rmp; 133 u32 lhp; 134 u32 lmp; 135 /* smc offsets */ 136 u16 state_table_start; 137 u16 soft_regs_start; 138 u16 sram_end; 139 /* scratch structs */ 140 RV770_SMC_STATETABLE smc_statetable; 141 }; 142 143 struct rv7xx_pl { 144 u32 sclk; 145 u32 mclk; 146 u16 vddc; 147 u16 vddci; /* eg+ only */ 148 u32 flags; 149 enum radeon_pcie_gen pcie_gen; /* si+ only */ 150 }; 151 152 struct rv7xx_ps { 153 struct rv7xx_pl high; 154 struct rv7xx_pl medium; 155 struct rv7xx_pl low; 156 bool dc_compatible; 157 }; 158 159 #define RV770_RLP_DFLT 10 160 #define RV770_RMP_DFLT 25 161 #define RV770_LHP_DFLT 25 162 #define RV770_LMP_DFLT 10 163 #define RV770_VRC_DFLT 0x003f 164 #define RV770_ASI_DFLT 1000 165 #define RV770_HASI_DFLT 200000 166 #define RV770_MGCGTTLOCAL0_DFLT 0x00100000 167 #define RV7XX_MGCGTTLOCAL0_DFLT 0 168 #define RV770_MGCGTTLOCAL1_DFLT 0xFFFF0000 169 #define RV770_MGCGCGTSSMCTRL_DFLT 0x55940000 170 171 #define MVDD_LOW_INDEX 0 172 #define MVDD_HIGH_INDEX 1 173 174 #define MVDD_LOW_VALUE 0 175 #define MVDD_HIGH_VALUE 0xffff 176 177 #define RV770_DEFAULT_VCLK_FREQ 53300 /* 10 khz */ 178 #define RV770_DEFAULT_DCLK_FREQ 40000 /* 10 khz */ 179 180 /* rv730/rv710 */ 181 int rv730_populate_sclk_value(struct radeon_device *rdev, 182 u32 engine_clock, 183 RV770_SMC_SCLK_VALUE *sclk); 184 int rv730_populate_mclk_value(struct radeon_device *rdev, 185 u32 engine_clock, u32 memory_clock, 186 LPRV7XX_SMC_MCLK_VALUE mclk); 187 void rv730_read_clock_registers(struct radeon_device *rdev); 188 int rv730_populate_smc_acpi_state(struct radeon_device *rdev, 189 RV770_SMC_STATETABLE *table); 190 int rv730_populate_smc_initial_state(struct radeon_device *rdev, 191 struct radeon_ps *radeon_initial_state, 192 RV770_SMC_STATETABLE *table); 193 void rv730_program_memory_timing_parameters(struct radeon_device *rdev, 194 struct radeon_ps *radeon_state); 195 void rv730_power_gating_enable(struct radeon_device *rdev, 196 bool enable); 197 void rv730_start_dpm(struct radeon_device *rdev); 198 void rv730_stop_dpm(struct radeon_device *rdev); 199 void rv730_program_dcodt(struct radeon_device *rdev, bool use_dcodt); 200 void rv730_get_odt_values(struct radeon_device *rdev); 201 202 /* rv740 */ 203 int rv740_populate_sclk_value(struct radeon_device *rdev, u32 engine_clock, 204 RV770_SMC_SCLK_VALUE *sclk); 205 int rv740_populate_mclk_value(struct radeon_device *rdev, 206 u32 engine_clock, u32 memory_clock, 207 RV7XX_SMC_MCLK_VALUE *mclk); 208 void rv740_read_clock_registers(struct radeon_device *rdev); 209 int rv740_populate_smc_acpi_state(struct radeon_device *rdev, 210 RV770_SMC_STATETABLE *table); 211 void rv740_enable_mclk_spread_spectrum(struct radeon_device *rdev, 212 bool enable); 213 u8 rv740_get_mclk_frequency_ratio(u32 memory_clock); 214 u32 rv740_get_dll_speed(bool is_gddr5, u32 memory_clock); 215 u32 rv740_get_decoded_reference_divider(u32 encoded_ref); 216 217 /* rv770 */ 218 u32 rv770_map_clkf_to_ibias(struct radeon_device *rdev, u32 clkf); 219 int rv770_populate_vddc_value(struct radeon_device *rdev, u16 vddc, 220 RV770_SMC_VOLTAGE_VALUE *voltage); 221 int rv770_populate_mvdd_value(struct radeon_device *rdev, u32 mclk, 222 RV770_SMC_VOLTAGE_VALUE *voltage); 223 u8 rv770_get_seq_value(struct radeon_device *rdev, 224 struct rv7xx_pl *pl); 225 int rv770_populate_initial_mvdd_value(struct radeon_device *rdev, 226 RV770_SMC_VOLTAGE_VALUE *voltage); 227 u32 rv770_calculate_memory_refresh_rate(struct radeon_device *rdev, 228 u32 engine_clock); 229 void rv770_program_response_times(struct radeon_device *rdev); 230 int rv770_populate_smc_sp(struct radeon_device *rdev, 231 struct radeon_ps *radeon_state, 232 RV770_SMC_SWSTATE *smc_state); 233 int rv770_populate_smc_t(struct radeon_device *rdev, 234 struct radeon_ps *radeon_state, 235 RV770_SMC_SWSTATE *smc_state); 236 void rv770_read_voltage_smio_registers(struct radeon_device *rdev); 237 void rv770_get_memory_type(struct radeon_device *rdev); 238 void r7xx_start_smc(struct radeon_device *rdev); 239 u8 rv770_get_memory_module_index(struct radeon_device *rdev); 240 void rv770_get_max_vddc(struct radeon_device *rdev); 241 void rv770_get_pcie_gen2_status(struct radeon_device *rdev); 242 void rv770_enable_acpi_pm(struct radeon_device *rdev); 243 void rv770_restore_cgcg(struct radeon_device *rdev); 244 bool rv770_dpm_enabled(struct radeon_device *rdev); 245 void rv770_enable_voltage_control(struct radeon_device *rdev, 246 bool enable); 247 void rv770_enable_backbias(struct radeon_device *rdev, 248 bool enable); 249 void rv770_enable_thermal_protection(struct radeon_device *rdev, 250 bool enable); 251 void rv770_enable_auto_throttle_source(struct radeon_device *rdev, 252 enum radeon_dpm_auto_throttle_src source, 253 bool enable); 254 void rv770_setup_bsp(struct radeon_device *rdev); 255 void rv770_program_git(struct radeon_device *rdev); 256 void rv770_program_tp(struct radeon_device *rdev); 257 void rv770_program_tpp(struct radeon_device *rdev); 258 void rv770_program_sstp(struct radeon_device *rdev); 259 void rv770_program_engine_speed_parameters(struct radeon_device *rdev); 260 void rv770_program_vc(struct radeon_device *rdev); 261 void rv770_clear_vc(struct radeon_device *rdev); 262 int rv770_upload_firmware(struct radeon_device *rdev); 263 void rv770_stop_dpm(struct radeon_device *rdev); 264 void r7xx_stop_smc(struct radeon_device *rdev); 265 void rv770_reset_smio_status(struct radeon_device *rdev); 266 int rv770_restrict_performance_levels_before_switch(struct radeon_device *rdev); 267 int rv770_dpm_force_performance_level(struct radeon_device *rdev, 268 enum radeon_dpm_forced_level level); 269 int rv770_halt_smc(struct radeon_device *rdev); 270 int rv770_resume_smc(struct radeon_device *rdev); 271 int rv770_set_sw_state(struct radeon_device *rdev); 272 int rv770_set_boot_state(struct radeon_device *rdev); 273 int rv7xx_parse_power_table(struct radeon_device *rdev); 274 void rv770_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev, 275 struct radeon_ps *new_ps, 276 struct radeon_ps *old_ps); 277 void rv770_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev, 278 struct radeon_ps *new_ps, 279 struct radeon_ps *old_ps); 280 void rv770_get_engine_memory_ss(struct radeon_device *rdev); 281 282 /* smc */ 283 int rv770_write_smc_soft_register(struct radeon_device *rdev, 284 u16 reg_offset, u32 value); 285 286 #endif 287
Indexes created Mon Oct 20 11:09:49 GMT 2025