smu7_discrete.h revision 1.1.1.2
1 /* $NetBSD: smu7_discrete.h,v 1.1.1.2 2018/08/27 01:34:59 riastradh Exp $ */ 2 3 /* 4 * Copyright 2013 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 26 #ifndef SMU7_DISCRETE_H 27 #define SMU7_DISCRETE_H 28 29 #include "smu7.h" 30 31 #pragma pack(push, 1) 32 33 #define SMU7_DTE_ITERATIONS 5 34 #define SMU7_DTE_SOURCES 3 35 #define SMU7_DTE_SINKS 1 36 #define SMU7_NUM_CPU_TES 0 37 #define SMU7_NUM_GPU_TES 1 38 #define SMU7_NUM_NON_TES 2 39 40 struct SMU7_SoftRegisters 41 { 42 uint32_t RefClockFrequency; 43 uint32_t PmTimerP; 44 uint32_t FeatureEnables; 45 uint32_t PreVBlankGap; 46 uint32_t VBlankTimeout; 47 uint32_t TrainTimeGap; 48 49 uint32_t MvddSwitchTime; 50 uint32_t LongestAcpiTrainTime; 51 uint32_t AcpiDelay; 52 uint32_t G5TrainTime; 53 uint32_t DelayMpllPwron; 54 uint32_t VoltageChangeTimeout; 55 uint32_t HandshakeDisables; 56 57 uint8_t DisplayPhy1Config; 58 uint8_t DisplayPhy2Config; 59 uint8_t DisplayPhy3Config; 60 uint8_t DisplayPhy4Config; 61 62 uint8_t DisplayPhy5Config; 63 uint8_t DisplayPhy6Config; 64 uint8_t DisplayPhy7Config; 65 uint8_t DisplayPhy8Config; 66 67 uint32_t AverageGraphicsA; 68 uint32_t AverageMemoryA; 69 uint32_t AverageGioA; 70 71 uint8_t SClkDpmEnabledLevels; 72 uint8_t MClkDpmEnabledLevels; 73 uint8_t LClkDpmEnabledLevels; 74 uint8_t PCIeDpmEnabledLevels; 75 76 uint8_t UVDDpmEnabledLevels; 77 uint8_t SAMUDpmEnabledLevels; 78 uint8_t ACPDpmEnabledLevels; 79 uint8_t VCEDpmEnabledLevels; 80 81 uint32_t DRAM_LOG_ADDR_H; 82 uint32_t DRAM_LOG_ADDR_L; 83 uint32_t DRAM_LOG_PHY_ADDR_H; 84 uint32_t DRAM_LOG_PHY_ADDR_L; 85 uint32_t DRAM_LOG_BUFF_SIZE; 86 uint32_t UlvEnterC; 87 uint32_t UlvTime; 88 uint32_t Reserved[3]; 89 90 }; 91 92 typedef struct SMU7_SoftRegisters SMU7_SoftRegisters; 93 94 struct SMU7_Discrete_VoltageLevel 95 { 96 uint16_t Voltage; 97 uint16_t StdVoltageHiSidd; 98 uint16_t StdVoltageLoSidd; 99 uint8_t Smio; 100 uint8_t padding; 101 }; 102 103 typedef struct SMU7_Discrete_VoltageLevel SMU7_Discrete_VoltageLevel; 104 105 struct SMU7_Discrete_GraphicsLevel 106 { 107 uint32_t Flags; 108 uint32_t MinVddc; 109 uint32_t MinVddcPhases; 110 111 uint32_t SclkFrequency; 112 113 uint8_t padding1[2]; 114 uint16_t ActivityLevel; 115 116 uint32_t CgSpllFuncCntl3; 117 uint32_t CgSpllFuncCntl4; 118 uint32_t SpllSpreadSpectrum; 119 uint32_t SpllSpreadSpectrum2; 120 uint32_t CcPwrDynRm; 121 uint32_t CcPwrDynRm1; 122 uint8_t SclkDid; 123 uint8_t DisplayWatermark; 124 uint8_t EnabledForActivity; 125 uint8_t EnabledForThrottle; 126 uint8_t UpH; 127 uint8_t DownH; 128 uint8_t VoltageDownH; 129 uint8_t PowerThrottle; 130 uint8_t DeepSleepDivId; 131 uint8_t padding[3]; 132 }; 133 134 typedef struct SMU7_Discrete_GraphicsLevel SMU7_Discrete_GraphicsLevel; 135 136 struct SMU7_Discrete_ACPILevel 137 { 138 uint32_t Flags; 139 uint32_t MinVddc; 140 uint32_t MinVddcPhases; 141 uint32_t SclkFrequency; 142 uint8_t SclkDid; 143 uint8_t DisplayWatermark; 144 uint8_t DeepSleepDivId; 145 uint8_t padding; 146 uint32_t CgSpllFuncCntl; 147 uint32_t CgSpllFuncCntl2; 148 uint32_t CgSpllFuncCntl3; 149 uint32_t CgSpllFuncCntl4; 150 uint32_t SpllSpreadSpectrum; 151 uint32_t SpllSpreadSpectrum2; 152 uint32_t CcPwrDynRm; 153 uint32_t CcPwrDynRm1; 154 }; 155 156 typedef struct SMU7_Discrete_ACPILevel SMU7_Discrete_ACPILevel; 157 158 struct SMU7_Discrete_Ulv 159 { 160 uint32_t CcPwrDynRm; 161 uint32_t CcPwrDynRm1; 162 uint16_t VddcOffset; 163 uint8_t VddcOffsetVid; 164 uint8_t VddcPhase; 165 uint32_t Reserved; 166 }; 167 168 typedef struct SMU7_Discrete_Ulv SMU7_Discrete_Ulv; 169 170 struct SMU7_Discrete_MemoryLevel 171 { 172 uint32_t MinVddc; 173 uint32_t MinVddcPhases; 174 uint32_t MinVddci; 175 uint32_t MinMvdd; 176 177 uint32_t MclkFrequency; 178 179 uint8_t EdcReadEnable; 180 uint8_t EdcWriteEnable; 181 uint8_t RttEnable; 182 uint8_t StutterEnable; 183 184 uint8_t StrobeEnable; 185 uint8_t StrobeRatio; 186 uint8_t EnabledForThrottle; 187 uint8_t EnabledForActivity; 188 189 uint8_t UpH; 190 uint8_t DownH; 191 uint8_t VoltageDownH; 192 uint8_t padding; 193 194 uint16_t ActivityLevel; 195 uint8_t DisplayWatermark; 196 uint8_t padding1; 197 198 uint32_t MpllFuncCntl; 199 uint32_t MpllFuncCntl_1; 200 uint32_t MpllFuncCntl_2; 201 uint32_t MpllAdFuncCntl; 202 uint32_t MpllDqFuncCntl; 203 uint32_t MclkPwrmgtCntl; 204 uint32_t DllCntl; 205 uint32_t MpllSs1; 206 uint32_t MpllSs2; 207 }; 208 209 typedef struct SMU7_Discrete_MemoryLevel SMU7_Discrete_MemoryLevel; 210 211 struct SMU7_Discrete_LinkLevel 212 { 213 uint8_t PcieGenSpeed; 214 uint8_t PcieLaneCount; 215 uint8_t EnabledForActivity; 216 uint8_t Padding; 217 uint32_t DownT; 218 uint32_t UpT; 219 uint32_t Reserved; 220 }; 221 222 typedef struct SMU7_Discrete_LinkLevel SMU7_Discrete_LinkLevel; 223 224 225 struct SMU7_Discrete_MCArbDramTimingTableEntry 226 { 227 uint32_t McArbDramTiming; 228 uint32_t McArbDramTiming2; 229 uint8_t McArbBurstTime; 230 uint8_t padding[3]; 231 }; 232 233 typedef struct SMU7_Discrete_MCArbDramTimingTableEntry SMU7_Discrete_MCArbDramTimingTableEntry; 234 235 struct SMU7_Discrete_MCArbDramTimingTable 236 { 237 SMU7_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS]; 238 }; 239 240 typedef struct SMU7_Discrete_MCArbDramTimingTable SMU7_Discrete_MCArbDramTimingTable; 241 242 struct SMU7_Discrete_UvdLevel 243 { 244 uint32_t VclkFrequency; 245 uint32_t DclkFrequency; 246 uint16_t MinVddc; 247 uint8_t MinVddcPhases; 248 uint8_t VclkDivider; 249 uint8_t DclkDivider; 250 uint8_t padding[3]; 251 }; 252 253 typedef struct SMU7_Discrete_UvdLevel SMU7_Discrete_UvdLevel; 254 255 struct SMU7_Discrete_ExtClkLevel 256 { 257 uint32_t Frequency; 258 uint16_t MinVoltage; 259 uint8_t MinPhases; 260 uint8_t Divider; 261 }; 262 263 typedef struct SMU7_Discrete_ExtClkLevel SMU7_Discrete_ExtClkLevel; 264 265 struct SMU7_Discrete_StateInfo 266 { 267 uint32_t SclkFrequency; 268 uint32_t MclkFrequency; 269 uint32_t VclkFrequency; 270 uint32_t DclkFrequency; 271 uint32_t SamclkFrequency; 272 uint32_t AclkFrequency; 273 uint32_t EclkFrequency; 274 uint16_t MvddVoltage; 275 uint16_t padding16; 276 uint8_t DisplayWatermark; 277 uint8_t McArbIndex; 278 uint8_t McRegIndex; 279 uint8_t SeqIndex; 280 uint8_t SclkDid; 281 int8_t SclkIndex; 282 int8_t MclkIndex; 283 uint8_t PCIeGen; 284 285 }; 286 287 typedef struct SMU7_Discrete_StateInfo SMU7_Discrete_StateInfo; 288 289 290 struct SMU7_Discrete_DpmTable 291 { 292 SMU7_PIDController GraphicsPIDController; 293 SMU7_PIDController MemoryPIDController; 294 SMU7_PIDController LinkPIDController; 295 296 uint32_t SystemFlags; 297 298 299 uint32_t SmioMaskVddcVid; 300 uint32_t SmioMaskVddcPhase; 301 uint32_t SmioMaskVddciVid; 302 uint32_t SmioMaskMvddVid; 303 304 uint32_t VddcLevelCount; 305 uint32_t VddciLevelCount; 306 uint32_t MvddLevelCount; 307 308 SMU7_Discrete_VoltageLevel VddcLevel [SMU7_MAX_LEVELS_VDDC]; 309 // SMU7_Discrete_VoltageLevel VddcStandardReference [SMU7_MAX_LEVELS_VDDC]; 310 SMU7_Discrete_VoltageLevel VddciLevel [SMU7_MAX_LEVELS_VDDCI]; 311 SMU7_Discrete_VoltageLevel MvddLevel [SMU7_MAX_LEVELS_MVDD]; 312 313 uint8_t GraphicsDpmLevelCount; 314 uint8_t MemoryDpmLevelCount; 315 uint8_t LinkLevelCount; 316 uint8_t UvdLevelCount; 317 uint8_t VceLevelCount; 318 uint8_t AcpLevelCount; 319 uint8_t SamuLevelCount; 320 uint8_t MasterDeepSleepControl; 321 uint32_t Reserved[5]; 322 // uint32_t SamuDefaultLevel; 323 324 SMU7_Discrete_GraphicsLevel GraphicsLevel [SMU7_MAX_LEVELS_GRAPHICS]; 325 SMU7_Discrete_MemoryLevel MemoryACPILevel; 326 SMU7_Discrete_MemoryLevel MemoryLevel [SMU7_MAX_LEVELS_MEMORY]; 327 SMU7_Discrete_LinkLevel LinkLevel [SMU7_MAX_LEVELS_LINK]; 328 SMU7_Discrete_ACPILevel ACPILevel; 329 SMU7_Discrete_UvdLevel UvdLevel [SMU7_MAX_LEVELS_UVD]; 330 SMU7_Discrete_ExtClkLevel VceLevel [SMU7_MAX_LEVELS_VCE]; 331 SMU7_Discrete_ExtClkLevel AcpLevel [SMU7_MAX_LEVELS_ACP]; 332 SMU7_Discrete_ExtClkLevel SamuLevel [SMU7_MAX_LEVELS_SAMU]; 333 SMU7_Discrete_Ulv Ulv; 334 335 uint32_t SclkStepSize; 336 uint32_t Smio [SMU7_MAX_ENTRIES_SMIO]; 337 338 uint8_t UvdBootLevel; 339 uint8_t VceBootLevel; 340 uint8_t AcpBootLevel; 341 uint8_t SamuBootLevel; 342 343 uint8_t UVDInterval; 344 uint8_t VCEInterval; 345 uint8_t ACPInterval; 346 uint8_t SAMUInterval; 347 348 uint8_t GraphicsBootLevel; 349 uint8_t GraphicsVoltageChangeEnable; 350 uint8_t GraphicsThermThrottleEnable; 351 uint8_t GraphicsInterval; 352 353 uint8_t VoltageInterval; 354 uint8_t ThermalInterval; 355 uint16_t TemperatureLimitHigh; 356 357 uint16_t TemperatureLimitLow; 358 uint8_t MemoryBootLevel; 359 uint8_t MemoryVoltageChangeEnable; 360 361 uint8_t MemoryInterval; 362 uint8_t MemoryThermThrottleEnable; 363 uint16_t VddcVddciDelta; 364 365 uint16_t VoltageResponseTime; 366 uint16_t PhaseResponseTime; 367 368 uint8_t PCIeBootLinkLevel; 369 uint8_t PCIeGenInterval; 370 uint8_t DTEInterval; 371 uint8_t DTEMode; 372 373 uint8_t SVI2Enable; 374 uint8_t VRHotGpio; 375 uint8_t AcDcGpio; 376 uint8_t ThermGpio; 377 378 uint16_t PPM_PkgPwrLimit; 379 uint16_t PPM_TemperatureLimit; 380 381 uint16_t DefaultTdp; 382 uint16_t TargetTdp; 383 384 uint16_t FpsHighT; 385 uint16_t FpsLowT; 386 387 uint16_t BAPMTI_R [SMU7_DTE_ITERATIONS][SMU7_DTE_SOURCES][SMU7_DTE_SINKS]; 388 uint16_t BAPMTI_RC [SMU7_DTE_ITERATIONS][SMU7_DTE_SOURCES][SMU7_DTE_SINKS]; 389 390 uint8_t DTEAmbientTempBase; 391 uint8_t DTETjOffset; 392 uint8_t GpuTjMax; 393 uint8_t GpuTjHyst; 394 395 uint16_t BootVddc; 396 uint16_t BootVddci; 397 398 uint16_t BootMVdd; 399 uint16_t padding; 400 401 uint32_t BAPM_TEMP_GRADIENT; 402 403 uint32_t LowSclkInterruptT; 404 }; 405 406 typedef struct SMU7_Discrete_DpmTable SMU7_Discrete_DpmTable; 407 408 #define SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE 16 409 #define SMU7_DISCRETE_MC_REGISTER_ARRAY_SET_COUNT SMU7_MAX_LEVELS_MEMORY 410 411 struct SMU7_Discrete_MCRegisterAddress 412 { 413 uint16_t s0; 414 uint16_t s1; 415 }; 416 417 typedef struct SMU7_Discrete_MCRegisterAddress SMU7_Discrete_MCRegisterAddress; 418 419 struct SMU7_Discrete_MCRegisterSet 420 { 421 uint32_t value[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE]; 422 }; 423 424 typedef struct SMU7_Discrete_MCRegisterSet SMU7_Discrete_MCRegisterSet; 425 426 struct SMU7_Discrete_MCRegisters 427 { 428 uint8_t last; 429 uint8_t reserved[3]; 430 SMU7_Discrete_MCRegisterAddress address[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE]; 431 SMU7_Discrete_MCRegisterSet data[SMU7_DISCRETE_MC_REGISTER_ARRAY_SET_COUNT]; 432 }; 433 434 typedef struct SMU7_Discrete_MCRegisters SMU7_Discrete_MCRegisters; 435 436 struct SMU7_Discrete_FanTable 437 { 438 uint16_t FdoMode; 439 int16_t TempMin; 440 int16_t TempMed; 441 int16_t TempMax; 442 int16_t Slope1; 443 int16_t Slope2; 444 int16_t FdoMin; 445 int16_t HystUp; 446 int16_t HystDown; 447 int16_t HystSlope; 448 int16_t TempRespLim; 449 int16_t TempCurr; 450 int16_t SlopeCurr; 451 int16_t PwmCurr; 452 uint32_t RefreshPeriod; 453 int16_t FdoMax; 454 uint8_t TempSrc; 455 int8_t Padding; 456 }; 457 458 typedef struct SMU7_Discrete_FanTable SMU7_Discrete_FanTable; 459 460 461 struct SMU7_Discrete_PmFuses { 462 // dw0-dw1 463 uint8_t BapmVddCVidHiSidd[8]; 464 465 // dw2-dw3 466 uint8_t BapmVddCVidLoSidd[8]; 467 468 // dw4-dw5 469 uint8_t VddCVid[8]; 470 471 // dw6 472 uint8_t SviLoadLineEn; 473 uint8_t SviLoadLineVddC; 474 uint8_t SviLoadLineTrimVddC; 475 uint8_t SviLoadLineOffsetVddC; 476 477 // dw7 478 uint16_t TDC_VDDC_PkgLimit; 479 uint8_t TDC_VDDC_ThrottleReleaseLimitPerc; 480 uint8_t TDC_MAWt; 481 482 // dw8 483 uint8_t TdcWaterfallCtl; 484 uint8_t LPMLTemperatureMin; 485 uint8_t LPMLTemperatureMax; 486 uint8_t Reserved; 487 488 // dw9-dw10 489 uint8_t BapmVddCVidHiSidd2[8]; 490 491 // dw11-dw12 492 int16_t FuzzyFan_ErrorSetDelta; 493 int16_t FuzzyFan_ErrorRateSetDelta; 494 int16_t FuzzyFan_PwmSetDelta; 495 uint16_t CalcMeasPowerBlend; 496 497 // dw13-dw16 498 uint8_t GnbLPML[16]; 499 500 // dw17 501 uint8_t GnbLPMLMaxVid; 502 uint8_t GnbLPMLMinVid; 503 uint8_t Reserved1[2]; 504 505 // dw18 506 uint16_t BapmVddCBaseLeakageHiSidd; 507 uint16_t BapmVddCBaseLeakageLoSidd; 508 }; 509 510 typedef struct SMU7_Discrete_PmFuses SMU7_Discrete_PmFuses; 511 512 513 #pragma pack(pop) 514 515 #endif 516 517
Indexes created Wed Oct 22 13:09:56 GMT 2025