sumo_dpm.h revision 1.1.1.1.30.1
1 /* $NetBSD: sumo_dpm.h,v 1.1.1.1.30.1 2018/09/06 06:56:33 pgoyette Exp $ */ 2 3 /* 4 * Copyright 2012 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 #ifndef __SUMO_DPM_H__ 26 #define __SUMO_DPM_H__ 27 28 #include "atom.h" 29 30 #define SUMO_MAX_HARDWARE_POWERLEVELS 5 31 #define SUMO_PM_NUMBER_OF_TC 15 32 33 struct sumo_pl { 34 u32 sclk; 35 u32 vddc_index; 36 u32 ds_divider_index; 37 u32 ss_divider_index; 38 u32 allow_gnb_slow; 39 u32 sclk_dpm_tdp_limit; 40 }; 41 42 /* used for the flags field */ 43 #define SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE (1 << 0) 44 #define SUMO_POWERSTATE_FLAGS_BOOST_STATE (1 << 1) 45 46 struct sumo_ps { 47 struct sumo_pl levels[SUMO_MAX_HARDWARE_POWERLEVELS]; 48 u32 num_levels; 49 /* flags */ 50 u32 flags; 51 }; 52 53 #define NUMBER_OF_M3ARB_PARAM_SETS 10 54 #define SUMO_MAX_NUMBER_VOLTAGES 4 55 56 struct sumo_disp_clock_voltage_mapping_table { 57 u32 num_max_voltage_levels; 58 u32 display_clock_frequency[SUMO_MAX_NUMBER_VOLTAGES]; 59 }; 60 61 struct sumo_vid_mapping_entry { 62 u16 vid_2bit; 63 u16 vid_7bit; 64 }; 65 66 struct sumo_vid_mapping_table { 67 u32 num_entries; 68 struct sumo_vid_mapping_entry entries[SUMO_MAX_NUMBER_VOLTAGES]; 69 }; 70 71 struct sumo_sclk_voltage_mapping_entry { 72 u32 sclk_frequency; 73 u16 vid_2bit; 74 u16 rsv; 75 }; 76 77 struct sumo_sclk_voltage_mapping_table { 78 u32 num_max_dpm_entries; 79 struct sumo_sclk_voltage_mapping_entry entries[SUMO_MAX_HARDWARE_POWERLEVELS]; 80 }; 81 82 struct sumo_sys_info { 83 u32 bootup_sclk; 84 u32 min_sclk; 85 u32 bootup_uma_clk; 86 u16 bootup_nb_voltage_index; 87 u8 htc_tmp_lmt; 88 u8 htc_hyst_lmt; 89 struct sumo_sclk_voltage_mapping_table sclk_voltage_mapping_table; 90 struct sumo_disp_clock_voltage_mapping_table disp_clk_voltage_mapping_table; 91 struct sumo_vid_mapping_table vid_mapping_table; 92 u32 csr_m3_arb_cntl_default[NUMBER_OF_M3ARB_PARAM_SETS]; 93 u32 csr_m3_arb_cntl_uvd[NUMBER_OF_M3ARB_PARAM_SETS]; 94 u32 csr_m3_arb_cntl_fs3d[NUMBER_OF_M3ARB_PARAM_SETS]; 95 u32 sclk_dpm_boost_margin; 96 u32 sclk_dpm_throttle_margin; 97 u32 sclk_dpm_tdp_limit_pg; 98 u32 gnb_tdp_limit; 99 u32 sclk_dpm_tdp_limit_boost; 100 u32 boost_sclk; 101 u32 boost_vid_2bit; 102 bool enable_boost; 103 }; 104 105 struct sumo_power_info { 106 u32 asi; 107 u32 pasi; 108 u32 bsp; 109 u32 bsu; 110 u32 pbsp; 111 u32 pbsu; 112 u32 dsp; 113 u32 psp; 114 u32 thermal_auto_throttling; 115 u32 uvd_m3_arbiter; 116 u32 fw_version; 117 struct sumo_sys_info sys_info; 118 struct sumo_pl acpi_pl; 119 struct sumo_pl boot_pl; 120 struct sumo_pl boost_pl; 121 bool disable_gfx_power_gating_in_uvd; 122 bool driver_nbps_policy_disable; 123 bool enable_alt_vddnb; 124 bool enable_dynamic_m3_arbiter; 125 bool enable_gfx_clock_gating; 126 bool enable_gfx_power_gating; 127 bool enable_mg_clock_gating; 128 bool enable_sclk_ds; 129 bool enable_auto_thermal_throttling; 130 bool enable_dynamic_patch_ps; 131 bool enable_dpm; 132 bool enable_boost; 133 struct radeon_ps current_rps; 134 struct sumo_ps current_ps; 135 struct radeon_ps requested_rps; 136 struct sumo_ps requested_ps; 137 }; 138 139 #define SUMO_UTC_DFLT_00 0x48 140 #define SUMO_UTC_DFLT_01 0x44 141 #define SUMO_UTC_DFLT_02 0x44 142 #define SUMO_UTC_DFLT_03 0x44 143 #define SUMO_UTC_DFLT_04 0x44 144 #define SUMO_UTC_DFLT_05 0x44 145 #define SUMO_UTC_DFLT_06 0x44 146 #define SUMO_UTC_DFLT_07 0x44 147 #define SUMO_UTC_DFLT_08 0x44 148 #define SUMO_UTC_DFLT_09 0x44 149 #define SUMO_UTC_DFLT_10 0x44 150 #define SUMO_UTC_DFLT_11 0x44 151 #define SUMO_UTC_DFLT_12 0x44 152 #define SUMO_UTC_DFLT_13 0x44 153 #define SUMO_UTC_DFLT_14 0x44 154 155 #define SUMO_DTC_DFLT_00 0x48 156 #define SUMO_DTC_DFLT_01 0x44 157 #define SUMO_DTC_DFLT_02 0x44 158 #define SUMO_DTC_DFLT_03 0x44 159 #define SUMO_DTC_DFLT_04 0x44 160 #define SUMO_DTC_DFLT_05 0x44 161 #define SUMO_DTC_DFLT_06 0x44 162 #define SUMO_DTC_DFLT_07 0x44 163 #define SUMO_DTC_DFLT_08 0x44 164 #define SUMO_DTC_DFLT_09 0x44 165 #define SUMO_DTC_DFLT_10 0x44 166 #define SUMO_DTC_DFLT_11 0x44 167 #define SUMO_DTC_DFLT_12 0x44 168 #define SUMO_DTC_DFLT_13 0x44 169 #define SUMO_DTC_DFLT_14 0x44 170 171 #define SUMO_AH_DFLT 5 172 173 #define SUMO_R_DFLT0 70 174 #define SUMO_R_DFLT1 70 175 #define SUMO_R_DFLT2 70 176 #define SUMO_R_DFLT3 70 177 #define SUMO_R_DFLT4 100 178 179 #define SUMO_L_DFLT0 0 180 #define SUMO_L_DFLT1 20 181 #define SUMO_L_DFLT2 20 182 #define SUMO_L_DFLT3 20 183 #define SUMO_L_DFLT4 20 184 #define SUMO_VRC_DFLT 0x30033 185 #define SUMO_MGCGTTLOCAL0_DFLT 0 186 #define SUMO_MGCGTTLOCAL1_DFLT 0 187 #define SUMO_GICST_DFLT 19 188 #define SUMO_SST_DFLT 8 189 #define SUMO_VOLTAGEDROPT_DFLT 1 190 #define SUMO_GFXPOWERGATINGT_DFLT 100 191 192 /* sumo_dpm.c */ 193 void sumo_gfx_clockgating_initialize(struct radeon_device *rdev); 194 void sumo_program_vc(struct radeon_device *rdev, u32 vrc); 195 void sumo_clear_vc(struct radeon_device *rdev); 196 void sumo_program_sstp(struct radeon_device *rdev); 197 void sumo_take_smu_control(struct radeon_device *rdev, bool enable); 198 void sumo_construct_sclk_voltage_mapping_table(struct radeon_device *rdev, 199 struct sumo_sclk_voltage_mapping_table *sclk_voltage_mapping_table, 200 ATOM_AVAILABLE_SCLK_LIST *table); 201 void sumo_construct_vid_mapping_table(struct radeon_device *rdev, 202 struct sumo_vid_mapping_table *vid_mapping_table, 203 ATOM_AVAILABLE_SCLK_LIST *table); 204 u32 sumo_convert_vid2_to_vid7(struct radeon_device *rdev, 205 struct sumo_vid_mapping_table *vid_mapping_table, 206 u32 vid_2bit); 207 u32 sumo_get_sleep_divider_from_id(u32 id); 208 u32 sumo_get_sleep_divider_id_from_clock(struct radeon_device *rdev, 209 u32 sclk, 210 u32 min_sclk_in_sr); 211 212 /* sumo_smc.c */ 213 void sumo_initialize_m3_arb(struct radeon_device *rdev); 214 void sumo_smu_pg_init(struct radeon_device *rdev); 215 void sumo_set_tdp_limit(struct radeon_device *rdev, u32 index, u32 tdp_limit); 216 void sumo_smu_notify_alt_vddnb_change(struct radeon_device *rdev, 217 bool powersaving, bool force_nbps1); 218 void sumo_boost_state_enable(struct radeon_device *rdev, bool enable); 219 void sumo_enable_boost_timer(struct radeon_device *rdev); 220 u32 sumo_get_running_fw_version(struct radeon_device *rdev); 221 222 #endif 223
Indexes created Wed Oct 22 00:09:40 GMT 2025