savage_drv.h revision 1.1.1.2.28.1
1 /* $NetBSD: savage_drv.h,v 1.1.1.2.28.1 2018/09/06 06:56:33 pgoyette Exp $ */ 2 3 /* savage_drv.h -- Private header for the savage driver */ 4 /* 5 * Copyright 2004 Felix Kuehling 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sub license, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the 16 * next paragraph) shall be included in all copies or substantial portions 17 * of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 20 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 22 * NON-INFRINGEMENT. IN NO EVENT SHALL FELIX KUEHLING BE LIABLE FOR 23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF 24 * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 25 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 26 */ 27 28 #ifndef __SAVAGE_DRV_H__ 29 #define __SAVAGE_DRV_H__ 30 31 #include <drm/drm_legacy.h> 32 33 #define DRIVER_AUTHOR "Felix Kuehling" 34 35 #define DRIVER_NAME "savage" 36 #define DRIVER_DESC "Savage3D/MX/IX, Savage4, SuperSavage, Twister, ProSavage[DDR]" 37 #define DRIVER_DATE "20050313" 38 39 #define DRIVER_MAJOR 2 40 #define DRIVER_MINOR 4 41 #define DRIVER_PATCHLEVEL 1 42 /* Interface history: 43 * 44 * 1.x The DRM driver from the VIA/S3 code drop, basically a dummy 45 * 2.0 The first real DRM 46 * 2.1 Scissors registers managed by the DRM, 3D operations clipped by 47 * cliprects of the cmdbuf ioctl 48 * 2.2 Implemented SAVAGE_CMD_DMA_IDX and SAVAGE_CMD_VB_IDX 49 * 2.3 Event counters used by BCI_EVENT_EMIT/WAIT ioctls are now 32 bits 50 * wide and thus very long lived (unlikely to ever wrap). The size 51 * in the struct was 32 bits before, but only 16 bits were used 52 * 2.4 Implemented command DMA. Now drm_savage_init_t.cmd_dma_offset is 53 * actually used 54 */ 55 56 typedef struct drm_savage_age { 57 uint16_t event; 58 unsigned int wrap; 59 } drm_savage_age_t; 60 61 typedef struct drm_savage_buf_priv { 62 struct drm_savage_buf_priv *next; 63 struct drm_savage_buf_priv *prev; 64 drm_savage_age_t age; 65 struct drm_buf *buf; 66 } drm_savage_buf_priv_t; 67 68 typedef struct drm_savage_dma_page { 69 drm_savage_age_t age; 70 unsigned int used, flushed; 71 } drm_savage_dma_page_t; 72 #define SAVAGE_DMA_PAGE_SIZE 1024 /* in dwords */ 73 /* Fake DMA buffer size in bytes. 4 pages. Allows a maximum command 74 * size of 16kbytes or 4k entries. Minimum requirement would be 75 * 10kbytes for 255 40-byte vertices in one drawing command. */ 76 #define SAVAGE_FAKE_DMA_SIZE (SAVAGE_DMA_PAGE_SIZE*4*4) 77 78 /* interesting bits of hardware state that are saved in dev_priv */ 79 typedef union { 80 struct drm_savage_common_state { 81 uint32_t vbaddr; 82 } common; 83 struct { 84 unsigned char pad[sizeof(struct drm_savage_common_state)]; 85 uint32_t texctrl, texaddr; 86 uint32_t scstart, new_scstart; 87 uint32_t scend, new_scend; 88 } s3d; 89 struct { 90 unsigned char pad[sizeof(struct drm_savage_common_state)]; 91 uint32_t texdescr, texaddr0, texaddr1; 92 uint32_t drawctrl0, new_drawctrl0; 93 uint32_t drawctrl1, new_drawctrl1; 94 } s4; 95 } drm_savage_state_t; 96 97 /* these chip tags should match the ones in the 2D driver in savage_regs.h. */ 98 enum savage_family { 99 S3_UNKNOWN = 0, 100 S3_SAVAGE3D, 101 S3_SAVAGE_MX, 102 S3_SAVAGE4, 103 S3_PROSAVAGE, 104 S3_TWISTER, 105 S3_PROSAVAGEDDR, 106 S3_SUPERSAVAGE, 107 S3_SAVAGE2000, 108 S3_LAST 109 }; 110 111 extern const struct drm_ioctl_desc savage_ioctls[]; 112 extern int savage_max_ioctl; 113 114 #define S3_SAVAGE3D_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE_MX)) 115 116 #define S3_SAVAGE4_SERIES(chip) ((chip==S3_SAVAGE4) \ 117 || (chip==S3_PROSAVAGE) \ 118 || (chip==S3_TWISTER) \ 119 || (chip==S3_PROSAVAGEDDR)) 120 121 #define S3_SAVAGE_MOBILE_SERIES(chip) ((chip==S3_SAVAGE_MX) || (chip==S3_SUPERSAVAGE)) 122 123 #define S3_SAVAGE_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE2000)) 124 125 #define S3_MOBILE_TWISTER_SERIES(chip) ((chip==S3_TWISTER) \ 126 ||(chip==S3_PROSAVAGEDDR)) 127 128 /* flags */ 129 #define SAVAGE_IS_AGP 1 130 131 typedef struct drm_savage_private { 132 drm_savage_sarea_t *sarea_priv; 133 134 drm_savage_buf_priv_t head, tail; 135 136 /* who am I? */ 137 enum savage_family chipset; 138 139 unsigned int cob_size; 140 unsigned int bci_threshold_lo, bci_threshold_hi; 141 unsigned int dma_type; 142 143 /* frame buffer layout */ 144 unsigned int fb_bpp; 145 unsigned int front_offset, front_pitch; 146 unsigned int back_offset, back_pitch; 147 unsigned int depth_bpp; 148 unsigned int depth_offset, depth_pitch; 149 150 /* bitmap descriptors for swap and clear */ 151 unsigned int front_bd, back_bd, depth_bd; 152 153 /* local textures */ 154 unsigned int texture_offset; 155 unsigned int texture_size; 156 157 /* memory regions in physical memory */ 158 drm_local_map_t *sarea; 159 drm_local_map_t *mmio; 160 drm_local_map_t *fb; 161 drm_local_map_t *aperture; 162 drm_local_map_t *status; 163 drm_local_map_t *agp_textures; 164 drm_local_map_t *cmd_dma; 165 drm_local_map_t fake_dma; 166 167 int mtrr_handles[3]; 168 169 /* BCI and status-related stuff */ 170 volatile uint32_t *status_ptr, *bci_ptr; 171 uint32_t status_used_mask; 172 uint16_t event_counter; 173 unsigned int event_wrap; 174 175 /* Savage4 command DMA */ 176 drm_savage_dma_page_t *dma_pages; 177 unsigned int nr_dma_pages, first_dma_page, current_dma_page; 178 drm_savage_age_t last_dma_age; 179 180 /* saved hw state for global/local check on S3D */ 181 uint32_t hw_draw_ctrl, hw_zbuf_ctrl; 182 /* and for scissors (global, so don't emit if not changed) */ 183 uint32_t hw_scissors_start, hw_scissors_end; 184 185 drm_savage_state_t state; 186 187 /* after emitting a wait cmd Savage3D needs 63 nops before next DMA */ 188 unsigned int waiting; 189 190 /* config/hardware-dependent function pointers */ 191 int (*wait_fifo) (struct drm_savage_private * dev_priv, unsigned int n); 192 int (*wait_evnt) (struct drm_savage_private * dev_priv, uint16_t e); 193 /* Err, there is a macro wait_event in include/linux/wait.h. 194 * Avoid unwanted macro expansion. */ 195 void (*emit_clip_rect) (struct drm_savage_private * dev_priv, 196 const struct drm_clip_rect * pbox); 197 void (*dma_flush) (struct drm_savage_private * dev_priv); 198 } drm_savage_private_t; 199 200 /* ioctls */ 201 extern int savage_bci_cmdbuf(struct drm_device *dev, void *data, struct drm_file *file_priv); 202 extern int savage_bci_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv); 203 204 /* BCI functions */ 205 extern uint16_t savage_bci_emit_event(drm_savage_private_t * dev_priv, 206 unsigned int flags); 207 extern void savage_freelist_put(struct drm_device * dev, struct drm_buf * buf); 208 extern void savage_dma_reset(drm_savage_private_t * dev_priv); 209 extern void savage_dma_wait(drm_savage_private_t * dev_priv, unsigned int page); 210 extern uint32_t *savage_dma_alloc(drm_savage_private_t * dev_priv, 211 unsigned int n); 212 extern int savage_driver_load(struct drm_device *dev, unsigned long chipset); 213 extern int savage_driver_firstopen(struct drm_device *dev); 214 extern void savage_driver_lastclose(struct drm_device *dev); 215 extern int savage_driver_unload(struct drm_device *dev); 216 extern void savage_reclaim_buffers(struct drm_device *dev, 217 struct drm_file *file_priv); 218 219 /* state functions */ 220 extern void savage_emit_clip_rect_s3d(drm_savage_private_t * dev_priv, 221 const struct drm_clip_rect * pbox); 222 extern void savage_emit_clip_rect_s4(drm_savage_private_t * dev_priv, 223 const struct drm_clip_rect * pbox); 224 225 #define SAVAGE_FB_SIZE_S3 0x01000000 /* 16MB */ 226 #define SAVAGE_FB_SIZE_S4 0x02000000 /* 32MB */ 227 #define SAVAGE_MMIO_SIZE 0x00080000 /* 512kB */ 228 #define SAVAGE_APERTURE_OFFSET 0x02000000 /* 32MB */ 229 #define SAVAGE_APERTURE_SIZE 0x05000000 /* 5 tiled surfaces, 16MB each */ 230 231 #define SAVAGE_BCI_OFFSET 0x00010000 /* offset of the BCI region 232 * inside the MMIO region */ 233 #define SAVAGE_BCI_FIFO_SIZE 32 /* number of entries in on-chip 234 * BCI FIFO */ 235 236 /* 237 * MMIO registers 238 */ 239 #define SAVAGE_STATUS_WORD0 0x48C00 240 #define SAVAGE_STATUS_WORD1 0x48C04 241 #define SAVAGE_ALT_STATUS_WORD0 0x48C60 242 243 #define SAVAGE_FIFO_USED_MASK_S3D 0x0001ffff 244 #define SAVAGE_FIFO_USED_MASK_S4 0x001fffff 245 246 /* Copied from savage_bci.h in the 2D driver with some renaming. */ 247 248 /* Bitmap descriptors */ 249 #define SAVAGE_BD_STRIDE_SHIFT 0 250 #define SAVAGE_BD_BPP_SHIFT 16 251 #define SAVAGE_BD_TILE_SHIFT 24 252 #define SAVAGE_BD_BW_DISABLE (1<<28) 253 /* common: */ 254 #define SAVAGE_BD_TILE_LINEAR 0 255 /* savage4, MX, IX, 3D */ 256 #define SAVAGE_BD_TILE_16BPP 2 257 #define SAVAGE_BD_TILE_32BPP 3 258 /* twister, prosavage, DDR, supersavage, 2000 */ 259 #define SAVAGE_BD_TILE_DEST 1 260 #define SAVAGE_BD_TILE_TEXTURE 2 261 /* GBD - BCI enable */ 262 /* savage4, MX, IX, 3D */ 263 #define SAVAGE_GBD_BCI_ENABLE 8 264 /* twister, prosavage, DDR, supersavage, 2000 */ 265 #define SAVAGE_GBD_BCI_ENABLE_TWISTER 0 266 267 #define SAVAGE_GBD_BIG_ENDIAN 4 268 #define SAVAGE_GBD_LITTLE_ENDIAN 0 269 #define SAVAGE_GBD_64 1 270 271 /* Global Bitmap Descriptor */ 272 #define SAVAGE_BCI_GLB_BD_LOW 0x8168 273 #define SAVAGE_BCI_GLB_BD_HIGH 0x816C 274 275 /* 276 * BCI registers 277 */ 278 /* Savage4/Twister/ProSavage 3D registers */ 279 #define SAVAGE_DRAWLOCALCTRL_S4 0x1e 280 #define SAVAGE_TEXPALADDR_S4 0x1f 281 #define SAVAGE_TEXCTRL0_S4 0x20 282 #define SAVAGE_TEXCTRL1_S4 0x21 283 #define SAVAGE_TEXADDR0_S4 0x22 284 #define SAVAGE_TEXADDR1_S4 0x23 285 #define SAVAGE_TEXBLEND0_S4 0x24 286 #define SAVAGE_TEXBLEND1_S4 0x25 287 #define SAVAGE_TEXXPRCLR_S4 0x26 /* never used */ 288 #define SAVAGE_TEXDESCR_S4 0x27 289 #define SAVAGE_FOGTABLE_S4 0x28 290 #define SAVAGE_FOGCTRL_S4 0x30 291 #define SAVAGE_STENCILCTRL_S4 0x31 292 #define SAVAGE_ZBUFCTRL_S4 0x32 293 #define SAVAGE_ZBUFOFF_S4 0x33 294 #define SAVAGE_DESTCTRL_S4 0x34 295 #define SAVAGE_DRAWCTRL0_S4 0x35 296 #define SAVAGE_DRAWCTRL1_S4 0x36 297 #define SAVAGE_ZWATERMARK_S4 0x37 298 #define SAVAGE_DESTTEXRWWATERMARK_S4 0x38 299 #define SAVAGE_TEXBLENDCOLOR_S4 0x39 300 /* Savage3D/MX/IX 3D registers */ 301 #define SAVAGE_TEXPALADDR_S3D 0x18 302 #define SAVAGE_TEXXPRCLR_S3D 0x19 /* never used */ 303 #define SAVAGE_TEXADDR_S3D 0x1A 304 #define SAVAGE_TEXDESCR_S3D 0x1B 305 #define SAVAGE_TEXCTRL_S3D 0x1C 306 #define SAVAGE_FOGTABLE_S3D 0x20 307 #define SAVAGE_FOGCTRL_S3D 0x30 308 #define SAVAGE_DRAWCTRL_S3D 0x31 309 #define SAVAGE_ZBUFCTRL_S3D 0x32 310 #define SAVAGE_ZBUFOFF_S3D 0x33 311 #define SAVAGE_DESTCTRL_S3D 0x34 312 #define SAVAGE_SCSTART_S3D 0x35 313 #define SAVAGE_SCEND_S3D 0x36 314 #define SAVAGE_ZWATERMARK_S3D 0x37 315 #define SAVAGE_DESTTEXRWWATERMARK_S3D 0x38 316 /* common stuff */ 317 #define SAVAGE_VERTBUFADDR 0x3e 318 #define SAVAGE_BITPLANEWTMASK 0xd7 319 #define SAVAGE_DMABUFADDR 0x51 320 321 /* texture enable bits (needed for tex addr checking) */ 322 #define SAVAGE_TEXCTRL_TEXEN_MASK 0x00010000 /* S3D */ 323 #define SAVAGE_TEXDESCR_TEX0EN_MASK 0x02000000 /* S4 */ 324 #define SAVAGE_TEXDESCR_TEX1EN_MASK 0x04000000 /* S4 */ 325 326 /* Global fields in Savage4/Twister/ProSavage 3D registers: 327 * 328 * All texture registers and DrawLocalCtrl are local. All other 329 * registers are global. */ 330 331 /* Global fields in Savage3D/MX/IX 3D registers: 332 * 333 * All texture registers are local. DrawCtrl and ZBufCtrl are 334 * partially local. All other registers are global. 335 * 336 * DrawCtrl global fields: cullMode, alphaTestCmpFunc, alphaTestEn, alphaRefVal 337 * ZBufCtrl global fields: zCmpFunc, zBufEn 338 */ 339 #define SAVAGE_DRAWCTRL_S3D_GLOBAL 0x03f3c00c 340 #define SAVAGE_ZBUFCTRL_S3D_GLOBAL 0x00000027 341 342 /* Masks for scissor bits (drawCtrl[01] on s4, scissorStart/End on s3d) 343 */ 344 #define SAVAGE_SCISSOR_MASK_S4 0x00fff7ff 345 #define SAVAGE_SCISSOR_MASK_S3D 0x07ff07ff 346 347 /* 348 * BCI commands 349 */ 350 #define BCI_CMD_NOP 0x40000000 351 #define BCI_CMD_RECT 0x48000000 352 #define BCI_CMD_RECT_XP 0x01000000 353 #define BCI_CMD_RECT_YP 0x02000000 354 #define BCI_CMD_SCANLINE 0x50000000 355 #define BCI_CMD_LINE 0x5C000000 356 #define BCI_CMD_LINE_LAST_PIXEL 0x58000000 357 #define BCI_CMD_BYTE_TEXT 0x63000000 358 #define BCI_CMD_NT_BYTE_TEXT 0x67000000 359 #define BCI_CMD_BIT_TEXT 0x6C000000 360 #define BCI_CMD_GET_ROP(cmd) (((cmd) >> 16) & 0xFF) 361 #define BCI_CMD_SET_ROP(cmd, rop) ((cmd) |= ((rop & 0xFF) << 16)) 362 #define BCI_CMD_SEND_COLOR 0x00008000 363 364 #define BCI_CMD_CLIP_NONE 0x00000000 365 #define BCI_CMD_CLIP_CURRENT 0x00002000 366 #define BCI_CMD_CLIP_LR 0x00004000 367 #define BCI_CMD_CLIP_NEW 0x00006000 368 369 #define BCI_CMD_DEST_GBD 0x00000000 370 #define BCI_CMD_DEST_PBD 0x00000800 371 #define BCI_CMD_DEST_PBD_NEW 0x00000C00 372 #define BCI_CMD_DEST_SBD 0x00001000 373 #define BCI_CMD_DEST_SBD_NEW 0x00001400 374 375 #define BCI_CMD_SRC_TRANSPARENT 0x00000200 376 #define BCI_CMD_SRC_SOLID 0x00000000 377 #define BCI_CMD_SRC_GBD 0x00000020 378 #define BCI_CMD_SRC_COLOR 0x00000040 379 #define BCI_CMD_SRC_MONO 0x00000060 380 #define BCI_CMD_SRC_PBD_COLOR 0x00000080 381 #define BCI_CMD_SRC_PBD_MONO 0x000000A0 382 #define BCI_CMD_SRC_PBD_COLOR_NEW 0x000000C0 383 #define BCI_CMD_SRC_PBD_MONO_NEW 0x000000E0 384 #define BCI_CMD_SRC_SBD_COLOR 0x00000100 385 #define BCI_CMD_SRC_SBD_MONO 0x00000120 386 #define BCI_CMD_SRC_SBD_COLOR_NEW 0x00000140 387 #define BCI_CMD_SRC_SBD_MONO_NEW 0x00000160 388 389 #define BCI_CMD_PAT_TRANSPARENT 0x00000010 390 #define BCI_CMD_PAT_NONE 0x00000000 391 #define BCI_CMD_PAT_COLOR 0x00000002 392 #define BCI_CMD_PAT_MONO 0x00000003 393 #define BCI_CMD_PAT_PBD_COLOR 0x00000004 394 #define BCI_CMD_PAT_PBD_MONO 0x00000005 395 #define BCI_CMD_PAT_PBD_COLOR_NEW 0x00000006 396 #define BCI_CMD_PAT_PBD_MONO_NEW 0x00000007 397 #define BCI_CMD_PAT_SBD_COLOR 0x00000008 398 #define BCI_CMD_PAT_SBD_MONO 0x00000009 399 #define BCI_CMD_PAT_SBD_COLOR_NEW 0x0000000A 400 #define BCI_CMD_PAT_SBD_MONO_NEW 0x0000000B 401 402 #define BCI_BD_BW_DISABLE 0x10000000 403 #define BCI_BD_TILE_MASK 0x03000000 404 #define BCI_BD_TILE_NONE 0x00000000 405 #define BCI_BD_TILE_16 0x02000000 406 #define BCI_BD_TILE_32 0x03000000 407 #define BCI_BD_GET_BPP(bd) (((bd) >> 16) & 0xFF) 408 #define BCI_BD_SET_BPP(bd, bpp) ((bd) |= (((bpp) & 0xFF) << 16)) 409 #define BCI_BD_GET_STRIDE(bd) ((bd) & 0xFFFF) 410 #define BCI_BD_SET_STRIDE(bd, st) ((bd) |= ((st) & 0xFFFF)) 411 412 #define BCI_CMD_SET_REGISTER 0x96000000 413 414 #define BCI_CMD_WAIT 0xC0000000 415 #define BCI_CMD_WAIT_3D 0x00010000 416 #define BCI_CMD_WAIT_2D 0x00020000 417 418 #define BCI_CMD_UPDATE_EVENT_TAG 0x98000000 419 420 #define BCI_CMD_DRAW_PRIM 0x80000000 421 #define BCI_CMD_DRAW_INDEXED_PRIM 0x88000000 422 #define BCI_CMD_DRAW_CONT 0x01000000 423 #define BCI_CMD_DRAW_TRILIST 0x00000000 424 #define BCI_CMD_DRAW_TRISTRIP 0x02000000 425 #define BCI_CMD_DRAW_TRIFAN 0x04000000 426 #define BCI_CMD_DRAW_SKIPFLAGS 0x000000ff 427 #define BCI_CMD_DRAW_NO_Z 0x00000001 428 #define BCI_CMD_DRAW_NO_W 0x00000002 429 #define BCI_CMD_DRAW_NO_CD 0x00000004 430 #define BCI_CMD_DRAW_NO_CS 0x00000008 431 #define BCI_CMD_DRAW_NO_U0 0x00000010 432 #define BCI_CMD_DRAW_NO_V0 0x00000020 433 #define BCI_CMD_DRAW_NO_UV0 0x00000030 434 #define BCI_CMD_DRAW_NO_U1 0x00000040 435 #define BCI_CMD_DRAW_NO_V1 0x00000080 436 #define BCI_CMD_DRAW_NO_UV1 0x000000c0 437 438 #define BCI_CMD_DMA 0xa8000000 439 440 #define BCI_W_H(w, h) ((((h) << 16) | (w)) & 0x0FFF0FFF) 441 #define BCI_X_Y(x, y) ((((y) << 16) | (x)) & 0x0FFF0FFF) 442 #define BCI_X_W(x, y) ((((w) << 16) | (x)) & 0x0FFF0FFF) 443 #define BCI_CLIP_LR(l, r) ((((r) << 16) | (l)) & 0x0FFF0FFF) 444 #define BCI_CLIP_TL(t, l) ((((t) << 16) | (l)) & 0x0FFF0FFF) 445 #define BCI_CLIP_BR(b, r) ((((b) << 16) | (r)) & 0x0FFF0FFF) 446 447 #define BCI_LINE_X_Y(x, y) (((y) << 16) | ((x) & 0xFFFF)) 448 #define BCI_LINE_STEPS(diag, axi) (((axi) << 16) | ((diag) & 0xFFFF)) 449 #define BCI_LINE_MISC(maj, ym, xp, yp, err) \ 450 (((maj) & 0x1FFF) | \ 451 ((ym) ? 1<<13 : 0) | \ 452 ((xp) ? 1<<14 : 0) | \ 453 ((yp) ? 1<<15 : 0) | \ 454 ((err) << 16)) 455 456 /* 457 * common commands 458 */ 459 #define BCI_SET_REGISTERS( first, n ) \ 460 BCI_WRITE(BCI_CMD_SET_REGISTER | \ 461 ((uint32_t)(n) & 0xff) << 16 | \ 462 ((uint32_t)(first) & 0xffff)) 463 #define DMA_SET_REGISTERS( first, n ) \ 464 DMA_WRITE(BCI_CMD_SET_REGISTER | \ 465 ((uint32_t)(n) & 0xff) << 16 | \ 466 ((uint32_t)(first) & 0xffff)) 467 468 #define BCI_DRAW_PRIMITIVE(n, type, skip) \ 469 BCI_WRITE(BCI_CMD_DRAW_PRIM | (type) | (skip) | \ 470 ((n) << 16)) 471 #define DMA_DRAW_PRIMITIVE(n, type, skip) \ 472 DMA_WRITE(BCI_CMD_DRAW_PRIM | (type) | (skip) | \ 473 ((n) << 16)) 474 475 #define BCI_DRAW_INDICES_S3D(n, type, i0) \ 476 BCI_WRITE(BCI_CMD_DRAW_INDEXED_PRIM | (type) | \ 477 ((n) << 16) | (i0)) 478 479 #define BCI_DRAW_INDICES_S4(n, type, skip) \ 480 BCI_WRITE(BCI_CMD_DRAW_INDEXED_PRIM | (type) | \ 481 (skip) | ((n) << 16)) 482 483 #define BCI_DMA(n) \ 484 BCI_WRITE(BCI_CMD_DMA | (((n) >> 1) - 1)) 485 486 /* 487 * access to MMIO 488 */ 489 #define SAVAGE_READ(reg) DRM_READ32( dev_priv->mmio, (reg) ) 490 #define SAVAGE_WRITE(reg) DRM_WRITE32( dev_priv->mmio, (reg) ) 491 492 /* 493 * access to the burst command interface (BCI) 494 */ 495 #define SAVAGE_BCI_DEBUG 1 496 497 #define BCI_LOCALS volatile uint32_t *bci_ptr; 498 499 #define BEGIN_BCI( n ) do { \ 500 dev_priv->wait_fifo(dev_priv, (n)); \ 501 bci_ptr = dev_priv->bci_ptr; \ 502 } while(0) 503 504 #define BCI_WRITE( val ) *bci_ptr++ = (uint32_t)(val) 505 506 /* 507 * command DMA support 508 */ 509 #define SAVAGE_DMA_DEBUG 1 510 511 #define DMA_LOCALS uint32_t *dma_ptr; 512 513 #define BEGIN_DMA( n ) do { \ 514 unsigned int cur = dev_priv->current_dma_page; \ 515 unsigned int rest = SAVAGE_DMA_PAGE_SIZE - \ 516 dev_priv->dma_pages[cur].used; \ 517 if ((n) > rest) { \ 518 dma_ptr = savage_dma_alloc(dev_priv, (n)); \ 519 } else { /* fast path for small allocations */ \ 520 dma_ptr = (uint32_t *)dev_priv->cmd_dma->handle + \ 521 cur * SAVAGE_DMA_PAGE_SIZE + \ 522 dev_priv->dma_pages[cur].used; \ 523 if (dev_priv->dma_pages[cur].used == 0) \ 524 savage_dma_wait(dev_priv, cur); \ 525 dev_priv->dma_pages[cur].used += (n); \ 526 } \ 527 } while(0) 528 529 #define DMA_WRITE( val ) *dma_ptr++ = (uint32_t)(val) 530 531 #define DMA_COPY(src, n) do { \ 532 memcpy(dma_ptr, (src), (n)*4); \ 533 dma_ptr += n; \ 534 } while(0) 535 536 #if SAVAGE_DMA_DEBUG 537 #define DMA_COMMIT() do { \ 538 unsigned int cur = dev_priv->current_dma_page; \ 539 uint32_t *expected = (uint32_t *)dev_priv->cmd_dma->handle + \ 540 cur * SAVAGE_DMA_PAGE_SIZE + \ 541 dev_priv->dma_pages[cur].used; \ 542 if (dma_ptr != expected) { \ 543 DRM_ERROR("DMA allocation and use don't match: " \ 544 "%p != %p\n", expected, dma_ptr); \ 545 savage_dma_reset(dev_priv); \ 546 } \ 547 } while(0) 548 #else 549 #define DMA_COMMIT() do {/* nothing */} while(0) 550 #endif 551 552 #define DMA_FLUSH() dev_priv->dma_flush(dev_priv) 553 554 /* Buffer aging via event tag 555 */ 556 557 #define UPDATE_EVENT_COUNTER( ) do { \ 558 if (dev_priv->status_ptr) { \ 559 uint16_t count; \ 560 /* coordinate with Xserver */ \ 561 count = dev_priv->status_ptr[1023]; \ 562 if (count < dev_priv->event_counter) \ 563 dev_priv->event_wrap++; \ 564 dev_priv->event_counter = count; \ 565 } \ 566 } while(0) 567 568 #define SET_AGE( age, e, w ) do { \ 569 (age)->event = e; \ 570 (age)->wrap = w; \ 571 } while(0) 572 573 #define TEST_AGE( age, e, w ) \ 574 ( (age)->wrap < (w) || ( (age)->wrap == (w) && (age)->event <= (e) ) ) 575 576 #endif /* __SAVAGE_DRV_H__ */ 577
Indexes created Sun Oct 19 02:09:48 GMT 2025