via_irq.c revision 1.3 1 /* via_irq.c
2 *
3 * Copyright 2004 BEAM Ltd.
4 * Copyright 2002 Tungsten Graphics, Inc.
5 * Copyright 2005 Thomas Hellstrom.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * BEAM LTD, TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
23 * DAMAGES OR
24 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
25 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
26 * DEALINGS IN THE SOFTWARE.
27 *
28 * Authors:
29 * Terry Barnaby <terry1 (at) beam.ltd.uk>
30 * Keith Whitwell <keith (at) tungstengraphics.com>
31 * Thomas Hellstrom <unichrome (at) shipmail.org>
32 *
33 * This code provides standard DRM access to the Via Unichrome / Pro Vertical blank
34 * interrupt, as well as an infrastructure to handle other interrupts of the chip.
35 * The refresh rate is also calculated for video playback sync purposes.
36 */
37
38 #include <drm/drmP.h>
39 #include <drm/via_drm.h>
40 #include "via_drv.h"
41
42 #define VIA_REG_INTERRUPT 0x200
43
44 /* VIA_REG_INTERRUPT */
45 #define VIA_IRQ_GLOBAL (1 << 31)
46 #define VIA_IRQ_VBLANK_ENABLE (1 << 19)
47 #define VIA_IRQ_VBLANK_PENDING (1 << 3)
48 #define VIA_IRQ_HQV0_ENABLE (1 << 11)
49 #define VIA_IRQ_HQV1_ENABLE (1 << 25)
50 #define VIA_IRQ_HQV0_PENDING (1 << 9)
51 #define VIA_IRQ_HQV1_PENDING (1 << 10)
52 #define VIA_IRQ_DMA0_DD_ENABLE (1 << 20)
53 #define VIA_IRQ_DMA0_TD_ENABLE (1 << 21)
54 #define VIA_IRQ_DMA1_DD_ENABLE (1 << 22)
55 #define VIA_IRQ_DMA1_TD_ENABLE (1 << 23)
56 #define VIA_IRQ_DMA0_DD_PENDING (1 << 4)
57 #define VIA_IRQ_DMA0_TD_PENDING (1 << 5)
58 #define VIA_IRQ_DMA1_DD_PENDING (1 << 6)
59 #define VIA_IRQ_DMA1_TD_PENDING (1 << 7)
60
61
62 /*
63 * Device-specific IRQs go here. This type might need to be extended with
64 * the register if there are multiple IRQ control registers.
65 * Currently we activate the HQV interrupts of Unichrome Pro group A.
66 */
67
68 static maskarray_t via_pro_group_a_irqs[] = {
69 {VIA_IRQ_HQV0_ENABLE, VIA_IRQ_HQV0_PENDING, 0x000003D0, 0x00008010,
70 0x00000000 },
71 {VIA_IRQ_HQV1_ENABLE, VIA_IRQ_HQV1_PENDING, 0x000013D0, 0x00008010,
72 0x00000000 },
73 {VIA_IRQ_DMA0_TD_ENABLE, VIA_IRQ_DMA0_TD_PENDING, VIA_PCI_DMA_CSR0,
74 VIA_DMA_CSR_TA | VIA_DMA_CSR_TD, 0x00000008},
75 {VIA_IRQ_DMA1_TD_ENABLE, VIA_IRQ_DMA1_TD_PENDING, VIA_PCI_DMA_CSR1,
76 VIA_DMA_CSR_TA | VIA_DMA_CSR_TD, 0x00000008},
77 };
78 static int via_num_pro_group_a = ARRAY_SIZE(via_pro_group_a_irqs);
79 static int via_irqmap_pro_group_a[] = {0, 1, -1, 2, -1, 3};
80
81 static maskarray_t via_unichrome_irqs[] = {
82 {VIA_IRQ_DMA0_TD_ENABLE, VIA_IRQ_DMA0_TD_PENDING, VIA_PCI_DMA_CSR0,
83 VIA_DMA_CSR_TA | VIA_DMA_CSR_TD, 0x00000008},
84 {VIA_IRQ_DMA1_TD_ENABLE, VIA_IRQ_DMA1_TD_PENDING, VIA_PCI_DMA_CSR1,
85 VIA_DMA_CSR_TA | VIA_DMA_CSR_TD, 0x00000008}
86 };
87 static int via_num_unichrome = ARRAY_SIZE(via_unichrome_irqs);
88 static int via_irqmap_unichrome[] = {-1, -1, -1, 0, -1, 1};
89
90
91 static unsigned time_diff(struct timeval *now, struct timeval *then)
92 {
93 return (now->tv_usec >= then->tv_usec) ?
94 now->tv_usec - then->tv_usec :
95 1000000 - (then->tv_usec - now->tv_usec);
96 }
97
98 u32 via_get_vblank_counter(struct drm_device *dev, int crtc)
99 {
100 drm_via_private_t *dev_priv = dev->dev_private;
101 if (crtc != 0)
102 return 0;
103
104 return atomic_read(&dev_priv->vbl_received);
105 }
106
107 irqreturn_t via_driver_irq_handler(int irq, void *arg)
108 {
109 struct drm_device *dev = (struct drm_device *) arg;
110 drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
111 u32 status;
112 int handled = 0;
113 struct timeval cur_vblank;
114 drm_via_irq_t *cur_irq = dev_priv->via_irqs;
115 int i;
116
117 status = VIA_READ(VIA_REG_INTERRUPT);
118 if (status & VIA_IRQ_VBLANK_PENDING) {
119 atomic_inc(&dev_priv->vbl_received);
120 if (!(atomic_read(&dev_priv->vbl_received) & 0x0F)) {
121 do_gettimeofday(&cur_vblank);
122 if (dev_priv->last_vblank_valid) {
123 dev_priv->usec_per_vblank =
124 time_diff(&cur_vblank,
125 &dev_priv->last_vblank) >> 4;
126 }
127 dev_priv->last_vblank = cur_vblank;
128 dev_priv->last_vblank_valid = 1;
129 }
130 if (!(atomic_read(&dev_priv->vbl_received) & 0xFF)) {
131 DRM_DEBUG("US per vblank is: %u\n",
132 dev_priv->usec_per_vblank);
133 }
134 drm_handle_vblank(dev, 0);
135 handled = 1;
136 }
137
138 for (i = 0; i < dev_priv->num_irqs; ++i) {
139 if (status & cur_irq->pending_mask) {
140 #ifdef __NetBSD__
141 spin_lock(&cur_irq->irq_lock);
142 cur_irq->irq_received++;
143 DRM_SPIN_WAKEUP_ONE(&cur_irq->irq_queue,
144 &cur_irq->irq_lock);
145 spin_unlock(&cur_irq->irq_lock);
146 #else
147 atomic_inc(&cur_irq->irq_received);
148 wake_up(&cur_irq->irq_queue);
149 #endif
150 handled = 1;
151 if (dev_priv->irq_map[drm_via_irq_dma0_td] == i)
152 via_dmablit_handler(dev, 0, 1);
153 else if (dev_priv->irq_map[drm_via_irq_dma1_td] == i)
154 via_dmablit_handler(dev, 1, 1);
155 }
156 cur_irq++;
157 }
158
159 /* Acknowledge interrupts */
160 VIA_WRITE(VIA_REG_INTERRUPT, status);
161
162
163 if (handled)
164 return IRQ_HANDLED;
165 else
166 return IRQ_NONE;
167 }
168
169 static __inline__ void viadrv_acknowledge_irqs(drm_via_private_t *dev_priv)
170 {
171 u32 status;
172
173 if (dev_priv) {
174 /* Acknowledge interrupts */
175 status = VIA_READ(VIA_REG_INTERRUPT);
176 VIA_WRITE(VIA_REG_INTERRUPT, status |
177 dev_priv->irq_pending_mask);
178 }
179 }
180
181 int via_enable_vblank(struct drm_device *dev, int crtc)
182 {
183 drm_via_private_t *dev_priv = dev->dev_private;
184 u32 status;
185
186 if (crtc != 0) {
187 DRM_ERROR("%s: bad crtc %d\n", __func__, crtc);
188 return -EINVAL;
189 }
190
191 status = VIA_READ(VIA_REG_INTERRUPT);
192 VIA_WRITE(VIA_REG_INTERRUPT, status | VIA_IRQ_VBLANK_ENABLE);
193
194 VIA_WRITE8(0x83d4, 0x11);
195 VIA_WRITE8(0x83d5, VIA_READ8(0x83d5) | 0x30);
196
197 return 0;
198 }
199
200 void via_disable_vblank(struct drm_device *dev, int crtc)
201 {
202 drm_via_private_t *dev_priv = dev->dev_private;
203 u32 status;
204
205 status = VIA_READ(VIA_REG_INTERRUPT);
206 VIA_WRITE(VIA_REG_INTERRUPT, status & ~VIA_IRQ_VBLANK_ENABLE);
207
208 VIA_WRITE8(0x83d4, 0x11);
209 VIA_WRITE8(0x83d5, VIA_READ8(0x83d5) & ~0x30);
210
211 if (crtc != 0)
212 DRM_ERROR("%s: bad crtc %d\n", __func__, crtc);
213 }
214
215 static int
216 via_driver_irq_wait(struct drm_device *dev, unsigned int irq, int force_sequence,
217 unsigned int *sequence)
218 {
219 drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
220 unsigned int cur_irq_sequence;
221 drm_via_irq_t *cur_irq;
222 int ret = 0;
223 maskarray_t *masks;
224 int real_irq;
225
226 DRM_DEBUG("\n");
227
228 if (!dev_priv) {
229 DRM_ERROR("called with no initialization\n");
230 return -EINVAL;
231 }
232
233 if (irq >= drm_via_irq_num) {
234 DRM_ERROR("Trying to wait on unknown irq %d\n", irq);
235 return -EINVAL;
236 }
237
238 real_irq = dev_priv->irq_map[irq];
239
240 if (real_irq < 0) {
241 DRM_ERROR("Video IRQ %d not available on this hardware.\n",
242 irq);
243 return -EINVAL;
244 }
245
246 masks = dev_priv->irq_masks;
247 cur_irq = dev_priv->via_irqs + real_irq;
248
249 #ifdef __NetBSD__
250 spin_lock(&cur_irq->irq_lock);
251 if (masks[real_irq][2] && !force_sequence) {
252 DRM_SPIN_TIMED_WAIT_UNTIL(ret, &cur_irq->irq_queue,
253 &cur_irq->irq_lock, 3 * DRM_HZ,
254 ((VIA_READ(masks[irq][2]) & masks[irq][3]) ==
255 masks[irq][4]));
256 cur_irq_sequence = cur_irq->irq_received;
257 } else {
258 DRM_SPIN_TIMED_WAIT_UNTIL(ret, &cur_irq->irq_queue,
259 &cur_irq->irq_lock, 3 * DRM_HZ,
260 (((cur_irq_sequence = cur_irq->irq_received) -
261 *sequence) <= (1 << 23)));
262 }
263 if (ret < 0) /* Failure: return negative error as is. */
264 ;
265 else if (ret == 0) /* Timed out: return -EBUSY like Linux. */
266 ret = -EBUSY;
267 else /* Success (ret > 0): return 0. */
268 ret = 0;
269 spin_unlock(&cur_irq->irq_lock);
270 #else
271 if (masks[real_irq][2] && !force_sequence) {
272 DRM_WAIT_ON(ret, cur_irq->irq_queue, 3 * HZ,
273 ((VIA_READ(masks[irq][2]) & masks[irq][3]) ==
274 masks[irq][4]));
275 cur_irq_sequence = atomic_read(&cur_irq->irq_received);
276 } else {
277 DRM_WAIT_ON(ret, cur_irq->irq_queue, 3 * HZ,
278 (((cur_irq_sequence =
279 atomic_read(&cur_irq->irq_received)) -
280 *sequence) <= (1 << 23)));
281 }
282 #endif
283 *sequence = cur_irq_sequence;
284 return ret;
285 }
286
287
288 /*
289 * drm_dma.h hooks
290 */
291
292 void via_driver_irq_preinstall(struct drm_device *dev)
293 {
294 drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
295 u32 status;
296 drm_via_irq_t *cur_irq;
297 int i;
298
299 DRM_DEBUG("dev_priv: %p\n", dev_priv);
300 if (dev_priv) {
301 cur_irq = dev_priv->via_irqs;
302
303 dev_priv->irq_enable_mask = VIA_IRQ_VBLANK_ENABLE;
304 dev_priv->irq_pending_mask = VIA_IRQ_VBLANK_PENDING;
305
306 if (dev_priv->chipset == VIA_PRO_GROUP_A ||
307 dev_priv->chipset == VIA_DX9_0) {
308 dev_priv->irq_masks = via_pro_group_a_irqs;
309 dev_priv->num_irqs = via_num_pro_group_a;
310 dev_priv->irq_map = via_irqmap_pro_group_a;
311 } else {
312 dev_priv->irq_masks = via_unichrome_irqs;
313 dev_priv->num_irqs = via_num_unichrome;
314 dev_priv->irq_map = via_irqmap_unichrome;
315 }
316
317 for (i = 0; i < dev_priv->num_irqs; ++i) {
318 #ifdef __NetBSD__
319 spin_lock_init(&cur_irq->irq_lock);
320 cur_irq->irq_received = 0;
321 #else
322 atomic_set(&cur_irq->irq_received, 0);
323 #endif
324 cur_irq->enable_mask = dev_priv->irq_masks[i][0];
325 cur_irq->pending_mask = dev_priv->irq_masks[i][1];
326 #ifdef __NetBSD__
327 DRM_INIT_WAITQUEUE(&cur_irq->irq_queue, "viairq");
328 #else
329 init_waitqueue_head(&cur_irq->irq_queue);
330 #endif
331 dev_priv->irq_enable_mask |= cur_irq->enable_mask;
332 dev_priv->irq_pending_mask |= cur_irq->pending_mask;
333 cur_irq++;
334
335 DRM_DEBUG("Initializing IRQ %d\n", i);
336 }
337
338 dev_priv->last_vblank_valid = 0;
339
340 /* Clear VSync interrupt regs */
341 status = VIA_READ(VIA_REG_INTERRUPT);
342 VIA_WRITE(VIA_REG_INTERRUPT, status &
343 ~(dev_priv->irq_enable_mask));
344
345 /* Clear bits if they're already high */
346 viadrv_acknowledge_irqs(dev_priv);
347 }
348 }
349
350 int via_driver_irq_postinstall(struct drm_device *dev)
351 {
352 drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
353 u32 status;
354
355 DRM_DEBUG("via_driver_irq_postinstall\n");
356 if (!dev_priv)
357 return -EINVAL;
358
359 status = VIA_READ(VIA_REG_INTERRUPT);
360 VIA_WRITE(VIA_REG_INTERRUPT, status | VIA_IRQ_GLOBAL
361 | dev_priv->irq_enable_mask);
362
363 /* Some magic, oh for some data sheets ! */
364 VIA_WRITE8(0x83d4, 0x11);
365 VIA_WRITE8(0x83d5, VIA_READ8(0x83d5) | 0x30);
366
367 return 0;
368 }
369
370 void via_driver_irq_uninstall(struct drm_device *dev)
371 {
372 drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
373 u32 status;
374
375 DRM_DEBUG("\n");
376 if (dev_priv) {
377
378 /* Some more magic, oh for some data sheets ! */
379
380 VIA_WRITE8(0x83d4, 0x11);
381 VIA_WRITE8(0x83d5, VIA_READ8(0x83d5) & ~0x30);
382
383 status = VIA_READ(VIA_REG_INTERRUPT);
384 VIA_WRITE(VIA_REG_INTERRUPT, status &
385 ~(VIA_IRQ_VBLANK_ENABLE | dev_priv->irq_enable_mask));
386
387 #ifdef __NetBSD__
388 {
389 int i;
390
391 for (i = 0; i < dev_priv->num_irqs; i++) {
392 DRM_DESTROY_WAITQUEUE(&dev_priv->via_irqs[i].irq_queue);
393 spin_lock_destroy(&dev_priv->via_irqs[i].irq_lock);
394 }
395 }
396 #endif
397 }
398 }
399
400 int via_wait_irq(struct drm_device *dev, void *data, struct drm_file *file_priv)
401 {
402 drm_via_irqwait_t *irqwait = data;
403 struct timeval now;
404 int ret = 0;
405 drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
406 drm_via_irq_t *cur_irq = dev_priv->via_irqs;
407 int force_sequence;
408
409 if (irqwait->request.irq >= dev_priv->num_irqs) {
410 DRM_ERROR("Trying to wait on unknown irq %d\n",
411 irqwait->request.irq);
412 return -EINVAL;
413 }
414
415 cur_irq += irqwait->request.irq;
416
417 switch (irqwait->request.type & ~VIA_IRQ_FLAGS_MASK) {
418 case VIA_IRQ_RELATIVE:
419 #ifdef __NetBSD__
420 irqwait->request.sequence += cur_irq->irq_received;
421 #else
422 irqwait->request.sequence +=
423 atomic_read(&cur_irq->irq_received);
424 #endif
425 irqwait->request.type &= ~_DRM_VBLANK_RELATIVE;
426 case VIA_IRQ_ABSOLUTE:
427 break;
428 default:
429 return -EINVAL;
430 }
431
432 if (irqwait->request.type & VIA_IRQ_SIGNAL) {
433 DRM_ERROR("Signals on Via IRQs not implemented yet.\n");
434 return -EINVAL;
435 }
436
437 force_sequence = (irqwait->request.type & VIA_IRQ_FORCE_SEQUENCE);
438
439 ret = via_driver_irq_wait(dev, irqwait->request.irq, force_sequence,
440 &irqwait->request.sequence);
441 do_gettimeofday(&now);
442 irqwait->reply.tval_sec = now.tv_sec;
443 irqwait->reply.tval_usec = now.tv_usec;
444
445 return ret;
446 }
447