vmwgfx_drv.c revision 1.1.1.3
1 /* $NetBSD: vmwgfx_drv.c,v 1.1.1.3 2018/08/27 01:34:59 riastradh Exp $ */ 2 3 /************************************************************************** 4 * 5 * Copyright 2009-2015 VMware, Inc., Palo Alto, CA., USA 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 22 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 23 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 24 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 25 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 26 * USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 **************************************************************************/ 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: vmwgfx_drv.c,v 1.1.1.3 2018/08/27 01:34:59 riastradh Exp $"); 31 32 #include <linux/module.h> 33 #include <linux/console.h> 34 35 #include <drm/drmP.h> 36 #include "vmwgfx_drv.h" 37 #include "vmwgfx_binding.h" 38 #include <drm/ttm/ttm_placement.h> 39 #include <drm/ttm/ttm_bo_driver.h> 40 #include <drm/ttm/ttm_object.h> 41 #include <drm/ttm/ttm_module.h> 42 #include <linux/dma_remapping.h> 43 44 #define VMWGFX_DRIVER_NAME "vmwgfx" 45 #define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices" 46 #define VMWGFX_CHIP_SVGAII 0 47 #define VMW_FB_RESERVATION 0 48 49 #define VMW_MIN_INITIAL_WIDTH 800 50 #define VMW_MIN_INITIAL_HEIGHT 600 51 52 53 /** 54 * Fully encoded drm commands. Might move to vmw_drm.h 55 */ 56 57 #define DRM_IOCTL_VMW_GET_PARAM \ 58 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM, \ 59 struct drm_vmw_getparam_arg) 60 #define DRM_IOCTL_VMW_ALLOC_DMABUF \ 61 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF, \ 62 union drm_vmw_alloc_dmabuf_arg) 63 #define DRM_IOCTL_VMW_UNREF_DMABUF \ 64 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF, \ 65 struct drm_vmw_unref_dmabuf_arg) 66 #define DRM_IOCTL_VMW_CURSOR_BYPASS \ 67 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS, \ 68 struct drm_vmw_cursor_bypass_arg) 69 70 #define DRM_IOCTL_VMW_CONTROL_STREAM \ 71 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM, \ 72 struct drm_vmw_control_stream_arg) 73 #define DRM_IOCTL_VMW_CLAIM_STREAM \ 74 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM, \ 75 struct drm_vmw_stream_arg) 76 #define DRM_IOCTL_VMW_UNREF_STREAM \ 77 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM, \ 78 struct drm_vmw_stream_arg) 79 80 #define DRM_IOCTL_VMW_CREATE_CONTEXT \ 81 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT, \ 82 struct drm_vmw_context_arg) 83 #define DRM_IOCTL_VMW_UNREF_CONTEXT \ 84 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT, \ 85 struct drm_vmw_context_arg) 86 #define DRM_IOCTL_VMW_CREATE_SURFACE \ 87 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE, \ 88 union drm_vmw_surface_create_arg) 89 #define DRM_IOCTL_VMW_UNREF_SURFACE \ 90 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE, \ 91 struct drm_vmw_surface_arg) 92 #define DRM_IOCTL_VMW_REF_SURFACE \ 93 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE, \ 94 union drm_vmw_surface_reference_arg) 95 #define DRM_IOCTL_VMW_EXECBUF \ 96 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF, \ 97 struct drm_vmw_execbuf_arg) 98 #define DRM_IOCTL_VMW_GET_3D_CAP \ 99 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP, \ 100 struct drm_vmw_get_3d_cap_arg) 101 #define DRM_IOCTL_VMW_FENCE_WAIT \ 102 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT, \ 103 struct drm_vmw_fence_wait_arg) 104 #define DRM_IOCTL_VMW_FENCE_SIGNALED \ 105 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED, \ 106 struct drm_vmw_fence_signaled_arg) 107 #define DRM_IOCTL_VMW_FENCE_UNREF \ 108 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF, \ 109 struct drm_vmw_fence_arg) 110 #define DRM_IOCTL_VMW_FENCE_EVENT \ 111 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT, \ 112 struct drm_vmw_fence_event_arg) 113 #define DRM_IOCTL_VMW_PRESENT \ 114 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT, \ 115 struct drm_vmw_present_arg) 116 #define DRM_IOCTL_VMW_PRESENT_READBACK \ 117 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK, \ 118 struct drm_vmw_present_readback_arg) 119 #define DRM_IOCTL_VMW_UPDATE_LAYOUT \ 120 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT, \ 121 struct drm_vmw_update_layout_arg) 122 #define DRM_IOCTL_VMW_CREATE_SHADER \ 123 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SHADER, \ 124 struct drm_vmw_shader_create_arg) 125 #define DRM_IOCTL_VMW_UNREF_SHADER \ 126 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SHADER, \ 127 struct drm_vmw_shader_arg) 128 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE \ 129 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE, \ 130 union drm_vmw_gb_surface_create_arg) 131 #define DRM_IOCTL_VMW_GB_SURFACE_REF \ 132 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF, \ 133 union drm_vmw_gb_surface_reference_arg) 134 #define DRM_IOCTL_VMW_SYNCCPU \ 135 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_SYNCCPU, \ 136 struct drm_vmw_synccpu_arg) 137 #define DRM_IOCTL_VMW_CREATE_EXTENDED_CONTEXT \ 138 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_EXTENDED_CONTEXT, \ 139 struct drm_vmw_context_arg) 140 141 /** 142 * The core DRM version of this macro doesn't account for 143 * DRM_COMMAND_BASE. 144 */ 145 146 #define VMW_IOCTL_DEF(ioctl, func, flags) \ 147 [DRM_IOCTL_NR(DRM_IOCTL_##ioctl) - DRM_COMMAND_BASE] = {DRM_IOCTL_##ioctl, flags, func} 148 149 /** 150 * Ioctl definitions. 151 */ 152 153 static const struct drm_ioctl_desc vmw_ioctls[] = { 154 VMW_IOCTL_DEF(VMW_GET_PARAM, vmw_getparam_ioctl, 155 DRM_AUTH | DRM_RENDER_ALLOW), 156 VMW_IOCTL_DEF(VMW_ALLOC_DMABUF, vmw_dmabuf_alloc_ioctl, 157 DRM_AUTH | DRM_RENDER_ALLOW), 158 VMW_IOCTL_DEF(VMW_UNREF_DMABUF, vmw_dmabuf_unref_ioctl, 159 DRM_RENDER_ALLOW), 160 VMW_IOCTL_DEF(VMW_CURSOR_BYPASS, 161 vmw_kms_cursor_bypass_ioctl, 162 DRM_MASTER | DRM_CONTROL_ALLOW), 163 164 VMW_IOCTL_DEF(VMW_CONTROL_STREAM, vmw_overlay_ioctl, 165 DRM_MASTER | DRM_CONTROL_ALLOW), 166 VMW_IOCTL_DEF(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl, 167 DRM_MASTER | DRM_CONTROL_ALLOW), 168 VMW_IOCTL_DEF(VMW_UNREF_STREAM, vmw_stream_unref_ioctl, 169 DRM_MASTER | DRM_CONTROL_ALLOW), 170 171 VMW_IOCTL_DEF(VMW_CREATE_CONTEXT, vmw_context_define_ioctl, 172 DRM_AUTH | DRM_RENDER_ALLOW), 173 VMW_IOCTL_DEF(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl, 174 DRM_RENDER_ALLOW), 175 VMW_IOCTL_DEF(VMW_CREATE_SURFACE, vmw_surface_define_ioctl, 176 DRM_AUTH | DRM_RENDER_ALLOW), 177 VMW_IOCTL_DEF(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl, 178 DRM_RENDER_ALLOW), 179 VMW_IOCTL_DEF(VMW_REF_SURFACE, vmw_surface_reference_ioctl, 180 DRM_AUTH | DRM_RENDER_ALLOW), 181 VMW_IOCTL_DEF(VMW_EXECBUF, NULL, DRM_AUTH | 182 DRM_RENDER_ALLOW), 183 VMW_IOCTL_DEF(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl, 184 DRM_RENDER_ALLOW), 185 VMW_IOCTL_DEF(VMW_FENCE_SIGNALED, 186 vmw_fence_obj_signaled_ioctl, 187 DRM_RENDER_ALLOW), 188 VMW_IOCTL_DEF(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl, 189 DRM_RENDER_ALLOW), 190 VMW_IOCTL_DEF(VMW_FENCE_EVENT, vmw_fence_event_ioctl, 191 DRM_AUTH | DRM_RENDER_ALLOW), 192 VMW_IOCTL_DEF(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl, 193 DRM_AUTH | DRM_RENDER_ALLOW), 194 195 /* these allow direct access to the framebuffers mark as master only */ 196 VMW_IOCTL_DEF(VMW_PRESENT, vmw_present_ioctl, 197 DRM_MASTER | DRM_AUTH), 198 VMW_IOCTL_DEF(VMW_PRESENT_READBACK, 199 vmw_present_readback_ioctl, 200 DRM_MASTER | DRM_AUTH), 201 VMW_IOCTL_DEF(VMW_UPDATE_LAYOUT, 202 vmw_kms_update_layout_ioctl, 203 DRM_MASTER), 204 VMW_IOCTL_DEF(VMW_CREATE_SHADER, 205 vmw_shader_define_ioctl, 206 DRM_AUTH | DRM_RENDER_ALLOW), 207 VMW_IOCTL_DEF(VMW_UNREF_SHADER, 208 vmw_shader_destroy_ioctl, 209 DRM_RENDER_ALLOW), 210 VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE, 211 vmw_gb_surface_define_ioctl, 212 DRM_AUTH | DRM_RENDER_ALLOW), 213 VMW_IOCTL_DEF(VMW_GB_SURFACE_REF, 214 vmw_gb_surface_reference_ioctl, 215 DRM_AUTH | DRM_RENDER_ALLOW), 216 VMW_IOCTL_DEF(VMW_SYNCCPU, 217 vmw_user_dmabuf_synccpu_ioctl, 218 DRM_RENDER_ALLOW), 219 VMW_IOCTL_DEF(VMW_CREATE_EXTENDED_CONTEXT, 220 vmw_extended_context_define_ioctl, 221 DRM_AUTH | DRM_RENDER_ALLOW), 222 }; 223 224 static struct pci_device_id vmw_pci_id_list[] = { 225 {0x15ad, 0x0405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VMWGFX_CHIP_SVGAII}, 226 {0, 0, 0} 227 }; 228 MODULE_DEVICE_TABLE(pci, vmw_pci_id_list); 229 230 static int enable_fbdev = IS_ENABLED(CONFIG_DRM_VMWGFX_FBCON); 231 static int vmw_force_iommu; 232 static int vmw_restrict_iommu; 233 static int vmw_force_coherent; 234 static int vmw_restrict_dma_mask; 235 static int vmw_assume_16bpp; 236 237 static int vmw_probe(struct pci_dev *, const struct pci_device_id *); 238 static void vmw_master_init(struct vmw_master *); 239 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, 240 void *ptr); 241 242 MODULE_PARM_DESC(enable_fbdev, "Enable vmwgfx fbdev"); 243 module_param_named(enable_fbdev, enable_fbdev, int, 0600); 244 MODULE_PARM_DESC(force_dma_api, "Force using the DMA API for TTM pages"); 245 module_param_named(force_dma_api, vmw_force_iommu, int, 0600); 246 MODULE_PARM_DESC(restrict_iommu, "Try to limit IOMMU usage for TTM pages"); 247 module_param_named(restrict_iommu, vmw_restrict_iommu, int, 0600); 248 MODULE_PARM_DESC(force_coherent, "Force coherent TTM pages"); 249 module_param_named(force_coherent, vmw_force_coherent, int, 0600); 250 MODULE_PARM_DESC(restrict_dma_mask, "Restrict DMA mask to 44 bits with IOMMU"); 251 module_param_named(restrict_dma_mask, vmw_restrict_dma_mask, int, 0600); 252 MODULE_PARM_DESC(assume_16bpp, "Assume 16-bpp when filtering modes"); 253 module_param_named(assume_16bpp, vmw_assume_16bpp, int, 0600); 254 255 256 static void vmw_print_capabilities(uint32_t capabilities) 257 { 258 DRM_INFO("Capabilities:\n"); 259 if (capabilities & SVGA_CAP_RECT_COPY) 260 DRM_INFO(" Rect copy.\n"); 261 if (capabilities & SVGA_CAP_CURSOR) 262 DRM_INFO(" Cursor.\n"); 263 if (capabilities & SVGA_CAP_CURSOR_BYPASS) 264 DRM_INFO(" Cursor bypass.\n"); 265 if (capabilities & SVGA_CAP_CURSOR_BYPASS_2) 266 DRM_INFO(" Cursor bypass 2.\n"); 267 if (capabilities & SVGA_CAP_8BIT_EMULATION) 268 DRM_INFO(" 8bit emulation.\n"); 269 if (capabilities & SVGA_CAP_ALPHA_CURSOR) 270 DRM_INFO(" Alpha cursor.\n"); 271 if (capabilities & SVGA_CAP_3D) 272 DRM_INFO(" 3D.\n"); 273 if (capabilities & SVGA_CAP_EXTENDED_FIFO) 274 DRM_INFO(" Extended Fifo.\n"); 275 if (capabilities & SVGA_CAP_MULTIMON) 276 DRM_INFO(" Multimon.\n"); 277 if (capabilities & SVGA_CAP_PITCHLOCK) 278 DRM_INFO(" Pitchlock.\n"); 279 if (capabilities & SVGA_CAP_IRQMASK) 280 DRM_INFO(" Irq mask.\n"); 281 if (capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) 282 DRM_INFO(" Display Topology.\n"); 283 if (capabilities & SVGA_CAP_GMR) 284 DRM_INFO(" GMR.\n"); 285 if (capabilities & SVGA_CAP_TRACES) 286 DRM_INFO(" Traces.\n"); 287 if (capabilities & SVGA_CAP_GMR2) 288 DRM_INFO(" GMR2.\n"); 289 if (capabilities & SVGA_CAP_SCREEN_OBJECT_2) 290 DRM_INFO(" Screen Object 2.\n"); 291 if (capabilities & SVGA_CAP_COMMAND_BUFFERS) 292 DRM_INFO(" Command Buffers.\n"); 293 if (capabilities & SVGA_CAP_CMD_BUFFERS_2) 294 DRM_INFO(" Command Buffers 2.\n"); 295 if (capabilities & SVGA_CAP_GBOBJECTS) 296 DRM_INFO(" Guest Backed Resources.\n"); 297 if (capabilities & SVGA_CAP_DX) 298 DRM_INFO(" DX Features.\n"); 299 } 300 301 /** 302 * vmw_dummy_query_bo_create - create a bo to hold a dummy query result 303 * 304 * @dev_priv: A device private structure. 305 * 306 * This function creates a small buffer object that holds the query 307 * result for dummy queries emitted as query barriers. 308 * The function will then map the first page and initialize a pending 309 * occlusion query result structure, Finally it will unmap the buffer. 310 * No interruptible waits are done within this function. 311 * 312 * Returns an error if bo creation or initialization fails. 313 */ 314 static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv) 315 { 316 int ret; 317 struct vmw_dma_buffer *vbo; 318 struct ttm_bo_kmap_obj map; 319 volatile SVGA3dQueryResult *result; 320 bool dummy; 321 322 /* 323 * Create the vbo as pinned, so that a tryreserve will 324 * immediately succeed. This is because we're the only 325 * user of the bo currently. 326 */ 327 vbo = kzalloc(sizeof(*vbo), GFP_KERNEL); 328 if (!vbo) 329 return -ENOMEM; 330 331 ret = vmw_dmabuf_init(dev_priv, vbo, PAGE_SIZE, 332 &vmw_sys_ne_placement, false, 333 &vmw_dmabuf_bo_free); 334 if (unlikely(ret != 0)) 335 return ret; 336 337 ret = ttm_bo_reserve(&vbo->base, false, true, false, NULL); 338 BUG_ON(ret != 0); 339 vmw_bo_pin_reserved(vbo, true); 340 341 ret = ttm_bo_kmap(&vbo->base, 0, 1, &map); 342 if (likely(ret == 0)) { 343 result = ttm_kmap_obj_virtual(&map, &dummy); 344 result->totalSize = sizeof(*result); 345 result->state = SVGA3D_QUERYSTATE_PENDING; 346 result->result32 = 0xff; 347 ttm_bo_kunmap(&map); 348 } 349 vmw_bo_pin_reserved(vbo, false); 350 ttm_bo_unreserve(&vbo->base); 351 352 if (unlikely(ret != 0)) { 353 DRM_ERROR("Dummy query buffer map failed.\n"); 354 vmw_dmabuf_unreference(&vbo); 355 } else 356 dev_priv->dummy_query_bo = vbo; 357 358 return ret; 359 } 360 361 /** 362 * vmw_request_device_late - Perform late device setup 363 * 364 * @dev_priv: Pointer to device private. 365 * 366 * This function performs setup of otables and enables large command 367 * buffer submission. These tasks are split out to a separate function 368 * because it reverts vmw_release_device_early and is intended to be used 369 * by an error path in the hibernation code. 370 */ 371 static int vmw_request_device_late(struct vmw_private *dev_priv) 372 { 373 int ret; 374 375 if (dev_priv->has_mob) { 376 ret = vmw_otables_setup(dev_priv); 377 if (unlikely(ret != 0)) { 378 DRM_ERROR("Unable to initialize " 379 "guest Memory OBjects.\n"); 380 return ret; 381 } 382 } 383 384 if (dev_priv->cman) { 385 ret = vmw_cmdbuf_set_pool_size(dev_priv->cman, 386 256*4096, 2*4096); 387 if (ret) { 388 struct vmw_cmdbuf_man *man = dev_priv->cman; 389 390 dev_priv->cman = NULL; 391 vmw_cmdbuf_man_destroy(man); 392 } 393 } 394 395 return 0; 396 } 397 398 static int vmw_request_device(struct vmw_private *dev_priv) 399 { 400 int ret; 401 402 ret = vmw_fifo_init(dev_priv, &dev_priv->fifo); 403 if (unlikely(ret != 0)) { 404 DRM_ERROR("Unable to initialize FIFO.\n"); 405 return ret; 406 } 407 vmw_fence_fifo_up(dev_priv->fman); 408 dev_priv->cman = vmw_cmdbuf_man_create(dev_priv); 409 if (IS_ERR(dev_priv->cman)) { 410 dev_priv->cman = NULL; 411 dev_priv->has_dx = false; 412 } 413 414 ret = vmw_request_device_late(dev_priv); 415 if (ret) 416 goto out_no_mob; 417 418 ret = vmw_dummy_query_bo_create(dev_priv); 419 if (unlikely(ret != 0)) 420 goto out_no_query_bo; 421 422 return 0; 423 424 out_no_query_bo: 425 if (dev_priv->cman) 426 vmw_cmdbuf_remove_pool(dev_priv->cman); 427 if (dev_priv->has_mob) { 428 (void) ttm_bo_evict_mm(&dev_priv->bdev, VMW_PL_MOB); 429 vmw_otables_takedown(dev_priv); 430 } 431 if (dev_priv->cman) 432 vmw_cmdbuf_man_destroy(dev_priv->cman); 433 out_no_mob: 434 vmw_fence_fifo_down(dev_priv->fman); 435 vmw_fifo_release(dev_priv, &dev_priv->fifo); 436 return ret; 437 } 438 439 /** 440 * vmw_release_device_early - Early part of fifo takedown. 441 * 442 * @dev_priv: Pointer to device private struct. 443 * 444 * This is the first part of command submission takedown, to be called before 445 * buffer management is taken down. 446 */ 447 static void vmw_release_device_early(struct vmw_private *dev_priv) 448 { 449 /* 450 * Previous destructions should've released 451 * the pinned bo. 452 */ 453 454 BUG_ON(dev_priv->pinned_bo != NULL); 455 456 vmw_dmabuf_unreference(&dev_priv->dummy_query_bo); 457 if (dev_priv->cman) 458 vmw_cmdbuf_remove_pool(dev_priv->cman); 459 460 if (dev_priv->has_mob) { 461 ttm_bo_evict_mm(&dev_priv->bdev, VMW_PL_MOB); 462 vmw_otables_takedown(dev_priv); 463 } 464 } 465 466 /** 467 * vmw_release_device_late - Late part of fifo takedown. 468 * 469 * @dev_priv: Pointer to device private struct. 470 * 471 * This is the last part of the command submission takedown, to be called when 472 * command submission is no longer needed. It may wait on pending fences. 473 */ 474 static void vmw_release_device_late(struct vmw_private *dev_priv) 475 { 476 vmw_fence_fifo_down(dev_priv->fman); 477 if (dev_priv->cman) 478 vmw_cmdbuf_man_destroy(dev_priv->cman); 479 480 vmw_fifo_release(dev_priv, &dev_priv->fifo); 481 } 482 483 /** 484 * Sets the initial_[width|height] fields on the given vmw_private. 485 * 486 * It does so by reading SVGA_REG_[WIDTH|HEIGHT] regs and then 487 * clamping the value to fb_max_[width|height] fields and the 488 * VMW_MIN_INITIAL_[WIDTH|HEIGHT]. 489 * If the values appear to be invalid, set them to 490 * VMW_MIN_INITIAL_[WIDTH|HEIGHT]. 491 */ 492 static void vmw_get_initial_size(struct vmw_private *dev_priv) 493 { 494 uint32_t width; 495 uint32_t height; 496 497 width = vmw_read(dev_priv, SVGA_REG_WIDTH); 498 height = vmw_read(dev_priv, SVGA_REG_HEIGHT); 499 500 width = max_t(uint32_t, width, VMW_MIN_INITIAL_WIDTH); 501 height = max_t(uint32_t, height, VMW_MIN_INITIAL_HEIGHT); 502 503 if (width > dev_priv->fb_max_width || 504 height > dev_priv->fb_max_height) { 505 506 /* 507 * This is a host error and shouldn't occur. 508 */ 509 510 width = VMW_MIN_INITIAL_WIDTH; 511 height = VMW_MIN_INITIAL_HEIGHT; 512 } 513 514 dev_priv->initial_width = width; 515 dev_priv->initial_height = height; 516 } 517 518 /** 519 * vmw_dma_select_mode - Determine how DMA mappings should be set up for this 520 * system. 521 * 522 * @dev_priv: Pointer to a struct vmw_private 523 * 524 * This functions tries to determine the IOMMU setup and what actions 525 * need to be taken by the driver to make system pages visible to the 526 * device. 527 * If this function decides that DMA is not possible, it returns -EINVAL. 528 * The driver may then try to disable features of the device that require 529 * DMA. 530 */ 531 static int vmw_dma_select_mode(struct vmw_private *dev_priv) 532 { 533 static const char *names[vmw_dma_map_max] = { 534 [vmw_dma_phys] = "Using physical TTM page addresses.", 535 [vmw_dma_alloc_coherent] = "Using coherent TTM pages.", 536 [vmw_dma_map_populate] = "Keeping DMA mappings.", 537 [vmw_dma_map_bind] = "Giving up DMA mappings early."}; 538 #ifdef CONFIG_X86 539 const struct dma_map_ops *dma_ops = get_dma_ops(dev_priv->dev->dev); 540 541 #ifdef CONFIG_INTEL_IOMMU 542 if (intel_iommu_enabled) { 543 dev_priv->map_mode = vmw_dma_map_populate; 544 goto out_fixup; 545 } 546 #endif 547 548 if (!(vmw_force_iommu || vmw_force_coherent)) { 549 dev_priv->map_mode = vmw_dma_phys; 550 DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]); 551 return 0; 552 } 553 554 dev_priv->map_mode = vmw_dma_map_populate; 555 556 if (dma_ops->sync_single_for_cpu) 557 dev_priv->map_mode = vmw_dma_alloc_coherent; 558 #ifdef CONFIG_SWIOTLB 559 if (swiotlb_nr_tbl() == 0) 560 dev_priv->map_mode = vmw_dma_map_populate; 561 #endif 562 563 #ifdef CONFIG_INTEL_IOMMU 564 out_fixup: 565 #endif 566 if (dev_priv->map_mode == vmw_dma_map_populate && 567 vmw_restrict_iommu) 568 dev_priv->map_mode = vmw_dma_map_bind; 569 570 if (vmw_force_coherent) 571 dev_priv->map_mode = vmw_dma_alloc_coherent; 572 573 #if !defined(CONFIG_SWIOTLB) && !defined(CONFIG_INTEL_IOMMU) 574 /* 575 * No coherent page pool 576 */ 577 if (dev_priv->map_mode == vmw_dma_alloc_coherent) 578 return -EINVAL; 579 #endif 580 581 #else /* CONFIG_X86 */ 582 dev_priv->map_mode = vmw_dma_map_populate; 583 #endif /* CONFIG_X86 */ 584 585 DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]); 586 587 return 0; 588 } 589 590 /** 591 * vmw_dma_masks - set required page- and dma masks 592 * 593 * @dev: Pointer to struct drm-device 594 * 595 * With 32-bit we can only handle 32 bit PFNs. Optionally set that 596 * restriction also for 64-bit systems. 597 */ 598 #ifdef CONFIG_INTEL_IOMMU 599 static int vmw_dma_masks(struct vmw_private *dev_priv) 600 { 601 struct drm_device *dev = dev_priv->dev; 602 603 if (intel_iommu_enabled && 604 (sizeof(unsigned long) == 4 || vmw_restrict_dma_mask)) { 605 DRM_INFO("Restricting DMA addresses to 44 bits.\n"); 606 return dma_set_mask(dev->dev, DMA_BIT_MASK(44)); 607 } 608 return 0; 609 } 610 #else 611 static int vmw_dma_masks(struct vmw_private *dev_priv) 612 { 613 return 0; 614 } 615 #endif 616 617 static int vmw_driver_load(struct drm_device *dev, unsigned long chipset) 618 { 619 struct vmw_private *dev_priv; 620 int ret; 621 uint32_t svga_id; 622 enum vmw_res_type i; 623 bool refuse_dma = false; 624 625 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL); 626 if (unlikely(dev_priv == NULL)) { 627 DRM_ERROR("Failed allocating a device private struct.\n"); 628 return -ENOMEM; 629 } 630 631 pci_set_master(dev->pdev); 632 633 dev_priv->dev = dev; 634 dev_priv->vmw_chipset = chipset; 635 dev_priv->last_read_seqno = (uint32_t) -100; 636 mutex_init(&dev_priv->cmdbuf_mutex); 637 mutex_init(&dev_priv->release_mutex); 638 mutex_init(&dev_priv->binding_mutex); 639 rwlock_init(&dev_priv->resource_lock); 640 ttm_lock_init(&dev_priv->reservation_sem); 641 spin_lock_init(&dev_priv->hw_lock); 642 spin_lock_init(&dev_priv->waiter_lock); 643 spin_lock_init(&dev_priv->cap_lock); 644 spin_lock_init(&dev_priv->svga_lock); 645 646 for (i = vmw_res_context; i < vmw_res_max; ++i) { 647 idr_init(&dev_priv->res_idr[i]); 648 INIT_LIST_HEAD(&dev_priv->res_lru[i]); 649 } 650 651 mutex_init(&dev_priv->init_mutex); 652 init_waitqueue_head(&dev_priv->fence_queue); 653 init_waitqueue_head(&dev_priv->fifo_queue); 654 dev_priv->fence_queue_waiters = 0; 655 dev_priv->fifo_queue_waiters = 0; 656 657 dev_priv->used_memory_size = 0; 658 659 dev_priv->io_start = pci_resource_start(dev->pdev, 0); 660 dev_priv->vram_start = pci_resource_start(dev->pdev, 1); 661 dev_priv->mmio_start = pci_resource_start(dev->pdev, 2); 662 663 dev_priv->assume_16bpp = !!vmw_assume_16bpp; 664 665 dev_priv->enable_fb = enable_fbdev; 666 667 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2); 668 svga_id = vmw_read(dev_priv, SVGA_REG_ID); 669 if (svga_id != SVGA_ID_2) { 670 ret = -ENOSYS; 671 DRM_ERROR("Unsupported SVGA ID 0x%x\n", svga_id); 672 goto out_err0; 673 } 674 675 dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES); 676 ret = vmw_dma_select_mode(dev_priv); 677 if (unlikely(ret != 0)) { 678 DRM_INFO("Restricting capabilities due to IOMMU setup.\n"); 679 refuse_dma = true; 680 } 681 682 dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE); 683 dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE); 684 dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH); 685 dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT); 686 687 vmw_get_initial_size(dev_priv); 688 689 if (dev_priv->capabilities & SVGA_CAP_GMR2) { 690 dev_priv->max_gmr_ids = 691 vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS); 692 dev_priv->max_gmr_pages = 693 vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES); 694 dev_priv->memory_size = 695 vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE); 696 dev_priv->memory_size -= dev_priv->vram_size; 697 } else { 698 /* 699 * An arbitrary limit of 512MiB on surface 700 * memory. But all HWV8 hardware supports GMR2. 701 */ 702 dev_priv->memory_size = 512*1024*1024; 703 } 704 dev_priv->max_mob_pages = 0; 705 dev_priv->max_mob_size = 0; 706 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) { 707 uint64_t mem_size = 708 vmw_read(dev_priv, 709 SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB); 710 711 /* 712 * Workaround for low memory 2D VMs to compensate for the 713 * allocation taken by fbdev 714 */ 715 if (!(dev_priv->capabilities & SVGA_CAP_3D)) 716 mem_size *= 3; 717 718 dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE; 719 dev_priv->prim_bb_mem = 720 vmw_read(dev_priv, 721 SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM); 722 dev_priv->max_mob_size = 723 vmw_read(dev_priv, SVGA_REG_MOB_MAX_SIZE); 724 dev_priv->stdu_max_width = 725 vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_WIDTH); 726 dev_priv->stdu_max_height = 727 vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_HEIGHT); 728 729 vmw_write(dev_priv, SVGA_REG_DEV_CAP, 730 SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH); 731 dev_priv->texture_max_width = vmw_read(dev_priv, 732 SVGA_REG_DEV_CAP); 733 vmw_write(dev_priv, SVGA_REG_DEV_CAP, 734 SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT); 735 dev_priv->texture_max_height = vmw_read(dev_priv, 736 SVGA_REG_DEV_CAP); 737 } else { 738 dev_priv->texture_max_width = 8192; 739 dev_priv->texture_max_height = 8192; 740 dev_priv->prim_bb_mem = dev_priv->vram_size; 741 } 742 743 vmw_print_capabilities(dev_priv->capabilities); 744 745 ret = vmw_dma_masks(dev_priv); 746 if (unlikely(ret != 0)) 747 goto out_err0; 748 749 if (dev_priv->capabilities & SVGA_CAP_GMR2) { 750 DRM_INFO("Max GMR ids is %u\n", 751 (unsigned)dev_priv->max_gmr_ids); 752 DRM_INFO("Max number of GMR pages is %u\n", 753 (unsigned)dev_priv->max_gmr_pages); 754 DRM_INFO("Max dedicated hypervisor surface memory is %u kiB\n", 755 (unsigned)dev_priv->memory_size / 1024); 756 } 757 DRM_INFO("Maximum display memory size is %u kiB\n", 758 dev_priv->prim_bb_mem / 1024); 759 DRM_INFO("VRAM at 0x%08x size is %u kiB\n", 760 dev_priv->vram_start, dev_priv->vram_size / 1024); 761 DRM_INFO("MMIO at 0x%08x size is %u kiB\n", 762 dev_priv->mmio_start, dev_priv->mmio_size / 1024); 763 764 ret = vmw_ttm_global_init(dev_priv); 765 if (unlikely(ret != 0)) 766 goto out_err0; 767 768 769 vmw_master_init(&dev_priv->fbdev_master); 770 ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM); 771 dev_priv->active_master = &dev_priv->fbdev_master; 772 773 dev_priv->mmio_virt = memremap(dev_priv->mmio_start, 774 dev_priv->mmio_size, MEMREMAP_WB); 775 776 if (unlikely(dev_priv->mmio_virt == NULL)) { 777 ret = -ENOMEM; 778 DRM_ERROR("Failed mapping MMIO.\n"); 779 goto out_err3; 780 } 781 782 /* Need mmio memory to check for fifo pitchlock cap. */ 783 if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) && 784 !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) && 785 !vmw_fifo_have_pitchlock(dev_priv)) { 786 ret = -ENOSYS; 787 DRM_ERROR("Hardware has no pitchlock\n"); 788 goto out_err4; 789 } 790 791 dev_priv->tdev = ttm_object_device_init 792 (dev_priv->mem_global_ref.object, 12, &vmw_prime_dmabuf_ops); 793 794 if (unlikely(dev_priv->tdev == NULL)) { 795 DRM_ERROR("Unable to initialize TTM object management.\n"); 796 ret = -ENOMEM; 797 goto out_err4; 798 } 799 800 dev->dev_private = dev_priv; 801 802 ret = pci_request_regions(dev->pdev, "vmwgfx probe"); 803 dev_priv->stealth = (ret != 0); 804 if (dev_priv->stealth) { 805 /** 806 * Request at least the mmio PCI resource. 807 */ 808 809 DRM_INFO("It appears like vesafb is loaded. " 810 "Ignore above error if any.\n"); 811 ret = pci_request_region(dev->pdev, 2, "vmwgfx stealth probe"); 812 if (unlikely(ret != 0)) { 813 DRM_ERROR("Failed reserving the SVGA MMIO resource.\n"); 814 goto out_no_device; 815 } 816 } 817 818 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) { 819 ret = drm_irq_install(dev, dev->pdev->irq); 820 if (ret != 0) { 821 DRM_ERROR("Failed installing irq: %d\n", ret); 822 goto out_no_irq; 823 } 824 } 825 826 dev_priv->fman = vmw_fence_manager_init(dev_priv); 827 if (unlikely(dev_priv->fman == NULL)) { 828 ret = -ENOMEM; 829 goto out_no_fman; 830 } 831 832 ret = ttm_bo_device_init(&dev_priv->bdev, 833 dev_priv->bo_global_ref.ref.object, 834 &vmw_bo_driver, 835 dev->anon_inode->i_mapping, 836 VMWGFX_FILE_PAGE_OFFSET, 837 false); 838 if (unlikely(ret != 0)) { 839 DRM_ERROR("Failed initializing TTM buffer object driver.\n"); 840 goto out_no_bdev; 841 } 842 843 /* 844 * Enable VRAM, but initially don't use it until SVGA is enabled and 845 * unhidden. 846 */ 847 ret = ttm_bo_init_mm(&dev_priv->bdev, TTM_PL_VRAM, 848 (dev_priv->vram_size >> PAGE_SHIFT)); 849 if (unlikely(ret != 0)) { 850 DRM_ERROR("Failed initializing memory manager for VRAM.\n"); 851 goto out_no_vram; 852 } 853 dev_priv->bdev.man[TTM_PL_VRAM].use_type = false; 854 855 dev_priv->has_gmr = true; 856 if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) || 857 refuse_dma || ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_GMR, 858 VMW_PL_GMR) != 0) { 859 DRM_INFO("No GMR memory available. " 860 "Graphics memory resources are very limited.\n"); 861 dev_priv->has_gmr = false; 862 } 863 864 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) { 865 dev_priv->has_mob = true; 866 if (ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_MOB, 867 VMW_PL_MOB) != 0) { 868 DRM_INFO("No MOB memory available. " 869 "3D will be disabled.\n"); 870 dev_priv->has_mob = false; 871 } 872 } 873 874 if (dev_priv->has_mob) { 875 spin_lock(&dev_priv->cap_lock); 876 vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_DX); 877 dev_priv->has_dx = !!vmw_read(dev_priv, SVGA_REG_DEV_CAP); 878 spin_unlock(&dev_priv->cap_lock); 879 } 880 881 882 ret = vmw_kms_init(dev_priv); 883 if (unlikely(ret != 0)) 884 goto out_no_kms; 885 vmw_overlay_init(dev_priv); 886 887 ret = vmw_request_device(dev_priv); 888 if (ret) 889 goto out_no_fifo; 890 891 DRM_INFO("DX: %s\n", dev_priv->has_dx ? "yes." : "no."); 892 893 if (dev_priv->enable_fb) { 894 vmw_fifo_resource_inc(dev_priv); 895 vmw_svga_enable(dev_priv); 896 vmw_fb_init(dev_priv); 897 } 898 899 dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier; 900 register_pm_notifier(&dev_priv->pm_nb); 901 902 return 0; 903 904 out_no_fifo: 905 vmw_overlay_close(dev_priv); 906 vmw_kms_close(dev_priv); 907 out_no_kms: 908 if (dev_priv->has_mob) 909 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB); 910 if (dev_priv->has_gmr) 911 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR); 912 (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM); 913 out_no_vram: 914 (void)ttm_bo_device_release(&dev_priv->bdev); 915 out_no_bdev: 916 vmw_fence_manager_takedown(dev_priv->fman); 917 out_no_fman: 918 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) 919 drm_irq_uninstall(dev_priv->dev); 920 out_no_irq: 921 if (dev_priv->stealth) 922 pci_release_region(dev->pdev, 2); 923 else 924 pci_release_regions(dev->pdev); 925 out_no_device: 926 ttm_object_device_release(&dev_priv->tdev); 927 out_err4: 928 memunmap(dev_priv->mmio_virt); 929 out_err3: 930 vmw_ttm_global_release(dev_priv); 931 out_err0: 932 for (i = vmw_res_context; i < vmw_res_max; ++i) 933 idr_destroy(&dev_priv->res_idr[i]); 934 935 if (dev_priv->ctx.staged_bindings) 936 vmw_binding_state_free(dev_priv->ctx.staged_bindings); 937 kfree(dev_priv); 938 return ret; 939 } 940 941 static int vmw_driver_unload(struct drm_device *dev) 942 { 943 struct vmw_private *dev_priv = vmw_priv(dev); 944 enum vmw_res_type i; 945 946 unregister_pm_notifier(&dev_priv->pm_nb); 947 948 if (dev_priv->ctx.res_ht_initialized) 949 drm_ht_remove(&dev_priv->ctx.res_ht); 950 vfree(dev_priv->ctx.cmd_bounce); 951 if (dev_priv->enable_fb) { 952 vmw_fb_off(dev_priv); 953 vmw_fb_close(dev_priv); 954 vmw_fifo_resource_dec(dev_priv); 955 vmw_svga_disable(dev_priv); 956 } 957 958 vmw_kms_close(dev_priv); 959 vmw_overlay_close(dev_priv); 960 961 if (dev_priv->has_gmr) 962 (void)ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR); 963 (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM); 964 965 vmw_release_device_early(dev_priv); 966 if (dev_priv->has_mob) 967 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB); 968 (void) ttm_bo_device_release(&dev_priv->bdev); 969 vmw_release_device_late(dev_priv); 970 vmw_fence_manager_takedown(dev_priv->fman); 971 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) 972 drm_irq_uninstall(dev_priv->dev); 973 if (dev_priv->stealth) 974 pci_release_region(dev->pdev, 2); 975 else 976 pci_release_regions(dev->pdev); 977 978 ttm_object_device_release(&dev_priv->tdev); 979 memunmap(dev_priv->mmio_virt); 980 if (dev_priv->ctx.staged_bindings) 981 vmw_binding_state_free(dev_priv->ctx.staged_bindings); 982 vmw_ttm_global_release(dev_priv); 983 984 for (i = vmw_res_context; i < vmw_res_max; ++i) 985 idr_destroy(&dev_priv->res_idr[i]); 986 987 kfree(dev_priv); 988 989 return 0; 990 } 991 992 static void vmw_preclose(struct drm_device *dev, 993 struct drm_file *file_priv) 994 { 995 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); 996 struct vmw_private *dev_priv = vmw_priv(dev); 997 998 vmw_event_fence_fpriv_gone(dev_priv->fman, &vmw_fp->fence_events); 999 } 1000 1001 static void vmw_postclose(struct drm_device *dev, 1002 struct drm_file *file_priv) 1003 { 1004 struct vmw_fpriv *vmw_fp; 1005 1006 vmw_fp = vmw_fpriv(file_priv); 1007 1008 if (vmw_fp->locked_master) { 1009 struct vmw_master *vmaster = 1010 vmw_master(vmw_fp->locked_master); 1011 1012 ttm_lock_set_kill(&vmaster->lock, true, SIGTERM); 1013 ttm_vt_unlock(&vmaster->lock); 1014 drm_master_put(&vmw_fp->locked_master); 1015 } 1016 1017 ttm_object_file_release(&vmw_fp->tfile); 1018 kfree(vmw_fp); 1019 } 1020 1021 static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv) 1022 { 1023 struct vmw_private *dev_priv = vmw_priv(dev); 1024 struct vmw_fpriv *vmw_fp; 1025 int ret = -ENOMEM; 1026 1027 vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL); 1028 if (unlikely(vmw_fp == NULL)) 1029 return ret; 1030 1031 INIT_LIST_HEAD(&vmw_fp->fence_events); 1032 vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev, 10); 1033 if (unlikely(vmw_fp->tfile == NULL)) 1034 goto out_no_tfile; 1035 1036 file_priv->driver_priv = vmw_fp; 1037 1038 return 0; 1039 1040 out_no_tfile: 1041 kfree(vmw_fp); 1042 return ret; 1043 } 1044 1045 static struct vmw_master *vmw_master_check(struct drm_device *dev, 1046 struct drm_file *file_priv, 1047 unsigned int flags) 1048 { 1049 int ret; 1050 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); 1051 struct vmw_master *vmaster; 1052 1053 if (file_priv->minor->type != DRM_MINOR_LEGACY || 1054 !(flags & DRM_AUTH)) 1055 return NULL; 1056 1057 ret = mutex_lock_interruptible(&dev->master_mutex); 1058 if (unlikely(ret != 0)) 1059 return ERR_PTR(-ERESTARTSYS); 1060 1061 if (file_priv->is_master) { 1062 mutex_unlock(&dev->master_mutex); 1063 return NULL; 1064 } 1065 1066 /* 1067 * Check if we were previously master, but now dropped. In that 1068 * case, allow at least render node functionality. 1069 */ 1070 if (vmw_fp->locked_master) { 1071 mutex_unlock(&dev->master_mutex); 1072 1073 if (flags & DRM_RENDER_ALLOW) 1074 return NULL; 1075 1076 DRM_ERROR("Dropped master trying to access ioctl that " 1077 "requires authentication.\n"); 1078 return ERR_PTR(-EACCES); 1079 } 1080 mutex_unlock(&dev->master_mutex); 1081 1082 /* 1083 * Take the TTM lock. Possibly sleep waiting for the authenticating 1084 * master to become master again, or for a SIGTERM if the 1085 * authenticating master exits. 1086 */ 1087 vmaster = vmw_master(file_priv->master); 1088 ret = ttm_read_lock(&vmaster->lock, true); 1089 if (unlikely(ret != 0)) 1090 vmaster = ERR_PTR(ret); 1091 1092 return vmaster; 1093 } 1094 1095 static long vmw_generic_ioctl(struct file *filp, unsigned int cmd, 1096 unsigned long arg, 1097 long (*ioctl_func)(struct file *, unsigned int, 1098 unsigned long)) 1099 { 1100 struct drm_file *file_priv = filp->private_data; 1101 struct drm_device *dev = file_priv->minor->dev; 1102 unsigned int nr = DRM_IOCTL_NR(cmd); 1103 struct vmw_master *vmaster; 1104 unsigned int flags; 1105 long ret; 1106 1107 /* 1108 * Do extra checking on driver private ioctls. 1109 */ 1110 1111 if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END) 1112 && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) { 1113 const struct drm_ioctl_desc *ioctl = 1114 &vmw_ioctls[nr - DRM_COMMAND_BASE]; 1115 1116 if (nr == DRM_COMMAND_BASE + DRM_VMW_EXECBUF) { 1117 ret = (long) drm_ioctl_permit(ioctl->flags, file_priv); 1118 if (unlikely(ret != 0)) 1119 return ret; 1120 1121 if (unlikely((cmd & (IOC_IN | IOC_OUT)) != IOC_IN)) 1122 goto out_io_encoding; 1123 1124 return (long) vmw_execbuf_ioctl(dev, arg, file_priv, 1125 _IOC_SIZE(cmd)); 1126 } 1127 1128 if (unlikely(ioctl->cmd != cmd)) 1129 goto out_io_encoding; 1130 1131 flags = ioctl->flags; 1132 } else if (!drm_ioctl_flags(nr, &flags)) 1133 return -EINVAL; 1134 1135 vmaster = vmw_master_check(dev, file_priv, flags); 1136 if (IS_ERR(vmaster)) { 1137 ret = PTR_ERR(vmaster); 1138 1139 if (ret != -ERESTARTSYS) 1140 DRM_INFO("IOCTL ERROR Command %d, Error %ld.\n", 1141 nr, ret); 1142 return ret; 1143 } 1144 1145 ret = ioctl_func(filp, cmd, arg); 1146 if (vmaster) 1147 ttm_read_unlock(&vmaster->lock); 1148 1149 return ret; 1150 1151 out_io_encoding: 1152 DRM_ERROR("Invalid command format, ioctl %d\n", 1153 nr - DRM_COMMAND_BASE); 1154 1155 return -EINVAL; 1156 } 1157 1158 static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd, 1159 unsigned long arg) 1160 { 1161 return vmw_generic_ioctl(filp, cmd, arg, &drm_ioctl); 1162 } 1163 1164 #ifdef CONFIG_COMPAT 1165 static long vmw_compat_ioctl(struct file *filp, unsigned int cmd, 1166 unsigned long arg) 1167 { 1168 return vmw_generic_ioctl(filp, cmd, arg, &drm_compat_ioctl); 1169 } 1170 #endif 1171 1172 static void vmw_lastclose(struct drm_device *dev) 1173 { 1174 } 1175 1176 static void vmw_master_init(struct vmw_master *vmaster) 1177 { 1178 ttm_lock_init(&vmaster->lock); 1179 } 1180 1181 static int vmw_master_create(struct drm_device *dev, 1182 struct drm_master *master) 1183 { 1184 struct vmw_master *vmaster; 1185 1186 vmaster = kzalloc(sizeof(*vmaster), GFP_KERNEL); 1187 if (unlikely(vmaster == NULL)) 1188 return -ENOMEM; 1189 1190 vmw_master_init(vmaster); 1191 ttm_lock_set_kill(&vmaster->lock, true, SIGTERM); 1192 master->driver_priv = vmaster; 1193 1194 return 0; 1195 } 1196 1197 static void vmw_master_destroy(struct drm_device *dev, 1198 struct drm_master *master) 1199 { 1200 struct vmw_master *vmaster = vmw_master(master); 1201 1202 master->driver_priv = NULL; 1203 kfree(vmaster); 1204 } 1205 1206 static int vmw_master_set(struct drm_device *dev, 1207 struct drm_file *file_priv, 1208 bool from_open) 1209 { 1210 struct vmw_private *dev_priv = vmw_priv(dev); 1211 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); 1212 struct vmw_master *active = dev_priv->active_master; 1213 struct vmw_master *vmaster = vmw_master(file_priv->master); 1214 int ret = 0; 1215 1216 if (active) { 1217 BUG_ON(active != &dev_priv->fbdev_master); 1218 ret = ttm_vt_lock(&active->lock, false, vmw_fp->tfile); 1219 if (unlikely(ret != 0)) 1220 return ret; 1221 1222 ttm_lock_set_kill(&active->lock, true, SIGTERM); 1223 dev_priv->active_master = NULL; 1224 } 1225 1226 ttm_lock_set_kill(&vmaster->lock, false, SIGTERM); 1227 if (!from_open) { 1228 ttm_vt_unlock(&vmaster->lock); 1229 BUG_ON(vmw_fp->locked_master != file_priv->master); 1230 drm_master_put(&vmw_fp->locked_master); 1231 } 1232 1233 dev_priv->active_master = vmaster; 1234 1235 return 0; 1236 } 1237 1238 static void vmw_master_drop(struct drm_device *dev, 1239 struct drm_file *file_priv, 1240 bool from_release) 1241 { 1242 struct vmw_private *dev_priv = vmw_priv(dev); 1243 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); 1244 struct vmw_master *vmaster = vmw_master(file_priv->master); 1245 int ret; 1246 1247 /** 1248 * Make sure the master doesn't disappear while we have 1249 * it locked. 1250 */ 1251 1252 vmw_fp->locked_master = drm_master_get(file_priv->master); 1253 ret = ttm_vt_lock(&vmaster->lock, false, vmw_fp->tfile); 1254 vmw_kms_legacy_hotspot_clear(dev_priv); 1255 if (unlikely((ret != 0))) { 1256 DRM_ERROR("Unable to lock TTM at VT switch.\n"); 1257 drm_master_put(&vmw_fp->locked_master); 1258 } 1259 1260 ttm_lock_set_kill(&vmaster->lock, false, SIGTERM); 1261 1262 if (!dev_priv->enable_fb) 1263 vmw_svga_disable(dev_priv); 1264 1265 dev_priv->active_master = &dev_priv->fbdev_master; 1266 ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM); 1267 ttm_vt_unlock(&dev_priv->fbdev_master.lock); 1268 1269 if (dev_priv->enable_fb) 1270 vmw_fb_on(dev_priv); 1271 } 1272 1273 /** 1274 * __vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM. 1275 * 1276 * @dev_priv: Pointer to device private struct. 1277 * Needs the reservation sem to be held in non-exclusive mode. 1278 */ 1279 static void __vmw_svga_enable(struct vmw_private *dev_priv) 1280 { 1281 spin_lock(&dev_priv->svga_lock); 1282 if (!dev_priv->bdev.man[TTM_PL_VRAM].use_type) { 1283 vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE); 1284 dev_priv->bdev.man[TTM_PL_VRAM].use_type = true; 1285 } 1286 spin_unlock(&dev_priv->svga_lock); 1287 } 1288 1289 /** 1290 * vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM. 1291 * 1292 * @dev_priv: Pointer to device private struct. 1293 */ 1294 void vmw_svga_enable(struct vmw_private *dev_priv) 1295 { 1296 ttm_read_lock(&dev_priv->reservation_sem, false); 1297 __vmw_svga_enable(dev_priv); 1298 ttm_read_unlock(&dev_priv->reservation_sem); 1299 } 1300 1301 /** 1302 * __vmw_svga_disable - Disable SVGA mode and use of VRAM. 1303 * 1304 * @dev_priv: Pointer to device private struct. 1305 * Needs the reservation sem to be held in exclusive mode. 1306 * Will not empty VRAM. VRAM must be emptied by caller. 1307 */ 1308 static void __vmw_svga_disable(struct vmw_private *dev_priv) 1309 { 1310 spin_lock(&dev_priv->svga_lock); 1311 if (dev_priv->bdev.man[TTM_PL_VRAM].use_type) { 1312 dev_priv->bdev.man[TTM_PL_VRAM].use_type = false; 1313 vmw_write(dev_priv, SVGA_REG_ENABLE, 1314 SVGA_REG_ENABLE_HIDE | 1315 SVGA_REG_ENABLE_ENABLE); 1316 } 1317 spin_unlock(&dev_priv->svga_lock); 1318 } 1319 1320 /** 1321 * vmw_svga_disable - Disable SVGA_MODE, and use of VRAM. Keep the fifo 1322 * running. 1323 * 1324 * @dev_priv: Pointer to device private struct. 1325 * Will empty VRAM. 1326 */ 1327 void vmw_svga_disable(struct vmw_private *dev_priv) 1328 { 1329 ttm_write_lock(&dev_priv->reservation_sem, false); 1330 spin_lock(&dev_priv->svga_lock); 1331 if (dev_priv->bdev.man[TTM_PL_VRAM].use_type) { 1332 dev_priv->bdev.man[TTM_PL_VRAM].use_type = false; 1333 spin_unlock(&dev_priv->svga_lock); 1334 if (ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM)) 1335 DRM_ERROR("Failed evicting VRAM buffers.\n"); 1336 vmw_write(dev_priv, SVGA_REG_ENABLE, 1337 SVGA_REG_ENABLE_HIDE | 1338 SVGA_REG_ENABLE_ENABLE); 1339 } else 1340 spin_unlock(&dev_priv->svga_lock); 1341 ttm_write_unlock(&dev_priv->reservation_sem); 1342 } 1343 1344 static void vmw_remove(struct pci_dev *pdev) 1345 { 1346 struct drm_device *dev = pci_get_drvdata(pdev); 1347 1348 pci_disable_device(pdev); 1349 drm_put_dev(dev); 1350 } 1351 1352 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, 1353 void *ptr) 1354 { 1355 struct vmw_private *dev_priv = 1356 container_of(nb, struct vmw_private, pm_nb); 1357 1358 switch (val) { 1359 case PM_HIBERNATION_PREPARE: 1360 if (dev_priv->enable_fb) 1361 vmw_fb_off(dev_priv); 1362 ttm_suspend_lock(&dev_priv->reservation_sem); 1363 1364 /* 1365 * This empties VRAM and unbinds all GMR bindings. 1366 * Buffer contents is moved to swappable memory. 1367 */ 1368 vmw_execbuf_release_pinned_bo(dev_priv); 1369 vmw_resource_evict_all(dev_priv); 1370 vmw_release_device_early(dev_priv); 1371 ttm_bo_swapout_all(&dev_priv->bdev); 1372 vmw_fence_fifo_down(dev_priv->fman); 1373 break; 1374 case PM_POST_HIBERNATION: 1375 case PM_POST_RESTORE: 1376 vmw_fence_fifo_up(dev_priv->fman); 1377 ttm_suspend_unlock(&dev_priv->reservation_sem); 1378 if (dev_priv->enable_fb) 1379 vmw_fb_on(dev_priv); 1380 break; 1381 case PM_RESTORE_PREPARE: 1382 break; 1383 default: 1384 break; 1385 } 1386 return 0; 1387 } 1388 1389 static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state) 1390 { 1391 struct drm_device *dev = pci_get_drvdata(pdev); 1392 struct vmw_private *dev_priv = vmw_priv(dev); 1393 1394 if (dev_priv->refuse_hibernation) 1395 return -EBUSY; 1396 1397 pci_save_state(pdev); 1398 pci_disable_device(pdev); 1399 pci_set_power_state(pdev, PCI_D3hot); 1400 return 0; 1401 } 1402 1403 static int vmw_pci_resume(struct pci_dev *pdev) 1404 { 1405 pci_set_power_state(pdev, PCI_D0); 1406 pci_restore_state(pdev); 1407 return pci_enable_device(pdev); 1408 } 1409 1410 static int vmw_pm_suspend(struct device *kdev) 1411 { 1412 struct pci_dev *pdev = to_pci_dev(kdev); 1413 struct pm_message dummy; 1414 1415 dummy.event = 0; 1416 1417 return vmw_pci_suspend(pdev, dummy); 1418 } 1419 1420 static int vmw_pm_resume(struct device *kdev) 1421 { 1422 struct pci_dev *pdev = to_pci_dev(kdev); 1423 1424 return vmw_pci_resume(pdev); 1425 } 1426 1427 static int vmw_pm_freeze(struct device *kdev) 1428 { 1429 struct pci_dev *pdev = to_pci_dev(kdev); 1430 struct drm_device *dev = pci_get_drvdata(pdev); 1431 struct vmw_private *dev_priv = vmw_priv(dev); 1432 1433 dev_priv->suspended = true; 1434 if (dev_priv->enable_fb) 1435 vmw_fifo_resource_dec(dev_priv); 1436 1437 if (atomic_read(&dev_priv->num_fifo_resources) != 0) { 1438 DRM_ERROR("Can't hibernate while 3D resources are active.\n"); 1439 if (dev_priv->enable_fb) 1440 vmw_fifo_resource_inc(dev_priv); 1441 WARN_ON(vmw_request_device_late(dev_priv)); 1442 dev_priv->suspended = false; 1443 return -EBUSY; 1444 } 1445 1446 if (dev_priv->enable_fb) 1447 __vmw_svga_disable(dev_priv); 1448 1449 vmw_release_device_late(dev_priv); 1450 1451 return 0; 1452 } 1453 1454 static int vmw_pm_restore(struct device *kdev) 1455 { 1456 struct pci_dev *pdev = to_pci_dev(kdev); 1457 struct drm_device *dev = pci_get_drvdata(pdev); 1458 struct vmw_private *dev_priv = vmw_priv(dev); 1459 int ret; 1460 1461 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2); 1462 (void) vmw_read(dev_priv, SVGA_REG_ID); 1463 1464 if (dev_priv->enable_fb) 1465 vmw_fifo_resource_inc(dev_priv); 1466 1467 ret = vmw_request_device(dev_priv); 1468 if (ret) 1469 return ret; 1470 1471 if (dev_priv->enable_fb) 1472 __vmw_svga_enable(dev_priv); 1473 1474 dev_priv->suspended = false; 1475 1476 return 0; 1477 } 1478 1479 static const struct dev_pm_ops vmw_pm_ops = { 1480 .freeze = vmw_pm_freeze, 1481 .thaw = vmw_pm_restore, 1482 .restore = vmw_pm_restore, 1483 .suspend = vmw_pm_suspend, 1484 .resume = vmw_pm_resume, 1485 }; 1486 1487 static const struct file_operations vmwgfx_driver_fops = { 1488 .owner = THIS_MODULE, 1489 .open = drm_open, 1490 .release = drm_release, 1491 .unlocked_ioctl = vmw_unlocked_ioctl, 1492 .mmap = vmw_mmap, 1493 .poll = vmw_fops_poll, 1494 .read = vmw_fops_read, 1495 #if defined(CONFIG_COMPAT) 1496 .compat_ioctl = vmw_compat_ioctl, 1497 #endif 1498 .llseek = noop_llseek, 1499 }; 1500 1501 static struct drm_driver driver = { 1502 .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | 1503 DRIVER_MODESET | DRIVER_PRIME | DRIVER_RENDER, 1504 .load = vmw_driver_load, 1505 .unload = vmw_driver_unload, 1506 .lastclose = vmw_lastclose, 1507 .irq_preinstall = vmw_irq_preinstall, 1508 .irq_postinstall = vmw_irq_postinstall, 1509 .irq_uninstall = vmw_irq_uninstall, 1510 .irq_handler = vmw_irq_handler, 1511 .get_vblank_counter = vmw_get_vblank_counter, 1512 .enable_vblank = vmw_enable_vblank, 1513 .disable_vblank = vmw_disable_vblank, 1514 .ioctls = vmw_ioctls, 1515 .num_ioctls = ARRAY_SIZE(vmw_ioctls), 1516 .master_create = vmw_master_create, 1517 .master_destroy = vmw_master_destroy, 1518 .master_set = vmw_master_set, 1519 .master_drop = vmw_master_drop, 1520 .open = vmw_driver_open, 1521 .preclose = vmw_preclose, 1522 .postclose = vmw_postclose, 1523 .set_busid = drm_pci_set_busid, 1524 1525 .dumb_create = vmw_dumb_create, 1526 .dumb_map_offset = vmw_dumb_map_offset, 1527 .dumb_destroy = vmw_dumb_destroy, 1528 1529 .prime_fd_to_handle = vmw_prime_fd_to_handle, 1530 .prime_handle_to_fd = vmw_prime_handle_to_fd, 1531 1532 .fops = &vmwgfx_driver_fops, 1533 .name = VMWGFX_DRIVER_NAME, 1534 .desc = VMWGFX_DRIVER_DESC, 1535 .date = VMWGFX_DRIVER_DATE, 1536 .major = VMWGFX_DRIVER_MAJOR, 1537 .minor = VMWGFX_DRIVER_MINOR, 1538 .patchlevel = VMWGFX_DRIVER_PATCHLEVEL 1539 }; 1540 1541 static struct pci_driver vmw_pci_driver = { 1542 .name = VMWGFX_DRIVER_NAME, 1543 .id_table = vmw_pci_id_list, 1544 .probe = vmw_probe, 1545 .remove = vmw_remove, 1546 .driver = { 1547 .pm = &vmw_pm_ops 1548 } 1549 }; 1550 1551 static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1552 { 1553 return drm_get_pci_dev(pdev, ent, &driver); 1554 } 1555 1556 static int __init vmwgfx_init(void) 1557 { 1558 int ret; 1559 1560 #ifdef CONFIG_VGA_CONSOLE 1561 if (vgacon_text_force()) 1562 return -EINVAL; 1563 #endif 1564 1565 ret = drm_pci_init(&driver, &vmw_pci_driver); 1566 if (ret) 1567 DRM_ERROR("Failed initializing DRM.\n"); 1568 return ret; 1569 } 1570 1571 static void __exit vmwgfx_exit(void) 1572 { 1573 drm_pci_exit(&driver, &vmw_pci_driver); 1574 } 1575 1576 module_init(vmwgfx_init); 1577 module_exit(vmwgfx_exit); 1578 1579 MODULE_AUTHOR("VMware Inc. and others"); 1580 MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device"); 1581 MODULE_LICENSE("GPL and additional rights"); 1582 MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR) "." 1583 __stringify(VMWGFX_DRIVER_MINOR) "." 1584 __stringify(VMWGFX_DRIVER_PATCHLEVEL) "." 1585 "0"); 1586
Indexes created Wed Oct 22 06:10:02 GMT 2025