vmwgfx_drv.c revision 1.1.1.4
1 /* $NetBSD: vmwgfx_drv.c,v 1.1.1.4 2021/12/18 20:15:54 riastradh Exp $ */ 2 3 // SPDX-License-Identifier: GPL-2.0 OR MIT 4 /************************************************************************** 5 * 6 * Copyright 2009-2016 VMware, Inc., Palo Alto, CA., USA 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 22 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 23 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 24 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 25 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 26 * USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 **************************************************************************/ 29 30 #include <sys/cdefs.h> 31 __KERNEL_RCSID(0, "$NetBSD: vmwgfx_drv.c,v 1.1.1.4 2021/12/18 20:15:54 riastradh Exp $"); 32 33 #include <linux/console.h> 34 #include <linux/dma-mapping.h> 35 #include <linux/module.h> 36 #include <linux/pci.h> 37 38 #include <drm/drm_drv.h> 39 #include <drm/drm_ioctl.h> 40 #include <drm/drm_sysfs.h> 41 #include <drm/ttm/ttm_bo_driver.h> 42 #include <drm/ttm/ttm_module.h> 43 #include <drm/ttm/ttm_placement.h> 44 45 #include "ttm_object.h" 46 #include "vmwgfx_binding.h" 47 #include "vmwgfx_drv.h" 48 49 #define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices" 50 #define VMWGFX_CHIP_SVGAII 0 51 #define VMW_FB_RESERVATION 0 52 53 #define VMW_MIN_INITIAL_WIDTH 800 54 #define VMW_MIN_INITIAL_HEIGHT 600 55 56 #ifndef VMWGFX_GIT_VERSION 57 #define VMWGFX_GIT_VERSION "Unknown" 58 #endif 59 60 #define VMWGFX_REPO "In Tree" 61 62 #define VMWGFX_VALIDATION_MEM_GRAN (16*PAGE_SIZE) 63 64 65 /** 66 * Fully encoded drm commands. Might move to vmw_drm.h 67 */ 68 69 #define DRM_IOCTL_VMW_GET_PARAM \ 70 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM, \ 71 struct drm_vmw_getparam_arg) 72 #define DRM_IOCTL_VMW_ALLOC_DMABUF \ 73 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF, \ 74 union drm_vmw_alloc_dmabuf_arg) 75 #define DRM_IOCTL_VMW_UNREF_DMABUF \ 76 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF, \ 77 struct drm_vmw_unref_dmabuf_arg) 78 #define DRM_IOCTL_VMW_CURSOR_BYPASS \ 79 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS, \ 80 struct drm_vmw_cursor_bypass_arg) 81 82 #define DRM_IOCTL_VMW_CONTROL_STREAM \ 83 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM, \ 84 struct drm_vmw_control_stream_arg) 85 #define DRM_IOCTL_VMW_CLAIM_STREAM \ 86 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM, \ 87 struct drm_vmw_stream_arg) 88 #define DRM_IOCTL_VMW_UNREF_STREAM \ 89 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM, \ 90 struct drm_vmw_stream_arg) 91 92 #define DRM_IOCTL_VMW_CREATE_CONTEXT \ 93 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT, \ 94 struct drm_vmw_context_arg) 95 #define DRM_IOCTL_VMW_UNREF_CONTEXT \ 96 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT, \ 97 struct drm_vmw_context_arg) 98 #define DRM_IOCTL_VMW_CREATE_SURFACE \ 99 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE, \ 100 union drm_vmw_surface_create_arg) 101 #define DRM_IOCTL_VMW_UNREF_SURFACE \ 102 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE, \ 103 struct drm_vmw_surface_arg) 104 #define DRM_IOCTL_VMW_REF_SURFACE \ 105 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE, \ 106 union drm_vmw_surface_reference_arg) 107 #define DRM_IOCTL_VMW_EXECBUF \ 108 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF, \ 109 struct drm_vmw_execbuf_arg) 110 #define DRM_IOCTL_VMW_GET_3D_CAP \ 111 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP, \ 112 struct drm_vmw_get_3d_cap_arg) 113 #define DRM_IOCTL_VMW_FENCE_WAIT \ 114 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT, \ 115 struct drm_vmw_fence_wait_arg) 116 #define DRM_IOCTL_VMW_FENCE_SIGNALED \ 117 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED, \ 118 struct drm_vmw_fence_signaled_arg) 119 #define DRM_IOCTL_VMW_FENCE_UNREF \ 120 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF, \ 121 struct drm_vmw_fence_arg) 122 #define DRM_IOCTL_VMW_FENCE_EVENT \ 123 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT, \ 124 struct drm_vmw_fence_event_arg) 125 #define DRM_IOCTL_VMW_PRESENT \ 126 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT, \ 127 struct drm_vmw_present_arg) 128 #define DRM_IOCTL_VMW_PRESENT_READBACK \ 129 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK, \ 130 struct drm_vmw_present_readback_arg) 131 #define DRM_IOCTL_VMW_UPDATE_LAYOUT \ 132 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT, \ 133 struct drm_vmw_update_layout_arg) 134 #define DRM_IOCTL_VMW_CREATE_SHADER \ 135 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SHADER, \ 136 struct drm_vmw_shader_create_arg) 137 #define DRM_IOCTL_VMW_UNREF_SHADER \ 138 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SHADER, \ 139 struct drm_vmw_shader_arg) 140 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE \ 141 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE, \ 142 union drm_vmw_gb_surface_create_arg) 143 #define DRM_IOCTL_VMW_GB_SURFACE_REF \ 144 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF, \ 145 union drm_vmw_gb_surface_reference_arg) 146 #define DRM_IOCTL_VMW_SYNCCPU \ 147 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_SYNCCPU, \ 148 struct drm_vmw_synccpu_arg) 149 #define DRM_IOCTL_VMW_CREATE_EXTENDED_CONTEXT \ 150 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_EXTENDED_CONTEXT, \ 151 struct drm_vmw_context_arg) 152 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE_EXT \ 153 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE_EXT, \ 154 union drm_vmw_gb_surface_create_ext_arg) 155 #define DRM_IOCTL_VMW_GB_SURFACE_REF_EXT \ 156 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF_EXT, \ 157 union drm_vmw_gb_surface_reference_ext_arg) 158 #define DRM_IOCTL_VMW_MSG \ 159 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_MSG, \ 160 struct drm_vmw_msg_arg) 161 162 /** 163 * The core DRM version of this macro doesn't account for 164 * DRM_COMMAND_BASE. 165 */ 166 167 #define VMW_IOCTL_DEF(ioctl, func, flags) \ 168 [DRM_IOCTL_NR(DRM_IOCTL_##ioctl) - DRM_COMMAND_BASE] = {DRM_IOCTL_##ioctl, flags, func} 169 170 /** 171 * Ioctl definitions. 172 */ 173 174 static const struct drm_ioctl_desc vmw_ioctls[] = { 175 VMW_IOCTL_DEF(VMW_GET_PARAM, vmw_getparam_ioctl, 176 DRM_RENDER_ALLOW), 177 VMW_IOCTL_DEF(VMW_ALLOC_DMABUF, vmw_bo_alloc_ioctl, 178 DRM_RENDER_ALLOW), 179 VMW_IOCTL_DEF(VMW_UNREF_DMABUF, vmw_bo_unref_ioctl, 180 DRM_RENDER_ALLOW), 181 VMW_IOCTL_DEF(VMW_CURSOR_BYPASS, 182 vmw_kms_cursor_bypass_ioctl, 183 DRM_MASTER), 184 185 VMW_IOCTL_DEF(VMW_CONTROL_STREAM, vmw_overlay_ioctl, 186 DRM_MASTER), 187 VMW_IOCTL_DEF(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl, 188 DRM_MASTER), 189 VMW_IOCTL_DEF(VMW_UNREF_STREAM, vmw_stream_unref_ioctl, 190 DRM_MASTER), 191 192 VMW_IOCTL_DEF(VMW_CREATE_CONTEXT, vmw_context_define_ioctl, 193 DRM_RENDER_ALLOW), 194 VMW_IOCTL_DEF(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl, 195 DRM_RENDER_ALLOW), 196 VMW_IOCTL_DEF(VMW_CREATE_SURFACE, vmw_surface_define_ioctl, 197 DRM_RENDER_ALLOW), 198 VMW_IOCTL_DEF(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl, 199 DRM_RENDER_ALLOW), 200 VMW_IOCTL_DEF(VMW_REF_SURFACE, vmw_surface_reference_ioctl, 201 DRM_RENDER_ALLOW), 202 VMW_IOCTL_DEF(VMW_EXECBUF, vmw_execbuf_ioctl, 203 DRM_RENDER_ALLOW), 204 VMW_IOCTL_DEF(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl, 205 DRM_RENDER_ALLOW), 206 VMW_IOCTL_DEF(VMW_FENCE_SIGNALED, 207 vmw_fence_obj_signaled_ioctl, 208 DRM_RENDER_ALLOW), 209 VMW_IOCTL_DEF(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl, 210 DRM_RENDER_ALLOW), 211 VMW_IOCTL_DEF(VMW_FENCE_EVENT, vmw_fence_event_ioctl, 212 DRM_RENDER_ALLOW), 213 VMW_IOCTL_DEF(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl, 214 DRM_RENDER_ALLOW), 215 216 /* these allow direct access to the framebuffers mark as master only */ 217 VMW_IOCTL_DEF(VMW_PRESENT, vmw_present_ioctl, 218 DRM_MASTER | DRM_AUTH), 219 VMW_IOCTL_DEF(VMW_PRESENT_READBACK, 220 vmw_present_readback_ioctl, 221 DRM_MASTER | DRM_AUTH), 222 /* 223 * The permissions of the below ioctl are overridden in 224 * vmw_generic_ioctl(). We require either 225 * DRM_MASTER or capable(CAP_SYS_ADMIN). 226 */ 227 VMW_IOCTL_DEF(VMW_UPDATE_LAYOUT, 228 vmw_kms_update_layout_ioctl, 229 DRM_RENDER_ALLOW), 230 VMW_IOCTL_DEF(VMW_CREATE_SHADER, 231 vmw_shader_define_ioctl, 232 DRM_RENDER_ALLOW), 233 VMW_IOCTL_DEF(VMW_UNREF_SHADER, 234 vmw_shader_destroy_ioctl, 235 DRM_RENDER_ALLOW), 236 VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE, 237 vmw_gb_surface_define_ioctl, 238 DRM_RENDER_ALLOW), 239 VMW_IOCTL_DEF(VMW_GB_SURFACE_REF, 240 vmw_gb_surface_reference_ioctl, 241 DRM_RENDER_ALLOW), 242 VMW_IOCTL_DEF(VMW_SYNCCPU, 243 vmw_user_bo_synccpu_ioctl, 244 DRM_RENDER_ALLOW), 245 VMW_IOCTL_DEF(VMW_CREATE_EXTENDED_CONTEXT, 246 vmw_extended_context_define_ioctl, 247 DRM_RENDER_ALLOW), 248 VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE_EXT, 249 vmw_gb_surface_define_ext_ioctl, 250 DRM_RENDER_ALLOW), 251 VMW_IOCTL_DEF(VMW_GB_SURFACE_REF_EXT, 252 vmw_gb_surface_reference_ext_ioctl, 253 DRM_RENDER_ALLOW), 254 VMW_IOCTL_DEF(VMW_MSG, 255 vmw_msg_ioctl, 256 DRM_RENDER_ALLOW), 257 }; 258 259 static const struct pci_device_id vmw_pci_id_list[] = { 260 {0x15ad, 0x0405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VMWGFX_CHIP_SVGAII}, 261 {0, 0, 0} 262 }; 263 MODULE_DEVICE_TABLE(pci, vmw_pci_id_list); 264 265 static int enable_fbdev = IS_ENABLED(CONFIG_DRM_VMWGFX_FBCON); 266 static int vmw_force_iommu; 267 static int vmw_restrict_iommu; 268 static int vmw_force_coherent; 269 static int vmw_restrict_dma_mask; 270 static int vmw_assume_16bpp; 271 272 static int vmw_probe(struct pci_dev *, const struct pci_device_id *); 273 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, 274 void *ptr); 275 276 MODULE_PARM_DESC(enable_fbdev, "Enable vmwgfx fbdev"); 277 module_param_named(enable_fbdev, enable_fbdev, int, 0600); 278 MODULE_PARM_DESC(force_dma_api, "Force using the DMA API for TTM pages"); 279 module_param_named(force_dma_api, vmw_force_iommu, int, 0600); 280 MODULE_PARM_DESC(restrict_iommu, "Try to limit IOMMU usage for TTM pages"); 281 module_param_named(restrict_iommu, vmw_restrict_iommu, int, 0600); 282 MODULE_PARM_DESC(force_coherent, "Force coherent TTM pages"); 283 module_param_named(force_coherent, vmw_force_coherent, int, 0600); 284 MODULE_PARM_DESC(restrict_dma_mask, "Restrict DMA mask to 44 bits with IOMMU"); 285 module_param_named(restrict_dma_mask, vmw_restrict_dma_mask, int, 0600); 286 MODULE_PARM_DESC(assume_16bpp, "Assume 16-bpp when filtering modes"); 287 module_param_named(assume_16bpp, vmw_assume_16bpp, int, 0600); 288 289 290 static void vmw_print_capabilities2(uint32_t capabilities2) 291 { 292 DRM_INFO("Capabilities2:\n"); 293 if (capabilities2 & SVGA_CAP2_GROW_OTABLE) 294 DRM_INFO(" Grow oTable.\n"); 295 if (capabilities2 & SVGA_CAP2_INTRA_SURFACE_COPY) 296 DRM_INFO(" IntraSurface copy.\n"); 297 } 298 299 static void vmw_print_capabilities(uint32_t capabilities) 300 { 301 DRM_INFO("Capabilities:\n"); 302 if (capabilities & SVGA_CAP_RECT_COPY) 303 DRM_INFO(" Rect copy.\n"); 304 if (capabilities & SVGA_CAP_CURSOR) 305 DRM_INFO(" Cursor.\n"); 306 if (capabilities & SVGA_CAP_CURSOR_BYPASS) 307 DRM_INFO(" Cursor bypass.\n"); 308 if (capabilities & SVGA_CAP_CURSOR_BYPASS_2) 309 DRM_INFO(" Cursor bypass 2.\n"); 310 if (capabilities & SVGA_CAP_8BIT_EMULATION) 311 DRM_INFO(" 8bit emulation.\n"); 312 if (capabilities & SVGA_CAP_ALPHA_CURSOR) 313 DRM_INFO(" Alpha cursor.\n"); 314 if (capabilities & SVGA_CAP_3D) 315 DRM_INFO(" 3D.\n"); 316 if (capabilities & SVGA_CAP_EXTENDED_FIFO) 317 DRM_INFO(" Extended Fifo.\n"); 318 if (capabilities & SVGA_CAP_MULTIMON) 319 DRM_INFO(" Multimon.\n"); 320 if (capabilities & SVGA_CAP_PITCHLOCK) 321 DRM_INFO(" Pitchlock.\n"); 322 if (capabilities & SVGA_CAP_IRQMASK) 323 DRM_INFO(" Irq mask.\n"); 324 if (capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) 325 DRM_INFO(" Display Topology.\n"); 326 if (capabilities & SVGA_CAP_GMR) 327 DRM_INFO(" GMR.\n"); 328 if (capabilities & SVGA_CAP_TRACES) 329 DRM_INFO(" Traces.\n"); 330 if (capabilities & SVGA_CAP_GMR2) 331 DRM_INFO(" GMR2.\n"); 332 if (capabilities & SVGA_CAP_SCREEN_OBJECT_2) 333 DRM_INFO(" Screen Object 2.\n"); 334 if (capabilities & SVGA_CAP_COMMAND_BUFFERS) 335 DRM_INFO(" Command Buffers.\n"); 336 if (capabilities & SVGA_CAP_CMD_BUFFERS_2) 337 DRM_INFO(" Command Buffers 2.\n"); 338 if (capabilities & SVGA_CAP_GBOBJECTS) 339 DRM_INFO(" Guest Backed Resources.\n"); 340 if (capabilities & SVGA_CAP_DX) 341 DRM_INFO(" DX Features.\n"); 342 if (capabilities & SVGA_CAP_HP_CMD_QUEUE) 343 DRM_INFO(" HP Command Queue.\n"); 344 } 345 346 /** 347 * vmw_dummy_query_bo_create - create a bo to hold a dummy query result 348 * 349 * @dev_priv: A device private structure. 350 * 351 * This function creates a small buffer object that holds the query 352 * result for dummy queries emitted as query barriers. 353 * The function will then map the first page and initialize a pending 354 * occlusion query result structure, Finally it will unmap the buffer. 355 * No interruptible waits are done within this function. 356 * 357 * Returns an error if bo creation or initialization fails. 358 */ 359 static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv) 360 { 361 int ret; 362 struct vmw_buffer_object *vbo; 363 struct ttm_bo_kmap_obj map; 364 volatile SVGA3dQueryResult *result; 365 bool dummy; 366 367 /* 368 * Create the vbo as pinned, so that a tryreserve will 369 * immediately succeed. This is because we're the only 370 * user of the bo currently. 371 */ 372 vbo = kzalloc(sizeof(*vbo), GFP_KERNEL); 373 if (!vbo) 374 return -ENOMEM; 375 376 ret = vmw_bo_init(dev_priv, vbo, PAGE_SIZE, 377 &vmw_sys_ne_placement, false, 378 &vmw_bo_bo_free); 379 if (unlikely(ret != 0)) 380 return ret; 381 382 ret = ttm_bo_reserve(&vbo->base, false, true, NULL); 383 BUG_ON(ret != 0); 384 vmw_bo_pin_reserved(vbo, true); 385 386 ret = ttm_bo_kmap(&vbo->base, 0, 1, &map); 387 if (likely(ret == 0)) { 388 result = ttm_kmap_obj_virtual(&map, &dummy); 389 result->totalSize = sizeof(*result); 390 result->state = SVGA3D_QUERYSTATE_PENDING; 391 result->result32 = 0xff; 392 ttm_bo_kunmap(&map); 393 } 394 vmw_bo_pin_reserved(vbo, false); 395 ttm_bo_unreserve(&vbo->base); 396 397 if (unlikely(ret != 0)) { 398 DRM_ERROR("Dummy query buffer map failed.\n"); 399 vmw_bo_unreference(&vbo); 400 } else 401 dev_priv->dummy_query_bo = vbo; 402 403 return ret; 404 } 405 406 /** 407 * vmw_request_device_late - Perform late device setup 408 * 409 * @dev_priv: Pointer to device private. 410 * 411 * This function performs setup of otables and enables large command 412 * buffer submission. These tasks are split out to a separate function 413 * because it reverts vmw_release_device_early and is intended to be used 414 * by an error path in the hibernation code. 415 */ 416 static int vmw_request_device_late(struct vmw_private *dev_priv) 417 { 418 int ret; 419 420 if (dev_priv->has_mob) { 421 ret = vmw_otables_setup(dev_priv); 422 if (unlikely(ret != 0)) { 423 DRM_ERROR("Unable to initialize " 424 "guest Memory OBjects.\n"); 425 return ret; 426 } 427 } 428 429 if (dev_priv->cman) { 430 ret = vmw_cmdbuf_set_pool_size(dev_priv->cman, 431 256*4096, 2*4096); 432 if (ret) { 433 struct vmw_cmdbuf_man *man = dev_priv->cman; 434 435 dev_priv->cman = NULL; 436 vmw_cmdbuf_man_destroy(man); 437 } 438 } 439 440 return 0; 441 } 442 443 static int vmw_request_device(struct vmw_private *dev_priv) 444 { 445 int ret; 446 447 ret = vmw_fifo_init(dev_priv, &dev_priv->fifo); 448 if (unlikely(ret != 0)) { 449 DRM_ERROR("Unable to initialize FIFO.\n"); 450 return ret; 451 } 452 vmw_fence_fifo_up(dev_priv->fman); 453 dev_priv->cman = vmw_cmdbuf_man_create(dev_priv); 454 if (IS_ERR(dev_priv->cman)) { 455 dev_priv->cman = NULL; 456 dev_priv->has_dx = false; 457 } 458 459 ret = vmw_request_device_late(dev_priv); 460 if (ret) 461 goto out_no_mob; 462 463 ret = vmw_dummy_query_bo_create(dev_priv); 464 if (unlikely(ret != 0)) 465 goto out_no_query_bo; 466 467 return 0; 468 469 out_no_query_bo: 470 if (dev_priv->cman) 471 vmw_cmdbuf_remove_pool(dev_priv->cman); 472 if (dev_priv->has_mob) { 473 (void) ttm_bo_evict_mm(&dev_priv->bdev, VMW_PL_MOB); 474 vmw_otables_takedown(dev_priv); 475 } 476 if (dev_priv->cman) 477 vmw_cmdbuf_man_destroy(dev_priv->cman); 478 out_no_mob: 479 vmw_fence_fifo_down(dev_priv->fman); 480 vmw_fifo_release(dev_priv, &dev_priv->fifo); 481 return ret; 482 } 483 484 /** 485 * vmw_release_device_early - Early part of fifo takedown. 486 * 487 * @dev_priv: Pointer to device private struct. 488 * 489 * This is the first part of command submission takedown, to be called before 490 * buffer management is taken down. 491 */ 492 static void vmw_release_device_early(struct vmw_private *dev_priv) 493 { 494 /* 495 * Previous destructions should've released 496 * the pinned bo. 497 */ 498 499 BUG_ON(dev_priv->pinned_bo != NULL); 500 501 vmw_bo_unreference(&dev_priv->dummy_query_bo); 502 if (dev_priv->cman) 503 vmw_cmdbuf_remove_pool(dev_priv->cman); 504 505 if (dev_priv->has_mob) { 506 ttm_bo_evict_mm(&dev_priv->bdev, VMW_PL_MOB); 507 vmw_otables_takedown(dev_priv); 508 } 509 } 510 511 /** 512 * vmw_release_device_late - Late part of fifo takedown. 513 * 514 * @dev_priv: Pointer to device private struct. 515 * 516 * This is the last part of the command submission takedown, to be called when 517 * command submission is no longer needed. It may wait on pending fences. 518 */ 519 static void vmw_release_device_late(struct vmw_private *dev_priv) 520 { 521 vmw_fence_fifo_down(dev_priv->fman); 522 if (dev_priv->cman) 523 vmw_cmdbuf_man_destroy(dev_priv->cman); 524 525 vmw_fifo_release(dev_priv, &dev_priv->fifo); 526 } 527 528 /** 529 * Sets the initial_[width|height] fields on the given vmw_private. 530 * 531 * It does so by reading SVGA_REG_[WIDTH|HEIGHT] regs and then 532 * clamping the value to fb_max_[width|height] fields and the 533 * VMW_MIN_INITIAL_[WIDTH|HEIGHT]. 534 * If the values appear to be invalid, set them to 535 * VMW_MIN_INITIAL_[WIDTH|HEIGHT]. 536 */ 537 static void vmw_get_initial_size(struct vmw_private *dev_priv) 538 { 539 uint32_t width; 540 uint32_t height; 541 542 width = vmw_read(dev_priv, SVGA_REG_WIDTH); 543 height = vmw_read(dev_priv, SVGA_REG_HEIGHT); 544 545 width = max_t(uint32_t, width, VMW_MIN_INITIAL_WIDTH); 546 height = max_t(uint32_t, height, VMW_MIN_INITIAL_HEIGHT); 547 548 if (width > dev_priv->fb_max_width || 549 height > dev_priv->fb_max_height) { 550 551 /* 552 * This is a host error and shouldn't occur. 553 */ 554 555 width = VMW_MIN_INITIAL_WIDTH; 556 height = VMW_MIN_INITIAL_HEIGHT; 557 } 558 559 dev_priv->initial_width = width; 560 dev_priv->initial_height = height; 561 } 562 563 /** 564 * vmw_dma_select_mode - Determine how DMA mappings should be set up for this 565 * system. 566 * 567 * @dev_priv: Pointer to a struct vmw_private 568 * 569 * This functions tries to determine what actions need to be taken by the 570 * driver to make system pages visible to the device. 571 * If this function decides that DMA is not possible, it returns -EINVAL. 572 * The driver may then try to disable features of the device that require 573 * DMA. 574 */ 575 static int vmw_dma_select_mode(struct vmw_private *dev_priv) 576 { 577 static const char *names[vmw_dma_map_max] = { 578 [vmw_dma_phys] = "Using physical TTM page addresses.", 579 [vmw_dma_alloc_coherent] = "Using coherent TTM pages.", 580 [vmw_dma_map_populate] = "Caching DMA mappings.", 581 [vmw_dma_map_bind] = "Giving up DMA mappings early."}; 582 583 if (vmw_force_coherent) 584 dev_priv->map_mode = vmw_dma_alloc_coherent; 585 else if (vmw_restrict_iommu) 586 dev_priv->map_mode = vmw_dma_map_bind; 587 else 588 dev_priv->map_mode = vmw_dma_map_populate; 589 590 if (!IS_ENABLED(CONFIG_DRM_TTM_DMA_PAGE_POOL) && 591 (dev_priv->map_mode == vmw_dma_alloc_coherent)) 592 return -EINVAL; 593 594 DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]); 595 return 0; 596 } 597 598 /** 599 * vmw_dma_masks - set required page- and dma masks 600 * 601 * @dev: Pointer to struct drm-device 602 * 603 * With 32-bit we can only handle 32 bit PFNs. Optionally set that 604 * restriction also for 64-bit systems. 605 */ 606 static int vmw_dma_masks(struct vmw_private *dev_priv) 607 { 608 struct drm_device *dev = dev_priv->dev; 609 int ret = 0; 610 611 ret = dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)); 612 if (dev_priv->map_mode != vmw_dma_phys && 613 (sizeof(unsigned long) == 4 || vmw_restrict_dma_mask)) { 614 DRM_INFO("Restricting DMA addresses to 44 bits.\n"); 615 return dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(44)); 616 } 617 618 return ret; 619 } 620 621 static int vmw_driver_load(struct drm_device *dev, unsigned long chipset) 622 { 623 struct vmw_private *dev_priv; 624 int ret; 625 uint32_t svga_id; 626 enum vmw_res_type i; 627 bool refuse_dma = false; 628 char host_log[100] = {0}; 629 630 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL); 631 if (unlikely(!dev_priv)) { 632 DRM_ERROR("Failed allocating a device private struct.\n"); 633 return -ENOMEM; 634 } 635 636 pci_set_master(dev->pdev); 637 638 dev_priv->dev = dev; 639 dev_priv->vmw_chipset = chipset; 640 dev_priv->last_read_seqno = (uint32_t) -100; 641 mutex_init(&dev_priv->cmdbuf_mutex); 642 mutex_init(&dev_priv->release_mutex); 643 mutex_init(&dev_priv->binding_mutex); 644 mutex_init(&dev_priv->global_kms_state_mutex); 645 ttm_lock_init(&dev_priv->reservation_sem); 646 spin_lock_init(&dev_priv->resource_lock); 647 spin_lock_init(&dev_priv->hw_lock); 648 spin_lock_init(&dev_priv->waiter_lock); 649 spin_lock_init(&dev_priv->cap_lock); 650 spin_lock_init(&dev_priv->svga_lock); 651 spin_lock_init(&dev_priv->cursor_lock); 652 653 for (i = vmw_res_context; i < vmw_res_max; ++i) { 654 idr_init(&dev_priv->res_idr[i]); 655 INIT_LIST_HEAD(&dev_priv->res_lru[i]); 656 } 657 658 init_waitqueue_head(&dev_priv->fence_queue); 659 init_waitqueue_head(&dev_priv->fifo_queue); 660 dev_priv->fence_queue_waiters = 0; 661 dev_priv->fifo_queue_waiters = 0; 662 663 dev_priv->used_memory_size = 0; 664 665 dev_priv->io_start = pci_resource_start(dev->pdev, 0); 666 dev_priv->vram_start = pci_resource_start(dev->pdev, 1); 667 dev_priv->mmio_start = pci_resource_start(dev->pdev, 2); 668 669 dev_priv->assume_16bpp = !!vmw_assume_16bpp; 670 671 dev_priv->enable_fb = enable_fbdev; 672 673 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2); 674 svga_id = vmw_read(dev_priv, SVGA_REG_ID); 675 if (svga_id != SVGA_ID_2) { 676 ret = -ENOSYS; 677 DRM_ERROR("Unsupported SVGA ID 0x%x\n", svga_id); 678 goto out_err0; 679 } 680 681 dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES); 682 683 if (dev_priv->capabilities & SVGA_CAP_CAP2_REGISTER) { 684 dev_priv->capabilities2 = vmw_read(dev_priv, SVGA_REG_CAP2); 685 } 686 687 688 ret = vmw_dma_select_mode(dev_priv); 689 if (unlikely(ret != 0)) { 690 DRM_INFO("Restricting capabilities due to IOMMU setup.\n"); 691 refuse_dma = true; 692 } 693 694 dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE); 695 dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE); 696 dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH); 697 dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT); 698 699 vmw_get_initial_size(dev_priv); 700 701 if (dev_priv->capabilities & SVGA_CAP_GMR2) { 702 dev_priv->max_gmr_ids = 703 vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS); 704 dev_priv->max_gmr_pages = 705 vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES); 706 dev_priv->memory_size = 707 vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE); 708 dev_priv->memory_size -= dev_priv->vram_size; 709 } else { 710 /* 711 * An arbitrary limit of 512MiB on surface 712 * memory. But all HWV8 hardware supports GMR2. 713 */ 714 dev_priv->memory_size = 512*1024*1024; 715 } 716 dev_priv->max_mob_pages = 0; 717 dev_priv->max_mob_size = 0; 718 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) { 719 uint64_t mem_size = 720 vmw_read(dev_priv, 721 SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB); 722 723 /* 724 * Workaround for low memory 2D VMs to compensate for the 725 * allocation taken by fbdev 726 */ 727 if (!(dev_priv->capabilities & SVGA_CAP_3D)) 728 mem_size *= 3; 729 730 dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE; 731 dev_priv->prim_bb_mem = 732 vmw_read(dev_priv, 733 SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM); 734 dev_priv->max_mob_size = 735 vmw_read(dev_priv, SVGA_REG_MOB_MAX_SIZE); 736 dev_priv->stdu_max_width = 737 vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_WIDTH); 738 dev_priv->stdu_max_height = 739 vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_HEIGHT); 740 741 vmw_write(dev_priv, SVGA_REG_DEV_CAP, 742 SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH); 743 dev_priv->texture_max_width = vmw_read(dev_priv, 744 SVGA_REG_DEV_CAP); 745 vmw_write(dev_priv, SVGA_REG_DEV_CAP, 746 SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT); 747 dev_priv->texture_max_height = vmw_read(dev_priv, 748 SVGA_REG_DEV_CAP); 749 } else { 750 dev_priv->texture_max_width = 8192; 751 dev_priv->texture_max_height = 8192; 752 dev_priv->prim_bb_mem = dev_priv->vram_size; 753 } 754 755 vmw_print_capabilities(dev_priv->capabilities); 756 if (dev_priv->capabilities & SVGA_CAP_CAP2_REGISTER) 757 vmw_print_capabilities2(dev_priv->capabilities2); 758 759 ret = vmw_dma_masks(dev_priv); 760 if (unlikely(ret != 0)) 761 goto out_err0; 762 763 dma_set_max_seg_size(dev->dev, min_t(unsigned int, U32_MAX & PAGE_MASK, 764 SCATTERLIST_MAX_SEGMENT)); 765 766 if (dev_priv->capabilities & SVGA_CAP_GMR2) { 767 DRM_INFO("Max GMR ids is %u\n", 768 (unsigned)dev_priv->max_gmr_ids); 769 DRM_INFO("Max number of GMR pages is %u\n", 770 (unsigned)dev_priv->max_gmr_pages); 771 DRM_INFO("Max dedicated hypervisor surface memory is %u kiB\n", 772 (unsigned)dev_priv->memory_size / 1024); 773 } 774 DRM_INFO("Maximum display memory size is %u kiB\n", 775 dev_priv->prim_bb_mem / 1024); 776 DRM_INFO("VRAM at 0x%08x size is %u kiB\n", 777 dev_priv->vram_start, dev_priv->vram_size / 1024); 778 DRM_INFO("MMIO at 0x%08x size is %u kiB\n", 779 dev_priv->mmio_start, dev_priv->mmio_size / 1024); 780 781 dev_priv->mmio_virt = memremap(dev_priv->mmio_start, 782 dev_priv->mmio_size, MEMREMAP_WB); 783 784 if (unlikely(dev_priv->mmio_virt == NULL)) { 785 ret = -ENOMEM; 786 DRM_ERROR("Failed mapping MMIO.\n"); 787 goto out_err0; 788 } 789 790 /* Need mmio memory to check for fifo pitchlock cap. */ 791 if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) && 792 !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) && 793 !vmw_fifo_have_pitchlock(dev_priv)) { 794 ret = -ENOSYS; 795 DRM_ERROR("Hardware has no pitchlock\n"); 796 goto out_err4; 797 } 798 799 dev_priv->tdev = ttm_object_device_init(&ttm_mem_glob, 12, 800 &vmw_prime_dmabuf_ops); 801 802 if (unlikely(dev_priv->tdev == NULL)) { 803 DRM_ERROR("Unable to initialize TTM object management.\n"); 804 ret = -ENOMEM; 805 goto out_err4; 806 } 807 808 dev->dev_private = dev_priv; 809 810 ret = pci_request_regions(dev->pdev, "vmwgfx probe"); 811 dev_priv->stealth = (ret != 0); 812 if (dev_priv->stealth) { 813 /** 814 * Request at least the mmio PCI resource. 815 */ 816 817 DRM_INFO("It appears like vesafb is loaded. " 818 "Ignore above error if any.\n"); 819 ret = pci_request_region(dev->pdev, 2, "vmwgfx stealth probe"); 820 if (unlikely(ret != 0)) { 821 DRM_ERROR("Failed reserving the SVGA MMIO resource.\n"); 822 goto out_no_device; 823 } 824 } 825 826 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) { 827 ret = vmw_irq_install(dev, dev->pdev->irq); 828 if (ret != 0) { 829 DRM_ERROR("Failed installing irq: %d\n", ret); 830 goto out_no_irq; 831 } 832 } 833 834 dev_priv->fman = vmw_fence_manager_init(dev_priv); 835 if (unlikely(dev_priv->fman == NULL)) { 836 ret = -ENOMEM; 837 goto out_no_fman; 838 } 839 840 drm_vma_offset_manager_init(&dev_priv->vma_manager, 841 DRM_FILE_PAGE_OFFSET_START, 842 DRM_FILE_PAGE_OFFSET_SIZE); 843 ret = ttm_bo_device_init(&dev_priv->bdev, 844 &vmw_bo_driver, 845 dev->anon_inode->i_mapping, 846 &dev_priv->vma_manager, 847 false); 848 if (unlikely(ret != 0)) { 849 DRM_ERROR("Failed initializing TTM buffer object driver.\n"); 850 goto out_no_bdev; 851 } 852 853 /* 854 * Enable VRAM, but initially don't use it until SVGA is enabled and 855 * unhidden. 856 */ 857 ret = ttm_bo_init_mm(&dev_priv->bdev, TTM_PL_VRAM, 858 (dev_priv->vram_size >> PAGE_SHIFT)); 859 if (unlikely(ret != 0)) { 860 DRM_ERROR("Failed initializing memory manager for VRAM.\n"); 861 goto out_no_vram; 862 } 863 dev_priv->bdev.man[TTM_PL_VRAM].use_type = false; 864 865 dev_priv->has_gmr = true; 866 if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) || 867 refuse_dma || ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_GMR, 868 VMW_PL_GMR) != 0) { 869 DRM_INFO("No GMR memory available. " 870 "Graphics memory resources are very limited.\n"); 871 dev_priv->has_gmr = false; 872 } 873 874 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) { 875 dev_priv->has_mob = true; 876 if (ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_MOB, 877 VMW_PL_MOB) != 0) { 878 DRM_INFO("No MOB memory available. " 879 "3D will be disabled.\n"); 880 dev_priv->has_mob = false; 881 } 882 } 883 884 if (dev_priv->has_mob) { 885 spin_lock(&dev_priv->cap_lock); 886 vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_DXCONTEXT); 887 dev_priv->has_dx = !!vmw_read(dev_priv, SVGA_REG_DEV_CAP); 888 spin_unlock(&dev_priv->cap_lock); 889 } 890 891 vmw_validation_mem_init_ttm(dev_priv, VMWGFX_VALIDATION_MEM_GRAN); 892 ret = vmw_kms_init(dev_priv); 893 if (unlikely(ret != 0)) 894 goto out_no_kms; 895 vmw_overlay_init(dev_priv); 896 897 ret = vmw_request_device(dev_priv); 898 if (ret) 899 goto out_no_fifo; 900 901 if (dev_priv->has_dx) { 902 /* 903 * SVGA_CAP2_DX2 (DefineGBSurface_v3) is needed for SM4_1 904 * support 905 */ 906 if ((dev_priv->capabilities2 & SVGA_CAP2_DX2) != 0) { 907 vmw_write(dev_priv, SVGA_REG_DEV_CAP, 908 SVGA3D_DEVCAP_SM41); 909 dev_priv->has_sm4_1 = vmw_read(dev_priv, 910 SVGA_REG_DEV_CAP); 911 } 912 } 913 914 DRM_INFO("DX: %s\n", dev_priv->has_dx ? "yes." : "no."); 915 DRM_INFO("Atomic: %s\n", (dev->driver->driver_features & DRIVER_ATOMIC) 916 ? "yes." : "no."); 917 DRM_INFO("SM4_1: %s\n", dev_priv->has_sm4_1 ? "yes." : "no."); 918 919 snprintf(host_log, sizeof(host_log), "vmwgfx: %s-%s", 920 VMWGFX_REPO, VMWGFX_GIT_VERSION); 921 vmw_host_log(host_log); 922 923 memset(host_log, 0, sizeof(host_log)); 924 snprintf(host_log, sizeof(host_log), "vmwgfx: Module Version: %d.%d.%d", 925 VMWGFX_DRIVER_MAJOR, VMWGFX_DRIVER_MINOR, 926 VMWGFX_DRIVER_PATCHLEVEL); 927 vmw_host_log(host_log); 928 929 if (dev_priv->enable_fb) { 930 vmw_fifo_resource_inc(dev_priv); 931 vmw_svga_enable(dev_priv); 932 vmw_fb_init(dev_priv); 933 } 934 935 dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier; 936 register_pm_notifier(&dev_priv->pm_nb); 937 938 return 0; 939 940 out_no_fifo: 941 vmw_overlay_close(dev_priv); 942 vmw_kms_close(dev_priv); 943 out_no_kms: 944 if (dev_priv->has_mob) 945 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB); 946 if (dev_priv->has_gmr) 947 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR); 948 (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM); 949 out_no_vram: 950 (void)ttm_bo_device_release(&dev_priv->bdev); 951 out_no_bdev: 952 vmw_fence_manager_takedown(dev_priv->fman); 953 out_no_fman: 954 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) 955 vmw_irq_uninstall(dev_priv->dev); 956 out_no_irq: 957 if (dev_priv->stealth) 958 pci_release_region(dev->pdev, 2); 959 else 960 pci_release_regions(dev->pdev); 961 out_no_device: 962 ttm_object_device_release(&dev_priv->tdev); 963 out_err4: 964 memunmap(dev_priv->mmio_virt); 965 out_err0: 966 for (i = vmw_res_context; i < vmw_res_max; ++i) 967 idr_destroy(&dev_priv->res_idr[i]); 968 969 if (dev_priv->ctx.staged_bindings) 970 vmw_binding_state_free(dev_priv->ctx.staged_bindings); 971 kfree(dev_priv); 972 return ret; 973 } 974 975 static void vmw_driver_unload(struct drm_device *dev) 976 { 977 struct vmw_private *dev_priv = vmw_priv(dev); 978 enum vmw_res_type i; 979 980 unregister_pm_notifier(&dev_priv->pm_nb); 981 982 if (dev_priv->ctx.res_ht_initialized) 983 drm_ht_remove(&dev_priv->ctx.res_ht); 984 vfree(dev_priv->ctx.cmd_bounce); 985 if (dev_priv->enable_fb) { 986 vmw_fb_off(dev_priv); 987 vmw_fb_close(dev_priv); 988 vmw_fifo_resource_dec(dev_priv); 989 vmw_svga_disable(dev_priv); 990 } 991 992 vmw_kms_close(dev_priv); 993 vmw_overlay_close(dev_priv); 994 995 if (dev_priv->has_gmr) 996 (void)ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR); 997 (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM); 998 999 vmw_release_device_early(dev_priv); 1000 if (dev_priv->has_mob) 1001 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB); 1002 (void) ttm_bo_device_release(&dev_priv->bdev); 1003 drm_vma_offset_manager_destroy(&dev_priv->vma_manager); 1004 vmw_release_device_late(dev_priv); 1005 vmw_fence_manager_takedown(dev_priv->fman); 1006 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) 1007 vmw_irq_uninstall(dev_priv->dev); 1008 if (dev_priv->stealth) 1009 pci_release_region(dev->pdev, 2); 1010 else 1011 pci_release_regions(dev->pdev); 1012 1013 ttm_object_device_release(&dev_priv->tdev); 1014 memunmap(dev_priv->mmio_virt); 1015 if (dev_priv->ctx.staged_bindings) 1016 vmw_binding_state_free(dev_priv->ctx.staged_bindings); 1017 1018 for (i = vmw_res_context; i < vmw_res_max; ++i) 1019 idr_destroy(&dev_priv->res_idr[i]); 1020 1021 kfree(dev_priv); 1022 } 1023 1024 static void vmw_postclose(struct drm_device *dev, 1025 struct drm_file *file_priv) 1026 { 1027 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); 1028 1029 ttm_object_file_release(&vmw_fp->tfile); 1030 kfree(vmw_fp); 1031 } 1032 1033 static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv) 1034 { 1035 struct vmw_private *dev_priv = vmw_priv(dev); 1036 struct vmw_fpriv *vmw_fp; 1037 int ret = -ENOMEM; 1038 1039 vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL); 1040 if (unlikely(!vmw_fp)) 1041 return ret; 1042 1043 vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev, 10); 1044 if (unlikely(vmw_fp->tfile == NULL)) 1045 goto out_no_tfile; 1046 1047 file_priv->driver_priv = vmw_fp; 1048 1049 return 0; 1050 1051 out_no_tfile: 1052 kfree(vmw_fp); 1053 return ret; 1054 } 1055 1056 static long vmw_generic_ioctl(struct file *filp, unsigned int cmd, 1057 unsigned long arg, 1058 long (*ioctl_func)(struct file *, unsigned int, 1059 unsigned long)) 1060 { 1061 struct drm_file *file_priv = filp->private_data; 1062 struct drm_device *dev = file_priv->minor->dev; 1063 unsigned int nr = DRM_IOCTL_NR(cmd); 1064 unsigned int flags; 1065 1066 /* 1067 * Do extra checking on driver private ioctls. 1068 */ 1069 1070 if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END) 1071 && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) { 1072 const struct drm_ioctl_desc *ioctl = 1073 &vmw_ioctls[nr - DRM_COMMAND_BASE]; 1074 1075 if (nr == DRM_COMMAND_BASE + DRM_VMW_EXECBUF) { 1076 return ioctl_func(filp, cmd, arg); 1077 } else if (nr == DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT) { 1078 if (!drm_is_current_master(file_priv) && 1079 !capable(CAP_SYS_ADMIN)) 1080 return -EACCES; 1081 } 1082 1083 if (unlikely(ioctl->cmd != cmd)) 1084 goto out_io_encoding; 1085 1086 flags = ioctl->flags; 1087 } else if (!drm_ioctl_flags(nr, &flags)) 1088 return -EINVAL; 1089 1090 return ioctl_func(filp, cmd, arg); 1091 1092 out_io_encoding: 1093 DRM_ERROR("Invalid command format, ioctl %d\n", 1094 nr - DRM_COMMAND_BASE); 1095 1096 return -EINVAL; 1097 } 1098 1099 static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd, 1100 unsigned long arg) 1101 { 1102 return vmw_generic_ioctl(filp, cmd, arg, &drm_ioctl); 1103 } 1104 1105 #ifdef CONFIG_COMPAT 1106 static long vmw_compat_ioctl(struct file *filp, unsigned int cmd, 1107 unsigned long arg) 1108 { 1109 return vmw_generic_ioctl(filp, cmd, arg, &drm_compat_ioctl); 1110 } 1111 #endif 1112 1113 static int vmw_master_set(struct drm_device *dev, 1114 struct drm_file *file_priv, 1115 bool from_open) 1116 { 1117 /* 1118 * Inform a new master that the layout may have changed while 1119 * it was gone. 1120 */ 1121 if (!from_open) 1122 drm_sysfs_hotplug_event(dev); 1123 1124 return 0; 1125 } 1126 1127 static void vmw_master_drop(struct drm_device *dev, 1128 struct drm_file *file_priv) 1129 { 1130 struct vmw_private *dev_priv = vmw_priv(dev); 1131 1132 vmw_kms_legacy_hotspot_clear(dev_priv); 1133 if (!dev_priv->enable_fb) 1134 vmw_svga_disable(dev_priv); 1135 } 1136 1137 /** 1138 * __vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM. 1139 * 1140 * @dev_priv: Pointer to device private struct. 1141 * Needs the reservation sem to be held in non-exclusive mode. 1142 */ 1143 static void __vmw_svga_enable(struct vmw_private *dev_priv) 1144 { 1145 spin_lock(&dev_priv->svga_lock); 1146 if (!dev_priv->bdev.man[TTM_PL_VRAM].use_type) { 1147 vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE); 1148 dev_priv->bdev.man[TTM_PL_VRAM].use_type = true; 1149 } 1150 spin_unlock(&dev_priv->svga_lock); 1151 } 1152 1153 /** 1154 * vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM. 1155 * 1156 * @dev_priv: Pointer to device private struct. 1157 */ 1158 void vmw_svga_enable(struct vmw_private *dev_priv) 1159 { 1160 (void) ttm_read_lock(&dev_priv->reservation_sem, false); 1161 __vmw_svga_enable(dev_priv); 1162 ttm_read_unlock(&dev_priv->reservation_sem); 1163 } 1164 1165 /** 1166 * __vmw_svga_disable - Disable SVGA mode and use of VRAM. 1167 * 1168 * @dev_priv: Pointer to device private struct. 1169 * Needs the reservation sem to be held in exclusive mode. 1170 * Will not empty VRAM. VRAM must be emptied by caller. 1171 */ 1172 static void __vmw_svga_disable(struct vmw_private *dev_priv) 1173 { 1174 spin_lock(&dev_priv->svga_lock); 1175 if (dev_priv->bdev.man[TTM_PL_VRAM].use_type) { 1176 dev_priv->bdev.man[TTM_PL_VRAM].use_type = false; 1177 vmw_write(dev_priv, SVGA_REG_ENABLE, 1178 SVGA_REG_ENABLE_HIDE | 1179 SVGA_REG_ENABLE_ENABLE); 1180 } 1181 spin_unlock(&dev_priv->svga_lock); 1182 } 1183 1184 /** 1185 * vmw_svga_disable - Disable SVGA_MODE, and use of VRAM. Keep the fifo 1186 * running. 1187 * 1188 * @dev_priv: Pointer to device private struct. 1189 * Will empty VRAM. 1190 */ 1191 void vmw_svga_disable(struct vmw_private *dev_priv) 1192 { 1193 /* 1194 * Disabling SVGA will turn off device modesetting capabilities, so 1195 * notify KMS about that so that it doesn't cache atomic state that 1196 * isn't valid anymore, for example crtcs turned on. 1197 * Strictly we'd want to do this under the SVGA lock (or an SVGA mutex), 1198 * but vmw_kms_lost_device() takes the reservation sem and thus we'll 1199 * end up with lock order reversal. Thus, a master may actually perform 1200 * a new modeset just after we call vmw_kms_lost_device() and race with 1201 * vmw_svga_disable(), but that should at worst cause atomic KMS state 1202 * to be inconsistent with the device, causing modesetting problems. 1203 * 1204 */ 1205 vmw_kms_lost_device(dev_priv->dev); 1206 ttm_write_lock(&dev_priv->reservation_sem, false); 1207 spin_lock(&dev_priv->svga_lock); 1208 if (dev_priv->bdev.man[TTM_PL_VRAM].use_type) { 1209 dev_priv->bdev.man[TTM_PL_VRAM].use_type = false; 1210 spin_unlock(&dev_priv->svga_lock); 1211 if (ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM)) 1212 DRM_ERROR("Failed evicting VRAM buffers.\n"); 1213 vmw_write(dev_priv, SVGA_REG_ENABLE, 1214 SVGA_REG_ENABLE_HIDE | 1215 SVGA_REG_ENABLE_ENABLE); 1216 } else 1217 spin_unlock(&dev_priv->svga_lock); 1218 ttm_write_unlock(&dev_priv->reservation_sem); 1219 } 1220 1221 static void vmw_remove(struct pci_dev *pdev) 1222 { 1223 struct drm_device *dev = pci_get_drvdata(pdev); 1224 1225 drm_dev_unregister(dev); 1226 vmw_driver_unload(dev); 1227 drm_dev_put(dev); 1228 pci_disable_device(pdev); 1229 } 1230 1231 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, 1232 void *ptr) 1233 { 1234 struct vmw_private *dev_priv = 1235 container_of(nb, struct vmw_private, pm_nb); 1236 1237 switch (val) { 1238 case PM_HIBERNATION_PREPARE: 1239 /* 1240 * Take the reservation sem in write mode, which will make sure 1241 * there are no other processes holding a buffer object 1242 * reservation, meaning we should be able to evict all buffer 1243 * objects if needed. 1244 * Once user-space processes have been frozen, we can release 1245 * the lock again. 1246 */ 1247 ttm_suspend_lock(&dev_priv->reservation_sem); 1248 dev_priv->suspend_locked = true; 1249 break; 1250 case PM_POST_HIBERNATION: 1251 case PM_POST_RESTORE: 1252 if (READ_ONCE(dev_priv->suspend_locked)) { 1253 dev_priv->suspend_locked = false; 1254 ttm_suspend_unlock(&dev_priv->reservation_sem); 1255 } 1256 break; 1257 default: 1258 break; 1259 } 1260 return 0; 1261 } 1262 1263 static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state) 1264 { 1265 struct drm_device *dev = pci_get_drvdata(pdev); 1266 struct vmw_private *dev_priv = vmw_priv(dev); 1267 1268 if (dev_priv->refuse_hibernation) 1269 return -EBUSY; 1270 1271 pci_save_state(pdev); 1272 pci_disable_device(pdev); 1273 pci_set_power_state(pdev, PCI_D3hot); 1274 return 0; 1275 } 1276 1277 static int vmw_pci_resume(struct pci_dev *pdev) 1278 { 1279 pci_set_power_state(pdev, PCI_D0); 1280 pci_restore_state(pdev); 1281 return pci_enable_device(pdev); 1282 } 1283 1284 static int vmw_pm_suspend(struct device *kdev) 1285 { 1286 struct pci_dev *pdev = to_pci_dev(kdev); 1287 struct pm_message dummy; 1288 1289 dummy.event = 0; 1290 1291 return vmw_pci_suspend(pdev, dummy); 1292 } 1293 1294 static int vmw_pm_resume(struct device *kdev) 1295 { 1296 struct pci_dev *pdev = to_pci_dev(kdev); 1297 1298 return vmw_pci_resume(pdev); 1299 } 1300 1301 static int vmw_pm_freeze(struct device *kdev) 1302 { 1303 struct pci_dev *pdev = to_pci_dev(kdev); 1304 struct drm_device *dev = pci_get_drvdata(pdev); 1305 struct vmw_private *dev_priv = vmw_priv(dev); 1306 int ret; 1307 1308 /* 1309 * Unlock for vmw_kms_suspend. 1310 * No user-space processes should be running now. 1311 */ 1312 ttm_suspend_unlock(&dev_priv->reservation_sem); 1313 ret = vmw_kms_suspend(dev_priv->dev); 1314 if (ret) { 1315 ttm_suspend_lock(&dev_priv->reservation_sem); 1316 DRM_ERROR("Failed to freeze modesetting.\n"); 1317 return ret; 1318 } 1319 if (dev_priv->enable_fb) 1320 vmw_fb_off(dev_priv); 1321 1322 ttm_suspend_lock(&dev_priv->reservation_sem); 1323 vmw_execbuf_release_pinned_bo(dev_priv); 1324 vmw_resource_evict_all(dev_priv); 1325 vmw_release_device_early(dev_priv); 1326 ttm_bo_swapout_all(&dev_priv->bdev); 1327 if (dev_priv->enable_fb) 1328 vmw_fifo_resource_dec(dev_priv); 1329 if (atomic_read(&dev_priv->num_fifo_resources) != 0) { 1330 DRM_ERROR("Can't hibernate while 3D resources are active.\n"); 1331 if (dev_priv->enable_fb) 1332 vmw_fifo_resource_inc(dev_priv); 1333 WARN_ON(vmw_request_device_late(dev_priv)); 1334 dev_priv->suspend_locked = false; 1335 ttm_suspend_unlock(&dev_priv->reservation_sem); 1336 if (dev_priv->suspend_state) 1337 vmw_kms_resume(dev); 1338 if (dev_priv->enable_fb) 1339 vmw_fb_on(dev_priv); 1340 return -EBUSY; 1341 } 1342 1343 vmw_fence_fifo_down(dev_priv->fman); 1344 __vmw_svga_disable(dev_priv); 1345 1346 vmw_release_device_late(dev_priv); 1347 return 0; 1348 } 1349 1350 static int vmw_pm_restore(struct device *kdev) 1351 { 1352 struct pci_dev *pdev = to_pci_dev(kdev); 1353 struct drm_device *dev = pci_get_drvdata(pdev); 1354 struct vmw_private *dev_priv = vmw_priv(dev); 1355 int ret; 1356 1357 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2); 1358 (void) vmw_read(dev_priv, SVGA_REG_ID); 1359 1360 if (dev_priv->enable_fb) 1361 vmw_fifo_resource_inc(dev_priv); 1362 1363 ret = vmw_request_device(dev_priv); 1364 if (ret) 1365 return ret; 1366 1367 if (dev_priv->enable_fb) 1368 __vmw_svga_enable(dev_priv); 1369 1370 vmw_fence_fifo_up(dev_priv->fman); 1371 dev_priv->suspend_locked = false; 1372 ttm_suspend_unlock(&dev_priv->reservation_sem); 1373 if (dev_priv->suspend_state) 1374 vmw_kms_resume(dev_priv->dev); 1375 1376 if (dev_priv->enable_fb) 1377 vmw_fb_on(dev_priv); 1378 1379 return 0; 1380 } 1381 1382 static const struct dev_pm_ops vmw_pm_ops = { 1383 .freeze = vmw_pm_freeze, 1384 .thaw = vmw_pm_restore, 1385 .restore = vmw_pm_restore, 1386 .suspend = vmw_pm_suspend, 1387 .resume = vmw_pm_resume, 1388 }; 1389 1390 static const struct file_operations vmwgfx_driver_fops = { 1391 .owner = THIS_MODULE, 1392 .open = drm_open, 1393 .release = drm_release, 1394 .unlocked_ioctl = vmw_unlocked_ioctl, 1395 .mmap = vmw_mmap, 1396 .poll = vmw_fops_poll, 1397 .read = vmw_fops_read, 1398 #if defined(CONFIG_COMPAT) 1399 .compat_ioctl = vmw_compat_ioctl, 1400 #endif 1401 .llseek = noop_llseek, 1402 }; 1403 1404 static struct drm_driver driver = { 1405 .driver_features = 1406 DRIVER_MODESET | DRIVER_RENDER | DRIVER_ATOMIC, 1407 .get_vblank_counter = vmw_get_vblank_counter, 1408 .enable_vblank = vmw_enable_vblank, 1409 .disable_vblank = vmw_disable_vblank, 1410 .ioctls = vmw_ioctls, 1411 .num_ioctls = ARRAY_SIZE(vmw_ioctls), 1412 .master_set = vmw_master_set, 1413 .master_drop = vmw_master_drop, 1414 .open = vmw_driver_open, 1415 .postclose = vmw_postclose, 1416 1417 .dumb_create = vmw_dumb_create, 1418 .dumb_map_offset = vmw_dumb_map_offset, 1419 .dumb_destroy = vmw_dumb_destroy, 1420 1421 .prime_fd_to_handle = vmw_prime_fd_to_handle, 1422 .prime_handle_to_fd = vmw_prime_handle_to_fd, 1423 1424 .fops = &vmwgfx_driver_fops, 1425 .name = VMWGFX_DRIVER_NAME, 1426 .desc = VMWGFX_DRIVER_DESC, 1427 .date = VMWGFX_DRIVER_DATE, 1428 .major = VMWGFX_DRIVER_MAJOR, 1429 .minor = VMWGFX_DRIVER_MINOR, 1430 .patchlevel = VMWGFX_DRIVER_PATCHLEVEL 1431 }; 1432 1433 static struct pci_driver vmw_pci_driver = { 1434 .name = VMWGFX_DRIVER_NAME, 1435 .id_table = vmw_pci_id_list, 1436 .probe = vmw_probe, 1437 .remove = vmw_remove, 1438 .driver = { 1439 .pm = &vmw_pm_ops 1440 } 1441 }; 1442 1443 static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1444 { 1445 struct drm_device *dev; 1446 int ret; 1447 1448 ret = pci_enable_device(pdev); 1449 if (ret) 1450 return ret; 1451 1452 dev = drm_dev_alloc(&driver, &pdev->dev); 1453 if (IS_ERR(dev)) { 1454 ret = PTR_ERR(dev); 1455 goto err_pci_disable_device; 1456 } 1457 1458 dev->pdev = pdev; 1459 pci_set_drvdata(pdev, dev); 1460 1461 ret = vmw_driver_load(dev, ent->driver_data); 1462 if (ret) 1463 goto err_drm_dev_put; 1464 1465 ret = drm_dev_register(dev, ent->driver_data); 1466 if (ret) 1467 goto err_vmw_driver_unload; 1468 1469 return 0; 1470 1471 err_vmw_driver_unload: 1472 vmw_driver_unload(dev); 1473 err_drm_dev_put: 1474 drm_dev_put(dev); 1475 err_pci_disable_device: 1476 pci_disable_device(pdev); 1477 return ret; 1478 } 1479 1480 static int __init vmwgfx_init(void) 1481 { 1482 int ret; 1483 1484 if (vgacon_text_force()) 1485 return -EINVAL; 1486 1487 ret = pci_register_driver(&vmw_pci_driver); 1488 if (ret) 1489 DRM_ERROR("Failed initializing DRM.\n"); 1490 return ret; 1491 } 1492 1493 static void __exit vmwgfx_exit(void) 1494 { 1495 pci_unregister_driver(&vmw_pci_driver); 1496 } 1497 1498 module_init(vmwgfx_init); 1499 module_exit(vmwgfx_exit); 1500 1501 MODULE_AUTHOR("VMware Inc. and others"); 1502 MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device"); 1503 MODULE_LICENSE("GPL and additional rights"); 1504 MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR) "." 1505 __stringify(VMWGFX_DRIVER_MINOR) "." 1506 __stringify(VMWGFX_DRIVER_PATCHLEVEL) "." 1507 "0"); 1508
Indexes created Wed Oct 22 00:09:40 GMT 2025